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@@ -21,6 +21,10 @@
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#define MT7621_SPI_TRANS 0x00
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#define MT7621_SPI_TRANS_START BIT(8)
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#define MT7621_SPI_TRANS_BUSY BIT(16)
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+#define TRANS_ADDR_SZ GENMASK(20, 19)
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+#define TRANS_ADDR_SZ_SHIFT 19
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+#define TRANS_MOSI_BCNT GENMASK(3, 0)
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+#define TRANS_MOSI_BCNT_SHIFT 0
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#define MT7621_SPI_OPCODE 0x04
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#define MT7621_SPI_DATA0 0x08
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@@ -50,20 +54,22 @@ struct mt7621_spi {
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unsigned int sys_freq;
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};
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-static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex)
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-{
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- setbits_le32(rs->base + MT7621_SPI_MASTER,
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- MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE);
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-}
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-
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static void mt7621_spi_set_cs(struct mt7621_spi *rs, int cs, int enable)
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{
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- u32 val = 0;
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-
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debug("%s: cs#%d -> %s\n", __func__, cs, enable ? "enable" : "disable");
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- if (enable)
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- val = BIT(cs);
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- iowrite32(val, rs->base + MT7621_SPI_POLAR);
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+
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+ if (enable) {
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+ setbits_le32(rs->base + MT7621_SPI_MASTER,
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+ MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE);
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+ iowrite32(BIT(cs), rs->base + MT7621_SPI_POLAR);
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+ } else {
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+ iowrite32(0, rs->base + MT7621_SPI_POLAR);
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+ iowrite32((2 << TRANS_ADDR_SZ_SHIFT) |
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+ (1 << TRANS_MOSI_BCNT_SHIFT),
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+ rs->base + MT7621_SPI_TRANS);
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+ clrbits_le32(rs->base + MT7621_SPI_MASTER,
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+ MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE);
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+ }
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}
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static int mt7621_spi_set_mode(struct udevice *bus, uint mode)
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@@ -273,8 +279,6 @@ static int mt7621_spi_probe(struct udevice *dev)
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return -EINVAL;
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}
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- mt7621_spi_reset(rs, 0);
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-
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return 0;
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}
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