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@@ -142,6 +142,9 @@ static struct mm_region imx8m_mem_map[] = {
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE
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#endif
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+ }, {
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+ /* empty entrie to split table entry 5 if needed when TEEs are used */
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+ 0,
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}, {
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/* List terminator */
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0,
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@@ -152,18 +155,123 @@ struct mm_region *mem_map = imx8m_mem_map;
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void enable_caches(void)
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{
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- /*
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- * If OPTEE runs, remove OPTEE memory from MMU table to
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- * avoid speculative prefetch. OPTEE runs at the top of
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- * the first memory bank
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- */
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- if (rom_pointer[1])
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- imx8m_mem_map[5].size -= rom_pointer[1];
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+ /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch */
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+ if (rom_pointer[1]) {
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+ /*
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+ * TEE are loaded, So the ddr bank structures
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+ * have been modified update mmu table accordingly
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+ */
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+ int i = 0;
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+ /*
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+ * please make sure that entry initial value matches
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+ * imx8m_mem_map for DRAM1
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+ */
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+ int entry = 5;
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+ u64 attrs = imx8m_mem_map[entry].attrs;
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+
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+ while (i < CONFIG_NR_DRAM_BANKS && entry < 8) {
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+ if (gd->bd->bi_dram[i].start == 0)
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+ break;
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+ imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
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+ imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
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+ imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
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+ imx8m_mem_map[entry].attrs = attrs;
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+ debug("Added memory mapping (%d): %llx %llx\n", entry,
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+ imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);
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+ i++; entry++;
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+ }
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+ }
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icache_enable();
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dcache_enable();
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}
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+__weak int board_phys_sdram_size(phys_size_t *size)
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+{
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+ if (!size)
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+ return -EINVAL;
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+
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+ *size = PHYS_SDRAM_SIZE;
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+ return 0;
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+}
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+
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+int dram_init(void)
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+{
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+ phys_size_t sdram_size;
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+ int ret;
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+
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+ ret = board_phys_sdram_size(&sdram_size);
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+ if (ret)
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+ return ret;
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+
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+ /* rom_pointer[1] contains the size of TEE occupies */
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+ if (rom_pointer[1])
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+ gd->ram_size = sdram_size - rom_pointer[1];
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+ else
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+ gd->ram_size = sdram_size;
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+
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+#ifdef PHYS_SDRAM_2_SIZE
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+ gd->ram_size += PHYS_SDRAM_2_SIZE;
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+#endif
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+
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+ return 0;
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+}
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+
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+int dram_init_banksize(void)
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+{
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+ int bank = 0;
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+ int ret;
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+ phys_size_t sdram_size;
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+
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+ ret = board_phys_sdram_size(&sdram_size);
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+ if (ret)
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+ return ret;
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+
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+ gd->bd->bi_dram[bank].start = PHYS_SDRAM;
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+ if (rom_pointer[1]) {
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+ phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
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+ phys_size_t optee_size = (size_t)rom_pointer[1];
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+
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+ gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
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+ if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) {
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+ if (++bank >= CONFIG_NR_DRAM_BANKS) {
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+ puts("CONFIG_NR_DRAM_BANKS is not enough\n");
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+ return -1;
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+ }
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+
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+ gd->bd->bi_dram[bank].start = optee_start + optee_size;
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+ gd->bd->bi_dram[bank].size = PHYS_SDRAM +
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+ sdram_size - gd->bd->bi_dram[bank].start;
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+ }
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+ } else {
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+ gd->bd->bi_dram[bank].size = sdram_size;
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+ }
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+
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+#ifdef PHYS_SDRAM_2_SIZE
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+ if (++bank >= CONFIG_NR_DRAM_BANKS) {
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+ puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
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+ return -1;
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+ }
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+ gd->bd->bi_dram[bank].start = PHYS_SDRAM_2;
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+ gd->bd->bi_dram[bank].size = PHYS_SDRAM_2_SIZE;
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+#endif
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+
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+ return 0;
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+}
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+
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+phys_size_t get_effective_memsize(void)
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+{
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+ /* return the first bank as effective memory */
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+ if (rom_pointer[1])
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+ return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
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+
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+#ifdef PHYS_SDRAM_2_SIZE
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+ return gd->ram_size - PHYS_SDRAM_2_SIZE;
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+#else
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+ return gd->ram_size;
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+#endif
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+}
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+
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static u32 get_cpu_variant_type(u32 type)
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{
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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