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@@ -46,7 +46,7 @@ struct fsl_ifc_ctrl {
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struct fsl_ifc_mtd *chips[MAX_BANKS];
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/* device info */
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- struct fsl_ifc *regs;
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+ struct fsl_ifc regs;
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uint8_t __iomem *addr; /* Address of assigned IFC buffer */
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unsigned int cs_nand; /* On which chipsel NAND is connected */
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unsigned int page; /* Last page written to / read from */
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@@ -225,7 +225,7 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
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struct nand_chip *chip = mtd->priv;
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struct fsl_ifc_mtd *priv = chip->priv;
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struct fsl_ifc_ctrl *ctrl = priv->ctrl;
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- struct fsl_ifc *ifc = ctrl->regs;
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+ struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
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int buf_num;
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ctrl->page = page_addr;
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@@ -289,7 +289,7 @@ static int fsl_ifc_run_command(struct mtd_info *mtd)
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struct nand_chip *chip = mtd->priv;
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struct fsl_ifc_mtd *priv = chip->priv;
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struct fsl_ifc_ctrl *ctrl = priv->ctrl;
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- struct fsl_ifc *ifc = ctrl->regs;
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+ struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
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u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
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u32 time_start;
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u32 eccstat[8] = {0};
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@@ -369,7 +369,7 @@ static void fsl_ifc_do_read(struct nand_chip *chip,
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{
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struct fsl_ifc_mtd *priv = chip->priv;
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struct fsl_ifc_ctrl *ctrl = priv->ctrl;
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- struct fsl_ifc *ifc = ctrl->regs;
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+ struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
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/* Program FIR/IFC_NAND_FCR0 for Small/Large page */
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if (mtd->writesize > 512) {
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@@ -407,7 +407,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
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struct nand_chip *chip = mtd->priv;
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struct fsl_ifc_mtd *priv = chip->priv;
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struct fsl_ifc_ctrl *ctrl = priv->ctrl;
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- struct fsl_ifc *ifc = ctrl->regs;
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+ struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
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/* clear the read buffer */
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ctrl->read_bytes = 0;
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@@ -697,7 +697,7 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
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{
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struct fsl_ifc_mtd *priv = chip->priv;
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struct fsl_ifc_ctrl *ctrl = priv->ctrl;
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- struct fsl_ifc *ifc = ctrl->regs;
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+ struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
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u32 nand_fsr;
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if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
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@@ -754,24 +754,33 @@ static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
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static void fsl_ifc_ctrl_init(void)
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{
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+ uint32_t ver = 0;
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ifc_ctrl = kzalloc(sizeof(*ifc_ctrl), GFP_KERNEL);
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if (!ifc_ctrl)
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return;
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- ifc_ctrl->regs = IFC_BASE_ADDR;
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+ ifc_ctrl->regs.gregs = IFC_FCM_BASE_ADDR;
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+
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+ ver = ifc_in32(&ifc_ctrl->regs.gregs->ifc_rev);
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+ if (ver >= FSL_IFC_V2_0_0)
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+ ifc_ctrl->regs.rregs =
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+ (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
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+ else
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+ ifc_ctrl->regs.rregs =
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+ (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
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/* clear event registers */
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- ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U);
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- ifc_out32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
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+ ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_stat, ~0U);
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+ ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
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/* Enable error and event for any detected errors */
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- ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_en,
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+ ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_en,
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IFC_NAND_EVTER_EN_OPC_EN |
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IFC_NAND_EVTER_EN_PGRDCMPL_EN |
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IFC_NAND_EVTER_EN_FTOER_EN |
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IFC_NAND_EVTER_EN_WPER_EN);
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- ifc_out32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0);
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+ ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.ncfgr, 0x0);
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}
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static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
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@@ -780,7 +789,7 @@ static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
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static int fsl_ifc_sram_init(uint32_t ver)
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{
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- struct fsl_ifc *ifc = ifc_ctrl->regs;
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+ struct fsl_ifc_runtime *ifc = ifc_ctrl->regs.rregs;
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uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0;
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uint32_t ncfgr = 0;
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u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
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@@ -806,13 +815,13 @@ static int fsl_ifc_sram_init(uint32_t ver)
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cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT;
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/* Save CSOR and CSOR_ext */
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- csor = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor);
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- csor_ext = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor_ext);
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+ csor = ifc_in32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor);
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+ csor_ext = ifc_in32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext);
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/* chage PageSize 8K and SpareSize 1K*/
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csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
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- ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k);
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- ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400);
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+ ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor, csor_8k);
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+ ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext, 0x0000400);
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/* READID */
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ifc_out32(&ifc->ifc_nand.nand_fir0,
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@@ -852,8 +861,8 @@ static int fsl_ifc_sram_init(uint32_t ver)
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ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
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/* Restore CSOR and CSOR_ext */
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- ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor);
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- ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext);
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+ ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor, csor);
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+ ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext, csor_ext);
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return 0;
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}
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@@ -864,6 +873,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
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struct nand_chip *nand;
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struct fsl_ifc_mtd *priv;
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struct nand_ecclayout *layout;
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+ struct fsl_ifc_fcm *gregs = NULL;
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uint32_t cspr = 0, csor = 0, ver = 0;
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int ret = 0;
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@@ -879,14 +889,15 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
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priv->ctrl = ifc_ctrl;
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priv->vbase = addr;
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+ gregs = ifc_ctrl->regs.gregs;
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/* Find which chip select it is connected to.
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*/
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for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
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phys_addr_t phys_addr = virt_to_phys(addr);
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- cspr = ifc_in32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr);
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- csor = ifc_in32(&ifc_ctrl->regs->csor_cs[priv->bank].csor);
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+ cspr = ifc_in32(&gregs->cspr_cs[priv->bank].cspr);
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+ csor = ifc_in32(&gregs->csor_cs[priv->bank].csor);
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if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
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(cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) {
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@@ -1005,7 +1016,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
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nand->ecc.mode = NAND_ECC_SOFT;
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}
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- ver = ifc_in32(&ifc_ctrl->regs->ifc_rev);
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+ ver = ifc_in32(&gregs->ifc_rev);
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if (ver >= FSL_IFC_V1_1_0)
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ret = fsl_ifc_sram_init(ver);
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if (ret)
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