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@@ -17,6 +17,7 @@
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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+#include <asm/arch/sys_proto.h>
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#include <dt-bindings/clock/stm32mp1-clks.h>
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#include <dt-bindings/clock/stm32mp1-clksrc.h>
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@@ -644,8 +645,18 @@ static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
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};
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#ifdef STM32MP1_CLOCK_TREE_INIT
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+
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/* define characteristic of PLL according type */
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+#define DIVM_MIN 0
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+#define DIVM_MAX 63
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#define DIVN_MIN 24
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+#define DIVP_MIN 0
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+#define DIVP_MAX 127
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+#define FRAC_MAX 8192
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+
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+#define PLL1600_VCO_MIN 800000000
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+#define PLL1600_VCO_MAX 1600000000
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+
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static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
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[PLL_800] = {
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.refclk_min = 4,
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@@ -1190,6 +1201,208 @@ static ulong stm32mp1_clk_get_rate(struct clk *clk)
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}
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#ifdef STM32MP1_CLOCK_TREE_INIT
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+
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+bool stm32mp1_supports_opp(u32 opp_id, u32 cpu_type)
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+{
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+ unsigned int id;
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+
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+ switch (opp_id) {
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+ case 1:
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+ case 2:
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+ id = opp_id;
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+ break;
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+ default:
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+ id = 1; /* default value */
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+ break;
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+ }
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+
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+ switch (cpu_type) {
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+ case CPU_STM32MP157Fxx:
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+ case CPU_STM32MP157Dxx:
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+ case CPU_STM32MP153Fxx:
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+ case CPU_STM32MP153Dxx:
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+ case CPU_STM32MP151Fxx:
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+ case CPU_STM32MP151Dxx:
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+ return true;
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+ default:
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+ return id == 1;
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+ }
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+}
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+
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+/*
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+ * gets OPP parameters (frequency in KHz and voltage in mV) from
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+ * an OPP table subnode. Platform HW support capabilities are also checked.
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+ * Returns 0 on success and a negative FDT error code on failure.
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+ */
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+static int stm32mp1_get_opp(u32 cpu_type, ofnode subnode,
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+ u32 *freq_khz, u32 *voltage_mv)
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+{
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+ u32 opp_hw;
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+ u64 read_freq_64;
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+ u32 read_voltage_32;
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+
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+ *freq_khz = 0;
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+ *voltage_mv = 0;
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+
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+ opp_hw = ofnode_read_u32_default(subnode, "opp-supported-hw", 0);
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+ if (opp_hw)
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+ if (!stm32mp1_supports_opp(opp_hw, cpu_type))
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+ return -FDT_ERR_BADVALUE;
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+
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+ read_freq_64 = ofnode_read_u64_default(subnode, "opp-hz", 0) /
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+ 1000ULL;
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+ read_voltage_32 = ofnode_read_u32_default(subnode, "opp-microvolt", 0) /
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+ 1000U;
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+
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+ if (!read_voltage_32 || !read_freq_64)
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+ return -FDT_ERR_NOTFOUND;
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+
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+ /* Frequency value expressed in KHz must fit on 32 bits */
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+ if (read_freq_64 > U32_MAX)
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+ return -FDT_ERR_BADVALUE;
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+
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+ /* Millivolt value must fit on 16 bits */
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+ if (read_voltage_32 > U16_MAX)
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+ return -FDT_ERR_BADVALUE;
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+
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+ *freq_khz = (u32)read_freq_64;
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+ *voltage_mv = read_voltage_32;
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+
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+ return 0;
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+}
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+
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+/*
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+ * parses OPP table in DT and finds the parameters for the
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+ * highest frequency supported by the HW platform.
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+ * Returns 0 on success and a negative FDT error code on failure.
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+ */
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+int stm32mp1_get_max_opp_freq(struct stm32mp1_clk_priv *priv, u64 *freq_hz)
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+{
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+ ofnode node, subnode;
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+ int ret;
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+ u32 freq = 0U, voltage = 0U;
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+ u32 cpu_type = get_cpu_type();
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+
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+ node = ofnode_by_compatible(ofnode_null(), "operating-points-v2");
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+ if (!ofnode_valid(node))
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+ return -FDT_ERR_NOTFOUND;
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+
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+ ofnode_for_each_subnode(subnode, node) {
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+ unsigned int read_freq;
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+ unsigned int read_voltage;
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+
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+ ret = stm32mp1_get_opp(cpu_type, subnode,
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+ &read_freq, &read_voltage);
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+ if (ret)
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+ continue;
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+
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+ if (read_freq > freq) {
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+ freq = read_freq;
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+ voltage = read_voltage;
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+ }
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+ }
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+
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+ if (!freq || !voltage)
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+ return -FDT_ERR_NOTFOUND;
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+
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+ *freq_hz = (u64)1000U * freq;
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+
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+ return 0;
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+}
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+
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+static int stm32mp1_pll1_opp(struct stm32mp1_clk_priv *priv, int clksrc,
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+ u32 *pllcfg, u32 *fracv)
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+{
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+ u32 post_divm;
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+ u32 input_freq;
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+ u64 output_freq;
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+ u64 freq;
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+ u64 vco;
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+ u32 divm, divn, divp, frac;
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+ int i, ret;
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+ u32 diff;
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+ u32 best_diff = U32_MAX;
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+
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+ /* PLL1 is 1600 */
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+ const u32 DIVN_MAX = stm32mp1_pll[PLL_1600].divn_max;
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+ const u32 POST_DIVM_MIN = stm32mp1_pll[PLL_1600].refclk_min * 1000000U;
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+ const u32 POST_DIVM_MAX = stm32mp1_pll[PLL_1600].refclk_max * 1000000U;
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+
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+ ret = stm32mp1_get_max_opp_freq(priv, &output_freq);
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+ if (ret) {
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+ debug("PLL1 OPP configuration not found (%d).\n", ret);
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+ return ret;
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+ }
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+
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+ switch (clksrc) {
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+ case CLK_PLL12_HSI:
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+ input_freq = stm32mp1_clk_get_fixed(priv, _HSI);
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+ break;
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+ case CLK_PLL12_HSE:
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+ input_freq = stm32mp1_clk_get_fixed(priv, _HSE);
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+ break;
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+ default:
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+ return -EINTR;
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+ }
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+
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+ /* Following parameters have always the same value */
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+ pllcfg[PLLCFG_Q] = 0;
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+ pllcfg[PLLCFG_R] = 0;
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+ pllcfg[PLLCFG_O] = PQR(1, 0, 0);
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+
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+ for (divm = DIVM_MAX; divm >= DIVM_MIN; divm--) {
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+ post_divm = (u32)(input_freq / (divm + 1));
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+ if (post_divm < POST_DIVM_MIN || post_divm > POST_DIVM_MAX)
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+ continue;
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+
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+ for (divp = DIVP_MIN; divp <= DIVP_MAX; divp++) {
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+ freq = output_freq * (divm + 1) * (divp + 1);
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+ divn = (u32)((freq / input_freq) - 1);
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+ if (divn < DIVN_MIN || divn > DIVN_MAX)
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+ continue;
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+
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+ frac = (u32)(((freq * FRAC_MAX) / input_freq) -
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+ ((divn + 1) * FRAC_MAX));
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+ /* 2 loops to refine the fractional part */
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+ for (i = 2; i != 0; i--) {
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+ if (frac > FRAC_MAX)
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+ break;
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+
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+ vco = (post_divm * (divn + 1)) +
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+ ((post_divm * (u64)frac) /
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+ FRAC_MAX);
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+ if (vco < (PLL1600_VCO_MIN / 2) ||
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+ vco > (PLL1600_VCO_MAX / 2)) {
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+ frac++;
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+ continue;
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+ }
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+ freq = vco / (divp + 1);
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+ if (output_freq < freq)
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+ diff = (u32)(freq - output_freq);
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+ else
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+ diff = (u32)(output_freq - freq);
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+ if (diff < best_diff) {
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+ pllcfg[PLLCFG_M] = divm;
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+ pllcfg[PLLCFG_N] = divn;
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+ pllcfg[PLLCFG_P] = divp;
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+ *fracv = frac;
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+
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+ if (diff == 0)
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+ return 0;
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+
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+ best_diff = diff;
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+ }
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+ frac++;
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+ }
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+ }
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+ }
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+
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+ if (best_diff == U32_MAX)
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+ return -1;
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+
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+ return 0;
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+}
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+
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static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
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u32 mask_on)
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{
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@@ -1661,9 +1874,12 @@ static int stm32mp1_clktree(struct udevice *dev)
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unsigned int clksrc[CLKSRC_NB];
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unsigned int clkdiv[CLKDIV_NB];
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unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
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- ofnode plloff[_PLL_NB];
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- int ret, len;
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- uint i;
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+ unsigned int pllfracv[_PLL_NB];
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+ unsigned int pllcsg[_PLL_NB][PLLCSG_NB];
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+ bool pllcfg_valid[_PLL_NB];
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+ bool pllcsg_set[_PLL_NB];
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+ int ret;
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+ int i, len;
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int lse_css = 0;
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const u32 *pkcs_cell;
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@@ -1683,16 +1899,43 @@ static int stm32mp1_clktree(struct udevice *dev)
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/* check mandatory field in each pll */
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for (i = 0; i < _PLL_NB; i++) {
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char name[12];
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+ ofnode node;
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sprintf(name, "st,pll@%d", i);
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- plloff[i] = dev_read_subnode(dev, name);
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- if (!ofnode_valid(plloff[i]))
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- continue;
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- ret = ofnode_read_u32_array(plloff[i], "cfg",
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- pllcfg[i], PLLCFG_NB);
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- if (ret < 0) {
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- debug("field cfg invalid: error %d\n", ret);
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- return -FDT_ERR_NOTFOUND;
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+ node = dev_read_subnode(dev, name);
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+ pllcfg_valid[i] = ofnode_valid(node);
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+ pllcsg_set[i] = false;
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+ if (pllcfg_valid[i]) {
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+ debug("DT for PLL %d @ %s\n", i, name);
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+ ret = ofnode_read_u32_array(node, "cfg",
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+ pllcfg[i], PLLCFG_NB);
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+ if (ret < 0) {
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+ debug("field cfg invalid: error %d\n", ret);
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+ return -FDT_ERR_NOTFOUND;
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+ }
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+ pllfracv[i] = ofnode_read_u32_default(node, "frac", 0);
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+
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+ ret = ofnode_read_u32_array(node, "csg", pllcsg[i],
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+ PLLCSG_NB);
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+ if (!ret) {
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+ pllcsg_set[i] = true;
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+ } else if (ret != -FDT_ERR_NOTFOUND) {
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+ debug("invalid csg node for pll@%d res=%d\n",
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+ i, ret);
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+ return ret;
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+ }
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+ } else if (i == _PLL1) {
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+ /* use OPP for PLL1 for A7 CPU */
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+ debug("DT for PLL %d with OPP\n", i);
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+ ret = stm32mp1_pll1_opp(priv,
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+ clksrc[CLKSRC_PLL12],
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+ pllcfg[i],
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+ &pllfracv[i]);
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+ if (ret) {
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+ debug("PLL %d with OPP error = %d\n", i, ret);
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+ return ret;
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+ }
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+ pllcfg_valid[i] = true;
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}
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}
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@@ -1778,29 +2021,18 @@ static int stm32mp1_clktree(struct udevice *dev)
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/* configure and start PLLs */
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debug("configure PLLs\n");
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for (i = 0; i < _PLL_NB; i++) {
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- u32 fracv;
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- u32 csg[PLLCSG_NB];
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-
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- debug("configure PLL %d @ %d\n", i,
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- ofnode_to_offset(plloff[i]));
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- if (!ofnode_valid(plloff[i]))
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+ if (!pllcfg_valid[i])
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continue;
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-
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- fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
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- pll_config(priv, i, pllcfg[i], fracv);
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- ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
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- if (!ret) {
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- pll_csg(priv, i, csg);
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- } else if (ret != -FDT_ERR_NOTFOUND) {
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- debug("invalid csg node for pll@%d res=%d\n", i, ret);
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- return ret;
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- }
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+ debug("configure PLL %d\n", i);
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+ pll_config(priv, i, pllcfg[i], pllfracv[i]);
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+ if (pllcsg_set[i])
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+ pll_csg(priv, i, pllcsg[i]);
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pll_start(priv, i);
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}
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/* wait and start PLLs ouptut when ready */
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for (i = 0; i < _PLL_NB; i++) {
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- if (!ofnode_valid(plloff[i]))
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+ if (!pllcfg_valid[i])
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continue;
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debug("output PLL %d\n", i);
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pll_output(priv, i, pllcfg[i][PLLCFG_O]);
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@@ -2050,6 +2282,8 @@ static int stm32mp1_clk_probe(struct udevice *dev)
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/* clock tree init is done only one time, before relocation */
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if (!(gd->flags & GD_FLG_RELOC))
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result = stm32mp1_clktree(dev);
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+ if (result)
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+ printf("clock tree initialization failed (%d)\n", result);
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#endif
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#ifndef CONFIG_SPL_BUILD
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