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@@ -9,23 +9,13 @@
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#include <asm/cacheops.h>
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#include <asm/mipsregs.h>
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-#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
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-
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static inline unsigned long icache_line_size(void)
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{
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- return CONFIG_SYS_CACHELINE_SIZE;
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-}
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-
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-static inline unsigned long dcache_line_size(void)
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-{
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- return CONFIG_SYS_CACHELINE_SIZE;
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-}
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+ unsigned long conf1, il;
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-#else /* !CONFIG_SYS_CACHELINE_SIZE */
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+ if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO))
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+ return CONFIG_SYS_ICACHE_LINE_SIZE;
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-static inline unsigned long icache_line_size(void)
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-{
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- unsigned long conf1, il;
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conf1 = read_c0_config1();
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il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
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if (!il)
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@@ -36,6 +26,10 @@ static inline unsigned long icache_line_size(void)
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static inline unsigned long dcache_line_size(void)
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{
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unsigned long conf1, dl;
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+
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+ if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO))
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+ return CONFIG_SYS_DCACHE_LINE_SIZE;
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+
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conf1 = read_c0_config1();
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dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
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if (!dl)
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@@ -43,8 +37,6 @@ static inline unsigned long dcache_line_size(void)
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return 2 << dl;
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}
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-#endif /* !CONFIG_SYS_CACHELINE_SIZE */
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-
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void flush_cache(ulong start_addr, ulong size)
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{
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unsigned long ilsize = icache_line_size();
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