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@@ -259,6 +259,8 @@ static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss)
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ddrss_phy_writel(DDRSS_DDRPHY_DTCR0, ctrl->ddrphy_dtcr0);
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ddrss_phy_writel(DDRSS_DDRPHY_DTCR1, ctrl->ddrphy_dtcr1);
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+ ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR0, ioctl->ddrphy_aciocr0);
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+ ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR3, ioctl->ddrphy_aciocr3);
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ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR5, ioctl->ddrphy_aciocr5);
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ddrss_phy_writel(DDRSS_DDRPHY_IOVCR0, ioctl->ddrphy_iovcr0);
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@@ -294,6 +296,10 @@ static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss)
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ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DXCTL2, cfg->ddrphy_dx8sl1dxctl2);
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ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DXCTL2, cfg->ddrphy_dx8sl2dxctl2);
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+ ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, cfg->ddrphy_dx8sl0dqsctl);
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+ ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, cfg->ddrphy_dx8sl1dqsctl);
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+ ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, cfg->ddrphy_dx8sl2dqsctl);
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+
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debug("%s: DDR phy register configuration completed\n", __func__);
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}
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@@ -479,18 +485,43 @@ int VREF_training(struct am654_ddrss_desc *ddrss)
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int enable_dqs_pd(struct am654_ddrss_desc *ddrss)
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{
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- ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, 0x012640F7);
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- ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, 0x012640F7);
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- ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, 0x012640F7);
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+ u32 val;
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+
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+ val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL0DQSCTL);
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+ val &= ~0xFF;
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+ val |= 0xF7;
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+ ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, val);
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+
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+ val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL1DQSCTL);
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+ val &= ~0xFF;
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+ val |= 0xF7;
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+ ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, val);
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+
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+ val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL2DQSCTL);
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+ val &= ~0xFF;
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+ val |= 0xF7;
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+ ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, val);
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+
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sdelay(16);
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return 0;
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}
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int disable_dqs_pd(struct am654_ddrss_desc *ddrss)
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{
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- ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, 0x01264000);
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- ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, 0x01264000);
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- ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, 0x01264000);
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+ u32 val;
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+
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+ val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL0DQSCTL);
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+ val &= ~0xFF;
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+ ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, val);
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+
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+ val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL1DQSCTL);
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+ val &= ~0xFF;
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+ ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, val);
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+
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+ val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL2DQSCTL);
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+ val &= ~0xFF;
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+ ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, val);
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+
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sdelay(16);
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return 0;
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}
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@@ -595,12 +626,14 @@ static int am654_ddrss_init(struct am654_ddrss_desc *ddrss)
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{
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int ret;
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u32 val;
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+ struct ddrss_ss_reg_params *reg = &ddrss->params.ss_reg;
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debug("Starting DDR initialization...\n");
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debug("%s(ddrss=%p)\n", __func__, ddrss);
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- ddrss_writel(ddrss->ddrss_ss_cfg, DDRSS_V2H_CTL_REG, 0x000073FF);
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+ ddrss_writel(ddrss->ddrss_ss_cfg, DDRSS_V2H_CTL_REG,
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+ reg->ddrss_v2h_ctl_reg);
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am654_ddrss_ctrl_configuration(ddrss);
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@@ -901,6 +934,14 @@ static int am654_ddrss_ofdata_to_priv(struct udevice *dev)
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}
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ddrss->ddrss_phy_cfg = (void *)reg;
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+ ret = dev_read_u32_array(dev, "ti,ss-reg",
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+ (u32 *)&ddrss->params.ss_reg,
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+ sizeof(ddrss->params.ss_reg) / sizeof(u32));
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+ if (ret) {
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+ dev_err(dev, "Cannot read ti,ss-reg params\n");
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+ return ret;
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+ }
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+
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ret = dev_read_u32_array(dev, "ti,ctl-reg",
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(u32 *)&ddrss->params.ctl_reg,
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sizeof(ddrss->params.ctl_reg) / sizeof(u32));
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