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@@ -274,6 +274,8 @@ static int socfpga_a10_clk_bind(struct udevice *dev)
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static int socfpga_a10_clk_probe(struct udevice *dev)
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{
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struct socfpga_a10_clk_platdata *plat = dev_get_platdata(dev);
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+ struct socfpga_a10_clk_platdata *pplat;
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+ struct udevice *pdev;
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const void *fdt = gd->fdt_blob;
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int offset = dev_of_offset(dev);
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@@ -281,6 +283,21 @@ static int socfpga_a10_clk_probe(struct udevice *dev)
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socfpga_a10_handoff_workaround(dev);
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+ if (!fdt_node_check_compatible(fdt, offset, "altr,clk-mgr")) {
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+ plat->regs = devfdt_get_addr(dev);
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+ } else {
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+ pdev = dev_get_parent(dev);
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+ if (!pdev)
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+ return -ENODEV;
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+
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+ pplat = dev_get_platdata(pdev);
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+ if (!pplat)
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+ return -EINVAL;
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+
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+ plat->ctl_reg = dev_read_u32_default(dev, "reg", 0x0);
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+ plat->regs = pplat->regs;
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+ }
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+
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if (!fdt_node_check_compatible(fdt, offset,
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"altr,socfpga-a10-pll-clock")) {
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/* Main PLL has 3 upstream clock */
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@@ -304,29 +321,8 @@ static int socfpga_a10_clk_probe(struct udevice *dev)
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static int socfpga_a10_ofdata_to_platdata(struct udevice *dev)
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{
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struct socfpga_a10_clk_platdata *plat = dev_get_platdata(dev);
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- struct socfpga_a10_clk_platdata *pplat;
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- struct udevice *pdev;
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- const void *fdt = gd->fdt_blob;
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unsigned int divreg[3], gatereg[2];
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- int ret, offset = dev_of_offset(dev);
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- u32 regs;
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-
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- regs = dev_read_u32_default(dev, "reg", 0x0);
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-
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- if (!fdt_node_check_compatible(fdt, offset, "altr,clk-mgr")) {
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- plat->regs = devfdt_get_addr(dev);
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- } else {
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- pdev = dev_get_parent(dev);
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- if (!pdev)
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- return -ENODEV;
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-
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- pplat = dev_get_platdata(pdev);
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- if (!pplat)
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- return -EINVAL;
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-
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- plat->ctl_reg = regs;
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- plat->regs = pplat->regs;
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- }
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+ int ret;
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plat->type = SOCFPGA_A10_CLK_UNKNOWN_CLK;
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