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@@ -13,6 +13,7 @@
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#include <asm/arch/clk.h>
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#define ATMEL_SDHC_MIN_FREQ 400000
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+#define ATMEL_SDHC_GCK_RATE 240000000
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#ifndef CONFIG_DM_MMC
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int atmel_sdhci_init(void *regbase, u32 id)
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@@ -57,9 +58,6 @@ static int atmel_sdhci_probe(struct udevice *dev)
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struct atmel_sdhci_plat *plat = dev_get_platdata(dev);
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struct sdhci_host *host = dev_get_priv(dev);
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u32 max_clk;
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- u32 caps, caps_1;
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- u32 clk_base, clk_mul;
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- ulong gck_rate;
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struct clk clk;
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int ret;
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@@ -78,17 +76,11 @@ static int atmel_sdhci_probe(struct udevice *dev)
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host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"bus-width", 4);
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- caps = sdhci_readl(host, SDHCI_CAPABILITIES);
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- clk_base = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
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- caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
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- clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
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- gck_rate = clk_base * 1000000 * (clk_mul + 1);
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-
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ret = clk_get_by_index(dev, 1, &clk);
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if (ret)
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return ret;
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- ret = clk_set_rate(&clk, gck_rate);
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+ ret = clk_set_rate(&clk, ATMEL_SDHC_GCK_RATE);
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if (ret)
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return ret;
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