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@@ -11,6 +11,8 @@
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#ifndef _MVEBU_SOC_H
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#define _MVEBU_SOC_H
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+#define BIT(x) (1 << (x))
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+
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#define SOC_MV78460_ID 0x7846
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#define SOC_88F6810_ID 0x6810
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#define SOC_88F6820_ID 0x6820
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@@ -25,6 +27,9 @@
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#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
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#endif
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+/* Armada XP PLL frequency (used for NAND clock generation) */
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+#define CONFIG_SYS_MVEBU_PLL_CLOCK 2000000000
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+
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/* SOC specific definations */
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#define INTREG_BASE 0xd0000000
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#define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080)
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@@ -53,6 +58,7 @@
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#define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140))
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#define MVEBU_GPIO2_BASE (MVEBU_REGISTER(0x18180))
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#define MVEBU_SYSTEM_REG_BASE (MVEBU_REGISTER(0x18200))
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+#define MVEBU_CLOCK_BASE (MVEBU_REGISTER(0x18700))
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#define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000))
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#define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180))
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#define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300))
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@@ -64,6 +70,7 @@
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#define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000))
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#define MVEBU_AXP_SATA_BASE (MVEBU_REGISTER(0xa0000))
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#define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000))
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+#define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000))
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#define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000))
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#define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200))
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@@ -72,6 +79,21 @@
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#define MBUS_BRIDGE_WIN_CTRL_REG (MVEBU_REGISTER(0x20250))
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#define MBUS_BRIDGE_WIN_BASE_REG (MVEBU_REGISTER(0x20254))
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+#define MVEBU_SOC_DEV_MUX_REG (MVEBU_SYSTEM_REG_BASE + 0x08)
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+#define NAND_EN BIT(0)
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+#define NAND_ARBITER_EN BIT(27)
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+
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+#define ARMADA_XP_PUP_ENABLE (MVEBU_SYSTEM_REG_BASE + 0x44c)
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+#define GE0_PUP_EN BIT(0)
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+#define GE1_PUP_EN BIT(1)
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+#define LCD_PUP_EN BIT(2)
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+#define NAND_PUP_EN BIT(4)
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+#define SPI_PUP_EN BIT(5)
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+
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+#define MVEBU_CORE_DIV_CLK_CTRL(i) (MVEBU_CLOCK_BASE + ((i) * 0x8))
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+#define NAND_ECC_DIVCKL_RATIO_OFFS 8
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+#define NAND_ECC_DIVCKL_RATIO_MASK (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS)
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+
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#define SDRAM_MAX_CS 4
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#define SDRAM_ADDR_MASK 0xFF000000
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