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@@ -12,60 +12,14 @@
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#include <common.h>
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#include <init.h>
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#include <net.h>
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-#include <asm/io.h>
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-#include <asm/arch/clock.h>
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-#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/mx6-ddr.h>
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-#include <asm/arch/iomux.h>
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-#include <asm/arch/mx6-pins.h>
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-#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/boot_mode.h>
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-#include <asm/mach-imx/mxc_i2c.h>
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-#include <asm/mach-imx/spi.h>
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-#include <linux/delay.h>
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-#include <linux/errno.h>
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-#include <asm/gpio.h>
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-#include <mmc.h>
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-#include <i2c.h>
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-#include <fsl_esdhc_imx.h>
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-#include <nand.h>
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-#include <miiphy.h>
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-#include <netdev.h>
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#include <asm/arch/sys_proto.h>
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-#include <asm/sections.h>
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+#include <dm.h>
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DECLARE_GLOBAL_DATA_PTR;
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-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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-
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-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
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- PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
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- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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-
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-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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-
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-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
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- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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-
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-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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- PAD_CTL_ODE | PAD_CTL_SRE_FAST)
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-
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-#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
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-
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-#define ASRC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
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- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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-
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-#define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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-
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-#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 14)
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-#define USDHC1_CD_GPIO IMX_GPIO_NR(6, 31)
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-#define USER_LED IMX_GPIO_NR(1, 4)
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#define IMX6Q_DRIVE_STRENGTH 0x30
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int dram_init(void)
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@@ -74,229 +28,16 @@ int dram_init(void)
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return 0;
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}
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-void board_turn_off_led(void)
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-{
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- gpio_direction_output(USER_LED, 0);
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-}
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-
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-static iomux_v3_cfg_t const uart1_pads[] = {
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- MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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- MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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-};
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-
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-static iomux_v3_cfg_t const enet_pads[] = {
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- MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_SD2_DAT1__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
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-};
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-
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-static iomux_v3_cfg_t const ecspi1_pads[] = {
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- MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
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- MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
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- MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
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- MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
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-};
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-
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-#ifdef CONFIG_CMD_NAND
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-/* NAND */
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-static iomux_v3_cfg_t const nfc_pads[] = {
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- MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
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- MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
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- MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
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- MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
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- MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
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- MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
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- MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
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- MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
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- MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
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- MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
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- MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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- MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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- MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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- MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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- MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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- MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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- MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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- MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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- MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL),
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-};
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-#endif
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-
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-static struct i2c_pads_info i2c_pad_info2 = {
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- .scl = {
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- .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | I2C_PAD,
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- .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | I2C_PAD,
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- .gp = IMX_GPIO_NR(1, 5)
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- },
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- .sda = {
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- .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
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- .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
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- .gp = IMX_GPIO_NR(1, 6)
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- }
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-};
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-
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-static struct fsl_esdhc_cfg usdhc_cfg[] = {
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- {.esdhc_base = USDHC1_BASE_ADDR,
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- .max_bus_width = 4},
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-#ifndef CONFIG_CMD_NAND
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- {USDHC4_BASE_ADDR},
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-#endif
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-};
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-
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-static iomux_v3_cfg_t const usdhc1_pads[] = {
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- MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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- MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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- MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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- MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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- MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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- MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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- MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
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-};
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-
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-#if !defined(CONFIG_CMD_NAND) && !defined(CONFIG_SPL_BUILD)
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-static iomux_v3_cfg_t const usdhc4_pads[] = {
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- MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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- MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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- MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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- MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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- MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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- MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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- MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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- MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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- MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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- MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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-};
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-#endif
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-
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int board_mmc_get_env_dev(int devno)
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{
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return devno - 1;
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}
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-int board_mmc_getcd(struct mmc *mmc)
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-{
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- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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- int ret = 0;
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-
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- switch (cfg->esdhc_base) {
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- case USDHC1_BASE_ADDR:
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- ret = !gpio_get_value(USDHC1_CD_GPIO);
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- break;
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- case USDHC4_BASE_ADDR:
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- ret = 1; /* eMMC/uSDHC4 is always present */
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- break;
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- }
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-
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- return ret;
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-}
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-
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-int board_mmc_init(bd_t *bis)
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-{
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-#ifndef CONFIG_SPL_BUILD
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- int ret;
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- int i;
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-
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- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
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- switch (i) {
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- case 0:
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- imx_iomux_v3_setup_multiple_pads(
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- usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
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- gpio_direction_input(USDHC1_CD_GPIO);
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- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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- break;
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-#ifndef CONFIG_CMD_NAND
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- case 1:
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- imx_iomux_v3_setup_multiple_pads(
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- usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
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- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
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- break;
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-#endif
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- default:
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- printf("Warning: you configured more USDHC controllers"
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- "(%d) then supported by the board (%d)\n",
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- i + 1, CONFIG_SYS_FSL_USDHC_NUM);
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- return -EINVAL;
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- }
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-
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- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
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- if (ret)
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- return ret;
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- }
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-
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- return 0;
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-#else
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- struct src *psrc = (struct src *)SRC_BASE_ADDR;
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- unsigned reg = readl(&psrc->sbmr1) >> 11;
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- /*
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- * Upon reading BOOT_CFG register the following map is done:
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- * Bit 11 and 12 of BOOT_CFG register can determine the current
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- * mmc port
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- * 0x1 SD1
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- * 0x2 SD2
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- * 0x3 SD4
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- */
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-
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- switch (reg & 0x3) {
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- case 0x0:
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- imx_iomux_v3_setup_multiple_pads(
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- usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
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- gpio_direction_input(USDHC1_CD_GPIO);
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- usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
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- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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- usdhc_cfg[0].max_bus_width = 4;
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- gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
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- break;
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- }
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- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
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-#endif
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-}
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-
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-static void setup_iomux_uart(void)
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-{
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- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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-}
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-
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-static void setup_iomux_enet(void)
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-{
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- imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
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-
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- gpio_direction_output(ENET_PHY_RESET_GPIO, 0);
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- mdelay(10);
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- gpio_set_value(ENET_PHY_RESET_GPIO, 1);
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- mdelay(30);
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-}
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-
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-static void setup_spi(void)
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-{
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- gpio_request(IMX_GPIO_NR(3, 19), "spi_cs0");
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- gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
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-
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- imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
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-
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- enable_spi_clk(true, 0);
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-}
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-
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#ifdef CONFIG_CMD_NAND
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static void setup_gpmi_nand(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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- /* config gpmi nand iomux */
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- imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
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-
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/* gate ENFC_CLK_ROOT clock first,before clk source switch */
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clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
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@@ -325,48 +66,17 @@ static void setup_gpmi_nand(void)
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}
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#endif
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-int board_spi_cs_gpio(unsigned bus, unsigned cs)
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-{
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- if (bus != 0 || (cs != 0))
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- return -EINVAL;
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-
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- return IMX_GPIO_NR(3, 19);
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-}
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-
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-int board_eth_init(bd_t *bis)
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-{
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- setup_iomux_enet();
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-
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- return cpu_eth_init(bis);
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-}
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-
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-int board_early_init_f(void)
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-{
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- setup_iomux_uart();
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-
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- return 0;
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-}
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-
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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-#ifdef CONFIG_SYS_I2C_MXC
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- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
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|
|
-#endif
|
|
|
-
|
|
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-#ifdef CONFIG_MXC_SPI
|
|
|
- setup_spi();
|
|
|
-#endif
|
|
|
-
|
|
|
#ifdef CONFIG_CMD_NAND
|
|
|
setup_gpmi_nand();
|
|
|
#endif
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
-
|
|
|
#ifdef CONFIG_CMD_BMODE
|
|
|
/*
|
|
|
* BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
|
|
@@ -535,11 +245,6 @@ void board_boot_order(u32 *spl_boot_list)
|
|
|
|
|
|
void board_init_f(ulong dummy)
|
|
|
{
|
|
|
-#ifdef CONFIG_CMD_NAND
|
|
|
- /* Enable NAND */
|
|
|
- setup_gpmi_nand();
|
|
|
-#endif
|
|
|
-
|
|
|
/* setup clock gating */
|
|
|
ccgr_init();
|
|
|
|
|
@@ -549,23 +254,33 @@ void board_init_f(ulong dummy)
|
|
|
/* setup AXI */
|
|
|
gpr_init();
|
|
|
|
|
|
- board_early_init_f();
|
|
|
-
|
|
|
/* setup GP timer */
|
|
|
timer_init();
|
|
|
|
|
|
- setup_spi();
|
|
|
-
|
|
|
- /* UART clocks enabled and gd valid - init serial console */
|
|
|
- preloader_console_init();
|
|
|
-
|
|
|
/* DDR initialization */
|
|
|
spl_dram_init();
|
|
|
|
|
|
/* Clear the BSS. */
|
|
|
memset(__bss_start, 0, __bss_end - __bss_start);
|
|
|
|
|
|
- /* load/boot image from boot device */
|
|
|
- board_init_r(NULL, 0);
|
|
|
+ /* Enable device tree and early DM support*/
|
|
|
+ spl_early_init();
|
|
|
+
|
|
|
+ /* UART clocks enabled and gd valid - init serial console */
|
|
|
+ preloader_console_init();
|
|
|
+}
|
|
|
+
|
|
|
+/*
|
|
|
+ * Manually probe the SPI bus devices, as this does not happen when the
|
|
|
+ * SPI Flash is probed, which then fails to find the bus.
|
|
|
+ */
|
|
|
+void spl_board_init(void)
|
|
|
+{
|
|
|
+ struct udevice *udev;
|
|
|
+ int ret = uclass_get_device_by_name(UCLASS_SPI, "spi@2008000", &udev);
|
|
|
+
|
|
|
+ if (ret) {
|
|
|
+ printf("SPI bus probe failed, err = %d\n", ret);
|
|
|
+ };
|
|
|
}
|
|
|
#endif
|