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@@ -7,3 +7,21 @@ config PCH
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northbridge / southbridge architecture that was previously used. The
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PCH allows for higher performance since the memory functions are
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handled in the CPU.
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+
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+config X86_PCH7
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+ bool "Add support for Intel PCH7"
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+ default y if X86
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+ help
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+ Enable this if your SoC uses Platform Controller Hub 7 (PCH7). This
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+ dates from about 2011 and is used on baytrail, for example. The
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+ PCH provides access to the GPIO and SPI base addresses, among other
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+ functions.
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+
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+config X86_PCH9
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+ bool "Add support for Intel PCH9"
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+ default y if X86
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+ help
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+ Enable this if your SoC uses Platform Controller Hub 9 (PCH9). This
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+ dates from about 2015 and is used on baytrail, for example. The
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+ PCH provides access to the GPIO and SPI base addresses, among other
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+ functions.
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