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+/*
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+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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+ *
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+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
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+ */
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+#include <common.h>
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+#include <clk.h>
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+#include <asm/io.h>
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+#include <asm/arch/stm32.h>
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+
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+void enable_caches(void)
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+{
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+ /* Enable D-cache. I-cache is already enabled in start.S */
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+ dcache_enable();
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+}
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+
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+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
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+/**********************************************
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+ * Security init
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+ *********************************************/
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+#define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
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+#define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
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+
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+#define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
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+#define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
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+#define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
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+
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+#define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
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+
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+#define PWR_CR1 (STM32_PWR_BASE + 0x00)
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+#define PWR_CR1_DBP BIT(8)
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+
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+#define RCC_TZCR (STM32_RCC_BASE + 0x00)
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+#define RCC_BDCR (STM32_RCC_BASE + 0x0140)
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+#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
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+
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+#define RCC_BDCR_VSWRST BIT(31)
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+#define RCC_BDCR_RTCSRC GENMASK(17, 16)
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+
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+static void security_init(void)
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+{
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+ /* Disable the backup domain write protection */
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+ /* the protection is enable at each reset by hardware */
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+ /* And must be disable by software */
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+ setbits_le32(PWR_CR1, PWR_CR1_DBP);
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+
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+ while (!(readl(PWR_CR1) & PWR_CR1_DBP))
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+ ;
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+
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+ /* If RTC clock isn't enable so this is a cold boot then we need
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+ * to reset the backup domain
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+ */
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+ if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
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+ setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
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+ while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
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+ ;
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+ clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
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+ }
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+
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+ /* allow non secure access in Write/Read for all peripheral */
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+ writel(GENMASK(25, 0), ETZPC_DECPROT0);
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+
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+ /* Open SYSRAM for no secure access */
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+ writel(0x0, ETZPC_TZMA1_SIZE);
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+
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+ /* enable TZC1 TZC2 clock */
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+ writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
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+
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+ /* Region 0 set to no access by default */
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+ /* bit 0 / 16 => nsaid0 read/write Enable
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+ * bit 1 / 17 => nsaid1 read/write Enable
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+ * ...
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+ * bit 15 / 31 => nsaid15 read/write Enable
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+ */
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+ writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
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+ /* bit 30 / 31 => Secure Global Enable : write/read */
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+ /* bit 0 / 1 => Region Enable for filter 0/1 */
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+ writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
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+
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+ /* Enable Filter 0 and 1 */
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+ setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
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+
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+ /* RCC trust zone deactivated */
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+ writel(0x0, RCC_TZCR);
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+
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+ /* TAMP: deactivate the internal tamper
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+ * Bit 23 ITAMP8E: monotonic counter overflow
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+ * Bit 20 ITAMP5E: RTC calendar overflow
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+ * Bit 19 ITAMP4E: HSE monitoring
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+ * Bit 18 ITAMP3E: LSE monitoring
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+ * Bit 16 ITAMP1E: RTC power domain supply monitoring
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+ */
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+ writel(0x0, TAMP_CR1);
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+}
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+
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+/**********************************************
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+ * Debug init
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+ *********************************************/
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+#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
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+#define RCC_DBGCFGR_DBGCKEN BIT(8)
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+
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+#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
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+#define DBGMCU_APB4FZ1_IWDG2 BIT(2)
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+
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+static void dbgmcu_init(void)
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+{
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+ setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
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+
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+ /* Freeze IWDG2 if Cortex-A7 is in debug mode */
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+ setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
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+}
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+#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
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+
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+int arch_cpu_init(void)
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+{
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+ /* early armv7 timer init: needed for polling */
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+ timer_init();
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+
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+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
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+ dbgmcu_init();
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+
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+ security_init();
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+#endif
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+
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+ return 0;
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+}
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+
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+#if defined(CONFIG_DISPLAY_CPUINFO)
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+int print_cpuinfo(void)
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+{
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+ printf("CPU: STM32MP15x\n");
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+
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+ return 0;
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+}
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+#endif /* CONFIG_DISPLAY_CPUINFO */
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+
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+void reset_cpu(ulong addr)
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+{
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+}
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