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@@ -0,0 +1,59 @@
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+/*
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+ * Copyright (C) STMicroelectronics SA 2017
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+ * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
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+ *
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+ * SPDX-License-Identifier: GPL-2.0+
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+ */
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+
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+#include <common.h>
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+#include <asm/io.h>
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+#include <asm/armv7m_mpu.h>
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+
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+u32 get_cpu_rev(void)
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+{
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+ return 0;
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+}
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+
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+int arch_cpu_init(void)
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+{
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+ int i;
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+
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+ struct mpu_region_config stm32_region_config[] = {
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+ /*
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+ * Make all 4GB cacheable & executable. We are overriding it
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+ * with next region for any requirement. e.g. below region1,
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+ * 2 etc.
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+ * In other words, the area not coming in following
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+ * regions configuration is the one configured here in region_0
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+ * (cacheable & executable).
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+ */
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+ { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
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+ O_I_WB_RD_WR_ALLOC, REGION_4GB },
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+
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+ /* Code area, executable & strongly ordered */
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+ { 0xD0000000, REGION_1, XN_EN, PRIV_RW_USR_RW,
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+ STRONG_ORDER, REGION_8MB },
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+
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+ /* Device area in all H7 : Not executable */
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+ { 0x40000000, REGION_2, XN_EN, PRIV_RW_USR_RW,
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+ DEVICE_NON_SHARED, REGION_512MB },
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+
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+ /*
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+ * Armv7m fixed configuration: strongly ordered & not
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+ * executable, not cacheable
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+ */
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+ { 0xE0000000, REGION_4, XN_EN, PRIV_RW_USR_RW,
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+ STRONG_ORDER, REGION_512MB },
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+ };
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+
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+ disable_mpu();
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+ for (i = 0; i < ARRAY_SIZE(stm32_region_config); i++)
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+ mpu_config(&stm32_region_config[i]);
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+ enable_mpu();
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+
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+ return 0;
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+}
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+
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+void s_init(void)
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+{
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+}
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