|
@@ -106,26 +106,6 @@
|
|
|
};
|
|
|
};
|
|
|
|
|
|
- pm_domain {
|
|
|
- #address-cells = <1>;
|
|
|
- #size-cells = <0>;
|
|
|
- compatible = "st,stm32mp157c-pd";
|
|
|
-
|
|
|
- pd_core_ret: core-ret-power-domain@1 {
|
|
|
- #address-cells = <1>;
|
|
|
- #size-cells = <0>;
|
|
|
- reg = <1>;
|
|
|
- #power-domain-cells = <0>;
|
|
|
- label = "CORE-RETENTION";
|
|
|
-
|
|
|
- pd_core: core-power-domain@2 {
|
|
|
- reg = <2>;
|
|
|
- #power-domain-cells = <0>;
|
|
|
- label = "CORE";
|
|
|
- };
|
|
|
- };
|
|
|
- };
|
|
|
-
|
|
|
soc {
|
|
|
compatible = "simple-bus";
|
|
|
#address-cells = <1>;
|
|
@@ -339,6 +319,34 @@
|
|
|
};
|
|
|
};
|
|
|
|
|
|
+ spi2: spi@4000b000 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ compatible = "st,stm32h7-spi";
|
|
|
+ reg = <0x4000b000 0x400>;
|
|
|
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&rcc SPI2_K>;
|
|
|
+ resets = <&rcc SPI2_R>;
|
|
|
+ dmas = <&dmamux1 39 0x400 0x05>,
|
|
|
+ <&dmamux1 40 0x400 0x05>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ spi3: spi@4000c000 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ compatible = "st,stm32h7-spi";
|
|
|
+ reg = <0x4000c000 0x400>;
|
|
|
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&rcc SPI3_K>;
|
|
|
+ resets = <&rcc SPI3_R>;
|
|
|
+ dmas = <&dmamux1 61 0x400 0x05>,
|
|
|
+ <&dmamux1 62 0x400 0x05>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
usart2: serial@4000e000 {
|
|
|
compatible = "st,stm32h7-uart";
|
|
|
reg = <0x4000e000 0x400>;
|
|
@@ -522,6 +530,34 @@
|
|
|
status = "disabled";
|
|
|
};
|
|
|
|
|
|
+ spi1: spi@44004000 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ compatible = "st,stm32h7-spi";
|
|
|
+ reg = <0x44004000 0x400>;
|
|
|
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&rcc SPI1_K>;
|
|
|
+ resets = <&rcc SPI1_R>;
|
|
|
+ dmas = <&dmamux1 37 0x400 0x05>,
|
|
|
+ <&dmamux1 38 0x400 0x05>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ spi4: spi@44005000 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ compatible = "st,stm32h7-spi";
|
|
|
+ reg = <0x44005000 0x400>;
|
|
|
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&rcc SPI4_K>;
|
|
|
+ resets = <&rcc SPI4_R>;
|
|
|
+ dmas = <&dmamux1 83 0x400 0x05>,
|
|
|
+ <&dmamux1 84 0x400 0x05>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
timers15: timer@44006000 {
|
|
|
#address-cells = <1>;
|
|
|
#size-cells = <0>;
|
|
@@ -584,6 +620,116 @@
|
|
|
};
|
|
|
};
|
|
|
|
|
|
+ spi5: spi@44009000 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ compatible = "st,stm32h7-spi";
|
|
|
+ reg = <0x44009000 0x400>;
|
|
|
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&rcc SPI5_K>;
|
|
|
+ resets = <&rcc SPI5_R>;
|
|
|
+ dmas = <&dmamux1 85 0x400 0x05>,
|
|
|
+ <&dmamux1 86 0x400 0x05>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ dfsdm: dfsdm@4400d000 {
|
|
|
+ compatible = "st,stm32mp1-dfsdm";
|
|
|
+ reg = <0x4400d000 0x800>;
|
|
|
+ clocks = <&rcc DFSDM_K>;
|
|
|
+ clock-names = "dfsdm";
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ dfsdm0: filter@0 {
|
|
|
+ compatible = "st,stm32-dfsdm-adc";
|
|
|
+ #io-channel-cells = <1>;
|
|
|
+ reg = <0>;
|
|
|
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ dmas = <&dmamux1 101 0x400 0x01>;
|
|
|
+ dma-names = "rx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ dfsdm1: filter@1 {
|
|
|
+ compatible = "st,stm32-dfsdm-adc";
|
|
|
+ #io-channel-cells = <1>;
|
|
|
+ reg = <1>;
|
|
|
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ dmas = <&dmamux1 102 0x400 0x01>;
|
|
|
+ dma-names = "rx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ dfsdm2: filter@2 {
|
|
|
+ compatible = "st,stm32-dfsdm-adc";
|
|
|
+ #io-channel-cells = <1>;
|
|
|
+ reg = <2>;
|
|
|
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ dmas = <&dmamux1 103 0x400 0x01>;
|
|
|
+ dma-names = "rx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ dfsdm3: filter@3 {
|
|
|
+ compatible = "st,stm32-dfsdm-adc";
|
|
|
+ #io-channel-cells = <1>;
|
|
|
+ reg = <3>;
|
|
|
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ dmas = <&dmamux1 104 0x400 0x01>;
|
|
|
+ dma-names = "rx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ dfsdm4: filter@4 {
|
|
|
+ compatible = "st,stm32-dfsdm-adc";
|
|
|
+ #io-channel-cells = <1>;
|
|
|
+ reg = <4>;
|
|
|
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ dmas = <&dmamux1 91 0x400 0x01>;
|
|
|
+ dma-names = "rx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ dfsdm5: filter@5 {
|
|
|
+ compatible = "st,stm32-dfsdm-adc";
|
|
|
+ #io-channel-cells = <1>;
|
|
|
+ reg = <5>;
|
|
|
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ dmas = <&dmamux1 92 0x400 0x01>;
|
|
|
+ dma-names = "rx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ m_can1: can@4400e000 {
|
|
|
+ compatible = "bosch,m_can";
|
|
|
+ reg = <0x4400e000 0x400>, <0x44011000 0x2800>;
|
|
|
+ reg-names = "m_can", "message_ram";
|
|
|
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ interrupt-names = "int0", "int1";
|
|
|
+ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
|
|
|
+ clock-names = "hclk", "cclk";
|
|
|
+ bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ m_can2: can@4400f000 {
|
|
|
+ compatible = "bosch,m_can";
|
|
|
+ reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
|
|
|
+ reg-names = "m_can", "message_ram";
|
|
|
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ interrupt-names = "int0", "int1";
|
|
|
+ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
|
|
|
+ clock-names = "hclk", "cclk";
|
|
|
+ bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
dma1: dma@48000000 {
|
|
|
compatible = "st,stm32-dma";
|
|
|
reg = <0x48000000 0x400>;
|
|
@@ -647,6 +793,8 @@
|
|
|
reg = <0x0>;
|
|
|
interrupt-parent = <&adc>;
|
|
|
interrupts = <0>;
|
|
|
+ dmas = <&dmamux1 9 0x400 0x01>;
|
|
|
+ dma-names = "rx";
|
|
|
status = "disabled";
|
|
|
};
|
|
|
|
|
@@ -656,6 +804,8 @@
|
|
|
reg = <0x100>;
|
|
|
interrupt-parent = <&adc>;
|
|
|
interrupts = <1>;
|
|
|
+ dmas = <&dmamux1 10 0x400 0x01>;
|
|
|
+ dma-names = "rx";
|
|
|
status = "disabled";
|
|
|
};
|
|
|
};
|
|
@@ -675,7 +825,7 @@
|
|
|
};
|
|
|
|
|
|
usbotg_hs: usb-otg@49000000 {
|
|
|
- compatible = "st,stm32mp1-hsotg", "snps,dwc2";
|
|
|
+ compatible = "snps,dwc2";
|
|
|
reg = <0x49000000 0x10000>;
|
|
|
clocks = <&rcc USBO_K>;
|
|
|
clock-names = "otg";
|
|
@@ -686,7 +836,6 @@
|
|
|
g-np-tx-fifo-size = <32>;
|
|
|
g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
|
|
|
dr_mode = "otg";
|
|
|
- power-domains = <&pd_core>;
|
|
|
status = "disabled";
|
|
|
};
|
|
|
|
|
@@ -753,7 +902,7 @@
|
|
|
reg = <0x5000d000 0x400>;
|
|
|
};
|
|
|
|
|
|
- syscfg: system-config@50020000 {
|
|
|
+ syscfg: syscon@50020000 {
|
|
|
compatible = "st,stm32mp157-syscfg", "syscon";
|
|
|
reg = <0x50020000 0x400>;
|
|
|
};
|
|
@@ -853,6 +1002,18 @@
|
|
|
status = "disabled";
|
|
|
};
|
|
|
|
|
|
+ hash1: hash@54002000 {
|
|
|
+ compatible = "st,stm32f756-hash";
|
|
|
+ reg = <0x54002000 0x400>;
|
|
|
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&rcc HASH1>;
|
|
|
+ resets = <&rcc HASH1_R>;
|
|
|
+ dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
|
|
|
+ dma-names = "in";
|
|
|
+ dma-maxburst = <2>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
rng1: rng@54003000 {
|
|
|
compatible = "st,stm32-rng";
|
|
|
reg = <0x54003000 0x400>;
|
|
@@ -871,7 +1032,7 @@
|
|
|
dma-requests = <48>;
|
|
|
};
|
|
|
|
|
|
- qspi: qspi@58003000 {
|
|
|
+ qspi: spi@58003000 {
|
|
|
compatible = "st,stm32f469-qspi";
|
|
|
reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
|
|
|
reg-names = "qspi", "qspi_mm";
|
|
@@ -915,6 +1076,36 @@
|
|
|
status = "disabled";
|
|
|
};
|
|
|
|
|
|
+ stmmac_axi_config_0: stmmac-axi-config {
|
|
|
+ snps,wr_osr_lmt = <0x7>;
|
|
|
+ snps,rd_osr_lmt = <0x7>;
|
|
|
+ snps,blen = <0 0 0 0 16 8 4>;
|
|
|
+ };
|
|
|
+
|
|
|
+ ethernet0: ethernet@5800a000 {
|
|
|
+ compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
|
|
|
+ reg = <0x5800a000 0x2000>;
|
|
|
+ reg-names = "stmmaceth";
|
|
|
+ interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ interrupt-names = "macirq";
|
|
|
+ clock-names = "stmmaceth",
|
|
|
+ "mac-clk-tx",
|
|
|
+ "mac-clk-rx",
|
|
|
+ "ethstp",
|
|
|
+ "syscfg-clk";
|
|
|
+ clocks = <&rcc ETHMAC>,
|
|
|
+ <&rcc ETHTX>,
|
|
|
+ <&rcc ETHRX>,
|
|
|
+ <&rcc ETHSTP>,
|
|
|
+ <&rcc SYSCFG>;
|
|
|
+ st,syscon = <&syscfg 0x4>;
|
|
|
+ snps,mixed-burst;
|
|
|
+ snps,pbl = <2>;
|
|
|
+ snps,axi-config = <&stmmac_axi_config_0>;
|
|
|
+ snps,tso;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
usbh_ohci: usbh-ohci@5800c000 {
|
|
|
compatible = "generic-ohci";
|
|
|
reg = <0x5800c000 0x1000>;
|
|
@@ -955,6 +1146,14 @@
|
|
|
status = "disabled";
|
|
|
};
|
|
|
|
|
|
+ iwdg2: watchdog@5a002000 {
|
|
|
+ compatible = "st,stm32mp1-iwdg";
|
|
|
+ reg = <0x5a002000 0x400>;
|
|
|
+ clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
|
|
|
+ clock-names = "pclk", "lsi";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
usbphyc: usbphyc@5a006000 {
|
|
|
#address-cells = <1>;
|
|
|
#size-cells = <0>;
|
|
@@ -983,6 +1182,20 @@
|
|
|
status = "disabled";
|
|
|
};
|
|
|
|
|
|
+ spi6: spi@5c001000 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ compatible = "st,stm32h7-spi";
|
|
|
+ reg = <0x5c001000 0x400>;
|
|
|
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&rcc SPI6_K>;
|
|
|
+ resets = <&rcc SPI6_R>;
|
|
|
+ dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
|
|
|
+ <&mdma1 35 0x0 0x40002 0x0 0x0>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
i2c4: i2c@5c002000 {
|
|
|
compatible = "st,stm32f7-i2c";
|
|
|
reg = <0x5c002000 0x400>;
|
|
@@ -996,6 +1209,15 @@
|
|
|
status = "disabled";
|
|
|
};
|
|
|
|
|
|
+ rtc: rtc@5c004000 {
|
|
|
+ compatible = "st,stm32mp1-rtc";
|
|
|
+ reg = <0x5c004000 0x400>;
|
|
|
+ clocks = <&rcc RTCAPB>, <&rcc RTC>;
|
|
|
+ clock-names = "pclk", "rtc_ck";
|
|
|
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
bsec: nvmem@5c005000 {
|
|
|
compatible = "st,stm32mp15-bsec";
|
|
|
reg = <0x5c005000 0x400>;
|