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@@ -61,11 +61,63 @@ static int sandbox_swap_case_get_devfn(struct udevice *dev)
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return plat->devfn;
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}
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+static int sandbox_swap_case_use_ea(struct udevice *dev)
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+{
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+ return !!ofnode_get_property(dev->node, "use-ea", NULL);
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+}
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+
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+/* Please keep these macros in sync with ea_regs below */
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+#define PCI_CAP_ID_EA_SIZE (sizeof(ea_regs) + 4)
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+#define PCI_CAP_ID_EA_ENTRY_CNT 4
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+/* Hardcoded EA structure, excluding 1st DW. */
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+static const u32 ea_regs[] = {
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+ /* BEI=0, ES=2, BAR0 32b Base + 32b MaxOffset, I/O space */
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+ (2 << 8) | 2,
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+ PCI_CAP_EA_BASE_LO0,
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+ 0,
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+ /* BEI=1, ES=2, BAR1 32b Base + 32b MaxOffset */
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+ (1 << 4) | 2,
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+ PCI_CAP_EA_BASE_LO1,
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+ MEM_TEXT_SIZE - 1,
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+ /* BEI=2, ES=3, BAR2 64b Base + 32b MaxOffset */
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+ (2 << 4) | 3,
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+ PCI_CAP_EA_BASE_LO2 | PCI_EA_IS_64,
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+ PCI_CAP_EA_SIZE_LO,
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+ PCI_CAP_EA_BASE_HI2,
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+ /* BEI=4, ES=4, BAR4 64b Base + 64b MaxOffset */
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+ (4 << 4) | 4,
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+ PCI_CAP_EA_BASE_LO4 | PCI_EA_IS_64,
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+ PCI_CAP_EA_SIZE_LO | PCI_EA_IS_64,
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+ PCI_CAP_EA_BASE_HI4,
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+ PCI_CAP_EA_SIZE_HI,
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+};
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+
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+static int sandbox_swap_case_read_ea(struct udevice *emul, uint offset,
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+ ulong *valuep, enum pci_size_t size)
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+{
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+ u32 reg;
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+
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+ offset = offset - PCI_CAP_ID_EA_OFFSET - 4;
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+ reg = ea_regs[offset >> 2];
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+ reg >>= (offset % 4) * 8;
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+
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+ *valuep = reg;
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+ return 0;
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+}
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+
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static int sandbox_swap_case_read_config(struct udevice *emul, uint offset,
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ulong *valuep, enum pci_size_t size)
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{
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struct swap_case_platdata *plat = dev_get_platdata(emul);
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+ /*
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+ * The content of the EA capability structure is handled elsewhere to
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+ * keep the switch/case below sane
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+ */
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+ if (offset > PCI_CAP_ID_EA_OFFSET + PCI_CAP_LIST_NEXT &&
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+ offset < PCI_CAP_ID_EA_OFFSET + PCI_CAP_ID_EA_SIZE)
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+ return sandbox_swap_case_read_ea(emul, offset, valuep, size);
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+
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switch (offset) {
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case PCI_COMMAND:
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*valuep = plat->command;
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@@ -134,9 +186,21 @@ static int sandbox_swap_case_read_config(struct udevice *emul, uint offset,
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*valuep = PCI_CAP_ID_MSIX_OFFSET;
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break;
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case PCI_CAP_ID_MSIX_OFFSET:
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- *valuep = PCI_CAP_ID_MSIX;
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+ if (sandbox_swap_case_use_ea(emul))
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+ *valuep = (PCI_CAP_ID_EA_OFFSET << 8) | PCI_CAP_ID_MSIX;
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+ else
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+ *valuep = PCI_CAP_ID_MSIX;
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break;
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case PCI_CAP_ID_MSIX_OFFSET + PCI_CAP_LIST_NEXT:
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+ if (sandbox_swap_case_use_ea(emul))
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+ *valuep = PCI_CAP_ID_EA_OFFSET;
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+ else
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+ *valuep = 0;
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+ break;
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+ case PCI_CAP_ID_EA_OFFSET:
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+ *valuep = (PCI_CAP_ID_EA_ENTRY_CNT << 16) | PCI_CAP_ID_EA;
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+ break;
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+ case PCI_CAP_ID_EA_OFFSET + PCI_CAP_LIST_NEXT:
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*valuep = 0;
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break;
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case PCI_EXT_CAP_ID_ERR_OFFSET:
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@@ -257,6 +321,9 @@ int sandbox_swap_case_write_io(struct udevice *dev, unsigned int addr,
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return 0;
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}
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+static int pci_ea_bar2_magic = PCI_EA_BAR2_MAGIC;
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+static int pci_ea_bar4_magic = PCI_EA_BAR4_MAGIC;
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+
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static int sandbox_swap_case_map_physmem(struct udevice *dev,
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phys_addr_t addr, unsigned long *lenp, void **ptrp)
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{
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@@ -265,9 +332,42 @@ static int sandbox_swap_case_map_physmem(struct udevice *dev,
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int barnum;
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int ret;
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+ if (sandbox_swap_case_use_ea(dev)) {
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+ /*
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+ * only support mapping base address in EA test for now, we
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+ * don't handle mapping an offset inside a BAR. Seems good
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+ * enough for the current test.
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+ */
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+ switch (addr) {
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+ case (phys_addr_t)PCI_CAP_EA_BASE_LO0:
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+ *ptrp = &priv->op;
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+ *lenp = 4;
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+ break;
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+ case (phys_addr_t)PCI_CAP_EA_BASE_LO1:
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+ *ptrp = priv->mem_text;
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+ *lenp = barinfo[1].size - 1;
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+ break;
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+ case (phys_addr_t)((PCI_CAP_EA_BASE_HI2 << 32) |
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+ PCI_CAP_EA_BASE_LO2):
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+ *ptrp = &pci_ea_bar2_magic;
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+ *lenp = PCI_CAP_EA_SIZE_LO;
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+ break;
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+ case (phys_addr_t)((PCI_CAP_EA_BASE_HI4 << 32) |
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+ PCI_CAP_EA_BASE_LO4):
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+ *ptrp = &pci_ea_bar4_magic;
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+ *lenp = (PCI_CAP_EA_SIZE_HI << 32) |
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+ PCI_CAP_EA_SIZE_LO;
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+ break;
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+ default:
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+ return -ENOENT;
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+ }
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+ return 0;
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+ }
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+
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ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset);
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if (ret)
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return ret;
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+
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if (barnum == 1) {
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*ptrp = priv->mem_text + offset;
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avail = barinfo[1].size - offset;
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