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@@ -560,6 +560,25 @@ static void __prci_ddr_release_reset(struct __prci_data *pd)
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asm volatile ("nop");
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}
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+/**
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+ * __prci_ethernet_release_reset() - Release ethernet reset
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+ * @pd: struct __prci_data * for the PRCI containing the Ethernet CLK mux reg
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+ *
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+ */
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+static void __prci_ethernet_release_reset(struct __prci_data *pd)
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+{
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+ u32 v;
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+
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+ /* Release GEMGXL reset */
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+ v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET);
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+ v |= PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK;
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+ __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd);
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+
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+ /* Procmon => core clock */
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+ __prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET,
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+ pd);
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+}
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+
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/*
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* PRCI integration data for each WRPLL instance
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*/
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@@ -580,6 +599,7 @@ static struct __prci_wrpll_data __prci_ddrpll_data = {
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static struct __prci_wrpll_data __prci_gemgxlpll_data = {
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.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
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+ .release_reset = __prci_ethernet_release_reset,
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};
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/*
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