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@@ -266,6 +266,141 @@ static void ft_hs_fixups(void *fdt, bd_t *bd)
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}
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#endif /* #ifdef CONFIG_TI_SECURE_DEVICE */
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+#if defined(CONFIG_TARGET_DRA7XX_EVM) || defined(CONFIG_TARGET_AM57XX_EVM)
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+#define OPP_DSP_CLK_NUM 3
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+#define OPP_IVA_CLK_NUM 2
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+#define OPP_GPU_CLK_NUM 2
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+
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+const char *dra7_opp_dsp_clk_names[OPP_DSP_CLK_NUM] = {
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+ "dpll_dsp_ck",
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+ "dpll_dsp_m2_ck",
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+ "dpll_dsp_m3x2_ck",
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+};
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+
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+const char *dra7_opp_iva_clk_names[OPP_IVA_CLK_NUM] = {
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+ "dpll_iva_ck",
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+ "dpll_iva_m2_ck",
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+};
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+
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+const char *dra7_opp_gpu_clk_names[OPP_GPU_CLK_NUM] = {
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+ "dpll_gpu_ck",
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+ "dpll_gpu_m2_ck",
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+};
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+
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+/* DSPEVE voltage domain */
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+u32 dra7_opp_dsp_clk_rates[NUM_OPPS][OPP_DSP_CLK_NUM] = {
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+ {}, /*OPP_LOW */
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+ {600000000, 600000000, 400000000}, /* OPP_NOM */
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+ {700000000, 700000000, 466666667}, /* OPP_OD */
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+ {750000000, 750000000, 500000000}, /* OPP_HIGH */
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+};
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+
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+/* IVA voltage domain */
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+u32 dra7_opp_iva_clk_rates[NUM_OPPS][OPP_IVA_CLK_NUM] = {
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+ {}, /* OPP_LOW */
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+ {1165000000, 388333334}, /* OPP_NOM */
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+ {860000000, 430000000}, /* OPP_OD */
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+ {1064000000, 532000000}, /* OPP_HIGH */
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+};
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+
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+/* GPU voltage domain */
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+u32 dra7_opp_gpu_clk_rates[NUM_OPPS][OPP_GPU_CLK_NUM] = {
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+ {}, /* OPP_LOW */
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+ {1277000000, 425666667}, /* OPP_NOM */
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+ {1000000000, 500000000}, /* OPP_OD */
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+ {1064000000, 532000000}, /* OPP_HIGH */
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+};
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+
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+static int ft_fixup_clocks(void *fdt, const char **names, u32 *rates, int num)
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+{
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+ int offs, node_offs, ret, i;
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+ uint32_t phandle;
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+
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+ offs = fdt_path_offset(fdt, "/ocp/l4@4a000000/cm_core_aon@5000/clocks");
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+ if (offs < 0) {
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+ debug("Could not find cm_core_aon clocks node path offset : %s\n",
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+ fdt_strerror(offs));
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+ return offs;
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+ }
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+
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+ for (i = 0; i < num; i++) {
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+ node_offs = fdt_subnode_offset(fdt, offs, names[i]);
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+ if (node_offs < 0) {
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+ debug("Could not find clock sub-node %s: %s\n",
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+ names[i], fdt_strerror(node_offs));
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+ return offs;
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+ }
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+
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+ phandle = fdt_get_phandle(fdt, node_offs);
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+ if (!phandle) {
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+ debug("Could not find phandle for clock %s\n",
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+ names[i]);
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+ return -1;
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+ }
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+
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+ ret = fdt_setprop_u32(fdt, node_offs, "assigned-clocks",
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+ phandle);
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+ if (ret < 0) {
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+ debug("Could not add assigned-clocks property to clock node %s: %s\n",
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+ names[i], fdt_strerror(ret));
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+ return ret;
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+ }
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+
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+ ret = fdt_setprop_u32(fdt, node_offs, "assigned-clock-rates",
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+ rates[i]);
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+ if (ret < 0) {
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+ debug("Could not add assigned-clock-rates property to clock node %s: %s\n",
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+ names[i], fdt_strerror(ret));
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+ return ret;
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+ }
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+ }
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+
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+ return 0;
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+}
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+
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+static void ft_opp_clock_fixups(void *fdt, bd_t *bd)
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+{
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+ const char **clk_names;
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+ u32 *clk_rates;
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+ int ret;
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+
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+ if (!is_dra72x() && !is_dra7xx())
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+ return;
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+
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+ /* fixup DSP clocks */
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+ clk_names = dra7_opp_dsp_clk_names;
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+ clk_rates = dra7_opp_dsp_clk_rates[get_voltrail_opp(VOLT_EVE)];
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+ ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_DSP_CLK_NUM);
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+ if (ret) {
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+ printf("ft_fixup_clocks failed for DSP voltage domain: %s\n",
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+ fdt_strerror(ret));
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+ return;
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+ }
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+
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+ /* fixup IVA clocks */
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+ clk_names = dra7_opp_iva_clk_names;
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+ clk_rates = dra7_opp_iva_clk_rates[get_voltrail_opp(VOLT_IVA)];
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+ ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_IVA_CLK_NUM);
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+ if (ret) {
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+ printf("ft_fixup_clocks failed for IVA voltage domain: %s\n",
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+ fdt_strerror(ret));
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+ return;
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+ }
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+
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+ /* fixup GPU clocks */
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+ clk_names = dra7_opp_gpu_clk_names;
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+ clk_rates = dra7_opp_gpu_clk_rates[get_voltrail_opp(VOLT_GPU)];
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+ ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_GPU_CLK_NUM);
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+ if (ret) {
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+ printf("ft_fixup_clocks failed for GPU voltage domain: %s\n",
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+ fdt_strerror(ret));
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+ return;
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+ }
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+}
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+#else
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+static void ft_opp_clock_fixups(void *fdt, bd_t *bd) { }
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+#endif /* CONFIG_TARGET_DRA7XX_EVM || CONFIG_TARGET_AM57XX_EVM */
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+
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/*
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* Place for general cpu/SoC FDT fixups. Board specific
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* fixups should remain in the board files which is where
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@@ -274,4 +409,5 @@ static void ft_hs_fixups(void *fdt, bd_t *bd)
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void ft_cpu_setup(void *fdt, bd_t *bd)
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{
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ft_hs_fixups(fdt, bd);
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+ ft_opp_clock_fixups(fdt, bd);
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}
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