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@@ -0,0 +1,88 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * (C) Copyright 2019
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+ * Angelo Dureghello <angleo@sysam.it>
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+ *
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+ * CPU specific dspi routines
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+ */
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+
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+#include <common.h>
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+#include <asm/immap.h>
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+#include <asm/io.h>
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+
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+#ifdef CONFIG_CF_DSPI
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+void dspi_chip_select(int cs)
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+{
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+ struct gpio *gpio = (struct gpio *)MMAP_GPIO;
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+
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+#ifdef CONFIG_MCF5445x
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+ switch (cs) {
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+ case 0:
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+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
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+ setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
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+ break;
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+ case 1:
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+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
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+ setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
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+ break;
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+ case 2:
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+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
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+ setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
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+ break;
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+ case 3:
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+ clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
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+ setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
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+ break;
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+ case 5:
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+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
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+ setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
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+ break;
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+ }
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+#endif
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+#ifdef CONFIG_MCF5441x
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+ switch (cs) {
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+ case 0:
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+ clrbits_8(&gpio->par_dspi0,
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+ ~GPIO_PAR_DSPI0_PCS0_MASK);
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+ setbits_8(&gpio->par_dspi0,
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+ GPIO_PAR_DSPI0_PCS0_DSPI0PCS0);
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+ break;
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+ case 1:
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+ clrbits_8(&gpio->par_dspiow,
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+ GPIO_PAR_DSPIOW_DSPI0PSC1);
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+ setbits_8(&gpio->par_dspiow,
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+ GPIO_PAR_DSPIOW_DSPI0PSC1);
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+ break;
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+ }
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+#endif
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+}
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+
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+void dspi_chip_unselect(int cs)
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+{
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+ struct gpio *gpio = (struct gpio *)MMAP_GPIO;
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+
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+#ifdef CONFIG_MCF5445x
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+ switch (cs) {
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+ case 0:
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+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
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+ break;
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+ case 1:
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+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
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+ break;
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+ case 2:
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+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
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+ break;
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+ case 3:
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+ clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
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+ break;
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+ case 5:
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+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
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+ break;
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+ }
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+#endif
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+#ifdef CONFIG_MCF5441x
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+ if (cs == 1)
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+ clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
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+#endif
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+}
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+#endif /* CONFIG_CF_DSPI */
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