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@@ -30,18 +30,6 @@
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#define CCM_CCMR_CONFIG 0x003F4208
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#define ESDCTL_DDR2_CONFIG 0x007FFC3F
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-#define ESDCTL_0x92220000 0x92220000
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-#define ESDCTL_0xA2220000 0xA2220000
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-#define ESDCTL_0xB2220000 0xB2220000
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-#define ESDCTL_0x82228080 0x82228080
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-#define ESDCTL_DDR2_EMR2 0x04000000
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-#define ESDCTL_DDR2_EMR3 0x06000000
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-#define ESDCTL_PRECHARGE 0x00000400
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-#define ESDCTL_DDR2_EN_DLL 0x02000400
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-#define ESDCTL_DDR2_RESET_DLL 0x00000333
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-#define ESDCTL_DDR2_MR 0x00000233
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-#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
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-#define ESDCTL_DELAY_LINE5 0x00F49F00
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static inline void dram_wait(unsigned int count)
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{
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@@ -61,83 +49,6 @@ int dram_init(void)
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return 0;
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}
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-static void board_setup_sdram_bank(u32 start_address)
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-
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-{
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- struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
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- u32 *cfg_reg, *ctl_reg;
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- u32 val;
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-
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- switch (start_address) {
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- case CSD0_BASE_ADDR:
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- cfg_reg = &esdc->esdcfg0;
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- ctl_reg = &esdc->esdctl0;
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- break;
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- case CSD1_BASE_ADDR:
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- cfg_reg = &esdc->esdcfg1;
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- ctl_reg = &esdc->esdctl1;
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- break;
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- default:
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- return;
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- }
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-
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- /* Initialize MISC register for DDR2 */
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- val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
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- ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
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- writel(val, &esdc->esdmisc);
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- val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
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- writel(val, &esdc->esdmisc);
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-
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- /*
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- * according to DDR2 specs, wait a while before
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- * the PRECHARGE_ALL command
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- */
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- dram_wait(0x20000);
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-
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- /* Load DDR2 config and timing */
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- writel(ESDCTL_DDR2_CONFIG, cfg_reg);
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-
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- /* Precharge ALL */
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- writel(ESDCTL_0x92220000,
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- ctl_reg);
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- writel(0xda, start_address + ESDCTL_PRECHARGE);
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-
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- /* Load mode */
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- writel(ESDCTL_0xB2220000,
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- ctl_reg);
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- writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
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- writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
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- writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
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- writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
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-
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- /* Precharge ALL */
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- writel(ESDCTL_0x92220000,
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- ctl_reg);
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- writel(0xda, start_address + ESDCTL_PRECHARGE);
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-
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- /* Set mode auto refresh : at least two refresh are required */
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- writel(ESDCTL_0xA2220000,
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- ctl_reg);
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- writel(0xda, start_address);
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- writel(0xda, start_address);
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-
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- writel(ESDCTL_0xB2220000,
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- ctl_reg);
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- writeb(0xda, start_address + ESDCTL_DDR2_MR);
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- writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
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-
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- /* OCD mode exit */
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- writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
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-
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- /* Set normal mode */
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- writel(ESDCTL_0x82228080,
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- ctl_reg);
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-
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- dram_wait(0x20000);
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-
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- /* Do not set delay lines, only for MDDR */
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-}
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-
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static void board_setup_sdram(void)
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{
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struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
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@@ -146,7 +57,9 @@ static void board_setup_sdram(void)
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writel(0x2000, &esdc->esdctl0);
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writel(0x2000, &esdc->esdctl1);
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- board_setup_sdram_bank(CSD0_BASE_ADDR);
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+
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+ mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
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+ 13, 10, 2, 0x8080);
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}
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static void setup_iomux_uart3(void)
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