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@@ -319,7 +319,8 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
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esdhc_write32(®s->cmdarg, cmd->cmdarg);
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#if defined(CONFIG_FSL_USDHC)
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esdhc_write32(®s->mixctrl,
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- (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F));
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+ (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
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+ | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
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esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
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#else
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esdhc_write32(®s->xfertyp, xfertyp);
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@@ -442,7 +443,7 @@ static void set_sysctl(struct mmc *mmc, uint clock)
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if ((sdhc_clk / (div * pre_div)) <= clock)
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break;
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- pre_div >>= 1;
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+ pre_div >>= mmc->ddr_mode ? 2 : 1;
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div -= 1;
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clk = (pre_div << 8) | (div << 4);
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@@ -601,6 +602,9 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
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}
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cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
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+#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
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+ cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz;
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+#endif
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if (cfg->max_bus_width > 0) {
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if (cfg->max_bus_width < 8)
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