Browse Source

Merge branch '2019-01-25-master-imports'

- snapdragon 820c improvements
- poplar updates
- DFU + SPL cleanups
- Improve the mediatek mmc driver
- Other minor cleanups / improvements
Tom Rini 5 years ago
parent
commit
0da9025508
61 changed files with 846 additions and 245 deletions
  1. 1 1
      MAINTAINERS
  2. 1 1
      Makefile
  3. 0 3
      README
  4. 9 1
      arch/arm/dts/dragonboard820c-uboot.dtsi
  5. 22 7
      arch/arm/dts/dragonboard820c.dts
  6. 64 11
      arch/arm/dts/hi3798cv200-poplar.dts
  7. 217 4
      arch/arm/dts/hi3798cv200.dtsi
  8. 98 0
      arch/arm/dts/poplar-pinctrl.dtsi
  9. 0 12
      arch/arm/include/asm/arch-hi3798cv200/dwmmc.h
  10. 0 1
      arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h
  11. 15 0
      arch/arm/mach-omap2/Kconfig
  12. 0 15
      arch/arm/mach-omap2/am33xx/Kconfig
  13. 1 1
      arch/arm/mach-omap2/boot-common.c
  14. 3 2
      arch/arm/mach-snapdragon/Makefile
  15. 34 0
      arch/arm/mach-snapdragon/clock-apq8096.c
  16. 9 0
      arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h
  17. 56 0
      arch/arm/mach-snapdragon/pinctrl-apq8096.c
  18. 3 3
      arch/arm/mach-snapdragon/pinctrl-snapdragon.c
  19. 1 0
      arch/arm/mach-snapdragon/pinctrl-snapdragon.h
  20. 3 3
      arch/arm/mach-stm32mp/config.mk
  21. 1 1
      arch/arm/mach-zynqmp/spl.c
  22. 0 12
      board/hisilicon/poplar/poplar.c
  23. 1 1
      cmd/ximg.c
  24. 1 2
      common/Makefile
  25. 1 1
      common/cli.c
  26. 3 3
      common/spl/Kconfig
  27. 1 1
      common/spl/Makefile
  28. 2 2
      common/spl/spl_ram.c
  29. 1 0
      configs/apalis_imx6_defconfig
  30. 1 0
      configs/apalis_imx6_nospl_com_defconfig
  31. 1 0
      configs/apalis_imx6_nospl_it_defconfig
  32. 0 2
      configs/bcm968380gerg_ram_defconfig
  33. 1 0
      configs/chiliboard_defconfig
  34. 1 0
      configs/colibri_imx6_defconfig
  35. 1 0
      configs/colibri_imx6_nospl_defconfig
  36. 2 0
      configs/dragonboard820c_defconfig
  37. 1 0
      configs/sama5d3_xplained_mmc_defconfig
  38. 1 2
      drivers/Makefile
  39. 6 6
      drivers/dfu/Makefile
  40. 1 0
      drivers/misc/i2c_eeprom.c
  41. 42 1
      drivers/mmc/fsl_esdhc.c
  42. 1 0
      drivers/mmc/hi6220_dw_mmc.c
  43. 13 13
      drivers/mmc/mtk-sd.c
  44. 1 1
      drivers/usb/gadget/Makefile
  45. 2 2
      env/common.c
  46. 19 6
      env/env.c
  47. 0 4
      include/configs/apalis_imx6.h
  48. 0 4
      include/configs/colibri_imx6.h
  49. 1 1
      include/configs/dra7xx_evm.h
  50. 1 1
      include/configs/ti_omap5_common.h
  51. 2 2
      include/configs/xilinx_zynqmp.h
  52. 5 5
      include/dfu.h
  53. 36 20
      include/dt-bindings/clock/histb-clock.h
  54. 74 0
      include/dt-bindings/pinctrl/hisi.h
  55. 1 0
      include/fsl_esdhc.h
  56. 1 1
      include/lmb.h
  57. 1 2
      lib/hashtable.c
  58. 43 45
      lib/lmb.c
  59. 1 1
      net/tftp.c
  60. 11 11
      test/lib/lmb.c
  61. 27 27
      tools/dtoc/test_dtoc.py

+ 1 - 1
MAINTAINERS

@@ -267,7 +267,7 @@ M:	Christophe Kerello <christophe.kerello@st.com>
 M:	Patrice Chotard <patrice.chotard@st.com>
 L:	uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
 S:	Maintained
-F:	arch/arm/mach-stm32mp
+F:	arch/arm/mach-stm32mp/
 F:	drivers/clk/clk_stm32mp1.c
 F:	drivers/i2c/stm32f7_i2c.c
 F:	drivers/misc/stm32mp_fuse.c

+ 1 - 1
Makefile

@@ -1795,7 +1795,7 @@ distclean: mrproper
 		-o -name '.*.rej' -o -name '*%' -o -name 'core' \
 		-o -name '*.pyc' \) \
 		-type f -print | xargs rm -f
-	@rm -f boards.cfg
+	@rm -f boards.cfg CHANGELOG
 
 backup:
 	F=`basename $(srctree)` ; cd .. ; \

+ 0 - 3
README

@@ -1146,9 +1146,6 @@ The following options need to be configured:
 		CONFIG_DFU_OVER_USB
 		This enables the USB portion of the DFU USB class
 
-		CONFIG_DFU_MMC
-		This enables support for exposing (e)MMC devices via DFU.
-
 		CONFIG_DFU_NAND
 		This enables support for exposing NAND devices via DFU.
 

+ 9 - 1
arch/arm/dts/dragonboard820c-uboot.dtsi

@@ -13,14 +13,22 @@
 	soc {
 		u-boot,dm-pre-reloc;
 
+		qcom,tlmm@1010000 {
+			u-boot,dm-pre-reloc;
+
+			uart {
+				u-boot,dm-pre-reloc;
+			};
+		};
+
 		clock-controller@300000 {
 			u-boot,dm-pre-reloc;
 		};
 
 		serial@75b0000 {
 			u-boot,dm-pre-reloc;
-			};
 		};
+	};
 };
 
 &pm8994_pon {

+ 22 - 7
arch/arm/dts/dragonboard820c.dts

@@ -8,6 +8,7 @@
 /dts-v1/;
 
 #include "skeleton64.dtsi"
+#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
 
 / {
 	model = "Qualcomm Technologies, Inc. DB820c";
@@ -16,7 +17,7 @@
 	#size-cells = <2>;
 
 	aliases {
-		serial0 = &blsp2_uart1;
+		serial0 = &blsp2_uart2;
 	};
 
 	chosen {
@@ -63,18 +64,32 @@
 			reg = <0x300000 0x90000>;
 		};
 
-		blsp2_uart1: serial@75b0000 {
+		pinctrl: qcom,tlmm@1010000 {
+			compatible = "qcom,tlmm-apq8096";
+			reg = <0x1010000 0x400000>;
+
+			blsp8_uart: uart {
+				function = "blsp_uart8";
+				pins = "GPIO_4", "GPIO_5";
+				drive-strength = <DRIVE_STRENGTH_8MA>;
+				bias-disable;
+			};
+		};
+
+		blsp2_uart2: serial@75b0000 {
 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 			reg = <0x75b0000 0x1000>;
 			clock = <&gcc 4>;
+			pinctrl-names = "uart";
+			pinctrl-0 = <&blsp8_uart>;
 		};
 
 		sdhc2: sdhci@74a4900 {
-			 compatible = "qcom,sdhci-msm-v4";
-			 reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
-			 index = <0x0>;
-			 bus-width = <4>;
-			 clock = <&gcc 0>;
+			compatible = "qcom,sdhci-msm-v4";
+			reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
+			index = <0x0>;
+			bus-width = <4>;
+			clock = <&gcc 0>;
 			clock-frequency = <200000000>;
 		 };
 

+ 64 - 11
arch/arm/dts/hi3798cv200-poplar.dts

@@ -1,14 +1,17 @@
-// SPDX-License-Identifier: GPL-2.0
 /*
  * DTS File for HiSilicon Poplar Development Board
  *
  * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
+ * Released under the GPLv2 only.
+ * SPDX-License-Identifier: GPL-2.0
  */
 
 /dts-v1/;
 
 #include <dt-bindings/gpio/gpio.h>
 #include "hi3798cv200.dtsi"
+#include "poplar-pinctrl.dtsi"
 
 / {
 	model = "HiSilicon Poplar Development Board";
@@ -28,6 +31,13 @@
 		reg = <0x0 0x0 0x0 0x80000000>;
 	};
 
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
+
 	leds {
 		compatible = "gpio-leds";
 
@@ -59,6 +69,33 @@
 			default-state = "off";
 		};
 	};
+
+	reg_pcie: regulator-pcie {
+		compatible = "regulator-fixed";
+		regulator-name = "3V3_PCIE0";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio6 7 0>;
+		enable-active-high;
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&emmc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_pins_1 &emmc_pins_2
+		     &emmc_pins_3 &emmc_pins_4>;
+	fifo-depth = <256>;
+	clock-frequency = <200000000>;
+	cap-mmc-highspeed;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	non-removable;
+	bus-width = <8>;
+	status = "okay";
 };
 
 &gmac1 {
@@ -76,17 +113,17 @@
 
 &gpio1 {
 	status = "okay";
-	gpio-line-names = "LS-GPIO-E",	"",
+	gpio-line-names = "GPIO-E",	"",
 			  "",		"",
-			  "",		"LS-GPIO-F",
-			  "",		"LS-GPIO-J";
+			  "",		"GPIO-F",
+			  "",		"GPIO-J";
 };
 
 &gpio2 {
 	status = "okay";
-	gpio-line-names = "LS-GPIO-H",	"LS-GPIO-I",
-			  "LS-GPIO-L",	"LS-GPIO-G",
-			  "LS-GPIO-K",	"",
+	gpio-line-names = "GPIO-H",	"GPIO-I",
+			  "GPIO-L",	"GPIO-G",
+			  "GPIO-K",	"",
 			  "",		"";
 };
 
@@ -94,15 +131,15 @@
 	status = "okay";
 	gpio-line-names = "",		"",
 			  "",		"",
-			  "LS-GPIO-C",	"",
-			  "",		"LS-GPIO-B";
+			  "GPIO-C",	"",
+			  "",		"GPIO-B";
 };
 
 &gpio4 {
 	status = "okay";
 	gpio-line-names = "",		"",
 			  "",		"",
-			  "",		"LS-GPIO-D",
+			  "",		"GPIO-D",
 			  "",		"";
 };
 
@@ -110,7 +147,7 @@
 	status = "okay";
 	gpio-line-names = "",		"USER-LED-1",
 			  "USER-LED-2",	"",
-			  "",		"LS-GPIO-A",
+			  "",		"GPIO-A",
 			  "",		"";
 };
 
@@ -144,6 +181,22 @@
 	status = "okay";
 };
 
+&ohci {
+	status = "okay";
+};
+
+&pcie {
+	reset-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
+	vpcie-supply = <&reg_pcie>;
+	status = "okay";
+};
+
+&sd0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	status = "okay";
+};
+
 &spi0 {
 	status = "okay";
 	label = "LS-SPI0";

+ 217 - 4
arch/arm/dts/hi3798cv200.dtsi

@@ -1,12 +1,16 @@
-// SPDX-License-Identifier: GPL-2.0
 /*
  * DTS File for HiSilicon Hi3798cv200 SoC.
  *
  * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
+ * Released under the GPLv2 only.
+ * SPDX-License-Identifier: GPL-2.0
  */
 
 #include <dt-bindings/clock/histb-clock.h>
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy.h>
 #include <dt-bindings/reset/ti-syscon.h>
 
 / {
@@ -104,6 +108,113 @@
 			#reset-cells = <2>;
 		};
 
+		perictrl: peripheral-controller@8a20000 {
+			compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
+				     "simple-mfd";
+			reg = <0x8a20000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x8a20000 0x1000>;
+
+			usb2_phy1: usb2-phy@120 {
+				compatible = "hisilicon,hi3798cv200-usb2-phy";
+				reg = <0x120 0x4>;
+				clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
+				resets = <&crg 0xbc 4>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				usb2_phy1_port0: phy@0 {
+					reg = <0>;
+					#phy-cells = <0>;
+					resets = <&crg 0xbc 8>;
+				};
+
+				usb2_phy1_port1: phy@1 {
+					reg = <1>;
+					#phy-cells = <0>;
+					resets = <&crg 0xbc 9>;
+				};
+			};
+
+			usb2_phy2: usb2-phy@124 {
+				compatible = "hisilicon,hi3798cv200-usb2-phy";
+				reg = <0x124 0x4>;
+				clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
+				resets = <&crg 0xbc 6>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				usb2_phy2_port0: phy@0 {
+					reg = <0>;
+					#phy-cells = <0>;
+					resets = <&crg 0xbc 10>;
+				};
+			};
+
+			combphy0: phy@850 {
+				compatible = "hisilicon,hi3798cv200-combphy";
+				reg = <0x850 0x8>;
+				#phy-cells = <1>;
+				clocks = <&crg HISTB_COMBPHY0_CLK>;
+				resets = <&crg 0x188 4>;
+				assigned-clocks = <&crg HISTB_COMBPHY0_CLK>;
+				assigned-clock-rates = <100000000>;
+				hisilicon,fixed-mode = <PHY_TYPE_USB3>;
+			};
+
+			combphy1: phy@858 {
+				compatible = "hisilicon,hi3798cv200-combphy";
+				reg = <0x858 0x8>;
+				#phy-cells = <1>;
+				clocks = <&crg HISTB_COMBPHY1_CLK>;
+				resets = <&crg 0x188 12>;
+				assigned-clocks = <&crg HISTB_COMBPHY1_CLK>;
+				assigned-clock-rates = <100000000>;
+				hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
+			};
+		};
+
+		pmx0: pinconf@8a21000 {
+			compatible = "pinconf-single";
+			reg = <0x8a21000 0x180>;
+			pinctrl-single,register-width = <32>;
+			pinctrl-single,function-mask = <7>;
+			pinctrl-single,gpio-range = <
+				&range 0  8 2  /* GPIO 0 */
+				&range 8  1 0  /* GPIO 1 */
+				&range 9  4 2
+				&range 13 1 0
+				&range 14 1 1
+				&range 15 1 0
+				&range 16 5 0  /* GPIO 2 */
+				&range 21 3 1
+				&range 24 4 1  /* GPIO 3 */
+				&range 28 2 2
+				&range 86 1 1
+				&range 87 1 0
+				&range 30 4 2  /* GPIO 4 */
+				&range 34 3 0
+				&range 37 1 2
+				&range 38 3 2  /* GPIO 6 */
+				&range 41 5 0
+				&range 46 8 1  /* GPIO 7 */
+				&range 54 8 1  /* GPIO 8 */
+				&range 64 7 1  /* GPIO 9 */
+				&range 71 1 0
+				&range 72 6 1  /* GPIO 10 */
+				&range 78 1 0
+				&range 79 1 1
+				&range 80 6 1  /* GPIO 11 */
+				&range 70 2 1
+				&range 88 8 0  /* GPIO 12 */
+			>;
+
+			range: gpio-range {
+				#pinctrl-single,gpio-range-cells = <3>;
+			};
+		};
+
 		uart0: serial@8b00000 {
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x8b00000 0x1000>;
@@ -190,13 +301,30 @@
 			status = "disabled";
 		};
 
-		emmc: mmc@9830000 {
+		sd0: mmc@9820000 {
 			compatible = "snps,dw-mshc";
+			reg = <0x9820000 0x10000>;
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg HISTB_SDIO0_CIU_CLK>,
+				 <&crg HISTB_SDIO0_BIU_CLK>;
+			clock-names = "ciu", "biu";
+			resets = <&crg 0x9c 4>;
+			reset-names = "reset";
+			status = "disabled";
+		};
+
+		emmc: mmc@9830000 {
+			compatible = "hisilicon,hi3798cv200-dw-mshc";
 			reg = <0x9830000 0x10000>;
 			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&crg HISTB_MMC_CIU_CLK>,
-				 <&crg HISTB_MMC_BIU_CLK>;
-			clock-names = "ciu", "biu";
+				 <&crg HISTB_MMC_BIU_CLK>,
+				 <&crg HISTB_MMC_SAMPLE_CLK>,
+				 <&crg HISTB_MMC_DRV_CLK>;
+			clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
+			resets = <&crg 0xa0 4>;
+			reset-names = "reset";
+			status = "disabled";
 		};
 
 		gpio0: gpio@8b20000 {
@@ -207,6 +335,7 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			gpio-ranges = <&pmx0 0 0 8>;
 			clocks = <&crg HISTB_APB_CLK>;
 			clock-names = "apb_pclk";
 			status = "disabled";
@@ -220,6 +349,13 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			gpio-ranges = <
+				&pmx0 0 8 1
+				&pmx0 1 9 4
+				&pmx0 5 13 1
+				&pmx0 6 14 1
+				&pmx0 7 15 1
+			>;
 			clocks = <&crg HISTB_APB_CLK>;
 			clock-names = "apb_pclk";
 			status = "disabled";
@@ -233,6 +369,7 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			gpio-ranges = <&pmx0 0 16 5 &pmx0 5 21 3>;
 			clocks = <&crg HISTB_APB_CLK>;
 			clock-names = "apb_pclk";
 			status = "disabled";
@@ -246,6 +383,12 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			gpio-ranges = <
+				&pmx0 0 24 4
+				&pmx0 4 28 2
+				&pmx0 6 86 1
+				&pmx0 7 87 1
+			>;
 			clocks = <&crg HISTB_APB_CLK>;
 			clock-names = "apb_pclk";
 			status = "disabled";
@@ -259,6 +402,7 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>;
 			clocks = <&crg HISTB_APB_CLK>;
 			clock-names = "apb_pclk";
 			status = "disabled";
@@ -285,6 +429,7 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			gpio-ranges = <&pmx0 0 38 3 &pmx0 0 41 5>;
 			clocks = <&crg HISTB_APB_CLK>;
 			clock-names = "apb_pclk";
 			status = "disabled";
@@ -298,6 +443,7 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			gpio-ranges = <&pmx0 0 46 8>;
 			clocks = <&crg HISTB_APB_CLK>;
 			clock-names = "apb_pclk";
 			status = "disabled";
@@ -311,6 +457,7 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			gpio-ranges = <&pmx0 0 54 8>;
 			clocks = <&crg HISTB_APB_CLK>;
 			clock-names = "apb_pclk";
 			status = "disabled";
@@ -324,6 +471,7 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>;
 			clocks = <&crg HISTB_APB_CLK>;
 			clock-names = "apb_pclk";
 			status = "disabled";
@@ -337,6 +485,7 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>;
 			clocks = <&crg HISTB_APB_CLK>;
 			clock-names = "apb_pclk";
 			status = "disabled";
@@ -350,6 +499,7 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			gpio-ranges = <&pmx0 0 80 6 &pmx0 6 70 2>;
 			clocks = <&crg HISTB_APB_CLK>;
 			clock-names = "apb_pclk";
 			status = "disabled";
@@ -363,6 +513,7 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			gpio-ranges = <&pmx0 0 88 8>;
 			clocks = <&crg HISTB_APB_CLK>;
 			clock-names = "apb_pclk";
 			status = "disabled";
@@ -405,5 +556,67 @@
 			clocks = <&sysctrl HISTB_IR_CLK>;
 			status = "disabled";
 		};
+
+		pcie: pcie@9860000 {
+			compatible = "hisilicon,hi3798cv200-pcie";
+			reg = <0x9860000 0x1000>,
+			      <0x0 0x2000>,
+			      <0x2000000 0x01000000>;
+			reg-names = "control", "rc-dbi", "config";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			bus-range = <0 15>;
+			num-lanes = <1>;
+			ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000
+				  0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>;
+			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi";
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0>;
+			interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg HISTB_PCIE_AUX_CLK>,
+				 <&crg HISTB_PCIE_PIPE_CLK>,
+				 <&crg HISTB_PCIE_SYS_CLK>,
+				 <&crg HISTB_PCIE_BUS_CLK>;
+			clock-names = "aux", "pipe", "sys", "bus";
+			resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
+			reset-names = "soft", "sys", "bus";
+			phys = <&combphy1 PHY_TYPE_PCIE>;
+			phy-names = "phy";
+			status = "disabled";
+		};
+
+		ohci: ohci@9880000 {
+			compatible = "generic-ohci";
+			reg = <0x9880000 0x10000>;
+			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg HISTB_USB2_BUS_CLK>,
+				 <&crg HISTB_USB2_12M_CLK>,
+				 <&crg HISTB_USB2_48M_CLK>;
+			clock-names = "bus", "clk12", "clk48";
+			resets = <&crg 0xb8 12>;
+			reset-names = "bus";
+			phys = <&usb2_phy1_port0>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ehci: ehci@9890000 {
+			compatible = "generic-ehci";
+			reg = <0x9890000 0x10000>;
+			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg HISTB_USB2_BUS_CLK>,
+				 <&crg HISTB_USB2_PHY_CLK>,
+				 <&crg HISTB_USB2_UTMI_CLK>;
+			clock-names = "bus", "phy", "utmi";
+			resets = <&crg 0xb8 12>,
+				 <&crg 0xb8 16>,
+				 <&crg 0xb8 13>;
+			reset-names = "bus", "phy", "utmi";
+			phys = <&usb2_phy1_port0>;
+			phy-names = "usb";
+			status = "disabled";
+		};
 	};
 };

+ 98 - 0
arch/arm/dts/poplar-pinctrl.dtsi

@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Pinctrl dts file for HiSilicon Poplar board
+ *
+ * Copyright (c) 2016-2018 HiSilicon Technologies Co., Ltd.
+ */
+
+#include <dt-bindings/pinctrl/hisi.h>
+
+/* value, enable bits, disable bits, mask */
+#define PINCTRL_PULLDOWN(value, enable, disable, mask) \
+	(value << 13) (enable << 13) (disable << 13) (mask << 13)
+#define PINCTRL_PULLUP(value, enable, disable, mask) \
+	(value << 12) (enable << 12) (disable << 12) (mask << 12)
+#define PINCTRL_SLEW_RATE(value, mask)	  (value << 8) (mask << 8)
+#define PINCTRL_DRV_STRENGTH(value, mask) (value << 4) (mask << 4)
+
+&pmx0 {
+	emmc_pins_1: emmc-pins-1 {
+		pinctrl-single,pins = <
+			0x000 MUX_M2
+			0x004 MUX_M2
+			0x008 MUX_M2
+			0x00c MUX_M2
+			0x010 MUX_M2
+			0x014 MUX_M2
+			0x018 MUX_M2
+			0x01c MUX_M2
+			0x024 MUX_M2
+		>;
+		pinctrl-single,bias-pulldown = <
+			PINCTRL_PULLDOWN(0, 1, 0, 1)
+		>;
+		pinctrl-single,bias-pullup = <
+			PINCTRL_PULLUP(0, 1, 0, 1)
+		>;
+		pinctrl-single,slew-rate = <
+			PINCTRL_SLEW_RATE(1, 1)
+		>;
+		pinctrl-single,drive-strength = <
+			PINCTRL_DRV_STRENGTH(0xb, 0xf)
+		>;
+	};
+
+	emmc_pins_2: emmc-pins-2 {
+		pinctrl-single,pins = <
+			0x028 MUX_M2
+		>;
+		pinctrl-single,bias-pulldown = <
+			PINCTRL_PULLDOWN(0, 1, 0, 1)
+		>;
+		pinctrl-single,bias-pullup = <
+			PINCTRL_PULLUP(0, 1, 0, 1)
+		>;
+		pinctrl-single,slew-rate = <
+			PINCTRL_SLEW_RATE(1, 1)
+		>;
+		pinctrl-single,drive-strength = <
+			PINCTRL_DRV_STRENGTH(0x9, 0xf)
+		>;
+	};
+
+	emmc_pins_3: emmc-pins-3 {
+		pinctrl-single,pins = <
+			0x02c MUX_M2
+		>;
+		pinctrl-single,bias-pulldown = <
+			PINCTRL_PULLDOWN(0, 1, 0, 1)
+		>;
+		pinctrl-single,bias-pullup = <
+			PINCTRL_PULLUP(0, 1, 0, 1)
+		>;
+		pinctrl-single,slew-rate = <
+			PINCTRL_SLEW_RATE(1, 1)
+		>;
+		pinctrl-single,drive-strength = <
+			PINCTRL_DRV_STRENGTH(3, 3)
+		>;
+	};
+
+	emmc_pins_4: emmc-pins-4 {
+		pinctrl-single,pins = <
+			0x030 MUX_M2
+		>;
+		pinctrl-single,bias-pulldown = <
+			PINCTRL_PULLDOWN(1, 1, 0, 1)
+		>;
+		pinctrl-single,bias-pullup = <
+			PINCTRL_PULLUP(0, 1, 0, 1)
+		>;
+		pinctrl-single,slew-rate = <
+			PINCTRL_SLEW_RATE(1, 1)
+		>;
+		pinctrl-single,drive-strength = <
+			PINCTRL_DRV_STRENGTH(3, 3)
+		>;
+	};
+};

+ 0 - 12
arch/arm/include/asm/arch-hi3798cv200/dwmmc.h

@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2017 Linaro
- * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
- */
-
-#ifndef _HI3798cv200_DWMMC_H_
-#define _HI3798cv200_DWMMC_H_
-
-int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width);
-
-#endif /* _HI3798cv200_DWMMC_H_ */

+ 0 - 1
arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h

@@ -11,7 +11,6 @@
 #define REG_BASE_CRG			0xF8A22000
 
 /* DEVICES */
-#define REG_BASE_MCI			0xF9830000
 #define REG_BASE_UART0			0xF8B00000
 #define HIOTG_BASE_ADDR			0xF98C0000
 

+ 15 - 0
arch/arm/mach-omap2/Kconfig

@@ -167,6 +167,21 @@ config TI_SECURE_EMIF_PROTECTED_REGION_SIZE
 	  using hardware memory firewalls. This value must be smaller than the
 	  TI_SECURE_EMIF_TOTAL_REGION_SIZE value.
 
+if AM43XX || AM33XX || OMAP54XX
+config ISW_ENTRY_ADDR
+	hex "Address in memory or XIP address of bootloader entry point"
+	default 0x402F4000 if AM43XX
+	default 0x402F0400 if AM33XX
+	default 0x40301350 if OMAP54XX
+	help
+	  After any reset, the boot ROM searches the boot media for a valid
+	  boot image. For non-XIP devices, the ROM then copies the image into
+	  internal memory. For all boot modes, after the ROM processes the
+	  boot image it eventually computes the entry point address depending
+	  on the device type (secure/non-secure), boot media (xip/non-xip) and
+	  image headers.
+endif
+
 source "arch/arm/mach-omap2/omap3/Kconfig"
 
 source "arch/arm/mach-omap2/omap4/Kconfig"

+ 0 - 15
arch/arm/mach-omap2/am33xx/Kconfig

@@ -275,21 +275,6 @@ config SPL_RTC_DDR_SUPPORT
 endif
 
 if AM43XX || AM33XX
-config ISW_ENTRY_ADDR
-	hex "Address in memory or XIP flash of bootloader entry point"
-	default 0x402F4000 if AM43XX
-	default 0x402F0400 if AM33XX
-	help
-	  After any reset, the boot ROM on the AM43XX SOC
-	  searches the boot media for a valid boot image.
-	  For non-XIP devices, the ROM then copies the
-	  image into internal memory.
-	  For all boot modes, after the ROM processes the
-	  boot image it eventually computes the entry
-	  point address depending on the device type
-	  (secure/non-secure), boot media (xip/non-xip) and
-	  image headers.
-
 config PUB_ROM_DATA_SIZE
 	hex "Size in bytes of the L3 SRAM reserved by ROM to store data"
 	default 0x8400

+ 1 - 1
arch/arm/mach-omap2/boot-common.c

@@ -108,7 +108,7 @@ void save_omap_boot_params(void)
 			sys_boot_device = 1;
 			break;
 #endif
-#if defined(BOOT_DEVICE_DFU) && !defined(CONFIG_SPL_DFU_SUPPORT)
+#if defined(BOOT_DEVICE_DFU) && !defined(CONFIG_SPL_DFU)
 		case BOOT_DEVICE_DFU:
 			sys_boot_device = 1;
 			break;

+ 3 - 2
arch/arm/mach-snapdragon/Makefile

@@ -6,8 +6,9 @@ obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o
 obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o
 obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o
 obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o
-obj-$(CONFIG_TARGET_DRAGONBOARD410C) += pinctrl-apq8016.o
-obj-$(CONFIG_TARGET_DRAGONBOARD410C) += pinctrl-snapdragon.o
 obj-y += misc.o
 obj-y += clock-snapdragon.o
 obj-y += dram.o
+obj-y += pinctrl-snapdragon.o
+obj-y += pinctrl-apq8016.o
+obj-y += pinctrl-apq8096.o

+ 34 - 0
arch/arm/mach-snapdragon/clock-apq8096.c

@@ -34,6 +34,12 @@ static const struct pll_vote_clk gpll0_vote_clk = {
 	.vote_bit = APCS_GPLL_ENA_VOTE_GPLL0,
 };
 
+static struct vote_clk gcc_blsp2_ahb_clk = {
+	.cbcr_reg = BLSP2_AHB_CBCR,
+	.ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE,
+	.vote_bit = BIT(15),
+};
+
 static int clk_init_sdc(struct msm_clk_priv *priv, uint rate)
 {
 	int div = 3;
@@ -47,6 +53,32 @@ static int clk_init_sdc(struct msm_clk_priv *priv, uint rate)
 	return rate;
 }
 
+static const struct bcr_regs uart2_regs = {
+	.cfg_rcgr = BLSP2_UART2_APPS_CFG_RCGR,
+	.cmd_rcgr = BLSP2_UART2_APPS_CMD_RCGR,
+	.M = BLSP2_UART2_APPS_M,
+	.N = BLSP2_UART2_APPS_N,
+	.D = BLSP2_UART2_APPS_D,
+};
+
+static int clk_init_uart(struct msm_clk_priv *priv)
+{
+	/* Enable AHB clock */
+	clk_enable_vote_clk(priv->base, &gcc_blsp2_ahb_clk);
+
+	/* 7372800 uart block clock @ GPLL0 */
+	clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 192, 15625,
+			     CFG_CLK_SRC_GPLL0);
+
+	/* Vote for gpll0 clock */
+	clk_enable_gpll0(priv->base, &gpll0_vote_clk);
+
+	/* Enable core clk */
+	clk_enable_cbc(priv->base + BLSP2_UART2_APPS_CBCR);
+
+	return 0;
+}
+
 ulong msm_set_rate(struct clk *clk, ulong rate)
 {
 	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
@@ -55,6 +87,8 @@ ulong msm_set_rate(struct clk *clk, ulong rate)
 	case 0: /* SDC1 */
 		return clk_init_sdc(priv, rate);
 		break;
+	case 4: /*UART2*/
+		return clk_init_uart(priv);
 	default:
 		return 0;
 	}

+ 9 - 0
arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h

@@ -15,6 +15,7 @@
 /* Clocks: (from CLK_CTL_BASE)  */
 #define GPLL0_STATUS			(0x0000)
 #define APCS_GPLL_ENA_VOTE		(0x52000)
+#define APCS_CLOCK_BRANCH_ENA_VOTE	(0x52004)
 
 #define SDCC2_BCR			(0x14000) /* block reset */
 #define SDCC2_APPS_CBCR			(0x14004) /* branch control */
@@ -25,4 +26,12 @@
 #define SDCC2_N				(0x1401C)
 #define SDCC2_D				(0x14020)
 
+#define BLSP2_AHB_CBCR			(0x25004)
+#define BLSP2_UART2_APPS_CBCR		(0x29004)
+#define BLSP2_UART2_APPS_CMD_RCGR	(0x2900C)
+#define BLSP2_UART2_APPS_CFG_RCGR	(0x29010)
+#define BLSP2_UART2_APPS_M		(0x29014)
+#define BLSP2_UART2_APPS_N		(0x29018)
+#define BLSP2_UART2_APPS_D		(0x2901C)
+
 #endif

+ 56 - 0
arch/arm/mach-snapdragon/pinctrl-apq8096.c

@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm APQ8096 pinctrl
+ *
+ * (C) Copyright 2019 Ramon Fried <ramon.fried@gmail.com>
+ *
+ */
+
+#include "pinctrl-snapdragon.h"
+#include <common.h>
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN];
+static const char * const msm_pinctrl_pins[] = {
+	"SDC1_CLK",
+	"SDC1_CMD",
+	"SDC1_DATA",
+	"SDC2_CLK",
+	"SDC2_CMD",
+	"SDC2_DATA",
+	"SDC1_RCLK",
+};
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+	{"blsp_uart8", 2},
+};
+
+static const char *apq8096_get_function_name(struct udevice *dev,
+					     unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].name;
+}
+
+static const char *apq8096_get_pin_name(struct udevice *dev,
+					unsigned int selector)
+{
+	if (selector < 150) {
+		snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
+		return pin_name;
+	} else {
+		return msm_pinctrl_pins[selector - 150];
+	}
+}
+
+static unsigned int apq8096_get_function_mux(unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].val;
+}
+
+struct msm_pinctrl_data apq8096_data = {
+	.pin_count = 157,
+	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+	.get_function_name = apq8096_get_function_name,
+	.get_function_mux = apq8096_get_function_mux,
+	.get_pin_name = apq8096_get_pin_name,
+};

+ 3 - 3
arch/arm/mach-snapdragon/pinctrl-snapdragon.c

@@ -22,7 +22,7 @@ struct msm_pinctrl_priv {
 #define TLMM_GPIO_PULL_MASK GENMASK(1, 0)
 #define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
 #define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
-#define TLMM_GPIO_ENABLE BIT(9)
+#define TLMM_GPIO_DISABLE BIT(9)
 
 static const struct pinconf_param msm_conf_params[] = {
 	{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 3 },
@@ -74,7 +74,7 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
 	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
 
 	clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
-			TLMM_FUNC_SEL_MASK | TLMM_GPIO_ENABLE,
+			TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
 			priv->data->get_function_mux(func_selector) << 2);
 	return 0;
 }
@@ -113,8 +113,8 @@ static struct pinctrl_ops msm_pinctrl_ops = {
 };
 
 static const struct udevice_id msm_pinctrl_ids[] = {
-	{ .compatible = "qcom,tlmm-msm8916", .data = (ulong)&apq8016_data },
 	{ .compatible = "qcom,tlmm-apq8016", .data = (ulong)&apq8016_data },
+	{ .compatible = "qcom,tlmm-apq8096", .data = (ulong)&apq8096_data },
 	{ }
 };
 

+ 1 - 0
arch/arm/mach-snapdragon/pinctrl-snapdragon.h

@@ -26,5 +26,6 @@ struct pinctrl_function {
 };
 
 extern struct msm_pinctrl_data apq8016_data;
+extern struct msm_pinctrl_data apq8096_data;
 
 #endif

+ 3 - 3
arch/arm/mach-stm32mp/config.mk

@@ -3,11 +3,11 @@
 # Copyright (C) 2018, STMicroelectronics - All Rights Reserved
 #
 
-ALL-$(CONFIG_SPL_BUILD) += spl/u-boot-spl.stm32
+ALL-$(CONFIG_SPL_BUILD) += u-boot-spl.stm32
 
 MKIMAGEFLAGS_u-boot-spl.stm32 = -T stm32image -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE)
 
-spl/u-boot-spl.stm32: MKIMAGEOUTPUT = spl/u-boot-spl.stm32.log
+u-boot-spl.stm32: MKIMAGEOUTPUT = u-boot-spl.stm32.log
 
-spl/u-boot-spl.stm32: spl/u-boot-spl.bin FORCE
+u-boot-spl.stm32: spl/u-boot-spl.bin FORCE
 	$(call if_changed,mkimage)

+ 1 - 1
arch/arm/mach-zynqmp/spl.c

@@ -93,7 +93,7 @@ u32 spl_boot_device(void)
 	case EMMC_MODE:
 		return BOOT_DEVICE_MMC1;
 #endif
-#ifdef CONFIG_SPL_DFU_SUPPORT
+#ifdef CONFIG_SPL_DFU
 	case USB_MODE:
 		return BOOT_DEVICE_DFU;
 #endif

+ 0 - 12
board/hisilicon/poplar/poplar.c

@@ -9,7 +9,6 @@
 #include <asm/io.h>
 #include <dm/platform_data/serial_pl01x.h>
 #include <asm/arch/hi3798cv200.h>
-#include <asm/arch/dwmmc.h>
 #include <asm/armv8/mmu.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -155,17 +154,6 @@ static void usb2_phy_init(void)
 	udelay(200);
 }
 
-int board_mmc_init(bd_t *bis)
-{
-	int ret;
-
-	ret = hi6220_dwmci_add_port(0, REG_BASE_MCI, 8);
-	if (ret)
-		printf("mmc init error (%d)\n", ret);
-
-	return ret;
-}
-
 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
 #include <usb.h>
 #include <usb/dwc2_udc.h>

+ 1 - 1
cmd/ximg.c

@@ -143,7 +143,7 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 			return 1;
 		}
 
-		if (fit_image_check_comp(fit_hdr, noffset, IH_COMP_NONE)
+		if (!fit_image_check_comp(fit_hdr, noffset, IH_COMP_NONE)
 		    && (argc < 4)) {
 			printf("Must specify load address for %s command "
 				"with compressed image\n",

+ 1 - 2
common/Makefile

@@ -64,10 +64,9 @@ obj-$(CONFIG_$(SPL_TPL_)BOOTSTAGE) += bootstage.o
 obj-$(CONFIG_$(SPL_TPL_)BLOBLIST) += bloblist.o
 
 ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_DFU_SUPPORT
+ifdef CONFIG_SPL_DFU
 obj-$(CONFIG_DFU_OVER_USB) += dfu.o
 endif
-obj-$(CONFIG_SPL_DFU_SUPPORT) += cli_hush.o
 obj-$(CONFIG_SPL_HASH_SUPPORT) += hash.o
 obj-$(CONFIG_TPL_HASH_SUPPORT) += hash.o
 obj-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o

+ 1 - 1
common/cli.c

@@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 int run_command(const char *cmd, int flag)
 {
-#ifndef CONFIG_HUSH_PARSER
+#if !CONFIG_IS_ENABLED(HUSH_PARSER)
 	/*
 	 * cli_run_command can return 0 or 1 for success, so clean up
 	 * its result.

+ 3 - 3
common/spl/Kconfig

@@ -794,7 +794,7 @@ config SPL_USB_ETHER
 	  since the network stack uses a number of environment variables.
 	  See also SPL_NET_SUPPORT and SPL_ETH_SUPPORT.
 
-config SPL_DFU_SUPPORT
+config SPL_DFU
 	bool "Support DFU (Device Firmware Upgrade)"
 	select SPL_HASH_SUPPORT
 	select SPL_DFU_NO_RESET
@@ -809,11 +809,11 @@ config SPL_DFU_SUPPORT
 
 choice
 	bool "DFU device selection"
-	depends on SPL_DFU_SUPPORT
+	depends on SPL_DFU
 
 config SPL_DFU_RAM
 	bool "RAM device"
-	depends on SPL_DFU_SUPPORT && SPL_RAM_SUPPORT
+	depends on SPL_DFU && SPL_RAM_SUPPORT
 	help
 	 select RAM/DDR memory device for loading binary images
 	 (u-boot/kernel) to the selected device partition using

+ 1 - 1
common/spl/Makefile

@@ -26,7 +26,7 @@ obj-$(CONFIG_$(SPL_TPL_)USB_SUPPORT) += spl_usb.o
 obj-$(CONFIG_$(SPL_TPL_)FAT_SUPPORT) += spl_fat.o
 obj-$(CONFIG_$(SPL_TPL_)EXT_SUPPORT) += spl_ext.o
 obj-$(CONFIG_$(SPL_TPL_)SATA_SUPPORT) += spl_sata.o
-obj-$(CONFIG_$(SPL_TPL_)DFU_SUPPORT) += spl_dfu.o
+obj-$(CONFIG_$(SPL_TPL_)DFU) += spl_dfu.o
 obj-$(CONFIG_$(SPL_TPL_)SPI_LOAD) += spl_spi.o
 obj-$(CONFIG_$(SPL_TPL_)RAM_SUPPORT) += spl_ram.o
 obj-$(CONFIG_$(SPL_TPL_)USB_SDP_SUPPORT) += spl_sdp.o

+ 2 - 2
common/spl/spl_ram.c

@@ -35,7 +35,7 @@ static int spl_ram_load_image(struct spl_image_info *spl_image,
 
 	header = (struct image_header *)CONFIG_SPL_LOAD_FIT_ADDRESS;
 
-#if CONFIG_IS_ENABLED(DFU_SUPPORT)
+#if CONFIG_IS_ENABLED(DFU)
 	if (bootdev->boot_device == BOOT_DEVICE_DFU)
 		spl_dfu_cmd(0, "dfu_alt_info_ram", "ram", "0");
 #endif
@@ -76,7 +76,7 @@ static int spl_ram_load_image(struct spl_image_info *spl_image,
 #if CONFIG_IS_ENABLED(RAM_DEVICE)
 SPL_LOAD_IMAGE_METHOD("RAM", 0, BOOT_DEVICE_RAM, spl_ram_load_image);
 #endif
-#if CONFIG_IS_ENABLED(DFU_SUPPORT)
+#if CONFIG_IS_ENABLED(DFU)
 SPL_LOAD_IMAGE_METHOD("DFU", 0, BOOT_DEVICE_DFU, spl_ram_load_image);
 #endif
 

+ 1 - 0
configs/apalis_imx6_defconfig

@@ -54,6 +54,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DWC_AHSATA=y
+CONFIG_DFU_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y

+ 1 - 0
configs/apalis_imx6_nospl_com_defconfig

@@ -43,6 +43,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DWC_AHSATA=y
+CONFIG_DFU_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y

+ 1 - 0
configs/apalis_imx6_nospl_it_defconfig

@@ -43,6 +43,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DWC_AHSATA=y
+CONFIG_DFU_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y

+ 0 - 2
configs/bcm968380gerg_ram_defconfig

@@ -34,8 +34,6 @@ CONFIG_DM_GPIO=y
 CONFIG_LED=y
 CONFIG_LED_BCM6328=y
 CONFIG_LED_BLINK=y
-CONFIG_SPI_FLASH=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHY=y
 CONFIG_BCM6368_USBH_PHY=y
 CONFIG_PINCTRL=y

+ 1 - 0
configs/chiliboard_defconfig

@@ -42,6 +42,7 @@ CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_OMAP3_SPI=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y

+ 1 - 0
configs/colibri_imx6_defconfig

@@ -53,6 +53,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DFU_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y

+ 1 - 0
configs/colibri_imx6_nospl_defconfig

@@ -42,6 +42,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DFU_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y

+ 2 - 0
configs/dragonboard820c_defconfig

@@ -31,6 +31,8 @@ CONFIG_PM8916_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_MSM=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_PM8916=y
 CONFIG_MSM_SERIAL=y

+ 1 - 0
configs/sama5d3_xplained_mmc_defconfig

@@ -77,6 +77,7 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_W1=y
 CONFIG_W1_GPIO=y
 CONFIG_W1_EEPROM=y

+ 1 - 2
drivers/Makefile

@@ -2,6 +2,7 @@
 
 obj-$(CONFIG_$(SPL_TPL_)CLK) += clk/
 obj-$(CONFIG_$(SPL_TPL_)DM) += core/
+obj-$(CONFIG_$(SPL_TPL_)DFU) += dfu/
 obj-$(CONFIG_$(SPL_TPL_)GPIO_SUPPORT) += gpio/
 obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC_SUPPORT) += misc/ sysreset/ firmware/
 obj-$(CONFIG_$(SPL_TPL_)I2C_SUPPORT) += i2c/
@@ -50,7 +51,6 @@ obj-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += usb/musb-new/
 obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/
 obj-$(CONFIG_SPL_USB_GADGET) += usb/common/
 obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/udc/
-obj-$(CONFIG_SPL_DFU_SUPPORT) += dfu/
 obj-$(CONFIG_SPL_WATCHDOG_SUPPORT) += watchdog/
 obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += usb/host/
 obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
@@ -86,7 +86,6 @@ obj-y += misc/
 obj-$(CONFIG_MMC) += mmc/
 obj-$(CONFIG_NVME) += nvme/
 obj-y += pcmcia/
-obj-y += dfu/
 obj-$(CONFIG_X86) += pch/
 obj-y += phy/allwinner/
 obj-y += phy/marvell/

+ 6 - 6
drivers/dfu/Makefile

@@ -3,9 +3,9 @@
 # Copyright (C) 2012 Samsung Electronics
 # Lukasz Majewski <l.majewski@samsung.com>
 
-obj-$(CONFIG_DFU) += dfu.o
-obj-$(CONFIG_DFU_MMC) += dfu_mmc.o
-obj-$(CONFIG_DFU_NAND) += dfu_nand.o
-obj-$(CONFIG_DFU_RAM) += dfu_ram.o
-obj-$(CONFIG_DFU_SF) += dfu_sf.o
-obj-$(CONFIG_DFU_TFTP) += dfu_tftp.o
+obj-$(CONFIG_$(SPL_)DFU) += dfu.o
+obj-$(CONFIG_$(SPL_)DFU_MMC) += dfu_mmc.o
+obj-$(CONFIG_$(SPL_)DFU_NAND) += dfu_nand.o
+obj-$(CONFIG_$(SPL_)DFU_RAM) += dfu_ram.o
+obj-$(CONFIG_$(SPL_)DFU_SF) += dfu_sf.o
+obj-$(CONFIG_$(SPL_)DFU_TFTP) += dfu_tftp.o

+ 1 - 0
drivers/misc/i2c_eeprom.c

@@ -69,6 +69,7 @@ static const struct udevice_id i2c_eeprom_std_ids[] = {
 	{ .compatible = "atmel,24c01a", .data = 3 },
 	{ .compatible = "atmel,24c02", .data = 3 },
 	{ .compatible = "atmel,24c04", .data = 4 },
+	{ .compatible = "atmel,24c08", .data = 4 },
 	{ .compatible = "atmel,24c08a", .data = 4 },
 	{ .compatible = "atmel,24c16a", .data = 4 },
 	{ .compatible = "atmel,24mac402", .data = 4 },

+ 42 - 1
drivers/mmc/fsl_esdhc.c

@@ -384,6 +384,25 @@ static void check_and_invalidate_dcache_range
 	invalidate_dcache_range(start, end);
 }
 
+#ifdef CONFIG_MCF5441x
+/*
+ * Swaps 32-bit words to little-endian byte order.
+ */
+static inline void sd_swap_dma_buff(struct mmc_data *data)
+{
+	int i, size = data->blocksize >> 2;
+	u32 *buffer = (u32 *)data->dest;
+	u32 sw;
+
+	while (data->blocks--) {
+		for (i = 0; i < size; i++) {
+			sw = __sw32(*buffer);
+			*buffer++ = sw;
+		}
+	}
+}
+#endif
+
 /*
  * Sends a command out on the bus.  Takes the mmc pointer,
  * a command pointer, and an optional data pointer.
@@ -546,8 +565,12 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
 		 * cache-fill during the DMA operations such as the
 		 * speculative pre-fetching etc.
 		 */
-		if (data->flags & MMC_DATA_READ)
+		if (data->flags & MMC_DATA_READ) {
 			check_and_invalidate_dcache_range(cmd, data);
+#ifdef CONFIG_MCF5441x
+			sd_swap_dma_buff(data);
+#endif
+		}
 #endif
 	}
 
@@ -1029,8 +1052,12 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
 	/* Disable the BRR and BWR bits in IRQSTAT */
 	esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
 
+#ifdef CONFIG_MCF5441x
+	esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
+#else
 	/* Put the PROCTL reg back to the default */
 	esdhc_write32(&regs->proctl, PROCTL_INIT);
+#endif
 
 	/* Set timout to the maximum value */
 	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
@@ -1138,6 +1165,11 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
 	if (ret)
 		return ret;
 
+#ifdef CONFIG_MCF5441x
+	/* ColdFire, using SDHC_DATA[3] for card detection */
+	esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
+#endif
+
 #ifndef CONFIG_FSL_USDHC
 	esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
 				| SYSCTL_IPGEN | SYSCTL_CKEN);
@@ -1162,6 +1194,15 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
 	voltage_caps = 0;
 	caps = esdhc_read32(&regs->hostcapblt);
 
+#ifdef CONFIG_MCF5441x
+	/*
+	 * MCF5441x RM declares in more points that sdhc clock speed must
+	 * never exceed 25 Mhz. From this, the HS bit needs to be disabled
+	 * from host capabilities.
+	 */
+	caps &= ~ESDHC_HOSTCAPBLT_HSS;
+#endif
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
 	caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
 			ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);

+ 1 - 0
drivers/mmc/hi6220_dw_mmc.c

@@ -77,6 +77,7 @@ static int hi6220_dwmmc_bind(struct udevice *dev)
 
 static const struct udevice_id hi6220_dwmmc_ids[] = {
 	{ .compatible = "hisilicon,hi6220-dw-mshc" },
+	{ .compatible = "hisilicon,hi3798cv200-dw-mshc" },
 	{ }
 };
 

+ 13 - 13
drivers/mmc/mtk-sd.c

@@ -269,7 +269,7 @@ struct msdc_host {
 	bool builtin_cd;
 
 	/* card detection / write protection GPIOs */
-#ifdef CONFIG_DM_GPIO
+#if IS_ENABLED(DM_GPIO)
 	struct gpio_desc gpio_wp;
 	struct gpio_desc gpio_cd;
 #endif
@@ -554,6 +554,14 @@ static int msdc_pio_read(struct msdc_host *host, u8 *ptr, u32 size)
 			break;
 		}
 
+		chksz = min(size, (u32)MSDC_FIFO_SIZE);
+
+		if (msdc_fifo_rx_bytes(host) >= chksz) {
+			msdc_fifo_read(host, ptr, chksz);
+			ptr += chksz;
+			size -= chksz;
+		}
+
 		if (status & MSDC_INT_XFER_COMPL) {
 			if (size) {
 				pr_err("data not fully read\n");
@@ -562,15 +570,7 @@ static int msdc_pio_read(struct msdc_host *host, u8 *ptr, u32 size)
 
 			break;
 		}
-
-		chksz = min(size, (u32)MSDC_FIFO_SIZE);
-
-		if (msdc_fifo_rx_bytes(host) >= chksz) {
-			msdc_fifo_read(host, ptr, chksz);
-			ptr += chksz;
-			size -= chksz;
-		}
-	}
+}
 
 	return ret;
 }
@@ -849,7 +849,7 @@ static int msdc_ops_get_cd(struct udevice *dev)
 		return !(val & MSDC_PS_CDSTS);
 	}
 
-#ifdef CONFIG_DM_GPIO
+#if IS_ENABLED(DM_GPIO)
 	if (!host->gpio_cd.dev)
 		return 1;
 
@@ -861,9 +861,9 @@ static int msdc_ops_get_cd(struct udevice *dev)
 
 static int msdc_ops_get_wp(struct udevice *dev)
 {
+#if IS_ENABLED(DM_GPIO)
 	struct msdc_host *host = dev_get_priv(dev);
 
-#ifdef CONFIG_DM_GPIO
 	if (!host->gpio_wp.dev)
 		return 0;
 
@@ -1332,7 +1332,7 @@ static int msdc_ofdata_to_platdata(struct udevice *dev)
 	if (ret < 0)
 		return ret;
 
-#ifdef CONFIG_DM_GPIO
+#if IS_ENABLED(DM_GPIO)
 	gpio_request_by_name(dev, "wp-gpios", 0, &host->gpio_wp, GPIOD_IS_IN);
 	gpio_request_by_name(dev, "cd-gpios", 0, &host->gpio_cd, GPIOD_IS_IN);
 #endif

+ 1 - 1
drivers/usb/gadget/Makefile

@@ -8,7 +8,7 @@ obj-$(CONFIG_USB_ETHER) += epautoconf.o config.o usbstring.o
 
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_USB_GADGET) += g_dnl.o
-obj-$(CONFIG_SPL_DFU_SUPPORT) += f_dfu.o
+obj-$(CONFIG_SPL_DFU) += f_dfu.o
 obj-$(CONFIG_SPL_USB_SDP_SUPPORT) += f_sdp.o
 endif
 

+ 2 - 2
env/common.c

@@ -115,7 +115,7 @@ int env_import(const char *buf, int check)
 
 		if (crc32(0, ep->data, ENV_SIZE) != crc) {
 			set_default_env("bad CRC", 0);
-			return -EIO;
+			return -ENOMSG; /* needed for env_load() */
 		}
 	}
 
@@ -169,7 +169,7 @@ int env_import_redund(const char *buf1, int buf1_read_fail,
 
 	if (!crc1_ok && !crc2_ok) {
 		set_default_env("bad CRC", 0);
-		return -EIO;
+		return -ENOMSG; /* needed for env_load() */
 	} else if (crc1_ok && !crc2_ok) {
 		gd->env_valid = ENV_VALID;
 	} else if (!crc1_ok && crc2_ok) {

+ 19 - 6
env/env.c

@@ -177,6 +177,7 @@ int env_get_char(int index)
 int env_load(void)
 {
 	struct env_driver *drv;
+	int best_prio = -1;
 	int prio;
 
 	for (prio = 0; (drv = env_driver_lookup(ENVOP_LOAD, prio)); prio++) {
@@ -195,20 +196,32 @@ int env_load(void)
 		 * one message.
 		 */
 		ret = drv->load();
-		if (ret) {
-			debug("Failed (%d)\n", ret);
-		} else {
+		if (!ret) {
 			printf("OK\n");
 			return 0;
+		} else if (ret == -ENOMSG) {
+			/* Handle "bad CRC" case */
+			if (best_prio == -1)
+				best_prio = prio;
+		} else {
+			debug("Failed (%d)\n", ret);
 		}
 	}
 
 	/*
 	 * In case of invalid environment, we set the 'default' env location
-	 * to the highest priority. In this way, next calls to env_save()
-	 * will restore the environment at the right place.
+	 * to the best choice, i.e.:
+	 *   1. Environment location with bad CRC, if such location was found
+	 *   2. Otherwise use the location with highest priority
+	 *
+	 * This way, next calls to env_save() will restore the environment
+	 * at the right place.
 	 */
-	env_get_location(ENVOP_LOAD, 0);
+	if (best_prio >= 0)
+		debug("Selecting environment with bad CRC\n");
+	else
+		best_prio = 0;
+	env_get_location(ENVOP_LOAD, best_prio);
 
 	return -ENODEV;
 }

+ 0 - 4
include/configs/apalis_imx6.h

@@ -83,10 +83,6 @@
 #define CONFIG_USBD_HS
 
 #define CONFIG_USB_GADGET_MASS_STORAGE
-/* USB DFU */
-#define CONFIG_DFU_MMC
-
-/* Miscellaneous commands */
 
 /* Framebuffer and LCD */
 #define CONFIG_VIDEO_IPUV3

+ 0 - 4
include/configs/colibri_imx6.h

@@ -71,10 +71,6 @@
 #define CONFIG_USBD_HS
 
 #define CONFIG_USB_GADGET_MASS_STORAGE
-/* USB DFU */
-#define CONFIG_DFU_MMC
-
-/* Miscellaneous commands */
 
 /* Framebuffer and LCD */
 #define CONFIG_VIDEO_IPUV3

+ 1 - 1
include/configs/dra7xx_evm.h

@@ -53,7 +53,7 @@
 
 #ifdef CONFIG_SPL_BUILD
 #undef CONFIG_CMD_BOOTD
-#ifdef CONFIG_SPL_DFU_SUPPORT
+#ifdef CONFIG_SPL_DFU
 #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000
 #define DFUARGS \
 	"dfu_bufsiz=0x10000\0" \

+ 1 - 1
include/configs/ti_omap5_common.h

@@ -81,7 +81,7 @@
  * RAM from address 0x40301350 (0x40300000+0x1000(reserved)+0x350(cert)).
  */
 #define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ	0x1000
-#define CONFIG_SPL_TEXT_BASE	0x40301350
+#define CONFIG_SPL_TEXT_BASE	CONFIG_ISW_ENTRY_ADDR
 /* If no specific start address is specified then the secure EMIF
  * region will be placed at the end of the DDR space. In order to prevent
  * the main u-boot relocation from clobbering that memory and causing a

+ 2 - 2
include/configs/xilinx_zynqmp.h

@@ -183,7 +183,7 @@
 #endif
 
 /* SPL can't handle all huge variables - define just DFU */
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU_SUPPORT)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU)
 #undef CONFIG_EXTRA_ENV_SETTINGS
 # define CONFIG_EXTRA_ENV_SETTINGS \
 	"dfu_alt_info_ram=uboot.bin ram 0x8000000 0x1000000;" \
@@ -228,7 +228,7 @@
 # define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
 #endif
 
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU_SUPPORT)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU)
 # undef CONFIG_CMD_BOOTD
 # define CONFIG_SPL_ENV_SUPPORT
 # define CONFIG_SPL_HASH_SUPPORT

+ 5 - 5
include/dfu.h

@@ -202,7 +202,7 @@ static inline void dfu_set_defer_flush(struct dfu_entity *dfu)
 int dfu_write_from_mem_addr(struct dfu_entity *dfu, void *buf, int size);
 
 /* Device specific */
-#ifdef CONFIG_DFU_MMC
+#if CONFIG_IS_ENABLED(DFU_MMC)
 extern int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *devstr, char *s);
 #else
 static inline int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *devstr,
@@ -213,7 +213,7 @@ static inline int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *devstr,
 }
 #endif
 
-#ifdef CONFIG_DFU_NAND
+#if CONFIG_IS_ENABLED(DFU_NAND)
 extern int dfu_fill_entity_nand(struct dfu_entity *dfu, char *devstr, char *s);
 #else
 static inline int dfu_fill_entity_nand(struct dfu_entity *dfu, char *devstr,
@@ -224,7 +224,7 @@ static inline int dfu_fill_entity_nand(struct dfu_entity *dfu, char *devstr,
 }
 #endif
 
-#ifdef CONFIG_DFU_RAM
+#if CONFIG_IS_ENABLED(DFU_RAM)
 extern int dfu_fill_entity_ram(struct dfu_entity *dfu, char *devstr, char *s);
 #else
 static inline int dfu_fill_entity_ram(struct dfu_entity *dfu, char *devstr,
@@ -235,7 +235,7 @@ static inline int dfu_fill_entity_ram(struct dfu_entity *dfu, char *devstr,
 }
 #endif
 
-#ifdef CONFIG_DFU_SF
+#if CONFIG_IS_ENABLED(DFU_SF)
 extern int dfu_fill_entity_sf(struct dfu_entity *dfu, char *devstr, char *s);
 #else
 static inline int dfu_fill_entity_sf(struct dfu_entity *dfu, char *devstr,
@@ -259,7 +259,7 @@ static inline int dfu_fill_entity_sf(struct dfu_entity *dfu, char *devstr,
  *
  * @return 0 on success, otherwise error code
  */
-#ifdef CONFIG_DFU_TFTP
+#if CONFIG_IS_ENABLED(DFU_TFTP)
 int dfu_tftp_write(char *dfu_entity_name, unsigned int addr, unsigned int len,
 		   char *interface, char *devstring);
 #else

+ 36 - 20
include/dt-bindings/clock/histb-clock.h

@@ -22,18 +22,18 @@
 #define HISTB_OSC_CLK			0
 #define HISTB_APB_CLK			1
 #define HISTB_AHB_CLK			2
-#define HISTB_UART1_CLK		3
-#define HISTB_UART2_CLK		4
-#define HISTB_UART3_CLK		5
-#define HISTB_I2C0_CLK		6
-#define HISTB_I2C1_CLK		7
-#define HISTB_I2C2_CLK		8
-#define HISTB_I2C3_CLK		9
-#define HISTB_I2C4_CLK		10
-#define HISTB_I2C5_CLK		11
-#define HISTB_SPI0_CLK		12
-#define HISTB_SPI1_CLK		13
-#define HISTB_SPI2_CLK		14
+#define HISTB_UART1_CLK			3
+#define HISTB_UART2_CLK			4
+#define HISTB_UART3_CLK			5
+#define HISTB_I2C0_CLK			6
+#define HISTB_I2C1_CLK			7
+#define HISTB_I2C2_CLK			8
+#define HISTB_I2C3_CLK			9
+#define HISTB_I2C4_CLK			10
+#define HISTB_I2C5_CLK			11
+#define HISTB_SPI0_CLK			12
+#define HISTB_SPI1_CLK			13
+#define HISTB_SPI2_CLK			14
 #define HISTB_SCI_CLK			15
 #define HISTB_FMC_CLK			16
 #define HISTB_MMC_BIU_CLK		17
@@ -43,7 +43,7 @@
 #define HISTB_SDIO0_BIU_CLK		21
 #define HISTB_SDIO0_CIU_CLK		22
 #define HISTB_SDIO0_DRV_CLK		23
-#define HISTB_SDIO0_SAMPLE_CLK	24
+#define HISTB_SDIO0_SAMPLE_CLK		24
 #define HISTB_PCIE_AUX_CLK		25
 #define HISTB_PCIE_PIPE_CLK		26
 #define HISTB_PCIE_SYS_CLK		27
@@ -53,14 +53,30 @@
 #define HISTB_ETH1_MAC_CLK		31
 #define HISTB_ETH1_MACIF_CLK		32
 #define HISTB_COMBPHY1_CLK		33
-
+#define HISTB_USB2_BUS_CLK		34
+#define HISTB_USB2_PHY_CLK		35
+#define HISTB_USB2_UTMI_CLK		36
+#define HISTB_USB2_12M_CLK		37
+#define HISTB_USB2_48M_CLK		38
+#define HISTB_USB2_OTG_UTMI_CLK		39
+#define HISTB_USB2_PHY1_REF_CLK		40
+#define HISTB_USB2_PHY2_REF_CLK		41
+#define HISTB_COMBPHY0_CLK		42
+#define HISTB_USB3_BUS_CLK		43
+#define HISTB_USB3_UTMI_CLK		44
+#define HISTB_USB3_PIPE_CLK		45
+#define HISTB_USB3_SUSPEND_CLK		46
+#define HISTB_USB3_BUS_CLK1		47
+#define HISTB_USB3_UTMI_CLK1		48
+#define HISTB_USB3_PIPE_CLK1		49
+#define HISTB_USB3_SUSPEND_CLK1		50
 
 /* clocks provided by mcu CRG */
-#define HISTB_MCE_CLK	1
-#define HISTB_IR_CLK	2
-#define HISTB_TIMER01_CLK	3
-#define HISTB_LEDC_CLK	4
-#define HISTB_UART0_CLK	5
-#define HISTB_LSADC_CLK	6
+#define HISTB_MCE_CLK			1
+#define HISTB_IR_CLK			2
+#define HISTB_TIMER01_CLK		3
+#define HISTB_LEDC_CLK			4
+#define HISTB_UART0_CLK			5
+#define HISTB_LSADC_CLK			6
 
 #endif	/* __DTS_HISTB_CLOCK_H */

+ 74 - 0
include/dt-bindings/pinctrl/hisi.h

@@ -0,0 +1,74 @@
+/*
+ * This header provides constants for hisilicon pinctrl bindings.
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ * Copyright (c) 2015 Linaro Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_HISI_H
+#define _DT_BINDINGS_PINCTRL_HISI_H
+
+/* iomg bit definition */
+#define MUX_M0		0
+#define MUX_M1		1
+#define MUX_M2		2
+#define MUX_M3		3
+#define MUX_M4		4
+#define MUX_M5		5
+#define MUX_M6		6
+#define MUX_M7		7
+
+/* iocg bit definition */
+#define PULL_MASK	(3)
+#define PULL_DIS	(0)
+#define PULL_UP		(1 << 0)
+#define PULL_DOWN	(1 << 1)
+
+/* drive strength definition */
+#define DRIVE_MASK	(7 << 4)
+#define DRIVE1_02MA	(0 << 4)
+#define DRIVE1_04MA	(1 << 4)
+#define DRIVE1_08MA	(2 << 4)
+#define DRIVE1_10MA	(3 << 4)
+#define DRIVE2_02MA	(0 << 4)
+#define DRIVE2_04MA	(1 << 4)
+#define DRIVE2_08MA	(2 << 4)
+#define DRIVE2_10MA	(3 << 4)
+#define DRIVE3_04MA	(0 << 4)
+#define DRIVE3_08MA	(1 << 4)
+#define DRIVE3_12MA	(2 << 4)
+#define DRIVE3_16MA	(3 << 4)
+#define DRIVE3_20MA	(4 << 4)
+#define DRIVE3_24MA	(5 << 4)
+#define DRIVE3_32MA	(6 << 4)
+#define DRIVE3_40MA	(7 << 4)
+#define DRIVE4_02MA	(0 << 4)
+#define DRIVE4_04MA	(2 << 4)
+#define DRIVE4_08MA	(4 << 4)
+#define DRIVE4_10MA	(6 << 4)
+
+/* drive strength definition for hi3660 */
+#define DRIVE6_MASK	(15 << 4)
+#define DRIVE6_04MA	(0 << 4)
+#define DRIVE6_12MA	(4 << 4)
+#define DRIVE6_19MA	(8 << 4)
+#define DRIVE6_27MA	(10 << 4)
+#define DRIVE6_32MA	(15 << 4)
+#define DRIVE7_02MA	(0 << 4)
+#define DRIVE7_04MA	(1 << 4)
+#define DRIVE7_06MA	(2 << 4)
+#define DRIVE7_08MA	(3 << 4)
+#define DRIVE7_10MA	(4 << 4)
+#define DRIVE7_12MA	(5 << 4)
+#define DRIVE7_14MA	(6 << 4)
+#define DRIVE7_16MA	(7 << 4)
+#endif

+ 1 - 0
include/fsl_esdhc.h

@@ -106,6 +106,7 @@
 #define PROCTL_INIT		0x00000020
 #define PROCTL_DTW_4		0x00000002
 #define PROCTL_DTW_8		0x00000004
+#define PROCTL_D3CD		0x00000008
 
 #define CMDARG			0x0002e008
 

+ 1 - 1
include/lmb.h

@@ -40,7 +40,7 @@ extern phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong ali
 			      phys_addr_t max_addr);
 extern phys_addr_t lmb_alloc_addr(struct lmb *lmb, phys_addr_t base,
 				  phys_size_t size);
-extern phys_size_t lmb_get_unreserved_size(struct lmb *lmb, phys_addr_t addr);
+extern phys_size_t lmb_get_free_size(struct lmb *lmb, phys_addr_t addr);
 extern int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr);
 extern long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size);
 

+ 1 - 2
lib/hashtable.c

@@ -542,9 +542,8 @@ static int match_string(int flag, const char *str, const char *pat, void *priv)
 	case H_MATCH_REGEX:
 		{
 			struct slre *slrep = (struct slre *)priv;
-			struct cap caps[slrep->num_caps + 2];
 
-			if (slre_match(slrep, str, strlen(str), caps))
+			if (slre_match(slrep, str, strlen(str), NULL))
 				return 1;
 		}
 		break;

+ 43 - 45
lib/lmb.c

@@ -20,28 +20,28 @@ void lmb_dump_all(struct lmb *lmb)
 	debug("    memory.cnt		   = 0x%lx\n", lmb->memory.cnt);
 	debug("    memory.size		   = 0x%llx\n",
 	      (unsigned long long)lmb->memory.size);
-	for (i=0; i < lmb->memory.cnt ;i++) {
+	for (i = 0; i < lmb->memory.cnt; i++) {
 		debug("    memory.reg[0x%lx].base   = 0x%llx\n", i,
-			(long long unsigned)lmb->memory.region[i].base);
+		      (unsigned long long)lmb->memory.region[i].base);
 		debug("		   .size   = 0x%llx\n",
-			(long long unsigned)lmb->memory.region[i].size);
+		      (unsigned long long)lmb->memory.region[i].size);
 	}
 
 	debug("\n    reserved.cnt	   = 0x%lx\n",
 		lmb->reserved.cnt);
 	debug("    reserved.size	   = 0x%llx\n",
-		(long long unsigned)lmb->reserved.size);
-	for (i=0; i < lmb->reserved.cnt ;i++) {
+		(unsigned long long)lmb->reserved.size);
+	for (i = 0; i < lmb->reserved.cnt; i++) {
 		debug("    reserved.reg[0x%lx].base = 0x%llx\n", i,
-			(long long unsigned)lmb->reserved.region[i].base);
+		      (unsigned long long)lmb->reserved.region[i].base);
 		debug("		     .size = 0x%llx\n",
-			(long long unsigned)lmb->reserved.region[i].size);
+		      (unsigned long long)lmb->reserved.region[i].size);
 	}
 #endif /* DEBUG */
 }
 
-static long lmb_addrs_overlap(phys_addr_t base1,
-		phys_size_t size1, phys_addr_t base2, phys_size_t size2)
+static long lmb_addrs_overlap(phys_addr_t base1, phys_size_t size1,
+			      phys_addr_t base2, phys_size_t size2)
 {
 	const phys_addr_t base1_end = base1 + size1 - 1;
 	const phys_addr_t base2_end = base2 + size2 - 1;
@@ -50,7 +50,7 @@ static long lmb_addrs_overlap(phys_addr_t base1,
 }
 
 static long lmb_addrs_adjacent(phys_addr_t base1, phys_size_t size1,
-		phys_addr_t base2, phys_size_t size2)
+			       phys_addr_t base2, phys_size_t size2)
 {
 	if (base2 == base1 + size1)
 		return 1;
@@ -60,8 +60,8 @@ static long lmb_addrs_adjacent(phys_addr_t base1, phys_size_t size1,
 	return 0;
 }
 
-static long lmb_regions_adjacent(struct lmb_region *rgn,
-		unsigned long r1, unsigned long r2)
+static long lmb_regions_adjacent(struct lmb_region *rgn, unsigned long r1,
+				 unsigned long r2)
 {
 	phys_addr_t base1 = rgn->region[r1].base;
 	phys_size_t size1 = rgn->region[r1].size;
@@ -83,8 +83,8 @@ static void lmb_remove_region(struct lmb_region *rgn, unsigned long r)
 }
 
 /* Assumption: base addr of region 1 < base addr of region 2 */
-static void lmb_coalesce_regions(struct lmb_region *rgn,
-		unsigned long r1, unsigned long r2)
+static void lmb_coalesce_regions(struct lmb_region *rgn, unsigned long r1,
+				 unsigned long r2)
 {
 	rgn->region[r1].size += rgn->region[r2].size;
 	lmb_remove_region(rgn, r2);
@@ -125,7 +125,7 @@ static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t
 	}
 
 	/* First try and coalesce this LMB with another. */
-	for (i=0; i < rgn->cnt; i++) {
+	for (i = 0; i < rgn->cnt; i++) {
 		phys_addr_t rgnbase = rgn->region[i].base;
 		phys_size_t rgnsize = rgn->region[i].size;
 
@@ -133,14 +133,13 @@ static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t
 			/* Already have this region, so we're done */
 			return 0;
 
-		adjacent = lmb_addrs_adjacent(base,size,rgnbase,rgnsize);
-		if ( adjacent > 0 ) {
+		adjacent = lmb_addrs_adjacent(base, size, rgnbase, rgnsize);
+		if (adjacent > 0) {
 			rgn->region[i].base -= size;
 			rgn->region[i].size += size;
 			coalesced++;
 			break;
-		}
-		else if ( adjacent < 0 ) {
+		} else if (adjacent < 0) {
 			rgn->region[i].size += size;
 			coalesced++;
 			break;
@@ -150,8 +149,8 @@ static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t
 		}
 	}
 
-	if ((i < rgn->cnt-1) && lmb_regions_adjacent(rgn, i, i+1) ) {
-		lmb_coalesce_regions(rgn, i, i+1);
+	if ((i < rgn->cnt - 1) && lmb_regions_adjacent(rgn, i, i + 1)) {
+		lmb_coalesce_regions(rgn, i, i + 1);
 		coalesced++;
 	}
 
@@ -163,11 +162,11 @@ static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t
 	/* Couldn't coalesce the LMB, so add it to the sorted table. */
 	for (i = rgn->cnt-1; i >= 0; i--) {
 		if (base < rgn->region[i].base) {
-			rgn->region[i+1].base = rgn->region[i].base;
-			rgn->region[i+1].size = rgn->region[i].size;
+			rgn->region[i + 1].base = rgn->region[i].base;
+			rgn->region[i + 1].size = rgn->region[i].size;
 		} else {
-			rgn->region[i+1].base = base;
-			rgn->region[i+1].size = size;
+			rgn->region[i + 1].base = base;
+			rgn->region[i + 1].size = size;
 			break;
 		}
 	}
@@ -200,7 +199,7 @@ long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size)
 	rgnbegin = rgnend = 0; /* supress gcc warnings */
 
 	/* Find the region where (base, size) belongs to */
-	for (i=0; i < rgn->cnt; i++) {
+	for (i = 0; i < rgn->cnt; i++) {
 		rgnbegin = rgn->region[i].base;
 		rgnend = rgnbegin + rgn->region[i].size - 1;
 
@@ -251,12 +250,11 @@ static long lmb_overlaps_region(struct lmb_region *rgn, phys_addr_t base,
 {
 	unsigned long i;
 
-	for (i=0; i < rgn->cnt; i++) {
+	for (i = 0; i < rgn->cnt; i++) {
 		phys_addr_t rgnbase = rgn->region[i].base;
 		phys_size_t rgnsize = rgn->region[i].size;
-		if ( lmb_addrs_overlap(base,size,rgnbase,rgnsize) ) {
+		if (lmb_addrs_overlap(base, size, rgnbase, rgnsize))
 			break;
-		}
 	}
 
 	return (i < rgn->cnt) ? i : -1;
@@ -275,7 +273,7 @@ phys_addr_t lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, phys_
 
 	if (alloc == 0)
 		printf("ERROR: Failed to allocate 0x%lx bytes below 0x%lx.\n",
-		      (ulong)size, (ulong)max_addr);
+		       (ulong)size, (ulong)max_addr);
 
 	return alloc;
 }
@@ -287,11 +285,11 @@ static phys_addr_t lmb_align_down(phys_addr_t addr, phys_size_t size)
 
 phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, phys_addr_t max_addr)
 {
-	long i, j;
+	long i, rgn;
 	phys_addr_t base = 0;
 	phys_addr_t res_base;
 
-	for (i = lmb->memory.cnt-1; i >= 0; i--) {
+	for (i = lmb->memory.cnt - 1; i >= 0; i--) {
 		phys_addr_t lmbbase = lmb->memory.region[i].base;
 		phys_size_t lmbsize = lmb->memory.region[i].size;
 
@@ -309,15 +307,15 @@ phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, phy
 			continue;
 
 		while (base && lmbbase <= base) {
-			j = lmb_overlaps_region(&lmb->reserved, base, size);
-			if (j < 0) {
+			rgn = lmb_overlaps_region(&lmb->reserved, base, size);
+			if (rgn < 0) {
 				/* This area isn't reserved, take it */
 				if (lmb_add_region(&lmb->reserved, base,
 						   size) < 0)
 					return 0;
 				return base;
 			}
-			res_base = lmb->reserved.region[j].base;
+			res_base = lmb->reserved.region[rgn].base;
 			if (res_base < size)
 				break;
 			base = lmb_align_down(res_base - size, align);
@@ -332,18 +330,18 @@ phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, phy
  */
 phys_addr_t lmb_alloc_addr(struct lmb *lmb, phys_addr_t base, phys_size_t size)
 {
-	long j;
+	long rgn;
 
 	/* Check if the requested address is in one of the memory regions */
-	j = lmb_overlaps_region(&lmb->memory, base, size);
-	if (j >= 0) {
+	rgn = lmb_overlaps_region(&lmb->memory, base, size);
+	if (rgn >= 0) {
 		/*
 		 * Check if the requested end address is in the same memory
 		 * region we found.
 		 */
-		if (lmb_addrs_overlap(lmb->memory.region[j].base,
-				      lmb->memory.region[j].size, base + size -
-				      1, 1)) {
+		if (lmb_addrs_overlap(lmb->memory.region[rgn].base,
+				      lmb->memory.region[rgn].size,
+				      base + size - 1, 1)) {
 			/* ok, reserve the memory */
 			if (lmb_reserve(lmb, base, size) >= 0)
 				return base;
@@ -353,14 +351,14 @@ phys_addr_t lmb_alloc_addr(struct lmb *lmb, phys_addr_t base, phys_size_t size)
 }
 
 /* Return number of bytes from a given address that are free */
-phys_size_t lmb_get_unreserved_size(struct lmb *lmb, phys_addr_t addr)
+phys_size_t lmb_get_free_size(struct lmb *lmb, phys_addr_t addr)
 {
 	int i;
-	long j;
+	long rgn;
 
 	/* check if the requested address is in the memory regions */
-	j = lmb_overlaps_region(&lmb->memory, addr, 1);
-	if (j >= 0) {
+	rgn = lmb_overlaps_region(&lmb->memory, addr, 1);
+	if (rgn >= 0) {
 		for (i = 0; i < lmb->reserved.cnt; i++) {
 			if (addr < lmb->reserved.region[i].base) {
 				/* first reserved range > requested address */

+ 1 - 1
net/tftp.c

@@ -609,7 +609,7 @@ static int tftp_init_load_addr(void)
 	lmb_init_and_reserve(&lmb, gd->bd->bi_dram[0].start,
 			     gd->bd->bi_dram[0].size, (void *)gd->fdt_blob);
 
-	max_size = lmb_get_unreserved_size(&lmb, load_addr);
+	max_size = lmb_get_free_size(&lmb, load_addr);
 	if (!max_size)
 		return -1;
 

+ 11 - 11
test/lib/lmb.c

@@ -560,31 +560,31 @@ static int test_get_unreserved_size(struct unit_test_state *uts,
 		   alloc_addr_b, 0x10000, alloc_addr_c, 0x10000);
 
 	/* check addresses in between blocks */
-	s = lmb_get_unreserved_size(&lmb, ram);
+	s = lmb_get_free_size(&lmb, ram);
 	ut_asserteq(s, alloc_addr_a - ram);
-	s = lmb_get_unreserved_size(&lmb, ram + 0x10000);
+	s = lmb_get_free_size(&lmb, ram + 0x10000);
 	ut_asserteq(s, alloc_addr_a - ram - 0x10000);
-	s = lmb_get_unreserved_size(&lmb, alloc_addr_a - 4);
+	s = lmb_get_free_size(&lmb, alloc_addr_a - 4);
 	ut_asserteq(s, 4);
 
-	s = lmb_get_unreserved_size(&lmb, alloc_addr_a + 0x10000);
+	s = lmb_get_free_size(&lmb, alloc_addr_a + 0x10000);
 	ut_asserteq(s, alloc_addr_b - alloc_addr_a - 0x10000);
-	s = lmb_get_unreserved_size(&lmb, alloc_addr_a + 0x20000);
+	s = lmb_get_free_size(&lmb, alloc_addr_a + 0x20000);
 	ut_asserteq(s, alloc_addr_b - alloc_addr_a - 0x20000);
-	s = lmb_get_unreserved_size(&lmb, alloc_addr_b - 4);
+	s = lmb_get_free_size(&lmb, alloc_addr_b - 4);
 	ut_asserteq(s, 4);
 
-	s = lmb_get_unreserved_size(&lmb, alloc_addr_c + 0x10000);
+	s = lmb_get_free_size(&lmb, alloc_addr_c + 0x10000);
 	ut_asserteq(s, ram_end - alloc_addr_c - 0x10000);
-	s = lmb_get_unreserved_size(&lmb, alloc_addr_c + 0x20000);
+	s = lmb_get_free_size(&lmb, alloc_addr_c + 0x20000);
 	ut_asserteq(s, ram_end - alloc_addr_c - 0x20000);
-	s = lmb_get_unreserved_size(&lmb, ram_end - 4);
+	s = lmb_get_free_size(&lmb, ram_end - 4);
 	ut_asserteq(s, 4);
 
 	return 0;
 }
 
-static int lib_test_lmb_get_unreserved_size(struct unit_test_state *uts)
+static int lib_test_lmb_get_free_size(struct unit_test_state *uts)
 {
 	int ret;
 
@@ -597,5 +597,5 @@ static int lib_test_lmb_get_unreserved_size(struct unit_test_state *uts)
 	return test_get_unreserved_size(uts, 0xE0000000);
 }
 
-DM_TEST(lib_test_lmb_get_unreserved_size,
+DM_TEST(lib_test_lmb_get_free_size,
 	DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);

+ 27 - 27
tools/dtoc/test_dtoc.py

@@ -196,7 +196,7 @@ struct dtd_sandbox_spl_test_2 {
         with open(output) as infile:
             data = infile.read()
         self._CheckStrings(C_HEADER + '''
-static struct dtd_sandbox_spl_test dtv_spl_test = {
+static const struct dtd_sandbox_spl_test dtv_spl_test = {
 \t.bytearray\t\t= {0x6, 0x0, 0x0},
 \t.byteval\t\t= 0x5,
 \t.intval\t\t\t= 0x1,
@@ -214,7 +214,7 @@ U_BOOT_DEVICE(spl_test) = {
 \t.platdata_size\t= sizeof(dtv_spl_test),
 };
 
-static struct dtd_sandbox_spl_test dtv_spl_test2 = {
+static const struct dtd_sandbox_spl_test dtv_spl_test2 = {
 \t.bytearray\t\t= {0x1, 0x23, 0x34},
 \t.byteval\t\t= 0x8,
 \t.intval\t\t\t= 0x3,
@@ -230,7 +230,7 @@ U_BOOT_DEVICE(spl_test2) = {
 \t.platdata_size\t= sizeof(dtv_spl_test2),
 };
 
-static struct dtd_sandbox_spl_test dtv_spl_test3 = {
+static const struct dtd_sandbox_spl_test dtv_spl_test3 = {
 \t.stringarray\t\t= {"one", "", ""},
 };
 U_BOOT_DEVICE(spl_test3) = {
@@ -239,7 +239,7 @@ U_BOOT_DEVICE(spl_test3) = {
 \t.platdata_size\t= sizeof(dtv_spl_test3),
 };
 
-static struct dtd_sandbox_spl_test_2 dtv_spl_test4 = {
+static const struct dtd_sandbox_spl_test_2 dtv_spl_test4 = {
 };
 U_BOOT_DEVICE(spl_test4) = {
 \t.name\t\t= "sandbox_spl_test_2",
@@ -247,7 +247,7 @@ U_BOOT_DEVICE(spl_test4) = {
 \t.platdata_size\t= sizeof(dtv_spl_test4),
 };
 
-static struct dtd_sandbox_i2c_test dtv_i2c_at_0 = {
+static const struct dtd_sandbox_i2c_test dtv_i2c_at_0 = {
 };
 U_BOOT_DEVICE(i2c_at_0) = {
 \t.name\t\t= "sandbox_i2c_test",
@@ -255,7 +255,7 @@ U_BOOT_DEVICE(i2c_at_0) = {
 \t.platdata_size\t= sizeof(dtv_i2c_at_0),
 };
 
-static struct dtd_sandbox_pmic_test dtv_pmic_at_9 = {
+static const struct dtd_sandbox_pmic_test dtv_pmic_at_9 = {
 \t.low_power\t\t= true,
 \t.reg\t\t\t= {0x9, 0x0},
 };
@@ -287,7 +287,7 @@ struct dtd_target {
         with open(output) as infile:
             data = infile.read()
         self._CheckStrings(C_HEADER + '''
-static struct dtd_target dtv_phandle_target = {
+static const struct dtd_target dtv_phandle_target = {
 \t.intval\t\t\t= 0x0,
 };
 U_BOOT_DEVICE(phandle_target) = {
@@ -296,7 +296,7 @@ U_BOOT_DEVICE(phandle_target) = {
 \t.platdata_size\t= sizeof(dtv_phandle_target),
 };
 
-static struct dtd_target dtv_phandle2_target = {
+static const struct dtd_target dtv_phandle2_target = {
 \t.intval\t\t\t= 0x1,
 };
 U_BOOT_DEVICE(phandle2_target) = {
@@ -305,7 +305,7 @@ U_BOOT_DEVICE(phandle2_target) = {
 \t.platdata_size\t= sizeof(dtv_phandle2_target),
 };
 
-static struct dtd_target dtv_phandle3_target = {
+static const struct dtd_target dtv_phandle3_target = {
 \t.intval\t\t\t= 0x2,
 };
 U_BOOT_DEVICE(phandle3_target) = {
@@ -314,7 +314,7 @@ U_BOOT_DEVICE(phandle3_target) = {
 \t.platdata_size\t= sizeof(dtv_phandle3_target),
 };
 
-static struct dtd_source dtv_phandle_source = {
+static const struct dtd_source dtv_phandle_source = {
 \t.clocks\t\t\t= {
 \t\t\t{&dtv_phandle_target, {}},
 \t\t\t{&dtv_phandle2_target, {11}},
@@ -327,7 +327,7 @@ U_BOOT_DEVICE(phandle_source) = {
 \t.platdata_size\t= sizeof(dtv_phandle_source),
 };
 
-static struct dtd_source dtv_phandle_source2 = {
+static const struct dtd_source dtv_phandle_source2 = {
 \t.clocks\t\t\t= {
 \t\t\t{&dtv_phandle_target, {}},},
 };
@@ -363,7 +363,7 @@ struct dtd_target {
         with open(output) as infile:
             data = infile.read()
         self._CheckStrings(C_HEADER + '''
-static struct dtd_target dtv_phandle_target = {
+static const struct dtd_target dtv_phandle_target = {
 };
 U_BOOT_DEVICE(phandle_target) = {
 \t.name\t\t= "target",
@@ -371,7 +371,7 @@ U_BOOT_DEVICE(phandle_target) = {
 \t.platdata_size\t= sizeof(dtv_phandle_target),
 };
 
-static struct dtd_source dtv_phandle_source2 = {
+static const struct dtd_source dtv_phandle_source2 = {
 \t.clocks\t\t\t= {
 \t\t\t{&dtv_phandle_target, {}},},
 };
@@ -422,7 +422,7 @@ struct dtd_compat1 {
         with open(output) as infile:
             data = infile.read()
         self._CheckStrings(C_HEADER + '''
-static struct dtd_compat1 dtv_spl_test = {
+static const struct dtd_compat1 dtv_spl_test = {
 \t.intval\t\t\t= 0x1,
 };
 U_BOOT_DEVICE(spl_test) = {
@@ -456,7 +456,7 @@ struct dtd_test3 {
         with open(output) as infile:
             data = infile.read()
         self._CheckStrings(C_HEADER + '''
-static struct dtd_test1 dtv_test1 = {
+static const struct dtd_test1 dtv_test1 = {
 \t.reg\t\t\t= {0x1234, 0x5678},
 };
 U_BOOT_DEVICE(test1) = {
@@ -465,7 +465,7 @@ U_BOOT_DEVICE(test1) = {
 \t.platdata_size\t= sizeof(dtv_test1),
 };
 
-static struct dtd_test2 dtv_test2 = {
+static const struct dtd_test2 dtv_test2 = {
 \t.reg\t\t\t= {0x1234567890123456, 0x9876543210987654},
 };
 U_BOOT_DEVICE(test2) = {
@@ -474,7 +474,7 @@ U_BOOT_DEVICE(test2) = {
 \t.platdata_size\t= sizeof(dtv_test2),
 };
 
-static struct dtd_test3 dtv_test3 = {
+static const struct dtd_test3 dtv_test3 = {
 \t.reg\t\t\t= {0x1234567890123456, 0x9876543210987654, 0x2, 0x3},
 };
 U_BOOT_DEVICE(test3) = {
@@ -505,7 +505,7 @@ struct dtd_test2 {
         with open(output) as infile:
             data = infile.read()
         self._CheckStrings(C_HEADER + '''
-static struct dtd_test1 dtv_test1 = {
+static const struct dtd_test1 dtv_test1 = {
 \t.reg\t\t\t= {0x1234, 0x5678},
 };
 U_BOOT_DEVICE(test1) = {
@@ -514,7 +514,7 @@ U_BOOT_DEVICE(test1) = {
 \t.platdata_size\t= sizeof(dtv_test1),
 };
 
-static struct dtd_test2 dtv_test2 = {
+static const struct dtd_test2 dtv_test2 = {
 \t.reg\t\t\t= {0x12345678, 0x98765432, 0x2, 0x3},
 };
 U_BOOT_DEVICE(test2) = {
@@ -548,7 +548,7 @@ struct dtd_test3 {
         with open(output) as infile:
             data = infile.read()
         self._CheckStrings(C_HEADER + '''
-static struct dtd_test1 dtv_test1 = {
+static const struct dtd_test1 dtv_test1 = {
 \t.reg\t\t\t= {0x123400000000, 0x5678},
 };
 U_BOOT_DEVICE(test1) = {
@@ -557,7 +557,7 @@ U_BOOT_DEVICE(test1) = {
 \t.platdata_size\t= sizeof(dtv_test1),
 };
 
-static struct dtd_test2 dtv_test2 = {
+static const struct dtd_test2 dtv_test2 = {
 \t.reg\t\t\t= {0x1234567890123456, 0x98765432},
 };
 U_BOOT_DEVICE(test2) = {
@@ -566,7 +566,7 @@ U_BOOT_DEVICE(test2) = {
 \t.platdata_size\t= sizeof(dtv_test2),
 };
 
-static struct dtd_test3 dtv_test3 = {
+static const struct dtd_test3 dtv_test3 = {
 \t.reg\t\t\t= {0x1234567890123456, 0x98765432, 0x2, 0x3},
 };
 U_BOOT_DEVICE(test3) = {
@@ -600,7 +600,7 @@ struct dtd_test3 {
         with open(output) as infile:
             data = infile.read()
         self._CheckStrings(C_HEADER + '''
-static struct dtd_test1 dtv_test1 = {
+static const struct dtd_test1 dtv_test1 = {
 \t.reg\t\t\t= {0x1234, 0x567800000000},
 };
 U_BOOT_DEVICE(test1) = {
@@ -609,7 +609,7 @@ U_BOOT_DEVICE(test1) = {
 \t.platdata_size\t= sizeof(dtv_test1),
 };
 
-static struct dtd_test2 dtv_test2 = {
+static const struct dtd_test2 dtv_test2 = {
 \t.reg\t\t\t= {0x12345678, 0x9876543210987654},
 };
 U_BOOT_DEVICE(test2) = {
@@ -618,7 +618,7 @@ U_BOOT_DEVICE(test2) = {
 \t.platdata_size\t= sizeof(dtv_test2),
 };
 
-static struct dtd_test3 dtv_test3 = {
+static const struct dtd_test3 dtv_test3 = {
 \t.reg\t\t\t= {0x12345678, 0x9876543210987654, 0x2, 0x3},
 };
 U_BOOT_DEVICE(test3) = {
@@ -667,7 +667,7 @@ struct dtd_sandbox_spl_test {
         with open(output) as infile:
             data = infile.read()
         self._CheckStrings(C_HEADER + '''
-static struct dtd_sandbox_spl_test dtv_spl_test = {
+static const struct dtd_sandbox_spl_test dtv_spl_test = {
 \t.intval\t\t\t= 0x1,
 };
 U_BOOT_DEVICE(spl_test) = {
@@ -676,7 +676,7 @@ U_BOOT_DEVICE(spl_test) = {
 \t.platdata_size\t= sizeof(dtv_spl_test),
 };
 
-static struct dtd_sandbox_spl_test dtv_spl_test2 = {
+static const struct dtd_sandbox_spl_test dtv_spl_test2 = {
 \t.intarray\t\t= 0x5,
 };
 U_BOOT_DEVICE(spl_test2) = {