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@@ -70,7 +70,7 @@
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#define IFC_AMASK_MASK 0xFFFF0000
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#define IFC_AMASK_SHIFT 16
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#define IFC_AMASK(n) (IFC_AMASK_MASK << \
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- (__ilog2(n) - IFC_AMASK_SHIFT))
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+ (LOG2(n) - IFC_AMASK_SHIFT))
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/*
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* Chip Select Option Register IFC_NAND Machine
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@@ -111,7 +111,7 @@
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/* Pages Per Block */
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#define CSOR_NAND_PB_MASK 0x00000700
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#define CSOR_NAND_PB_SHIFT 8
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-#define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
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+#define CSOR_NAND_PB(n) ((LOG2(n) - 5) << CSOR_NAND_PB_SHIFT)
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/* Time for Read Enable High to Output High Impedance */
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#define CSOR_NAND_TRHZ_MASK 0x0000001C
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#define CSOR_NAND_TRHZ_SHIFT 2
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@@ -164,7 +164,7 @@
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/* GPCM Timeout Count */
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#define CSOR_GPCM_GPTO_MASK 0x0F000000
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#define CSOR_GPCM_GPTO_SHIFT 24
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-#define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
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+#define CSOR_GPCM_GPTO(n) ((LOG2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
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/* GPCM External Access Termination mode for read access */
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#define CSOR_GPCM_RGETA_EXT 0x00080000
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/* GPCM External Access Termination mode for write access */
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@@ -644,7 +644,7 @@ enum ifc_nand_fir_opcodes {
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*/
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#define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000
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#define IFC_NAND_NCR_FTOCNT_SHIFT 25
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-#define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT)
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+#define IFC_NAND_NCR_FTOCNT(n) ((LOG2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT)
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/*
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* NAND_AUTOBOOT_TRGR
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@@ -727,7 +727,7 @@ enum ifc_nand_fir_opcodes {
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/* Sequence Timeout Count */
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#define IFC_NORCR_STOCNT_MASK 0x000F0000
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#define IFC_NORCR_STOCNT_SHIFT 16
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-#define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
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+#define IFC_NORCR_STOCNT(n) ((LOG2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
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/*
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* GPCM Machine specific registers
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