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@@ -19,30 +19,36 @@
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#include <net.h>
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#include <config.h>
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+#include <phy.h>
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+#include <asm/fsl_enet.h>
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#define TSEC_SIZE 0x01000
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#define TSEC_MDIO_OFFSET 0x01000
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+#define CONFIG_SYS_MDIO_BASE_ADDR (TSEC_BASE_ADDR + 0x520)
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+
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+#define DEFAULT_MII_NAME "FSL_MDIO"
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+
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#define STD_TSEC_INFO(num) \
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{ \
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.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \
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- .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR), \
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- .miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR \
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+ .miiregs_sgmii = (struct tsec_mii_mng *)(CONFIG_SYS_MDIO_BASE_ADDR \
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+ (num - 1) * TSEC_MDIO_OFFSET), \
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.devname = CONFIG_TSEC##num##_NAME, \
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.phyaddr = TSEC##num##_PHY_ADDR, \
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- .flags = TSEC##num##_FLAGS \
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+ .flags = TSEC##num##_FLAGS, \
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+ .mii_devname = DEFAULT_MII_NAME \
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}
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#define SET_STD_TSEC_INFO(x, num) \
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{ \
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x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \
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- x.miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR); \
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- x.miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR \
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+ x.miiregs_sgmii = (struct tsec_mii_mng *)(CONFIG_SYS_MDIO_BASE_ADDR \
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+ (num - 1) * TSEC_MDIO_OFFSET); \
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x.devname = CONFIG_TSEC##num##_NAME; \
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x.phyaddr = TSEC##num##_PHY_ADDR; \
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x.flags = TSEC##num##_FLAGS;\
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+ x.mii_devname = DEFAULT_MII_NAME;\
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}
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#define MAC_ADDR_LEN 6
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@@ -51,8 +57,6 @@
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#define TSEC_TIMEOUT 1000
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#define TOUT_LOOP 1000000
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-#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */
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-
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/* TBI register addresses */
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#define TBI_CR 0x00
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#define TBI_SR 0x01
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@@ -96,204 +100,14 @@
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#define ECNTRL_INIT_SETTINGS 0x00001000
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#define ECNTRL_TBI_MODE 0x00000020
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+#define ECNTRL_REDUCED_MODE 0x00000010
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#define ECNTRL_R100 0x00000008
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+#define ECNTRL_REDUCED_MII_MODE 0x00000004
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#define ECNTRL_SGMII_MODE 0x00000002
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-#define miim_end -2
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-#define miim_read -1
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-
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#ifndef CONFIG_SYS_TBIPA_VALUE
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#define CONFIG_SYS_TBIPA_VALUE 0x1f
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#endif
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-#define MIIMCFG_INIT_VALUE 0x00000003
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-#define MIIMCFG_RESET 0x80000000
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-
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-#define MIIMIND_BUSY 0x00000001
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-#define MIIMIND_NOTVALID 0x00000004
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-
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-#define MIIM_CONTROL 0x00
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-#define MIIM_CONTROL_RESET 0x00009140
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-#define MIIM_CONTROL_INIT 0x00001140
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-#define MIIM_CONTROL_RESTART 0x00001340
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-#define MIIM_ANEN 0x00001000
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-
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-#define MIIM_CR 0x00
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-#define MIIM_CR_RST 0x00008000
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-#define MIIM_CR_INIT 0x00001000
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-
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-#define MIIM_STATUS 0x1
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-#define MIIM_STATUS_AN_DONE 0x00000020
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-#define MIIM_STATUS_LINK 0x0004
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-
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-#define MIIM_PHYIR1 0x2
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-#define MIIM_PHYIR2 0x3
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-
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-#define MIIM_ANAR 0x4
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-#define MIIM_ANAR_INIT 0x1e1
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-
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-#define MIIM_TBI_ANLPBPA 0x5
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-#define MIIM_TBI_ANLPBPA_HALF 0x00000040
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-#define MIIM_TBI_ANLPBPA_FULL 0x00000020
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-
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-#define MIIM_TBI_ANEX 0x6
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-#define MIIM_TBI_ANEX_NP 0x00000004
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-#define MIIM_TBI_ANEX_PRX 0x00000002
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-
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-#define MIIM_GBIT_CONTROL 0x9
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-#define MIIM_GBIT_CONTROL_INIT 0xe00
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-
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-#define MIIM_EXT_PAGE_ACCESS 0x1f
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-
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-/* Broadcom BCM54xx -- taken from linux sungem_phy */
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-#define MIIM_BCM54xx_AUXCNTL 0x18
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-#define MIIM_BCM54xx_AUXCNTL_ENCODE(val) ((val & 0x7) << 12)|(val & 0x7)
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-#define MIIM_BCM54xx_AUXSTATUS 0x19
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-#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700
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-#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8
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-
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-#define MIIM_BCM54XX_SHD 0x1c /* 0x1c shadow registers */
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-#define MIIM_BCM54XX_SHD_WRITE 0x8000
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-#define MIIM_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10)
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-#define MIIM_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0)
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-#define MIIM_BCM54XX_SHD_WR_ENCODE(val, data) \
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- (MIIM_BCM54XX_SHD_WRITE | MIIM_BCM54XX_SHD_VAL(val) | \
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- MIIM_BCM54XX_SHD_DATA(data))
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-
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-#define MIIM_BCM54XX_EXP_DATA 0x15 /* Expansion register data */
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-#define MIIM_BCM54XX_EXP_SEL 0x17 /* Expansion register select */
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-#define MIIM_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */
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-#define MIIM_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */
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-
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-/* Cicada Auxiliary Control/Status Register */
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-#define MIIM_CIS8201_AUX_CONSTAT 0x1c
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-#define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004
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-#define MIIM_CIS8201_AUXCONSTAT_DUPLEX 0x0020
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-#define MIIM_CIS8201_AUXCONSTAT_SPEED 0x0018
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-#define MIIM_CIS8201_AUXCONSTAT_GBIT 0x0010
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-#define MIIM_CIS8201_AUXCONSTAT_100 0x0008
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-
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-/* Cicada Extended Control Register 1 */
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-#define MIIM_CIS8201_EXT_CON1 0x17
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-#define MIIM_CIS8201_EXTCON1_INIT 0x0000
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-
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-/* Cicada 8204 Extended PHY Control Register 1 */
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-#define MIIM_CIS8204_EPHY_CON 0x17
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-#define MIIM_CIS8204_EPHYCON_INIT 0x0006
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-#define MIIM_CIS8204_EPHYCON_RGMII 0x1100
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-
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-/* Cicada 8204 Serial LED Control Register */
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-#define MIIM_CIS8204_SLED_CON 0x1b
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-#define MIIM_CIS8204_SLEDCON_INIT 0x1115
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-
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-#define MIIM_GBIT_CON 0x09
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-#define MIIM_GBIT_CON_ADVERT 0x0e00
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-
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-/* Entry for Vitesse VSC8244 regs starts here */
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-/* Vitesse VSC8244 Auxiliary Control/Status Register */
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-#define MIIM_VSC8244_AUX_CONSTAT 0x1c
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-#define MIIM_VSC8244_AUXCONSTAT_INIT 0x0000
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-#define MIIM_VSC8244_AUXCONSTAT_DUPLEX 0x0020
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-#define MIIM_VSC8244_AUXCONSTAT_SPEED 0x0018
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-#define MIIM_VSC8244_AUXCONSTAT_GBIT 0x0010
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-#define MIIM_VSC8244_AUXCONSTAT_100 0x0008
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-#define MIIM_CONTROL_INIT_LOOPBACK 0x4000
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-
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-/* Vitesse VSC8244 Extended PHY Control Register 1 */
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-#define MIIM_VSC8244_EPHY_CON 0x17
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-#define MIIM_VSC8244_EPHYCON_INIT 0x0006
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-
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-/* Vitesse VSC8244 Serial LED Control Register */
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-#define MIIM_VSC8244_LED_CON 0x1b
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-#define MIIM_VSC8244_LEDCON_INIT 0xF011
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-
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-/* Entry for Vitesse VSC8601 regs starts here (Not complete) */
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-/* Vitesse VSC8601 Extended PHY Control Register 1 */
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-#define MIIM_VSC8601_EPHY_CON 0x17
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-#define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120
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-#define MIIM_VSC8601_SKEW_CTRL 0x1c
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-
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-/* 88E1011 PHY Status Register */
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-#define MIIM_88E1011_PHY_STATUS 0x11
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-#define MIIM_88E1011_PHYSTAT_SPEED 0xc000
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-#define MIIM_88E1011_PHYSTAT_GBIT 0x8000
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-#define MIIM_88E1011_PHYSTAT_100 0x4000
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-#define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000
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-#define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800
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-#define MIIM_88E1011_PHYSTAT_LINK 0x0400
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-
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-#define MIIM_88E1011_PHY_SCR 0x10
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-#define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060
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-
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-/* 88E1111 PHY LED Control Register */
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-#define MIIM_88E1111_PHY_LED_CONTROL 24
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-#define MIIM_88E1111_PHY_LED_DIRECT 0x4100
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-#define MIIM_88E1111_PHY_LED_COMBINE 0x411C
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-
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-/* 88E1121 PHY LED Control Register */
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-#define MIIM_88E1121_PHY_LED_CTRL 16
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-#define MIIM_88E1121_PHY_LED_PAGE 3
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-#define MIIM_88E1121_PHY_LED_DEF 0x0030
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-
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-/* 88E1121 PHY IRQ Enable/Status Register */
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-#define MIIM_88E1121_PHY_IRQ_EN 18
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-#define MIIM_88E1121_PHY_IRQ_STATUS 19
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-
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-#define MIIM_88E1121_PHY_PAGE 22
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-
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-/* 88E1145 Extended PHY Specific Control Register */
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-#define MIIM_88E1145_PHY_EXT_CR 20
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-#define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
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-#define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
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-
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-#define MIIM_88E1145_PHY_PAGE 29
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-#define MIIM_88E1145_PHY_CAL_OV 30
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-
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-/* RTL8211B PHY Status Register */
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-#define MIIM_RTL8211B_PHY_STATUS 0x11
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-#define MIIM_RTL8211B_PHYSTAT_SPEED 0xc000
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-#define MIIM_RTL8211B_PHYSTAT_GBIT 0x8000
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-#define MIIM_RTL8211B_PHYSTAT_100 0x4000
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-#define MIIM_RTL8211B_PHYSTAT_DUPLEX 0x2000
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-#define MIIM_RTL8211B_PHYSTAT_SPDDONE 0x0800
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-#define MIIM_RTL8211B_PHYSTAT_LINK 0x0400
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-
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-/* DM9161 Control register values */
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-#define MIIM_DM9161_CR_STOP 0x0400
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-#define MIIM_DM9161_CR_RSTAN 0x1200
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-
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-#define MIIM_DM9161_SCR 0x10
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-#define MIIM_DM9161_SCR_INIT 0x0610
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-
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-/* DM9161 Specified Configuration and Status Register */
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-#define MIIM_DM9161_SCSR 0x11
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-#define MIIM_DM9161_SCSR_100F 0x8000
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-#define MIIM_DM9161_SCSR_100H 0x4000
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-#define MIIM_DM9161_SCSR_10F 0x2000
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-#define MIIM_DM9161_SCSR_10H 0x1000
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-
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-/* DM9161 10BT Configuration/Status */
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-#define MIIM_DM9161_10BTCSR 0x12
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-#define MIIM_DM9161_10BTCSR_INIT 0x7800
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-
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-/* LXT971 Status 2 registers */
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-#define MIIM_LXT971_SR2 0x11 /* Status Register 2 */
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-#define MIIM_LXT971_SR2_SPEED_MASK 0x4200
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-#define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */
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-#define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */
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-#define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */
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-#define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */
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-
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-/* DP83865 Control register values */
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-#define MIIM_DP83865_CR_INIT 0x9200
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-
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-/* DP83865 Link and Auto-Neg Status Register */
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-#define MIIM_DP83865_LANR 0x11
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-#define MIIM_DP83865_SPD_MASK 0x0018
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-#define MIIM_DP83865_SPD_1000 0x0010
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-#define MIIM_DP83865_SPD_100 0x0008
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-#define MIIM_DP83865_DPX_FULL 0x0002
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-
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-#define MIIM_READ_COMMAND 0x00000001
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#define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
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@@ -467,22 +281,6 @@ typedef struct tsec_hash_regs
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uint res2[24];
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} tsec_hash_t;
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-typedef struct tsec_mdio {
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- uint res1[4];
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- uint ieventm;
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- uint imaskm;
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- uint res2;
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- uint emapm;
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- uint res3[320];
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- uint miimcfg; /* MII Management: Configuration */
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- uint miimcom; /* MII Management: Command */
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- uint miimadd; /* MII Management: Address */
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- uint miimcon; /* MII Management: Control */
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- uint miimstat; /* MII Management: Status */
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- uint miimind; /* MII Management: Indicators */
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- uint res4[690];
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-} tsec_mdio_t;
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-
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typedef struct tsec
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{
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/* General Control and Status Registers (0x2_n000) */
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@@ -578,79 +376,29 @@ typedef struct tsec
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uint resc00[256];
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} tsec_t;
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-#define TSEC_GIGABIT (1)
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+#define TSEC_GIGABIT (1 << 0)
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-/* This flag currently only has
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- * meaning if we're using the eTSEC */
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+/* These flags currently only have meaning if we're using the eTSEC */
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#define TSEC_REDUCED (1 << 1) /* MAC-PHY interface uses RGMII */
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#define TSEC_SGMII (1 << 2) /* MAC-PHY interface uses SGMII */
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-#define TSEC_FIBER (1 << 3) /* PHY uses fiber, eg 1000 Base-X */
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struct tsec_private {
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tsec_t *regs;
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- tsec_mdio_t *phyregs;
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- tsec_mdio_t *phyregs_sgmii;
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- struct phy_info *phyinfo;
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+ struct tsec_mii_mng *phyregs_sgmii;
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+ struct phy_device *phydev;
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+ phy_interface_t interface;
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+ struct mii_dev *bus;
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uint phyaddr;
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+ char mii_devname[16];
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u32 flags;
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- uint link;
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- uint duplexity;
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- uint speed;
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-};
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-
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-
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-/*
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- * struct phy_cmd: A command for reading or writing a PHY register
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- *
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- * mii_reg: The register to read or write
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- *
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- * mii_data: For writes, the value to put in the register.
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- * A value of -1 indicates this is a read.
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- *
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- * funct: A function pointer which is invoked for each command.
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- * For reads, this function will be passed the value read
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- * from the PHY, and process it.
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- * For writes, the result of this function will be written
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- * to the PHY register
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- */
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-struct phy_cmd {
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- uint mii_reg;
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- uint mii_data;
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- uint (*funct) (uint mii_reg, struct tsec_private * priv);
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-};
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-
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-/* struct phy_info: a structure which defines attributes for a PHY
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- *
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- * id will contain a number which represents the PHY. During
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- * startup, the driver will poll the PHY to find out what its
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- * UID--as defined by registers 2 and 3--is. The 32-bit result
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- * gotten from the PHY will be shifted right by "shift" bits to
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- * discard any bits which may change based on revision numbers
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- * unimportant to functionality
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- *
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- * The struct phy_cmd entries represent pointers to an arrays of
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- * commands which tell the driver what to do to the PHY.
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- */
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-struct phy_info {
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- uint id;
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|
|
- char *name;
|
|
|
- uint shift;
|
|
|
- /* Called to configure the PHY, and modify the controller
|
|
|
- * based on the results */
|
|
|
- struct phy_cmd *config;
|
|
|
-
|
|
|
- /* Called when starting up the controller */
|
|
|
- struct phy_cmd *startup;
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|
|
-
|
|
|
- /* Called when bringing down the controller */
|
|
|
- struct phy_cmd *shutdown;
|
|
|
};
|
|
|
|
|
|
struct tsec_info_struct {
|
|
|
tsec_t *regs;
|
|
|
- tsec_mdio_t *miiregs;
|
|
|
- tsec_mdio_t *miiregs_sgmii;
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|
|
+ struct tsec_mii_mng *miiregs_sgmii;
|
|
|
char *devname;
|
|
|
+ char *mii_devname;
|
|
|
+ phy_interface_t interface;
|
|
|
unsigned int phyaddr;
|
|
|
u32 flags;
|
|
|
};
|