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@@ -806,12 +806,30 @@ static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
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{
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}
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-static void fsl_ifc_sram_init(void)
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+static int fsl_ifc_sram_init(uint32_t ver)
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{
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struct fsl_ifc *ifc = ifc_ctrl->regs;
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uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0;
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+ uint32_t ncfgr = 0;
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long long end_tick;
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+ if (ver > FSL_IFC_V1_1_0) {
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+ ncfgr = ifc_in32(&ifc->ifc_nand.ncfgr);
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+ ifc_out32(&ifc->ifc_nand.ncfgr, ncfgr | IFC_NAND_SRAM_INIT_EN);
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+
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+ /* wait for SRAM_INIT bit to be clear or timeout */
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+ end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
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+ while (end_tick > get_ticks()) {
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+ ifc_ctrl->status =
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+ ifc_in32(&ifc->ifc_nand.nand_evter_stat);
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+
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+ if (!(ifc_ctrl->status & IFC_NAND_SRAM_INIT_EN))
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+ return 0;
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+ }
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+ printf("fsl-ifc: Failed to Initialise SRAM\n");
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+ return 1;
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+ }
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+
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cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT;
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/* Save CSOR and CSOR_ext */
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@@ -854,11 +872,18 @@ static void fsl_ifc_sram_init(void)
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break;
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}
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+ if (ifc_ctrl->status != IFC_NAND_EVTER_STAT_OPC) {
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+ printf("fsl-ifc: Failed to Initialise SRAM\n");
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+ return 1;
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+ }
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+
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ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
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/* Restore CSOR and CSOR_ext */
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ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor);
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ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext);
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+
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+ return 0;
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}
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static int fsl_ifc_chip_init(int devnum, u8 *addr)
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@@ -868,7 +893,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
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struct fsl_ifc_mtd *priv;
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struct nand_ecclayout *layout;
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uint32_t cspr = 0, csor = 0, ver = 0;
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- int ret;
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+ int ret = 0;
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if (!ifc_ctrl) {
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fsl_ifc_ctrl_init();
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@@ -1010,8 +1035,10 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
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}
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ver = ifc_in32(&ifc_ctrl->regs->ifc_rev);
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- if (ver == FSL_IFC_V1_1_0)
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- fsl_ifc_sram_init();
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+ if (ver >= FSL_IFC_V1_1_0)
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+ ret = fsl_ifc_sram_init(ver);
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+ if (ret)
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+ return ret;
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ret = nand_scan_ident(mtd, 1, NULL);
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if (ret)
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