Overview
--------
The T1040RDB is a Freescale reference board that hosts the T1040 SoC
(and variants). Variants inclued T1042 presonality of T1040, in which
case T1040RDB can also be called T1042RDB.

The T1042RDB is a Freescale reference board that hosts the T1042 SoC
(and variants). The board is similar to T1040RDB, T1040 is a reduced
personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch).

The T1042RDB_PI is a Freescale reference board that hosts the T1042 SoC.
(a personality of T1040 SoC). The board is similar to T1040RDB but is
designed specially with low power features targeted for Printing Image Market.

The T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
The board is re-designed T1040RDB board with following changes :
    - Support of DDR4 memory and some enhancements

The T1042D4RDB is a Freescale reference board that hosts the T1042 SoC.
The board is re-designed T1040RDB board with following changes :
    - Support of DDR4 memory
    - Support for 0x86 serdes protocol which can support following interfaces
        - 2 RGMII's on DTSEC4, DTSEC5
        - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3

Basic difference's among T1040RDB, T1042RDB_PI, T1042RDB
-------------------------------------------------------------------------
Board		Si		Protocol		Targeted Market
-------------------------------------------------------------------------
T1040RDB	T1040		0x66                    Networking
T1040RDB	T1042		0x86                    Networking
T1042RDB_PI	T1042		0x06                    Printing & Imaging
T1040D4RDB	T1040		0x66                    Networking
T1042D4RDB	T1042		0x86                    Networking


T1040 SoC Overview
------------------
The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
processor cores with high-performance data path acceleration architecture
and network peripheral interfaces required for networking & telecommunications.

The T1040/T1042 SoC includes the following function and features:

 - Four e5500 cores, each with a private 256 KB L2 cache
 - 256 KB shared L3 CoreNet platform cache (CPC)
 - Interconnect CoreNet platform
 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
   support
 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
 for the following functions:
    -  Packet parsing, classification, and distribution
    -  Queue management for scheduling, packet sequencing, and congestion
       management
    -  Cryptography Acceleration (SEC 5.0)
    - RegEx Pattern Matching Acceleration (PME 2.2)
    - IEEE Std 1588 support
    - Hardware buffer management for buffer allocation and deallocation
 - Ethernet interfaces
    - Integrated 8-port Gigabit Ethernet switch (T1040 only)
    - Four 1 Gbps Ethernet controllers
 - Two RGMII interfaces or one RGMII and one MII interfaces
 - High speed peripheral interfaces
   - Four PCI Express 2.0 controllers running at up to 5 GHz
   - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
   - Upto two QSGMII interface
   - Upto six SGMII interface supporting 1000 Mbps
   - One SGMII interface supporting upto 2500 Mbps
 - Additional peripheral interfaces
   - Two USB 2.0 controllers with integrated PHY
   - SD/eSDHC/eMMC
   - eSPI controller
   - Four I2C controllers
   - Four UARTs
   - Four GPIO controllers
   - Integrated flash controller (IFC)
   - LCD and HDMI interface (DIU) with 12 bit dual data rate
   - TDM interface
 - Multicore programmable interrupt controller (PIC)
 - Two 8-channel DMA engines
 - Single source clocking implementation
 - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)

T1040 SoC Personalities
-------------------------
T1022 Personality:
T1022 is a reduced personality of T1040 with less core/clusters.

T1042 Personality:
T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit
Ethernet switch. Rest of the blocks are same as T1040


T1040RDB board Overview
-------------------------
 - SERDES Connections, 8 lanes information:
	1: None
	2: SGMII
	3: QSGMII
	4: QSGMII
	5: PCIe1 x1 slot
	6: mini PCIe connector
	7: mini PCIe connector
	8: SATA connector
 - DDR Controller
     - Supports rates of up to 1600 MHz data-rate
     - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
 - IFC/Local Bus
     - NAND flash: 1GB 8-bit NAND flash
     - NOR: 128MB 16-bit NOR Flash
 - Ethernet
     - Two on-board RGMII 10/100/1G ethernet ports.
 - CPLD
 - Clocks
     - System and DDR clock (SYSCLK, “DDRCLK”)
     - SERDES clocks
 - Power Supplies
 - USB
     - Supports two USB 2.0 ports with integrated PHYs
     - Two type A ports with 5V@1.5A per port.
 - SDHC
     - SDHC/SDXC connector
 - SPI
    -  On-board 64MB SPI flash
 - Other IO
    - Two Serial ports
    - Four I2C ports

T1042RDB_PI board Overview
-------------------------
 - SERDES Connections, 8 lanes information:
	1, 2, 3, 4 : PCIe x4 slot
	5: mini PCIe connector
	6: mini PCIe connector
	7: NA
	8: SATA connector
 - DDR Controller
     - Supports rates of up to 1600 MHz data-rate
     - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
 - IFC/Local Bus
     - NAND flash: 1GB 8-bit NAND flash
     - NOR: 128MB 16-bit NOR Flash
 - Ethernet
     - Two on-board RGMII 10/100/1G ethernet ports.
 - CPLD
 - Clocks
     - System and DDR clock (SYSCLK, “DDRCLK”)
     - SERDES clocks
 - Video
     - DIU supports video at up to 1280x1024x32bpp
 - Power Supplies
 - USB
     - Supports two USB 2.0 ports with integrated PHYs
     - Two type A ports with 5V@1.5A per port.
 - SDHC
     - SDHC/SDXC connector
 - SPI
    -  On-board 64MB SPI flash
 - Other IO
    - Two Serial ports
    - Four I2C ports

Memory map
-----------
The addresses in brackets are physical addresses.

Start Address  End Address      Description                     Size
0xF_FFDF_0000  0xF_FFDF_0FFF    IFC - CPLD                      4KB
0xF_FF80_0000  0xF_FF80_FFFF    IFC - NAND Flash                64KB
0xF_FE00_0000  0xF_FEFF_FFFF    CCSRBAR                         16MB
0xF_F803_0000  0xF_F803_FFFF    PCI Express 4 I/O Space         64KB
0xF_F802_0000  0xF_F802_FFFF    PCI Express 3 I/O Space	        64KB
0xF_F801_0000  0xF_F801_FFFF    PCI Express 2 I/O Space         64KB
0xF_F800_0000  0xF_F800_FFFF    PCI Express 1 I/O Space	        64KB
0xF_F600_0000  0xF_F7FF_FFFF    Queue manager software portal   32MB
0xF_F400_0000  0xF_F5FF_FFFF    Buffer manager software portal  32MB
0xF_E800_0000  0xF_EFFF_FFFF    IFC - NOR Flash                 128MB
0xF_0000_0000  0xF_003F_FFFF    DCSR                            4MB
0xC_3000_0000  0xC_3FFF_FFFF    PCI Express 4 Mem Space         256MB
0xC_2000_0000  0xC_2FFF_FFFF    PCI Express 3 Mem Space         256MB
0xC_1000_0000  0xC_1FFF_FFFF    PCI Express 2 Mem Space         256MB
0xC_0000_0000  0xC_0FFF_FFFF    PCI Express 1 Mem Space         256MB
0x0_0000_0000  0x0_ffff_ffff    DDR                             2GB


NOR Flash memory Map
---------------------
 Start          End             Definition                       Size
0xEFF40000      0xEFFFFFFF      U-Boot (current bank)            768KB
0xEFF20000      0xEFF3FFFF      U-Boot env (current bank)        128KB
0xEFF00000      0xEFF1FFFF      FMAN Ucode (current bank)        128KB
0xED300000      0xEFEFFFFF      rootfs (alt bank)                44MB
0xEC800000      0xEC8FFFFF      Hardware device tree (alt bank)  1MB
0xEC020000      0xEC7FFFFF      Linux.uImage (alt bank)          7MB + 875KB
0xEC000000      0xEC01FFFF      RCW (alt bank)                   128KB
0xEBF40000      0xEBFFFFFF      U-Boot (alt bank)                768KB
0xEBF20000      0xEBF3FFFF      U-Boot env (alt bank)            128KB
0xEBF00000      0xEBF1FFFF      FMAN ucode (alt bank)            128KB
0xE9300000      0xEBEFFFFF      rootfs (current bank)            44MB
0xE8800000      0xE88FFFFF      Hardware device tree (cur bank)  11MB + 512KB
0xE8020000      0xE86FFFFF      Linux.uImage (current bank)      7MB + 875KB
0xE8000000      0xE801FFFF      RCW (current bank)               128KB


Various Software configurations/environment variables/commands
--------------------------------------------------------------
The below commands apply to the board

1. U-Boot environment variable hwconfig
   The default hwconfig is:
	hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:
					dr_mode=host,phy_type=utmi
   Note: For USB gadget set "dr_mode=peripheral"

2. FMAN Ucode versions
   fsl_fman_ucode_t1040.bin

3. Switching to alternate bank
   Commands for switching to alternate bank.

	1. To change from vbank0 to vbank4
		=> cpld reset altbank (it will boot using vbank4)

	2.To change from vbank4 to vbank0
		=> cpld reset (it will boot using vbank0)

NAND boot with 2 Stage boot loader
----------------------------------
PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
SPL further initialise DDR using SPD and environment variables and copy
U-Boot(768 KB) from flash to DDR.
Finally SPL transer control to U-Boot for futher booting.

SPL has following features:
 - Executes within 256K
 - No relocation required

 Run time view of SPL framework during  boot :-
 -----------------------------------------------
 Area        | Address                         |
-----------------------------------------------
 Secure boot | 0xFFFC0000 (32KB)               |
 headers     |                                 |
 -----------------------------------------------
 GD, BD      | 0xFFFC8000 (4KB)                |
 -----------------------------------------------
 ENV         | 0xFFFC9000 (8KB)                |
 -----------------------------------------------
 HEAP        | 0xFFFCB000 (30KB)               |
 -----------------------------------------------
 STACK       | 0xFFFD8000 (22KB)               |
 -----------------------------------------------
 U-Boot SPL  | 0xFFFD8000 (160KB)              |
 -----------------------------------------------

NAND Flash memory Map on T104xRDB
------------------------------------------
 Start		 End		Definition			Size
0x000000	0x0FFFFF	U-Boot                          1MB
0x180000	0x19FFFF	U-Boot env                      128KB
0x280000	0x29FFFF	FMAN Ucode                      128KB
0x380000	0x39FFFF	QE Firmware                     128KB

SD Card memory Map on T104xRDB
------------------------------------------
 Block		#blocks		Definition			Size
0x008		2048		U-Boot                          1MB
0x800		0024		U-Boot env                      8KB
0x820		0256		FMAN Ucode                      128KB
0x920		0256		QE Firmware                     128KB

SPI Flash memory Map on T104xRDB
------------------------------------------
 Start		 End		Definition			Size
0x000000	0x0FFFFF	U-Boot                          1MB
0x100000	0x101FFF	U-Boot env                      8KB
0x110000	0x12FFFF	FMAN Ucode                      128KB
0x130000	0x14FFFF	QE Firmware                     128KB

Please note QE Firmware is only valid for T1040RDB


Switch Settings for T104xRDB boards: (ON is 0, OFF is 1)
==========================================================
NOR boot SW setting:
SW1: 00010011
SW2: 10111011
SW3: 11100001

NAND boot SW setting:
SW1: 10001000
SW2: 00111011
SW3: 11110001

SPI boot SW setting:
SW1: 00100010
SW2: 10111011
SW3: 11100001

SD boot SW setting:
SW1: 00100000
SW2: 00111011
SW3: 11100001

Switch Settings for T104xD4RDB boards: (ON is 0, OFF is 1)
=============================================================
NOR boot SW setting:
SW1: 00010011
SW2: 10111001
SW3: 11100001

NAND boot SW setting:
SW1: 10001000
SW2: 00111001
SW3: 11110001

SPI boot SW setting:
SW1: 00100010
SW2: 10111001
SW3: 11100001

SD boot SW setting:
SW1: 00100000
SW2: 00111001
SW3: 11100001

PBL-based image generation
==========================
Changes only the required register bit in in PBI commands.

Provides reference code which might needs some
modification as per requirement.
example:
By default PBI_SRC=14 (which is for IFC-NAND/NOR) in rcw.cfg file
which needs to be changed for SPI and SD.

For SD-boot
==============
1. Set RCW[192:195], PBI_SRC bits as 6 in RCW file (t1040d4_rcw.cfg type files)

example:
 RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg

Change
66000002 40000002 ec027000 01000000
to
66000002 40000002 6c027000 01000000

2. SD does not support flush so remove flush from pbl, make changes in
   tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000
   with 0x091380c0

For SPI-boot
==============
1. Set RCW[192:195], PBI_SRC bits as 5 in RCW file (t1040d4_rcw.cfg type files)

example:
 RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg

Change
66000002 40000002 ec027000 01000000
to
66000002 40000002 5c027000 01000000

2. SPI does not support flush so remove flush from pbl, make changes in
   tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000
   with 0x091380c0

Device tree support and how to enable it for different configs
--------------------------------------------------------------
Device tree support is available for t1042d4rdb for below mentioned boot,
1. NOR Boot
2. NAND Boot
3. SD Boot
4. SPIFLASH Boot

To enable device tree support for other boot, below configs need to be
enabled in relative defconfig file,
1. CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" (Change default device tree name if required)
2. CONFIG_OF_CONTROL
3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
   CONFIG_RESET_VECTOR_ADDRESS - 0xffc

If device tree support is enabled in defconfig,
1. use 'u-boot-with-dtb.bin' for NOR boot.
2. use 'u-boot-with-spl-pbl.bin' for other boot.
