memory.c 36 KB

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  1. /*
  2. * memory handling
  3. * (c) Copyright Dave, 2004
  4. * (C) notaz, 2006-2010
  5. *
  6. * This work is licensed under the terms of MAME license.
  7. * See COPYING file in the top-level directory.
  8. */
  9. #include "pico_int.h"
  10. #include "memory.h"
  11. #include "sound/ym2612.h"
  12. #include "sound/sn76496.h"
  13. extern unsigned int lastSSRamWrite; // used by serial eeprom code
  14. uptr m68k_read8_map [0x1000000 >> M68K_MEM_SHIFT];
  15. uptr m68k_read16_map [0x1000000 >> M68K_MEM_SHIFT];
  16. uptr m68k_write8_map [0x1000000 >> M68K_MEM_SHIFT];
  17. uptr m68k_write16_map[0x1000000 >> M68K_MEM_SHIFT];
  18. static void xmap_set(uptr *map, int shift, int start_addr, int end_addr,
  19. const void *func_or_mh, int is_func)
  20. {
  21. #ifdef __clang__
  22. // workaround bug (segfault) in
  23. // Apple LLVM version 4.2 (clang-425.0.27) (based on LLVM 3.2svn)
  24. volatile
  25. #endif
  26. uptr addr = (uptr)func_or_mh;
  27. int mask = (1 << shift) - 1;
  28. int i;
  29. if ((start_addr & mask) != 0 || (end_addr & mask) != mask) {
  30. elprintf(EL_STATUS|EL_ANOMALY, "xmap_set: tried to map bad range: %06x-%06x",
  31. start_addr, end_addr);
  32. return;
  33. }
  34. if (addr & 1) {
  35. elprintf(EL_STATUS|EL_ANOMALY, "xmap_set: ptr is not aligned: %08lx", addr);
  36. return;
  37. }
  38. if (!is_func)
  39. addr -= start_addr;
  40. for (i = start_addr >> shift; i <= end_addr >> shift; i++) {
  41. map[i] = addr >> 1;
  42. if (is_func)
  43. map[i] |= MAP_FLAG;
  44. }
  45. }
  46. void z80_map_set(uptr *map, int start_addr, int end_addr,
  47. const void *func_or_mh, int is_func)
  48. {
  49. xmap_set(map, Z80_MEM_SHIFT, start_addr, end_addr, func_or_mh, is_func);
  50. }
  51. void cpu68k_map_set(uptr *map, int start_addr, int end_addr,
  52. const void *func_or_mh, int is_func)
  53. {
  54. xmap_set(map, M68K_MEM_SHIFT, start_addr, end_addr, func_or_mh, is_func);
  55. #ifdef EMU_F68K
  56. // setup FAME fetchmap
  57. if (!is_func)
  58. {
  59. int shiftout = 24 - FAMEC_FETCHBITS;
  60. int i = start_addr >> shiftout;
  61. uptr base = (uptr)func_or_mh - (i << shiftout);
  62. for (; i <= (end_addr >> shiftout); i++)
  63. PicoCpuFM68k.Fetch[i] = base;
  64. }
  65. #endif
  66. }
  67. // more specialized/optimized function (does same as above)
  68. void cpu68k_map_all_ram(int start_addr, int end_addr, void *ptr, int is_sub)
  69. {
  70. uptr *r8map, *r16map, *w8map, *w16map;
  71. uptr addr = (uptr)ptr;
  72. int shift = M68K_MEM_SHIFT;
  73. int i;
  74. if (!is_sub) {
  75. r8map = m68k_read8_map;
  76. r16map = m68k_read16_map;
  77. w8map = m68k_write8_map;
  78. w16map = m68k_write16_map;
  79. } else {
  80. r8map = s68k_read8_map;
  81. r16map = s68k_read16_map;
  82. w8map = s68k_write8_map;
  83. w16map = s68k_write16_map;
  84. }
  85. addr -= start_addr;
  86. addr >>= 1;
  87. for (i = start_addr >> shift; i <= end_addr >> shift; i++)
  88. r8map[i] = r16map[i] = w8map[i] = w16map[i] = addr;
  89. #ifdef EMU_F68K
  90. // setup FAME fetchmap
  91. {
  92. M68K_CONTEXT *ctx = is_sub ? &PicoCpuFS68k : &PicoCpuFM68k;
  93. int shiftout = 24 - FAMEC_FETCHBITS;
  94. i = start_addr >> shiftout;
  95. addr = (uptr)ptr - (i << shiftout);
  96. for (; i <= (end_addr >> shiftout); i++)
  97. ctx->Fetch[i] = addr;
  98. }
  99. #endif
  100. }
  101. static u32 m68k_unmapped_read8(u32 a)
  102. {
  103. elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
  104. return 0; // assume pulldown, as if MegaCD2 was attached
  105. }
  106. static u32 m68k_unmapped_read16(u32 a)
  107. {
  108. elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
  109. return 0;
  110. }
  111. static void m68k_unmapped_write8(u32 a, u32 d)
  112. {
  113. elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
  114. }
  115. static void m68k_unmapped_write16(u32 a, u32 d)
  116. {
  117. elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
  118. }
  119. void m68k_map_unmap(int start_addr, int end_addr)
  120. {
  121. #ifdef __clang__
  122. // workaround bug (segfault) in
  123. // Apple LLVM version 4.2 (clang-425.0.27) (based on LLVM 3.2svn)
  124. volatile
  125. #endif
  126. uptr addr;
  127. int shift = M68K_MEM_SHIFT;
  128. int i;
  129. addr = (uptr)m68k_unmapped_read8;
  130. for (i = start_addr >> shift; i <= end_addr >> shift; i++)
  131. m68k_read8_map[i] = (addr >> 1) | MAP_FLAG;
  132. addr = (uptr)m68k_unmapped_read16;
  133. for (i = start_addr >> shift; i <= end_addr >> shift; i++)
  134. m68k_read16_map[i] = (addr >> 1) | MAP_FLAG;
  135. addr = (uptr)m68k_unmapped_write8;
  136. for (i = start_addr >> shift; i <= end_addr >> shift; i++)
  137. m68k_write8_map[i] = (addr >> 1) | MAP_FLAG;
  138. addr = (uptr)m68k_unmapped_write16;
  139. for (i = start_addr >> shift; i <= end_addr >> shift; i++)
  140. m68k_write16_map[i] = (addr >> 1) | MAP_FLAG;
  141. }
  142. #ifndef _ASM_MEMORY_C
  143. MAKE_68K_READ8(m68k_read8, m68k_read8_map)
  144. MAKE_68K_READ16(m68k_read16, m68k_read16_map)
  145. MAKE_68K_READ32(m68k_read32, m68k_read16_map)
  146. MAKE_68K_WRITE8(m68k_write8, m68k_write8_map)
  147. MAKE_68K_WRITE16(m68k_write16, m68k_write16_map)
  148. MAKE_68K_WRITE32(m68k_write32, m68k_write16_map)
  149. #endif
  150. // -----------------------------------------------------------------
  151. static u32 ym2612_read_local_68k(void);
  152. static int ym2612_write_local(u32 a, u32 d, int is_from_z80);
  153. static void z80_mem_setup(void);
  154. #ifdef _ASM_MEMORY_C
  155. u32 PicoRead8_sram(u32 a);
  156. u32 PicoRead16_sram(u32 a);
  157. #endif
  158. #ifdef EMU_CORE_DEBUG
  159. u32 lastread_a, lastread_d[16]={0,}, lastwrite_cyc_d[16]={0,}, lastwrite_mus_d[16]={0,};
  160. int lrp_cyc=0, lrp_mus=0, lwp_cyc=0, lwp_mus=0;
  161. extern unsigned int ppop;
  162. #endif
  163. #ifdef IO_STATS
  164. void log_io(unsigned int addr, int bits, int rw);
  165. #elif defined(_MSC_VER)
  166. #define log_io
  167. #else
  168. #define log_io(...)
  169. #endif
  170. #if defined(EMU_C68K)
  171. void cyclone_crashed(u32 pc, struct Cyclone *context)
  172. {
  173. elprintf(EL_STATUS|EL_ANOMALY, "%c68k crash detected @ %06x",
  174. context == &PicoCpuCM68k ? 'm' : 's', pc);
  175. context->membase = (u32)Pico.rom;
  176. context->pc = (u32)Pico.rom + Pico.romsize;
  177. }
  178. #endif
  179. // -----------------------------------------------------------------
  180. // memmap helpers
  181. static u32 read_pad_3btn(int i, u32 out_bits)
  182. {
  183. u32 pad = ~PicoIn.padInt[i]; // Get inverse of pad MXYZ SACB RLDU
  184. u32 value;
  185. if (out_bits & 0x40) // TH
  186. value = pad & 0x3f; // ?1CB RLDU
  187. else
  188. value = ((pad & 0xc0) >> 2) | (pad & 3); // ?0SA 00DU
  189. value |= out_bits & 0x40;
  190. return value;
  191. }
  192. static u32 read_pad_6btn(int i, u32 out_bits)
  193. {
  194. u32 pad = ~PicoIn.padInt[i]; // Get inverse of pad MXYZ SACB RLDU
  195. int phase = Pico.m.padTHPhase[i];
  196. u32 value;
  197. if (phase == 2 && !(out_bits & 0x40)) {
  198. value = (pad & 0xc0) >> 2; // ?0SA 0000
  199. goto out;
  200. }
  201. else if(phase == 3) {
  202. if (out_bits & 0x40)
  203. return (pad & 0x30) | ((pad >> 8) & 0xf); // ?1CB MXYZ
  204. else
  205. return ((pad & 0xc0) >> 2) | 0x0f; // ?0SA 1111
  206. goto out;
  207. }
  208. if (out_bits & 0x40) // TH
  209. value = pad & 0x3f; // ?1CB RLDU
  210. else
  211. value = ((pad & 0xc0) >> 2) | (pad & 3); // ?0SA 00DU
  212. out:
  213. value |= out_bits & 0x40;
  214. return value;
  215. }
  216. static u32 read_nothing(int i, u32 out_bits)
  217. {
  218. return 0xff;
  219. }
  220. typedef u32 (port_read_func)(int index, u32 out_bits);
  221. static port_read_func *port_readers[3] = {
  222. read_pad_3btn,
  223. read_pad_3btn,
  224. read_nothing
  225. };
  226. static NOINLINE u32 port_read(int i)
  227. {
  228. u32 data_reg = PicoMem.ioports[i + 1];
  229. u32 ctrl_reg = PicoMem.ioports[i + 4] | 0x80;
  230. u32 in, out;
  231. out = data_reg & ctrl_reg;
  232. out |= 0x7f & ~ctrl_reg; // pull-ups
  233. in = port_readers[i](i, out);
  234. return (in & ~ctrl_reg) | (data_reg & ctrl_reg);
  235. }
  236. void PicoSetInputDevice(int port, enum input_device device)
  237. {
  238. port_read_func *func;
  239. if (port < 0 || port > 2)
  240. return;
  241. switch (device) {
  242. case PICO_INPUT_PAD_3BTN:
  243. func = read_pad_3btn;
  244. break;
  245. case PICO_INPUT_PAD_6BTN:
  246. func = read_pad_6btn;
  247. break;
  248. default:
  249. func = read_nothing;
  250. break;
  251. }
  252. port_readers[port] = func;
  253. }
  254. NOINLINE u32 io_ports_read(u32 a)
  255. {
  256. u32 d;
  257. a = (a>>1) & 0xf;
  258. switch (a) {
  259. case 0: d = Pico.m.hardware; break; // Hardware value (Version register)
  260. case 1: d = port_read(0); break;
  261. case 2: d = port_read(1); break;
  262. case 3: d = port_read(2); break;
  263. default: d = PicoMem.ioports[a]; break; // IO ports can be used as RAM
  264. }
  265. return d;
  266. }
  267. NOINLINE void io_ports_write(u32 a, u32 d)
  268. {
  269. a = (a>>1) & 0xf;
  270. // 6 button gamepad: if TH went from 0 to 1, gamepad changes state
  271. if (1 <= a && a <= 2)
  272. {
  273. Pico.m.padDelay[a - 1] = 0;
  274. if (!(PicoMem.ioports[a] & 0x40) && (d & 0x40))
  275. Pico.m.padTHPhase[a - 1]++;
  276. }
  277. // certain IO ports can be used as RAM
  278. PicoMem.ioports[a] = d;
  279. }
  280. static int z80_cycles_from_68k(void)
  281. {
  282. int m68k_cnt = SekCyclesDone() - Pico.t.m68c_frame_start;
  283. return cycles_68k_to_z80(m68k_cnt);
  284. }
  285. void NOINLINE ctl_write_z80busreq(u32 d)
  286. {
  287. d&=1; d^=1;
  288. elprintf(EL_BUSREQ, "set_zrun: %i->%i [%u] @%06x", Pico.m.z80Run, d, SekCyclesDone(), SekPc);
  289. if (d ^ Pico.m.z80Run)
  290. {
  291. if (d)
  292. {
  293. Pico.t.z80c_cnt = z80_cycles_from_68k() + 2;
  294. }
  295. else
  296. {
  297. if ((PicoIn.opt & POPT_EN_Z80) && !Pico.m.z80_reset) {
  298. pprof_start(m68k);
  299. PicoSyncZ80(SekCyclesDone());
  300. pprof_end_sub(m68k);
  301. }
  302. }
  303. Pico.m.z80Run = d;
  304. }
  305. }
  306. void NOINLINE ctl_write_z80reset(u32 d)
  307. {
  308. d&=1; d^=1;
  309. elprintf(EL_BUSREQ, "set_zreset: %i->%i [%u] @%06x", Pico.m.z80_reset, d, SekCyclesDone(), SekPc);
  310. if (d ^ Pico.m.z80_reset)
  311. {
  312. if (d)
  313. {
  314. if ((PicoIn.opt & POPT_EN_Z80) && Pico.m.z80Run) {
  315. pprof_start(m68k);
  316. PicoSyncZ80(SekCyclesDone());
  317. pprof_end_sub(m68k);
  318. }
  319. YM2612ResetChip();
  320. timers_reset();
  321. }
  322. else
  323. {
  324. Pico.t.z80c_cnt = z80_cycles_from_68k() + 2;
  325. z80_reset();
  326. }
  327. Pico.m.z80_reset = d;
  328. }
  329. }
  330. static int get_scanline(int is_from_z80);
  331. static void psg_write_68k(u32 d)
  332. {
  333. // look for volume write and update if needed
  334. if ((d & 0x90) == 0x90)
  335. PsndDoPSG(Pico.m.scanline);
  336. SN76496Write(d);
  337. }
  338. static void psg_write_z80(u32 d)
  339. {
  340. if ((d & 0x90) == 0x90) {
  341. int scanline = get_scanline(1);
  342. PsndDoPSG(scanline);
  343. }
  344. SN76496Write(d);
  345. }
  346. // -----------------------------------------------------------------
  347. #ifndef _ASM_MEMORY_C
  348. // cart (save) RAM area (usually 0x200000 - ...)
  349. static u32 PicoRead8_sram(u32 a)
  350. {
  351. u32 d;
  352. if (Pico.sv.start <= a && a <= Pico.sv.end && (Pico.m.sram_reg & SRR_MAPPED))
  353. {
  354. if (Pico.sv.flags & SRF_EEPROM) {
  355. d = EEPROM_read();
  356. if (!(a & 1))
  357. d >>= 8;
  358. d &= 0xff;
  359. } else
  360. d = *(u8 *)(Pico.sv.data - Pico.sv.start + a);
  361. elprintf(EL_SRAMIO, "sram r8 [%06x] %02x @ %06x", a, d, SekPc);
  362. return d;
  363. }
  364. // XXX: this is banking unfriendly
  365. if (a < Pico.romsize)
  366. return Pico.rom[a ^ 1];
  367. return m68k_unmapped_read8(a);
  368. }
  369. static u32 PicoRead16_sram(u32 a)
  370. {
  371. u32 d;
  372. if (Pico.sv.start <= a && a <= Pico.sv.end && (Pico.m.sram_reg & SRR_MAPPED))
  373. {
  374. if (Pico.sv.flags & SRF_EEPROM)
  375. d = EEPROM_read();
  376. else {
  377. u8 *pm = (u8 *)(Pico.sv.data - Pico.sv.start + a);
  378. d = pm[0] << 8;
  379. d |= pm[1];
  380. }
  381. elprintf(EL_SRAMIO, "sram r16 [%06x] %04x @ %06x", a, d, SekPc);
  382. return d;
  383. }
  384. if (a < Pico.romsize)
  385. return *(u16 *)(Pico.rom + a);
  386. return m68k_unmapped_read16(a);
  387. }
  388. #endif // _ASM_MEMORY_C
  389. static void PicoWrite8_sram(u32 a, u32 d)
  390. {
  391. if (a > Pico.sv.end || a < Pico.sv.start || !(Pico.m.sram_reg & SRR_MAPPED)) {
  392. m68k_unmapped_write8(a, d);
  393. return;
  394. }
  395. elprintf(EL_SRAMIO, "sram w8 [%06x] %02x @ %06x", a, d & 0xff, SekPc);
  396. if (Pico.sv.flags & SRF_EEPROM)
  397. {
  398. EEPROM_write8(a, d);
  399. }
  400. else {
  401. u8 *pm = (u8 *)(Pico.sv.data - Pico.sv.start + a);
  402. if (*pm != (u8)d) {
  403. Pico.sv.changed = 1;
  404. *pm = (u8)d;
  405. }
  406. }
  407. }
  408. static void PicoWrite16_sram(u32 a, u32 d)
  409. {
  410. if (a > Pico.sv.end || a < Pico.sv.start || !(Pico.m.sram_reg & SRR_MAPPED)) {
  411. m68k_unmapped_write16(a, d);
  412. return;
  413. }
  414. elprintf(EL_SRAMIO, "sram w16 [%06x] %04x @ %06x", a, d & 0xffff, SekPc);
  415. if (Pico.sv.flags & SRF_EEPROM)
  416. {
  417. EEPROM_write16(d);
  418. }
  419. else {
  420. u8 *pm = (u8 *)(Pico.sv.data - Pico.sv.start + a);
  421. if (pm[0] != (u8)(d >> 8)) {
  422. Pico.sv.changed = 1;
  423. pm[0] = (u8)(d >> 8);
  424. }
  425. if (pm[1] != (u8)d) {
  426. Pico.sv.changed = 1;
  427. pm[1] = (u8)d;
  428. }
  429. }
  430. }
  431. // z80 area (0xa00000 - 0xa0ffff)
  432. // TODO: verify mirrors VDP and bank reg (bank area mirroring verified)
  433. static u32 PicoRead8_z80(u32 a)
  434. {
  435. u32 d = 0xff;
  436. if ((Pico.m.z80Run & 1) || Pico.m.z80_reset) {
  437. elprintf(EL_ANOMALY, "68k z80 read with no bus! [%06x] @ %06x", a, SekPc);
  438. // open bus. Pulled down if MegaCD2 is attached.
  439. return 0;
  440. }
  441. if ((a & 0x4000) == 0x0000)
  442. d = PicoMem.zram[a & 0x1fff];
  443. else if ((a & 0x6000) == 0x4000) // 0x4000-0x5fff
  444. d = ym2612_read_local_68k();
  445. else
  446. elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);
  447. return d;
  448. }
  449. static u32 PicoRead16_z80(u32 a)
  450. {
  451. u32 d = PicoRead8_z80(a);
  452. return d | (d << 8);
  453. }
  454. static void PicoWrite8_z80(u32 a, u32 d)
  455. {
  456. if ((Pico.m.z80Run & 1) || Pico.m.z80_reset) {
  457. // verified on real hw
  458. elprintf(EL_ANOMALY, "68k z80 write with no bus or reset! [%06x] %02x @ %06x", a, d&0xff, SekPc);
  459. return;
  460. }
  461. if ((a & 0x4000) == 0x0000) { // z80 RAM
  462. PicoMem.zram[a & 0x1fff] = (u8)d;
  463. return;
  464. }
  465. if ((a & 0x6000) == 0x4000) { // FM Sound
  466. if (PicoIn.opt & POPT_EN_FM)
  467. ym2612_write_local(a & 3, d & 0xff, 0);
  468. return;
  469. }
  470. // TODO: probably other VDP access too? Maybe more mirrors?
  471. if ((a & 0x7ff9) == 0x7f11) { // PSG Sound
  472. psg_write_68k(d);
  473. return;
  474. }
  475. if ((a & 0x7f00) == 0x6000) // Z80 BANK register
  476. {
  477. Pico.m.z80_bank68k >>= 1;
  478. Pico.m.z80_bank68k |= d << 8;
  479. Pico.m.z80_bank68k &= 0x1ff; // 9 bits and filled in the new top one
  480. elprintf(EL_Z80BNK, "z80 bank=%06x", Pico.m.z80_bank68k << 15);
  481. return;
  482. }
  483. elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %02x @ %06x", a, d&0xff, SekPc);
  484. }
  485. static void PicoWrite16_z80(u32 a, u32 d)
  486. {
  487. // for RAM, only most significant byte is sent
  488. // TODO: verify remaining accesses
  489. PicoWrite8_z80(a, d >> 8);
  490. }
  491. #ifndef _ASM_MEMORY_C
  492. // IO/control area (0xa10000 - 0xa1ffff)
  493. u32 PicoRead8_io(u32 a)
  494. {
  495. u32 d;
  496. if ((a & 0xffe0) == 0x0000) { // I/O ports
  497. d = io_ports_read(a);
  498. goto end;
  499. }
  500. // faking open bus (MegaCD pulldowns don't work here curiously)
  501. d = Pico.m.rotate++;
  502. d ^= d << 6;
  503. if ((a & 0xfc00) == 0x1000) {
  504. // bit8 seems to be readable in this range
  505. if (!(a & 1))
  506. d &= ~0x01;
  507. if ((a & 0xff01) == 0x1100) { // z80 busreq (verified)
  508. d |= (Pico.m.z80Run | Pico.m.z80_reset) & 1;
  509. elprintf(EL_BUSREQ, "get_zrun: %02x [%u] @%06x", d, SekCyclesDone(), SekPc);
  510. }
  511. goto end;
  512. }
  513. d = PicoRead8_32x(a);
  514. end:
  515. return d;
  516. }
  517. u32 PicoRead16_io(u32 a)
  518. {
  519. u32 d;
  520. if ((a & 0xffe0) == 0x0000) { // I/O ports
  521. d = io_ports_read(a);
  522. d |= d << 8;
  523. goto end;
  524. }
  525. // faking open bus
  526. d = (Pico.m.rotate += 0x41);
  527. d ^= (d << 5) ^ (d << 8);
  528. // bit8 seems to be readable in this range
  529. if ((a & 0xfc00) == 0x1000) {
  530. d &= ~0x0100;
  531. if ((a & 0xff00) == 0x1100) { // z80 busreq
  532. d |= ((Pico.m.z80Run | Pico.m.z80_reset) & 1) << 8;
  533. elprintf(EL_BUSREQ, "get_zrun: %04x [%u] @%06x", d, SekCyclesDone(), SekPc);
  534. }
  535. goto end;
  536. }
  537. d = PicoRead16_32x(a);
  538. end:
  539. return d;
  540. }
  541. void PicoWrite8_io(u32 a, u32 d)
  542. {
  543. if ((a & 0xffe1) == 0x0001) { // I/O ports (verified: only LSB!)
  544. io_ports_write(a, d);
  545. return;
  546. }
  547. if ((a & 0xff01) == 0x1100) { // z80 busreq
  548. ctl_write_z80busreq(d);
  549. return;
  550. }
  551. if ((a & 0xff01) == 0x1200) { // z80 reset
  552. ctl_write_z80reset(d);
  553. return;
  554. }
  555. if (a == 0xa130f1) { // sram access register
  556. elprintf(EL_SRAMIO, "sram reg=%02x", d);
  557. Pico.m.sram_reg &= ~(SRR_MAPPED|SRR_READONLY);
  558. Pico.m.sram_reg |= (u8)(d & 3);
  559. return;
  560. }
  561. PicoWrite8_32x(a, d);
  562. }
  563. void PicoWrite16_io(u32 a, u32 d)
  564. {
  565. if ((a & 0xffe0) == 0x0000) { // I/O ports (verified: only LSB!)
  566. io_ports_write(a, d);
  567. return;
  568. }
  569. if ((a & 0xff00) == 0x1100) { // z80 busreq
  570. ctl_write_z80busreq(d >> 8);
  571. return;
  572. }
  573. if ((a & 0xff00) == 0x1200) { // z80 reset
  574. ctl_write_z80reset(d >> 8);
  575. return;
  576. }
  577. if (a == 0xa130f0) { // sram access register
  578. elprintf(EL_SRAMIO, "sram reg=%02x", d);
  579. Pico.m.sram_reg &= ~(SRR_MAPPED|SRR_READONLY);
  580. Pico.m.sram_reg |= (u8)(d & 3);
  581. return;
  582. }
  583. PicoWrite16_32x(a, d);
  584. }
  585. #endif // _ASM_MEMORY_C
  586. // VDP area (0xc00000 - 0xdfffff)
  587. // TODO: verify if lower byte goes to PSG on word writes
  588. u32 PicoRead8_vdp(u32 a)
  589. {
  590. if ((a & 0x00f0) == 0x0000) {
  591. switch (a & 0x0d)
  592. {
  593. case 0x00: return PicoVideoRead8DataH();
  594. case 0x01: return PicoVideoRead8DataL();
  595. case 0x04: return PicoVideoRead8CtlH();
  596. case 0x05: return PicoVideoRead8CtlL();
  597. case 0x08:
  598. case 0x0c: return PicoVideoRead8HV_H();
  599. case 0x09:
  600. case 0x0d: return PicoVideoRead8HV_L();
  601. }
  602. }
  603. elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);
  604. return 0;
  605. }
  606. static u32 PicoRead16_vdp(u32 a)
  607. {
  608. if ((a & 0x00e0) == 0x0000)
  609. return PicoVideoRead(a);
  610. elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);
  611. return 0;
  612. }
  613. static void PicoWrite8_vdp(u32 a, u32 d)
  614. {
  615. if ((a & 0x00f9) == 0x0011) { // PSG Sound
  616. psg_write_68k(d);
  617. return;
  618. }
  619. if ((a & 0x00e0) == 0x0000) {
  620. d &= 0xff;
  621. PicoVideoWrite(a, d | (d << 8));
  622. return;
  623. }
  624. elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %02x @%06x", a, d & 0xff, SekPc);
  625. }
  626. static void PicoWrite16_vdp(u32 a, u32 d)
  627. {
  628. if ((a & 0x00f9) == 0x0010) { // PSG Sound
  629. psg_write_68k(d);
  630. return;
  631. }
  632. if ((a & 0x00e0) == 0x0000) {
  633. PicoVideoWrite(a, d);
  634. return;
  635. }
  636. elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %04x @%06x", a, d & 0xffff, SekPc);
  637. }
  638. // -----------------------------------------------------------------
  639. #ifdef EMU_M68K
  640. static void m68k_mem_setup(void);
  641. #endif
  642. PICO_INTERNAL void PicoMemSetup(void)
  643. {
  644. int mask, rs, sstart, a;
  645. // setup the memory map
  646. cpu68k_map_set(m68k_read8_map, 0x000000, 0xffffff, m68k_unmapped_read8, 1);
  647. cpu68k_map_set(m68k_read16_map, 0x000000, 0xffffff, m68k_unmapped_read16, 1);
  648. cpu68k_map_set(m68k_write8_map, 0x000000, 0xffffff, m68k_unmapped_write8, 1);
  649. cpu68k_map_set(m68k_write16_map, 0x000000, 0xffffff, m68k_unmapped_write16, 1);
  650. // ROM
  651. // align to bank size. We know ROM loader allocated enough for this
  652. mask = (1 << M68K_MEM_SHIFT) - 1;
  653. rs = (Pico.romsize + mask) & ~mask;
  654. cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico.rom, 0);
  655. cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico.rom, 0);
  656. // Common case of on-cart (save) RAM, usually at 0x200000-...
  657. if ((Pico.sv.flags & SRF_ENABLED) && Pico.sv.data != NULL) {
  658. sstart = Pico.sv.start;
  659. rs = Pico.sv.end - sstart;
  660. rs = (rs + mask) & ~mask;
  661. if (sstart + rs >= 0x1000000)
  662. rs = 0x1000000 - sstart;
  663. cpu68k_map_set(m68k_read8_map, sstart, sstart + rs - 1, PicoRead8_sram, 1);
  664. cpu68k_map_set(m68k_read16_map, sstart, sstart + rs - 1, PicoRead16_sram, 1);
  665. cpu68k_map_set(m68k_write8_map, sstart, sstart + rs - 1, PicoWrite8_sram, 1);
  666. cpu68k_map_set(m68k_write16_map, sstart, sstart + rs - 1, PicoWrite16_sram, 1);
  667. }
  668. // Z80 region
  669. cpu68k_map_set(m68k_read8_map, 0xa00000, 0xa0ffff, PicoRead8_z80, 1);
  670. cpu68k_map_set(m68k_read16_map, 0xa00000, 0xa0ffff, PicoRead16_z80, 1);
  671. cpu68k_map_set(m68k_write8_map, 0xa00000, 0xa0ffff, PicoWrite8_z80, 1);
  672. cpu68k_map_set(m68k_write16_map, 0xa00000, 0xa0ffff, PicoWrite16_z80, 1);
  673. // IO/control region
  674. cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_io, 1);
  675. cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_io, 1);
  676. cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_io, 1);
  677. cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_io, 1);
  678. // VDP region
  679. for (a = 0xc00000; a < 0xe00000; a += 0x010000) {
  680. if ((a & 0xe700e0) != 0xc00000)
  681. continue;
  682. cpu68k_map_set(m68k_read8_map, a, a + 0xffff, PicoRead8_vdp, 1);
  683. cpu68k_map_set(m68k_read16_map, a, a + 0xffff, PicoRead16_vdp, 1);
  684. cpu68k_map_set(m68k_write8_map, a, a + 0xffff, PicoWrite8_vdp, 1);
  685. cpu68k_map_set(m68k_write16_map, a, a + 0xffff, PicoWrite16_vdp, 1);
  686. }
  687. // RAM and it's mirrors
  688. for (a = 0xe00000; a < 0x1000000; a += 0x010000) {
  689. cpu68k_map_set(m68k_read8_map, a, a + 0xffff, PicoMem.ram, 0);
  690. cpu68k_map_set(m68k_read16_map, a, a + 0xffff, PicoMem.ram, 0);
  691. cpu68k_map_set(m68k_write8_map, a, a + 0xffff, PicoMem.ram, 0);
  692. cpu68k_map_set(m68k_write16_map, a, a + 0xffff, PicoMem.ram, 0);
  693. }
  694. // Setup memory callbacks:
  695. #ifdef EMU_C68K
  696. PicoCpuCM68k.read8 = (void *)m68k_read8_map;
  697. PicoCpuCM68k.read16 = (void *)m68k_read16_map;
  698. PicoCpuCM68k.read32 = (void *)m68k_read16_map;
  699. PicoCpuCM68k.write8 = (void *)m68k_write8_map;
  700. PicoCpuCM68k.write16 = (void *)m68k_write16_map;
  701. PicoCpuCM68k.write32 = (void *)m68k_write16_map;
  702. PicoCpuCM68k.checkpc = NULL; /* unused */
  703. PicoCpuCM68k.fetch8 = NULL;
  704. PicoCpuCM68k.fetch16 = NULL;
  705. PicoCpuCM68k.fetch32 = NULL;
  706. #endif
  707. #ifdef EMU_F68K
  708. PicoCpuFM68k.read_byte = m68k_read8;
  709. PicoCpuFM68k.read_word = m68k_read16;
  710. PicoCpuFM68k.read_long = m68k_read32;
  711. PicoCpuFM68k.write_byte = m68k_write8;
  712. PicoCpuFM68k.write_word = m68k_write16;
  713. PicoCpuFM68k.write_long = m68k_write32;
  714. // setup FAME fetchmap
  715. {
  716. int i;
  717. // by default, point everything to first 64k of ROM
  718. for (i = 0; i < M68K_FETCHBANK1 * 0xe0 / 0x100; i++)
  719. PicoCpuFM68k.Fetch[i] = (uptr)Pico.rom - (i<<(24-FAMEC_FETCHBITS));
  720. // now real ROM
  721. for (i = 0; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < Pico.romsize; i++)
  722. PicoCpuFM68k.Fetch[i] = (uptr)Pico.rom;
  723. // RAM already set
  724. }
  725. #endif
  726. #ifdef EMU_M68K
  727. m68k_mem_setup();
  728. #endif
  729. z80_mem_setup();
  730. }
  731. #ifdef EMU_M68K
  732. unsigned int (*pm68k_read_memory_8) (unsigned int address) = NULL;
  733. unsigned int (*pm68k_read_memory_16)(unsigned int address) = NULL;
  734. unsigned int (*pm68k_read_memory_32)(unsigned int address) = NULL;
  735. void (*pm68k_write_memory_8) (unsigned int address, unsigned char value) = NULL;
  736. void (*pm68k_write_memory_16)(unsigned int address, unsigned short value) = NULL;
  737. void (*pm68k_write_memory_32)(unsigned int address, unsigned int value) = NULL;
  738. /* it appears that Musashi doesn't always mask the unused bits */
  739. unsigned int m68k_read_memory_8 (unsigned int address) { return pm68k_read_memory_8 (address) & 0xff; }
  740. unsigned int m68k_read_memory_16(unsigned int address) { return pm68k_read_memory_16(address) & 0xffff; }
  741. unsigned int m68k_read_memory_32(unsigned int address) { return pm68k_read_memory_32(address); }
  742. void m68k_write_memory_8 (unsigned int address, unsigned int value) { pm68k_write_memory_8 (address, (u8)value); }
  743. void m68k_write_memory_16(unsigned int address, unsigned int value) { pm68k_write_memory_16(address,(u16)value); }
  744. void m68k_write_memory_32(unsigned int address, unsigned int value) { pm68k_write_memory_32(address, value); }
  745. static void m68k_mem_setup(void)
  746. {
  747. pm68k_read_memory_8 = m68k_read8;
  748. pm68k_read_memory_16 = m68k_read16;
  749. pm68k_read_memory_32 = m68k_read32;
  750. pm68k_write_memory_8 = m68k_write8;
  751. pm68k_write_memory_16 = m68k_write16;
  752. pm68k_write_memory_32 = m68k_write32;
  753. }
  754. #endif // EMU_M68K
  755. // -----------------------------------------------------------------
  756. static int get_scanline(int is_from_z80)
  757. {
  758. if (is_from_z80) {
  759. int mclk_z80 = (z80_cyclesLeft<0 ? Pico.t.z80c_aim : z80_cyclesDone()) * 15;
  760. int mclk_line = Pico.t.z80_scanline * 488 * 7;
  761. while (mclk_z80 - mclk_line >= 488 * 7)
  762. Pico.t.z80_scanline++, mclk_line += 488 * 7;
  763. return Pico.t.z80_scanline;
  764. }
  765. return Pico.m.scanline;
  766. }
  767. /* probably should not be in this file, but it's near related code here */
  768. void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new)
  769. {
  770. int xcycles = z80_cycles << 8;
  771. /* check for overflows */
  772. if ((mode_old & 4) && xcycles >= Pico.t.timer_a_next_oflow)
  773. ym2612.OPN.ST.status |= 1;
  774. if ((mode_old & 8) && xcycles >= Pico.t.timer_b_next_oflow)
  775. ym2612.OPN.ST.status |= 2;
  776. /* update timer a */
  777. if (mode_old & 1)
  778. while (xcycles > Pico.t.timer_a_next_oflow)
  779. Pico.t.timer_a_next_oflow += Pico.t.timer_a_step;
  780. if ((mode_old ^ mode_new) & 1) // turning on/off
  781. {
  782. if (mode_old & 1)
  783. Pico.t.timer_a_next_oflow = TIMER_NO_OFLOW;
  784. else
  785. Pico.t.timer_a_next_oflow = xcycles + Pico.t.timer_a_step;
  786. }
  787. if (mode_new & 1)
  788. elprintf(EL_YMTIMER, "timer a upd to %i @ %i", Pico.t.timer_a_next_oflow>>8, z80_cycles);
  789. /* update timer b */
  790. if (mode_old & 2)
  791. while (xcycles > Pico.t.timer_b_next_oflow)
  792. Pico.t.timer_b_next_oflow += Pico.t.timer_b_step;
  793. if ((mode_old ^ mode_new) & 2)
  794. {
  795. if (mode_old & 2)
  796. Pico.t.timer_b_next_oflow = TIMER_NO_OFLOW;
  797. else
  798. Pico.t.timer_b_next_oflow = xcycles + Pico.t.timer_b_step;
  799. }
  800. if (mode_new & 2)
  801. elprintf(EL_YMTIMER, "timer b upd to %i @ %i", Pico.t.timer_b_next_oflow>>8, z80_cycles);
  802. }
  803. // ym2612 DAC and timer I/O handlers for z80
  804. static int ym2612_write_local(u32 a, u32 d, int is_from_z80)
  805. {
  806. int addr;
  807. a &= 3;
  808. if (a == 1 && ym2612.OPN.ST.address == 0x2a) /* DAC data */
  809. {
  810. int cycles = is_from_z80 ? z80_cyclesDone() : z80_cycles_from_68k();
  811. //elprintf(EL_STATUS, "%03i dac w %08x z80 %i", cycles, d, is_from_z80);
  812. ym2612.dacout = ((int)d - 0x80) << 6;
  813. if (ym2612.dacen)
  814. PsndDoDAC(cycles);
  815. return 0;
  816. }
  817. switch (a)
  818. {
  819. case 0: /* address port 0 */
  820. ym2612.OPN.ST.address = d;
  821. ym2612.addr_A1 = 0;
  822. #ifdef __GP2X__
  823. if (PicoIn.opt & POPT_EXT_FM) YM2612Write_940(a, d, -1);
  824. #endif
  825. return 0;
  826. case 1: /* data port 0 */
  827. if (ym2612.addr_A1 != 0)
  828. return 0;
  829. addr = ym2612.OPN.ST.address;
  830. ym2612.REGS[addr] = d;
  831. switch (addr)
  832. {
  833. case 0x24: // timer A High 8
  834. case 0x25: { // timer A Low 2
  835. int TAnew = (addr == 0x24) ? ((ym2612.OPN.ST.TA & 0x03)|(((int)d)<<2))
  836. : ((ym2612.OPN.ST.TA & 0x3fc)|(d&3));
  837. if (ym2612.OPN.ST.TA != TAnew)
  838. {
  839. //elprintf(EL_STATUS, "timer a set %i", TAnew);
  840. ym2612.OPN.ST.TA = TAnew;
  841. //ym2612.OPN.ST.TAC = (1024-TAnew)*18;
  842. //ym2612.OPN.ST.TAT = 0;
  843. Pico.t.timer_a_step = TIMER_A_TICK_ZCYCLES * (1024 - TAnew);
  844. if (ym2612.OPN.ST.mode & 1) {
  845. // this is not right, should really be done on overflow only
  846. int cycles = is_from_z80 ? z80_cyclesDone() : z80_cycles_from_68k();
  847. Pico.t.timer_a_next_oflow = (cycles << 8) + Pico.t.timer_a_step;
  848. }
  849. elprintf(EL_YMTIMER, "timer a set to %i, %i", 1024 - TAnew, Pico.t.timer_a_next_oflow>>8);
  850. }
  851. return 0;
  852. }
  853. case 0x26: // timer B
  854. if (ym2612.OPN.ST.TB != d) {
  855. //elprintf(EL_STATUS, "timer b set %i", d);
  856. ym2612.OPN.ST.TB = d;
  857. //ym2612.OPN.ST.TBC = (256-d) * 288;
  858. //ym2612.OPN.ST.TBT = 0;
  859. Pico.t.timer_b_step = TIMER_B_TICK_ZCYCLES * (256 - d); // 262800
  860. if (ym2612.OPN.ST.mode & 2) {
  861. int cycles = is_from_z80 ? z80_cyclesDone() : z80_cycles_from_68k();
  862. Pico.t.timer_b_next_oflow = (cycles << 8) + Pico.t.timer_b_step;
  863. }
  864. elprintf(EL_YMTIMER, "timer b set to %i, %i", 256 - d, Pico.t.timer_b_next_oflow>>8);
  865. }
  866. return 0;
  867. case 0x27: { /* mode, timer control */
  868. int old_mode = ym2612.OPN.ST.mode;
  869. int cycles = is_from_z80 ? z80_cyclesDone() : z80_cycles_from_68k();
  870. ym2612.OPN.ST.mode = d;
  871. elprintf(EL_YMTIMER, "st mode %02x", d);
  872. ym2612_sync_timers(cycles, old_mode, d);
  873. /* reset Timer a flag */
  874. if (d & 0x10)
  875. ym2612.OPN.ST.status &= ~1;
  876. /* reset Timer b flag */
  877. if (d & 0x20)
  878. ym2612.OPN.ST.status &= ~2;
  879. if ((d ^ old_mode) & 0xc0) {
  880. #ifdef __GP2X__
  881. if (PicoIn.opt & POPT_EXT_FM) return YM2612Write_940(a, d, get_scanline(is_from_z80));
  882. #endif
  883. return 1;
  884. }
  885. return 0;
  886. }
  887. case 0x2b: { /* DAC Sel (YM2612) */
  888. ym2612.dacen = d & 0x80;
  889. #ifdef __GP2X__
  890. if (PicoIn.opt & POPT_EXT_FM) YM2612Write_940(a, d, get_scanline(is_from_z80));
  891. #endif
  892. return 0;
  893. }
  894. }
  895. break;
  896. case 2: /* address port 1 */
  897. ym2612.OPN.ST.address = d;
  898. ym2612.addr_A1 = 1;
  899. #ifdef __GP2X__
  900. if (PicoIn.opt & POPT_EXT_FM) YM2612Write_940(a, d, -1);
  901. #endif
  902. return 0;
  903. case 3: /* data port 1 */
  904. if (ym2612.addr_A1 != 1)
  905. return 0;
  906. addr = ym2612.OPN.ST.address | 0x100;
  907. ym2612.REGS[addr] = d;
  908. break;
  909. }
  910. #ifdef __GP2X__
  911. if (PicoIn.opt & POPT_EXT_FM)
  912. return YM2612Write_940(a, d, get_scanline(is_from_z80));
  913. #endif
  914. PsndDoFM(is_from_z80 ? z80_cyclesDone() : z80_cycles_from_68k());
  915. return YM2612Write_(a, d);
  916. }
  917. #define ym2612_read_local() \
  918. if (xcycles >= Pico.t.timer_a_next_oflow) \
  919. ym2612.OPN.ST.status |= (ym2612.OPN.ST.mode >> 2) & 1; \
  920. if (xcycles >= Pico.t.timer_b_next_oflow) \
  921. ym2612.OPN.ST.status |= (ym2612.OPN.ST.mode >> 2) & 2
  922. static u32 ym2612_read_local_z80(void)
  923. {
  924. int xcycles = z80_cyclesDone() << 8;
  925. ym2612_read_local();
  926. elprintf(EL_YMTIMER, "timer z80 read %i, sched %i, %i @ %i|%i",
  927. ym2612.OPN.ST.status, Pico.t.timer_a_next_oflow >> 8,
  928. Pico.t.timer_b_next_oflow >> 8, xcycles >> 8, (xcycles >> 8) / 228);
  929. return ym2612.OPN.ST.status;
  930. }
  931. static u32 ym2612_read_local_68k(void)
  932. {
  933. int xcycles = z80_cycles_from_68k() << 8;
  934. ym2612_read_local();
  935. elprintf(EL_YMTIMER, "timer 68k read %i, sched %i, %i @ %i|%i",
  936. ym2612.OPN.ST.status, Pico.t.timer_a_next_oflow >> 8,
  937. Pico.t.timer_b_next_oflow >> 8, xcycles >> 8, (xcycles >> 8) / 228);
  938. return ym2612.OPN.ST.status;
  939. }
  940. void ym2612_pack_state(void)
  941. {
  942. // timers are saved as tick counts, in 16.16 int format
  943. int tac, tat = 0, tbc, tbt = 0;
  944. tac = 1024 - ym2612.OPN.ST.TA;
  945. tbc = 256 - ym2612.OPN.ST.TB;
  946. if (Pico.t.timer_a_next_oflow != TIMER_NO_OFLOW)
  947. tat = (int)((double)(Pico.t.timer_a_step - Pico.t.timer_a_next_oflow)
  948. / (double)Pico.t.timer_a_step * tac * 65536);
  949. if (Pico.t.timer_b_next_oflow != TIMER_NO_OFLOW)
  950. tbt = (int)((double)(Pico.t.timer_b_step - Pico.t.timer_b_next_oflow)
  951. / (double)Pico.t.timer_b_step * tbc * 65536);
  952. elprintf(EL_YMTIMER, "save: timer a %i/%i", tat >> 16, tac);
  953. elprintf(EL_YMTIMER, "save: timer b %i/%i", tbt >> 16, tbc);
  954. #ifdef __GP2X__
  955. if (PicoIn.opt & POPT_EXT_FM)
  956. YM2612PicoStateSave2_940(tat, tbt);
  957. else
  958. #endif
  959. YM2612PicoStateSave2(tat, tbt);
  960. }
  961. void ym2612_unpack_state(void)
  962. {
  963. int i, ret, tac, tat, tbc, tbt;
  964. YM2612PicoStateLoad();
  965. // feed all the registers and update internal state
  966. for (i = 0x20; i < 0xA0; i++) {
  967. ym2612_write_local(0, i, 0);
  968. ym2612_write_local(1, ym2612.REGS[i], 0);
  969. }
  970. for (i = 0x30; i < 0xA0; i++) {
  971. ym2612_write_local(2, i, 0);
  972. ym2612_write_local(3, ym2612.REGS[i|0x100], 0);
  973. }
  974. for (i = 0xAF; i >= 0xA0; i--) { // must apply backwards
  975. ym2612_write_local(2, i, 0);
  976. ym2612_write_local(3, ym2612.REGS[i|0x100], 0);
  977. ym2612_write_local(0, i, 0);
  978. ym2612_write_local(1, ym2612.REGS[i], 0);
  979. }
  980. for (i = 0xB0; i < 0xB8; i++) {
  981. ym2612_write_local(0, i, 0);
  982. ym2612_write_local(1, ym2612.REGS[i], 0);
  983. ym2612_write_local(2, i, 0);
  984. ym2612_write_local(3, ym2612.REGS[i|0x100], 0);
  985. }
  986. #ifdef __GP2X__
  987. if (PicoIn.opt & POPT_EXT_FM)
  988. ret = YM2612PicoStateLoad2_940(&tat, &tbt);
  989. else
  990. #endif
  991. ret = YM2612PicoStateLoad2(&tat, &tbt);
  992. if (ret != 0) {
  993. elprintf(EL_STATUS, "old ym2612 state");
  994. return; // no saved timers
  995. }
  996. tac = (1024 - ym2612.OPN.ST.TA) << 16;
  997. tbc = (256 - ym2612.OPN.ST.TB) << 16;
  998. if (ym2612.OPN.ST.mode & 1)
  999. Pico.t.timer_a_next_oflow = (int)((double)(tac - tat) / (double)tac * Pico.t.timer_a_step);
  1000. else
  1001. Pico.t.timer_a_next_oflow = TIMER_NO_OFLOW;
  1002. if (ym2612.OPN.ST.mode & 2)
  1003. Pico.t.timer_b_next_oflow = (int)((double)(tbc - tbt) / (double)tbc * Pico.t.timer_b_step);
  1004. else
  1005. Pico.t.timer_b_next_oflow = TIMER_NO_OFLOW;
  1006. elprintf(EL_YMTIMER, "load: %i/%i, timer_a_next_oflow %i", tat>>16, tac>>16, Pico.t.timer_a_next_oflow >> 8);
  1007. elprintf(EL_YMTIMER, "load: %i/%i, timer_b_next_oflow %i", tbt>>16, tbc>>16, Pico.t.timer_b_next_oflow >> 8);
  1008. }
  1009. #if defined(NO_32X) && defined(_ASM_MEMORY_C)
  1010. // referenced by asm code
  1011. u32 PicoRead8_32x(u32 a) { return 0; }
  1012. u32 PicoRead16_32x(u32 a) { return 0; }
  1013. void PicoWrite8_32x(u32 a, u32 d) {}
  1014. void PicoWrite16_32x(u32 a, u32 d) {}
  1015. #endif
  1016. // -----------------------------------------------------------------
  1017. // z80 memhandlers
  1018. static unsigned char z80_md_vdp_read(unsigned short a)
  1019. {
  1020. z80_subCLeft(2);
  1021. if ((a & 0x00f0) == 0x0000) {
  1022. switch (a & 0x0d)
  1023. {
  1024. case 0x00: return PicoVideoRead8DataH();
  1025. case 0x01: return PicoVideoRead8DataL();
  1026. case 0x04: return PicoVideoRead8CtlH();
  1027. case 0x05: return PicoVideoRead8CtlL();
  1028. case 0x08:
  1029. case 0x0c: return get_scanline(1); // FIXME: make it proper
  1030. case 0x09:
  1031. case 0x0d: return Pico.m.rotate++;
  1032. }
  1033. }
  1034. elprintf(EL_ANOMALY, "z80 invalid r8 [%06x] %02x", a, 0xff);
  1035. return 0xff;
  1036. }
  1037. static unsigned char z80_md_bank_read(unsigned short a)
  1038. {
  1039. unsigned int addr68k;
  1040. unsigned char ret;
  1041. z80_subCLeft(3);
  1042. addr68k = Pico.m.z80_bank68k << 15;
  1043. addr68k |= a & 0x7fff;
  1044. ret = m68k_read8(addr68k);
  1045. elprintf(EL_Z80BNK, "z80->68k r8 [%06x] %02x", addr68k, ret);
  1046. return ret;
  1047. }
  1048. static void z80_md_ym2612_write(unsigned int a, unsigned char data)
  1049. {
  1050. if (PicoIn.opt & POPT_EN_FM)
  1051. ym2612_write_local(a, data, 1);
  1052. }
  1053. static void z80_md_vdp_br_write(unsigned int a, unsigned char data)
  1054. {
  1055. if ((a&0xfff9) == 0x7f11) // 7f11 7f13 7f15 7f17
  1056. {
  1057. psg_write_z80(data);
  1058. return;
  1059. }
  1060. // at least VDP data writes hang my machine
  1061. if ((a>>8) == 0x60)
  1062. {
  1063. Pico.m.z80_bank68k >>= 1;
  1064. Pico.m.z80_bank68k |= data << 8;
  1065. Pico.m.z80_bank68k &= 0x1ff; // 9 bits and filled in the new top one
  1066. return;
  1067. }
  1068. elprintf(EL_ANOMALY, "z80 invalid w8 [%06x] %02x", a, data);
  1069. }
  1070. static void z80_md_bank_write(unsigned int a, unsigned char data)
  1071. {
  1072. unsigned int addr68k;
  1073. addr68k = Pico.m.z80_bank68k << 15;
  1074. addr68k += a & 0x7fff;
  1075. elprintf(EL_Z80BNK, "z80->68k w8 [%06x] %02x", addr68k, data);
  1076. m68k_write8(addr68k, data);
  1077. }
  1078. // -----------------------------------------------------------------
  1079. static unsigned char z80_md_in(unsigned short p)
  1080. {
  1081. elprintf(EL_ANOMALY, "Z80 port %04x read", p);
  1082. return 0xff;
  1083. }
  1084. static void z80_md_out(unsigned short p, unsigned char d)
  1085. {
  1086. elprintf(EL_ANOMALY, "Z80 port %04x write %02x", p, d);
  1087. }
  1088. static void z80_mem_setup(void)
  1089. {
  1090. z80_map_set(z80_read_map, 0x0000, 0x1fff, PicoMem.zram, 0);
  1091. z80_map_set(z80_read_map, 0x2000, 0x3fff, PicoMem.zram, 0);
  1092. z80_map_set(z80_read_map, 0x4000, 0x5fff, ym2612_read_local_z80, 1);
  1093. z80_map_set(z80_read_map, 0x6000, 0x7fff, z80_md_vdp_read, 1);
  1094. z80_map_set(z80_read_map, 0x8000, 0xffff, z80_md_bank_read, 1);
  1095. z80_map_set(z80_write_map, 0x0000, 0x1fff, PicoMem.zram, 0);
  1096. z80_map_set(z80_write_map, 0x2000, 0x3fff, PicoMem.zram, 0);
  1097. z80_map_set(z80_write_map, 0x4000, 0x5fff, z80_md_ym2612_write, 1);
  1098. z80_map_set(z80_write_map, 0x6000, 0x7fff, z80_md_vdp_br_write, 1);
  1099. z80_map_set(z80_write_map, 0x8000, 0xffff, z80_md_bank_write, 1);
  1100. #ifdef _USE_DRZ80
  1101. drZ80.z80_in = z80_md_in;
  1102. drZ80.z80_out = z80_md_out;
  1103. #endif
  1104. #ifdef _USE_CZ80
  1105. Cz80_Set_Fetch(&CZ80, 0x0000, 0x1fff, (FPTR)PicoMem.zram); // main RAM
  1106. Cz80_Set_Fetch(&CZ80, 0x2000, 0x3fff, (FPTR)PicoMem.zram); // mirror
  1107. Cz80_Set_INPort(&CZ80, z80_md_in);
  1108. Cz80_Set_OUTPort(&CZ80, z80_md_out);
  1109. #endif
  1110. }
  1111. // vim:shiftwidth=2:ts=2:expandtab