emit_ppc.c 55 KB

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  1. /*
  2. * Basic macros to emit PowerISA 2.03 64 bit instructions and some utils
  3. * Copyright (C) 2020 kub
  4. *
  5. * This work is licensed under the terms of MAME license.
  6. * See COPYING file in the top-level directory.
  7. */
  8. // NB bit numbers are reversed in PPC (MSB is bit 0). The emith_* functions and
  9. // macros must take this into account.
  10. // NB PPC was a 64 bit architecture from the onset, so basically all operations
  11. // are operating on 64 bits. 32 bit arch was only added later on, and there are
  12. // very few 32 bit operations (cmp*, shift/rotate, extract/insert, load/store).
  13. // For most operations the upper bits don't spill into the lower word, for the
  14. // others there is an appropriate 32 bit operation available.
  15. // NB PowerPC isn't a clean RISC design. Several insns use microcode, which is
  16. // AFAIK notably slower than using some 2-3 non-microcode insns. So, using
  17. // such insns should by avoided if possible. Listed in Cell handbook, App. A:
  18. // - shift/rotate having the amount in a register
  19. // - arithmetic/logical having the RC flag set (except cmp*)
  20. // - load/store algebraic (l?a*), multiple (lmw/stmw), string (ls*/sts*)
  21. // - mtcrf (and some more SPR related, not used here)
  22. // moreover, misaligned load/store crossing a cacheline boundary are microcoded.
  23. // Note also that load/store string isn't available in little endian mode.
  24. // NB flag handling in PPC differs grossly from the ARM/X86 model. There are 8
  25. // fields in the condition register, each having 4 condition bits. However, only
  26. // the EQ bit is similar to the Z flag. The CA and OV bits in the XER register
  27. // are similar to the C and V bits, but shifts don't use CA, and cmp* doesn't
  28. // use CA and OV.
  29. // Moreover, there's no easy possibility to get CA and OV for 32 bit arithmetic
  30. // since all arithmetic/logical insns use 64 bit.
  31. // For now, use the "no flags" code from the RISC-V backend.
  32. #define HOST_REGS 32
  33. // PPC64: params: r3-r10, return: r3, temp: r0,r11-r12, saved: r14-r31
  34. // reserved: r0(zero), r1(stack), r2(TOC), r13(TID)
  35. #define RET_REG 3
  36. #define PARAM_REGS { 3, 4, 5, 6, 7, 8, 9, 10 }
  37. #define PRESERVED_REGS { 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 }
  38. #define TEMPORARY_REGS { 11, 12 }
  39. #define CONTEXT_REG 31
  40. #define STATIC_SH2_REGS { SHR_SR,30 , SHR_R(0),29 , SHR_R(1),28 }
  41. // if RA is 0 in non-update memory insns, ADDI/ADDIS, ISEL, it aliases with zero
  42. #define Z0 0 // zero register
  43. #define SP 1 // stack pointer
  44. // SPR registers
  45. #define XER -1 // exception register
  46. #define LR -8 // link register
  47. #define CTR -9 // counter register
  48. // internally used by code emitter:
  49. #define AT 0 // emitter temporary (can't be fully used anyway)
  50. #define FNZ 14 // emulated processor flags: N (bit 31) ,Z (all bits)
  51. #define FC 15 // emulated processor flags: C (bit 0), others 0
  52. #define FV 16 // emulated processor flags: Nt^Ns (bit 31). others x
  53. // unified conditions; virtual, not corresponding to anything real on PPC
  54. #define DCOND_EQ 0x0
  55. #define DCOND_NE 0x1
  56. #define DCOND_HS 0x2
  57. #define DCOND_LO 0x3
  58. #define DCOND_MI 0x4
  59. #define DCOND_PL 0x5
  60. #define DCOND_VS 0x6
  61. #define DCOND_VC 0x7
  62. #define DCOND_HI 0x8
  63. #define DCOND_LS 0x9
  64. #define DCOND_GE 0xa
  65. #define DCOND_LT 0xb
  66. #define DCOND_GT 0xc
  67. #define DCOND_LE 0xd
  68. #define DCOND_CS DCOND_LO
  69. #define DCOND_CC DCOND_HS
  70. // unified insn; use right-aligned bit offsets for the bitfields
  71. #define PPC_INSN(op, b10, b15, b20, b31) \
  72. (((op)<<26)|((b10)<<21)|((b15)<<16)|((b20)<<11)|((b31)<<0))
  73. #define _ 0 // marker for "field unused"
  74. #define __(n) o##n // enum marker for "undefined"
  75. #define _CB(v,l,s,d) ((((v)>>(s))&((1<<(l))-1))<<(d)) // copy l bits
  76. // NB everything privileged or unneeded at 1st sight is left out
  77. // opcode field (encoded in OPCD, bits 0-5)
  78. enum { OP__LMA=004, OP_MULLI=007,
  79. OP_SUBFIC, __(11), OP_CMPLI, OP_CMPI, OP_ADDIC, OP_ADDICF, OP_ADDI, OP_ADDIS,
  80. OP_BC, __(21), OP_B, OP__CR, OP_RLWIMI, OP_RLWINM, __(26), OP_RLWNM,
  81. OP_ORI, OP_ORIS, OP_XORI, OP_XORIS, OP_ANDI, OP_ANDIS, OP__RLD, OP__EXT,
  82. OP_LWZ, OP_LWZU, OP_LBZ, OP_LBZU, OP_STW, OP_STWU, OP_STB, OP_STBU,
  83. OP_LHZ, OP_LHZU, OP_LHA, OP_LHAU, OP_STH, OP_STHU, OP_LMW, OP_STMW,
  84. /*OP_LQ=070,*/ OP__LD=072, OP__ST=076 };
  85. // CR subops (encoded in bits 21-31)
  86. enum { OPC_MCRF=0, OPC_BCLR=32, OPC_BCCTR=1056 };
  87. // RLD subops (encoded in XO bits 27-31)
  88. enum { OPR_RLDICL=0, OPR_RLDICR=4, OPR_RLDIC=8, OPR_RLDIMI=12, OPR_RLDCL=16, OPR_RLDCR=18 };
  89. // EXT subops (encoded in XO bits 21-31)
  90. enum {
  91. // arith/logical
  92. OPE_CMP=0, OPE_SUBFC=16, OPE_ADDC=20, OPE_AND=56,
  93. OPE_CMPL=64, OPE_SUBF=80, OPE_ANDC=120, OPE_NEG=208, OPE_NOR=248,
  94. OPE_SUBFE=272, OPE_ADDE=276, OPE_SUBFZE=400, OPE_ADDZE=404, OPE_SUBFME=464, OPE_ADDME=468,
  95. OPE_ADD=532, OPE_EQV=568, OPE_XOR=632, OPE_ORC=824, OPE_OR=888, OPE_NAND=952,
  96. // shift
  97. OPE_SLW=48, OPE_SLD=54, OPE_SRW=1072, OPE_SRD=1078, OPE_SRAW=1584, OPE_SRAD=1588, OPE_SRAWI=1648, OPE_SRADI=1652,
  98. // extend, bitcount
  99. OPE_CNTLZW=52, OPE_CNTLZD=116, OPE_EXTSH=1844, OPE_EXTSB=1908, OPE_EXTSW=1972,
  100. // mult/div
  101. OPE_MULHDU=18, OPE_MULHWU=22, OPE_MULHD=146, OPE_MULHW=150, OPE_MULLD=466, OPE_MULLW=470,
  102. OPE_DIVDU=914, OPE_DIVWU=918, OPE_DIVD=978, OPE_DIVW=982,
  103. // load/store indexed
  104. OPE_LDX=42, OPE_LDUX=106, OPE_STDX=298, OPE_STDUX=362,
  105. OPE_LWZX=46, OPE_LWZUX=110, OPE_LWAX=682, OPE_LWAUX=746, OPE_STWX=302, OPE_STWUX=366,
  106. OPE_LBZX=174, OPE_LBZUX=238, /* no LBAX/LBAUX... */ OPE_STBX=430, OPE_STBUX=494,
  107. OPE_LHZX=558, OPE_LHZUX=622, OPE_LHAX=686, OPE_LHAUX=750, OPE_STHX=814, OPE_STHUX=878,
  108. // SPR, CR related
  109. OPE_ISEL=15, OPE_MFCR=38, OPE_MTCRF=288, OPE_MFSPR=678, OPE_MTSPR=934, OPE_MCRXR=1024,
  110. };
  111. // LD subops (encoded in XO bits 30-31)
  112. enum { OPL_LD, OPL_LDU, OPL_LWA };
  113. // ST subops (encoded in XO bits 30-31)
  114. enum { OPS_STD, OPS_STDU /*,OPS_STQ*/ };
  115. // X*,M*-forms insns often have overflow detect in b21 and CR0 update in b31
  116. #define XOE (1<<10) // (31-21)
  117. #define XRC (1<<0) // (31-31)
  118. #define XF (XOE|XRC)
  119. // MB and ME in M*-forms rotate left
  120. #define MM(b,e) (((b)<<6)|((e)<<1))
  121. #define MD(b,s) (_CB(b,5,0,6)|_CB(b,1,5,5)|_CB(s,5,0,11)|_CB(s,1,5,1))
  122. // AA and LK in I,B-forms branches
  123. #define BAA (1<<1)
  124. #define BLK (1<<0)
  125. // BO and BI condition codes in B-form, BO0-BO4:BI2-BI4 since we only need CR0
  126. #define BLT 0x60
  127. #define BGE 0x20
  128. #define BGT 0x61
  129. #define BLE 0x21
  130. #define BEQ 0x62
  131. #define BNE 0x22
  132. #define BXX 0xa0 // unconditional, aka always
  133. #define PPC_NOP \
  134. PPC_INSN(OP_ORI, 0, 0, _, 0) // ori r0, r0, 0
  135. // arithmetic/logical
  136. #define PPC_OP_REG(op, xop, rt, ra, rb) /* X*,M*-form */ \
  137. PPC_INSN((unsigned)op, rt, ra, rb, xop)
  138. #define PPC_OP_IMM(op, rt, ra, imm) /* D,B,I-form */ \
  139. PPC_INSN((unsigned)op, rt, ra, _, imm)
  140. // rt = ra OP rb
  141. #define PPC_ADD_REG(rt, ra, rb) \
  142. PPC_OP_REG(OP__EXT,OPE_ADD,rt,ra,rb)
  143. #define PPC_ADDC_REG(rt, ra, rb) \
  144. PPC_OP_REG(OP__EXT,OPE_ADD|XOE,rt,ra,rb)
  145. #define PPC_SUB_REG(rt, rb, ra) /* NB reversed args (rb-ra) */ \
  146. PPC_OP_REG(OP__EXT,OPE_SUBF,rt,ra,rb)
  147. #define PPC_SUBC_REG(rt, rb, ra) \
  148. PPC_OP_REG(OP__EXT,OPE_SUBF|XOE,rt,ra,rb)
  149. #define PPC_NEG_REG(rt, ra) \
  150. PPC_OP_REG(OP__EXT,OPE_NEG,rt,ra,_)
  151. #define PPC_NEGC_REG(rt, ra) \
  152. PPC_OP_REG(OP__EXT,OPE_NEG|XOE,rt,ra,_)
  153. #define PPC_CMP_REG(ra, rb) \
  154. PPC_OP_REG(OP__EXT,OPE_CMP,1,ra,rb)
  155. #define PPC_CMPL_REG(ra, rb) \
  156. PPC_OP_REG(OP__EXT,OPE_CMPL,1,ra,rb)
  157. #define PPC_CMPW_REG(ra, rb) \
  158. PPC_OP_REG(OP__EXT,OPE_CMP,0,ra,rb)
  159. #define PPC_CMPLW_REG(ra, rb) \
  160. PPC_OP_REG(OP__EXT,OPE_CMPL,0,ra,rb)
  161. #define PPC_XOR_REG(ra, rt, rb) \
  162. PPC_OP_REG(OP__EXT,OPE_XOR,rt,ra,rb)
  163. #define PPC_OR_REG(ra, rt, rb) \
  164. PPC_OP_REG(OP__EXT,OPE_OR,rt,ra,rb)
  165. #define PPC_ORN_REG(ra, rt, rb) \
  166. PPC_OP_REG(OP__EXT,OPE_ORC,rt,ra,rb)
  167. #define PPC_NOR_REG(ra, rt, rb) \
  168. PPC_OP_REG(OP__EXT,OPE_NOR,rt,ra,rb)
  169. #define PPC_AND_REG(ra, rt, rb) \
  170. PPC_OP_REG(OP__EXT,OPE_AND,rt,ra,rb)
  171. #define PPC_BIC_REG(ra, rt, rb) \
  172. PPC_OP_REG(OP__EXT,OPE_ANDC,rt,ra,rb)
  173. #define PPC_MOV_REG(rt, ra) \
  174. PPC_OR_REG(rt, ra, ra)
  175. #define PPC_MVN_REG(rt, ra) \
  176. PPC_NOR_REG(rt, ra, ra)
  177. // rt = ra OP rb OP carry
  178. #define PPC_ADC_REG(rt, ra, rb) \
  179. PPC_OP_REG(OP__EXT,OPE_ADDE,rt,ra,rb)
  180. #define PPC_SBC_REG(rt, rb, ra) \
  181. PPC_OP_REG(OP__EXT,OPE_SUBFE,rt,ra,rb)
  182. #define PPC_NGC_REG(rt, ra) \
  183. PPC_OP_REG(OP__EXT,OPE_SUBFZE,rt,ra,_)
  184. // rt = ra SHIFT rb
  185. #define PPC_LSL_REG(ra, rt, rb) \
  186. PPC_OP_REG(OP__EXT,OPE_SLD,rt,ra,rb)
  187. #define PPC_LSR_REG(ra, rt, rb) \
  188. PPC_OP_REG(OP__EXT,OPE_SRD,rt,ra,rb)
  189. #define PPC_ASR_REG(ra, rt, rb) \
  190. PPC_OP_REG(OP__EXT,OPE_SRAD,rt,ra,rb)
  191. #define PPC_ROL_REG(ra, rt, rb) \
  192. PPC_OP_REG(OP__RLD,OPR_RLDCL,rt,ra,rb,0)
  193. #define PPC_LSLW_REG(ra, rt, rb) \
  194. PPC_OP_REG(OP__EXT,OPE_SLW,rt,ra,rb)
  195. #define PPC_LSRW_REG(ra, rt, rb) \
  196. PPC_OP_REG(OP__EXT,OPE_SRW,rt,ra,rb)
  197. #define PPC_ASRW_REG(ra, rt, rb) \
  198. PPC_OP_REG(OP__EXT,OPE_SRAW,rt,ra,rb)
  199. #define PPC_ROLW_REG(ra, rt, rb) \
  200. PPC_OP_REG(OP_RLWNM,MM(0,31),rt,ra,rb)
  201. // rt = ra OP (imm16 << (0|16))
  202. #define PPC_ADD_IMM(rt, ra, imm16) \
  203. PPC_OP_IMM(OP_ADDI, rt, ra, imm16)
  204. #define PPC_ADDT_IMM(rt, ra, imm16) \
  205. PPC_OP_IMM(OP_ADDIS, rt, ra, imm16)
  206. #define PPC_XOR_IMM(ra, rt, imm16) \
  207. PPC_OP_IMM(OP_XORI, rt, ra, imm16)
  208. #define PPC_XORT_IMM(ra, rt, imm16) \
  209. PPC_OP_IMM(OP_XORIS, rt, ra, imm16)
  210. #define PPC_OR_IMM(ra, rt, imm16) \
  211. PPC_OP_IMM(OP_ORI, rt, ra, imm16)
  212. #define PPC_ORT_IMM(ra, rt, imm16) \
  213. PPC_OP_IMM(OP_ORIS, rt, ra, imm16)
  214. #define PPC_ANDS_IMM(rt, ra, imm16) \
  215. PPC_OP_IMM(OP_ANDI, rt, ra, imm16)
  216. #define PPC_ANDTS_IMM(rt, ra, imm16) \
  217. PPC_OP_IMM(OP_ANDIS, rt, ra, imm16)
  218. #define PPC_CMP_IMM(ra, imm16) \
  219. PPC_OP_IMM(OP_CMPI, 1, ra, imm16)
  220. #define PPC_CMPL_IMM(ra, imm16) \
  221. PPC_OP_IMM(OP_CMPLI, 1, ra, imm16)
  222. #define PPC_CMPW_IMM(ra, imm16) \
  223. PPC_OP_IMM(OP_CMPI, 0, ra, imm16)
  224. #define PPC_CMPLW_IMM(ra, imm16) \
  225. PPC_OP_IMM(OP_CMPLI, 0, ra, imm16)
  226. #define PPC_TST_IMM(rt, imm16) \
  227. PPC_ANDS_IMM(Z0,ra,imm16)
  228. #define PPC_MOV_IMM(rt, ra, imm16) \
  229. PPC_ADD_IMM(rt,ra,imm16)
  230. #define PPC_MOVT_IMM(rt, ra, imm16) \
  231. PPC_ADDT_IMM(rt,ra,imm16)
  232. // rt = EXTEND ra
  233. #define PPC_EXTSW_REG(ra, rt) \
  234. PPC_OP_REG(OP__EXT,OPE_EXTSW,rt,ra,_)
  235. #define PPC_EXTSH_REG(ra, rt) \
  236. PPC_OP_REG(OP__EXT,OPE_EXTSH,rt,ra,_)
  237. #define PPC_EXTSB_REG(ra, rt) \
  238. PPC_OP_REG(OP__EXT,OPE_EXTSB,rt,ra,_)
  239. #define PPC_EXTUW_REG(ra, rt) \
  240. PPC_OP_REG(OP__RLD,OPR_RLDICL|MD(32,0),rt,ra,_)
  241. #define PPC_EXTUH_REG(ra, rt) \
  242. PPC_OP_REG(OP__RLD,OPR_RLDICL|MD(48,0),rt,ra,_)
  243. #define PPC_EXTUB_REG(ra, rt) \
  244. PPC_OP_REG(OP__RLD,OPR_RLDICL|MD(56,0),rt,ra,_)
  245. // rt = ra SHIFT imm5/imm6
  246. #define PPC_LSL_IMM(ra, rt, bits) \
  247. PPC_OP_REG(OP__RLD,OPR_RLDICR|MD(63-(bits),bits),rt,ra,_)
  248. #define PPC_LSR_IMM(ra, rt, bits) \
  249. PPC_OP_REG(OP__RLD,OPR_RLDICL|MD(bits,64-(bits)),rt,ra,_)
  250. #define PPC_ASR_IMM(ra, rt, bits) \
  251. PPC_OP_REG(OP__EXT,OPE_SRADI|MD(_,bits),rt,ra,_)
  252. #define PPC_ROL_IMM(ra, rt, bits) \
  253. PPC_OP_REG(OP__RLD,OPR_RLDICL|MD(0,bits),rt,ra,_)
  254. #define PPC_LSLW_IMM(ra, rt, bits) \
  255. PPC_OP_REG(OP_RLWINM,MM(0,31-(bits)),rt,ra,bits)
  256. #define PPC_LSRW_IMM(ra, rt, bits) \
  257. PPC_OP_REG(OP_RLWINM,MM(bits,31),rt,ra,32-(bits))
  258. #define PPC_ASRW_IMM(ra, rt, bits) \
  259. PPC_OP_REG(OP__EXT,OPE_SRAWI,rt,ra,bits)
  260. #define PPC_ROLW_IMM(ra, rt, bits) \
  261. PPC_OP_REG(OP_RLWINM,MM(0,31),rt,ra,bits)
  262. // rt = EXTRACT/INSERT ra
  263. #define PPC_BFX_IMM(ra, rt, lsb, bits) \
  264. PPC_OP_REG(OP__RLD,OPR_RLDICL|MD(64-(bits),63&(lsb+bits)),rt,ra,_)
  265. #define PPC_BFXD_IMM(ra, rt, lsb, bits) /* extract to high bits, 64 bit */ \
  266. PPC_OP_REG(OP__RLD,OPR_RLDICR|MD(bits-1,lsb),rt,ra,_)
  267. #define PPC_BFI_IMM(ra, rt, lsb, bits) \
  268. PPC_OP_REG(OP__RLD,OPR_RLDIMI|MD(lsb,64-(lsb+bits)),rt,ra,_)
  269. #define PPC_BFXW_IMM(ra, rt, lsb, bits) \
  270. PPC_OP_REG(OP_RLWINM,MM(32-(bits),31),rt,ra,31&(lsb+bits))
  271. #define PPC_BFXT_IMM(ra, rt, lsb, bits) /* extract to high bits, 32 bit */ \
  272. PPC_OP_REG(OP_RLWINM,MM(0,bits-1),rt,ra,lsb)
  273. #define PPC_BFIW_IMM(ra, rt, lsb, bits) \
  274. PPC_OP_REG(OP_RLWIMI,MM(lsb,lsb+bits-1),rt,ra,32-(lsb+bits))
  275. // multiplication; NB in 32 bit results the topmost 32 bits are undefined
  276. #define PPC_MULL(rt, ra, rb) /* 64 bit */ \
  277. PPC_OP_REG(OP__EXT,OPE_MULLD,rt,ra,rb)
  278. #define PPC_MUL(rt, ra, rb) /* low 32 bit */ \
  279. PPC_OP_REG(OP__EXT,OPE_MULLW,rt,ra,rb)
  280. #define PPC_MULHS(rt, ra, rb) /* high 32 bit, signed */ \
  281. PPC_OP_REG(OP__EXT,OPE_MULHW,rt,ra,rb)
  282. #define PPC_MULHU(rt, ra, rb) /* high 32 bit, unsigned */ \
  283. PPC_OP_REG(OP__EXT,OPE_MULHWU,rt,ra,rb)
  284. // XXX use MAC* insns from the LMA group?
  285. // branching (only PC-relative)
  286. #define PPC_B(offs26) \
  287. PPC_OP_IMM(OP_B,_,_,(offs26)&~3)
  288. #define PPC_BL(offs26) \
  289. PPC_OP_IMM(OP_B,_,_,((offs26)&~3)|BLK)
  290. #define PPC_RET() \
  291. PPC_OP_REG(OP__CR,OPC_BCLR,BXX>>3,_,_)
  292. #define PPC_RETCOND(cond) \
  293. PPC_OP_REG(OP__CR,OPC_BCLR,(cond)>>3,(cond)&0x7,_)
  294. #define PPC_BCTRCOND(cond) \
  295. PPC_OP_REG(OP__CR,OPC_BCCTR,(cond)>>3,(cond)&0x7,_)
  296. #define PPC_BLCTRCOND(cond) \
  297. PPC_OP_REG(OP__CR,OPC_BCCTR|BLK,(cond)>>3,(cond)&0x7,_)
  298. #define PPC_BCOND(cond, offs19) \
  299. PPC_OP_IMM(OP_BC,(cond)>>3,(cond)&0x7,(offs19)&~3)
  300. // load/store, offset
  301. #define PPC_LDX_IMM(rt, ra, offs16) \
  302. PPC_OP_IMM(OP__LD,rt,ra,((u16)(offs16)&~3)|OPL_LD)
  303. #define PPC_LDW_IMM(rt, ra, offs16) \
  304. PPC_OP_IMM(OP_LWZ,rt,ra,(u16)(offs16))
  305. #define PPC_LDH_IMM(rt, ra, offs16) \
  306. PPC_OP_IMM(OP_LHZ,rt,ra,(u16)(offs16))
  307. #define PPC_LDB_IMM(rt, ra, offs16) \
  308. PPC_OP_IMM(OP_LBZ,rt,ra,(u16)(offs16))
  309. #define PPC_LDSH_IMM(rt, ra, offs16) \
  310. PPC_OP_IMM(OP_LHA,rt,ra,(u16)(offs16))
  311. #define PPC_STX_IMM(rt, ra, offs16) \
  312. PPC_OP_IMM(OP__ST,rt,ra,((u16)(offs16)&~3)|OPS_STD)
  313. #define PPC_STW_IMM(rt, ra, offs16) \
  314. PPC_OP_IMM(OP_STW,rt,ra,(u16)(offs16))
  315. #define PPC_STH_IMM(rt, ra, offs16) \
  316. PPC_OP_IMM(OP_STH,rt,ra,(u16)(offs16))
  317. #define PPC_STB_IMM(rt, ra, offs16) \
  318. PPC_OP_IMM(OP_STB,rt,ra,(u16)(offs16))
  319. // load/store, indexed
  320. #define PPC_LDX_REG(rt, ra, rb) \
  321. PPC_OP_REG(OP__EXT,OPE_LDX,rt,ra,rb)
  322. #define PPC_LDW_REG(rt, ra, rb) \
  323. PPC_OP_REG(OP__EXT,OPE_LWZX,rt,ra,rb)
  324. #define PPC_LDH_REG(rt, ra, rb) \
  325. PPC_OP_REG(OP__EXT,OPE_LHZX,rt,ra,rb)
  326. #define PPC_LDB_REG(rt, ra, rb) \
  327. PPC_OP_REG(OP__EXT,OPE_LBZX,rt,ra,rb)
  328. #define PPC_LDSH_REG(rt, ra, rb) \
  329. PPC_OP_REG(OP__EXT,OPE_LHAX,rt,ra,rb)
  330. #define PPC_STX_REG(rt, ra, rb) \
  331. PPC_OP_REG(OP__EXT,OPE_STX,rt,ra,rb)
  332. #define PPC_STW_REG(rt, ra, rb) \
  333. PPC_OP_REG(OP__EXT,OPE_STWX,rt,ra,rb)
  334. #define PPC_STH_REG(rt, ra, rb) \
  335. PPC_OP_REG(OP__EXT,OPE_STHX,rt,ra,rb)
  336. #define PPC_STB_REG(rt, ra, rb) \
  337. PPC_OP_REG(OP__EXT,OPE_STBX,rt,ra,rb)
  338. // special regs: LR, CTR, XER, CR
  339. #define PPC_MFSP_REG(rt, spr) \
  340. PPC_OP_REG(OP__EXT,OPE_MFSPR,rt,_,_CB(-(spr),5,0,5)|_CB(-(spr),5,5,0))
  341. #define PPC_MTSP_REG(rs, spr) \
  342. PPC_OP_REG(OP__EXT,OPE_MTSPR,rs,_,_CB(-(spr),5,0,5)|_CB(-(spr),5,5,0))
  343. #define PPC_MFCR_REG(rt) \
  344. PPC_OP_REG(OP__EXT,OPE_MFCR,rt,_,_)
  345. #define PPC_MTCRF_REG(rs, fm) \
  346. PPC_OP_REG(OP__EXT,OPE_MTCRF,rs,_,(fm)<<1)
  347. #define PPC_MCRXR_REG(crt) \
  348. PPC_OP_REG(OP__EXT,OPE_MCRXR,(crt)<<2,_,_)
  349. #define PPC_MCRCR_REG(crt, crf) \
  350. PPC_OP_REG(OP__CR,OPC_MCRF,(crt)<<2,(crf)<<1,_)
  351. #ifdef __powerpc64__
  352. #define PTR_SCALE 3
  353. #define PPC_LDP_IMM PPC_LDX_IMM
  354. #define PPC_LDP_REG PPC_LDX_REG
  355. #define PPC_STP_IMM PPC_STX_IMM
  356. #define PPC_STP_REG PPC_STX_REG
  357. #define PPC_BFXP_IMM PPC_BFX_IMM
  358. #define emith_uext_ptr(r) EMIT(PPC_EXTUW_REG(r, r))
  359. // "long" multiplication, 32x32 bit = 64 bit
  360. #define EMIT_PPC_MULLU_REG(dlo, dhi, s1, s2) do { \
  361. EMIT(PPC_EXTUW_REG(s1, s1)); \
  362. EMIT(PPC_EXTUW_REG(s2, s2)); \
  363. EMIT(PPC_MULL(dlo, s1, s2)); \
  364. EMIT(PPC_ASR_IMM(dhi, dlo, 32)); \
  365. } while (0)
  366. #define EMIT_PPC_MULLS_REG(dlo, dhi, s1, s2) do { \
  367. EMIT(PPC_EXTSW_REG(s1, s1)); \
  368. EMIT(PPC_EXTSW_REG(s2, s2)); \
  369. EMIT(PPC_MULL(dlo, s1, s2)); \
  370. EMIT(PPC_ASR_IMM(dhi, dlo, 32)); \
  371. } while (0)
  372. #define EMIT_PPC_MACLS_REG(dlo, dhi, s1, s2) do { \
  373. EMIT(PPC_EXTSW_REG(s1, s1)); \
  374. EMIT(PPC_EXTSW_REG(s2, s2)); \
  375. EMIT(PPC_MULL(AT, s1, s2)); \
  376. EMIT(PPC_BFI_IMM(dlo, dhi, 0, 32)); \
  377. emith_add_r_r(dlo, AT); \
  378. EMIT(PPC_ASR_IMM(dhi, dlo, 32)); \
  379. } while (0)
  380. #else
  381. #define PTR_SCALE 2
  382. #define PPC_LDP_IMM PPC_LDW_IMM
  383. #define PPC_LDP_REG PPC_LDW_REG
  384. #define PPC_STP_IMM PPC_STW_IMM
  385. #define PPC_STP_REG PPC_STW_REG
  386. #define PPC_BFXP_IMM PPC_BFXW_IMM
  387. #define emith_uext_ptr(r) /**/
  388. // "long" multiplication, 32x32 bit = 64 bit
  389. #define EMIT_PPC_MULLU_REG(dlo, dhi, s1, s2) do { \
  390. int at = (dlo == s1 || dlo == s2 ? AT : dlo); \
  391. EMIT(PPC_MUL(at, s1, s2)); \
  392. EMIT(PPC_MULHU(dhi, s1, s2)); \
  393. if (at != dlo) emith_move_r_r(dlo, at); \
  394. } while (0)
  395. #define EMIT_PPC_MULLS_REG(dlo, dhi, s1, s2) do { \
  396. int at = (dlo == s1 || dlo == s2 ? AT : dlo); \
  397. EMIT(PPC_MUL(at, s1, s2)); \
  398. EMIT(PPC_MULHS(dhi, s1, s2)); \
  399. if (at != dlo) emith_move_r_r(dlo, at); \
  400. } while (0)
  401. #define EMIT_PPC_MACLS_REG(dlo, dhi, s1, s2) do { \
  402. int t_ = rcache_get_tmp(); \
  403. EMIT_PPC_MULLS_REG(t_, AT, s1, s2); \
  404. EMIT(PPC_ADDC_REG(dlo, dlo, t_)); \
  405. EMIT(PPC_ADC_REG(dhi, dhi, AT)); \
  406. rcache_free_tmp(t_); \
  407. } while (0)
  408. #endif
  409. #define PTR_SIZE (1<<PTR_SCALE)
  410. // "emulated" RISC-V SLTU insn for the flag handling stuff XXX cumbersome
  411. #define EMIT_PPC_SLTWU_REG(rt, ra, rb) do { \
  412. EMIT(PPC_CMPLW_REG(ra, rb)); \
  413. EMIT(PPC_MFCR_REG(rt)); \
  414. EMIT(PPC_BFXW_IMM(rt, rt, 0, 1)); \
  415. } while (0)
  416. // XXX: tcache_ptr type for SVP and SH2 compilers differs..
  417. #define EMIT_PTR(ptr, x) \
  418. do { \
  419. *(u32 *)(ptr) = x; \
  420. ptr = (void *)((u8 *)(ptr) + sizeof(u32)); \
  421. } while (0)
  422. #define EMIT(op) \
  423. do { \
  424. EMIT_PTR(tcache_ptr, op); \
  425. COUNT_OP; \
  426. } while (0)
  427. // if-then-else conditional execution helpers
  428. #define JMP_POS(ptr) { \
  429. ptr = tcache_ptr; \
  430. EMIT(PPC_BCOND(cond_m, 0)); \
  431. }
  432. #define JMP_EMIT(cond, ptr) { \
  433. u32 val_ = (u8 *)tcache_ptr - (u8 *)(ptr); \
  434. EMIT_PTR(ptr, PPC_BCOND(cond_m, val_ & 0x0000fffc)); \
  435. }
  436. #define JMP_EMIT_NC(ptr) { \
  437. u32 val_ = (u8 *)tcache_ptr - (u8 *)(ptr); \
  438. EMIT_PTR(ptr, PPC_B(val_ & 0x03ffffffc)); \
  439. }
  440. #define EMITH_JMP_START(cond) { \
  441. int cond_m = emith_cond_check(cond); \
  442. u8 *cond_ptr; \
  443. JMP_POS(cond_ptr)
  444. #define EMITH_JMP_END(cond) \
  445. JMP_EMIT(cond, cond_ptr); \
  446. }
  447. #define EMITH_JMP3_START(cond) { \
  448. int cond_m = emith_cond_check(cond); \
  449. u8 *cond_ptr, *else_ptr; \
  450. JMP_POS(cond_ptr)
  451. #define EMITH_JMP3_MID(cond) \
  452. JMP_POS(else_ptr); \
  453. JMP_EMIT(cond, cond_ptr);
  454. #define EMITH_JMP3_END() \
  455. JMP_EMIT_NC(else_ptr); \
  456. }
  457. // "simple" jump (no more than a few insns)
  458. // ARM32 will use conditional instructions here
  459. #define EMITH_SJMP_START EMITH_JMP_START
  460. #define EMITH_SJMP_END EMITH_JMP_END
  461. #define EMITH_SJMP3_START EMITH_JMP3_START
  462. #define EMITH_SJMP3_MID EMITH_JMP3_MID
  463. #define EMITH_SJMP3_END EMITH_JMP3_END
  464. #define EMITH_SJMP2_START(cond) \
  465. EMITH_SJMP3_START(cond)
  466. #define EMITH_SJMP2_MID(cond) \
  467. EMITH_SJMP3_MID(cond)
  468. #define EMITH_SJMP2_END(cond) \
  469. EMITH_SJMP3_END()
  470. // flag register emulation. this is modelled after arm/x86.
  471. // the FNZ register stores the result of the last flag setting operation for
  472. // N and Z flag, used for EQ,NE,MI,PL branches.
  473. // the FC register stores the C flag (used for HI,HS,LO,LS,CC,CS).
  474. // the FV register stores information for V flag calculation (used for
  475. // GT,GE,LT,LE,VC,VS). V flag is costly and only fully calculated when needed.
  476. // the core registers may be temp registers, since the condition after calls
  477. // is undefined anyway.
  478. // flag emulation creates 2 (ie cmp #0/beq) up to 9 (ie adcf/ble) extra insns.
  479. // flag handling shortcuts may reduce this by 1-4 insns, see emith_cond_check()
  480. static int emith_cmp_ra, emith_cmp_rb; // registers used in cmp_r_r/cmp_r_imm
  481. static s32 emith_cmp_imm; // immediate value used in cmp_r_imm
  482. enum { _FHC=1, _FHV=2 } emith_flg_hint; // C/V flag usage hinted by compiler
  483. static int emith_flg_noV; // V flag known not to be set
  484. #define EMITH_HINT_COND(cond) do { \
  485. /* only need to check cond>>1 since the lowest bit inverts the cond */ \
  486. unsigned _mv = BITMASK3(DCOND_VS>>1,DCOND_GE>>1,DCOND_GT>>1); \
  487. unsigned _mc = _mv | BITMASK2(DCOND_HS>>1,DCOND_HI>>1); \
  488. emith_flg_hint = (_mv & BITMASK1(cond >> 1) ? _FHV : 0); \
  489. emith_flg_hint |= (_mc & BITMASK1(cond >> 1) ? _FHC : 0); \
  490. } while (0)
  491. // store minimal cc information: rt, rb^ra, carry
  492. // NB: the result *must* first go to FNZ, in case rt == ra or rt == rb.
  493. // NB: for adcf and sbcf, carry-in must be dealt with separately (see there)
  494. static void emith_set_arith_flags(int rt, int ra, int rb, s32 imm, int sub)
  495. {
  496. if (emith_flg_hint & _FHC) {
  497. if (sub) // C = sub:rb<rt, add:rt<rb
  498. EMIT_PPC_SLTWU_REG(FC, ra, FNZ);
  499. else EMIT_PPC_SLTWU_REG(FC, FNZ, ra);// C in FC, bit 0
  500. }
  501. if (emith_flg_hint & _FHV) {
  502. emith_flg_noV = 0;
  503. if (rb >= 0) // Nt^Ns in FV, bit 31
  504. EMIT(PPC_XOR_REG(FV, ra, rb));
  505. else if (imm == 0)
  506. emith_flg_noV = 1; // imm #0 can't overflow
  507. else if ((imm < 0) == !sub)
  508. EMIT(PPC_MVN_REG(FV, ra));
  509. else if ((imm > 0) == !sub)
  510. EMIT(PPC_MOV_REG(FV, ra));
  511. }
  512. // full V = Nd^Nt^Ns^C calculation is deferred until really needed
  513. if (rt && rt != FNZ)
  514. EMIT(PPC_MOV_REG(rt, FNZ)); // N,Z via result value in FNZ
  515. emith_cmp_ra = emith_cmp_rb = -1;
  516. }
  517. // handle cmp separately by storing the involved regs for later use.
  518. // this works for all conditions but VC/VS, but this is fortunately never used.
  519. static void emith_set_compare_flags(int ra, int rb, s32 imm)
  520. {
  521. emith_cmp_rb = rb;
  522. emith_cmp_ra = ra;
  523. emith_cmp_imm = imm;
  524. }
  525. // data processing, register
  526. #define emith_move_r_r_ptr(d, s) \
  527. EMIT(PPC_MOV_REG(d, s))
  528. #define emith_move_r_r_ptr_c(cond, d, s) \
  529. emith_move_r_r_ptr(d, s)
  530. #define emith_move_r_r(d, s) \
  531. emith_move_r_r_ptr(d, s)
  532. #define emith_move_r_r_c(cond, d, s) \
  533. emith_move_r_r(d, s)
  534. #define emith_mvn_r_r(d, s) \
  535. EMIT(PPC_MVN_REG(d, s))
  536. #define emith_add_r_r_r_lsl_ptr(d, s1, s2, simm) do { \
  537. if (simm) { \
  538. EMIT(PPC_LSLW_IMM(AT, s2, simm)); \
  539. EMIT(PPC_ADD_REG(d, s1, AT)); \
  540. } else EMIT(PPC_ADD_REG(d, s1, s2)); \
  541. } while (0)
  542. #define emith_add_r_r_r_lsl(d, s1, s2, simm) \
  543. emith_add_r_r_r_lsl_ptr(d, s1, s2, simm)
  544. #define emith_add_r_r_r_lsr(d, s1, s2, simm) do { \
  545. if (simm) { \
  546. EMIT(PPC_LSRW_IMM(AT, s2, simm)); \
  547. EMIT(PPC_ADD_REG(d, s1, AT)); \
  548. } else EMIT(PPC_ADD_REG(d, s1, s2)); \
  549. } while (0)
  550. #define emith_addf_r_r_r_lsl_ptr(d, s1, s2, simm) do { \
  551. if (simm) { \
  552. EMIT(PPC_LSLW_IMM(AT, s2, simm)); \
  553. EMIT(PPC_ADD_REG(FNZ, s1, AT)); \
  554. emith_set_arith_flags(d, s1, AT, 0, 0); \
  555. } else { \
  556. EMIT(PPC_ADD_REG(FNZ, s1, s2)); \
  557. emith_set_arith_flags(d, s1, s2, 0, 0); \
  558. } \
  559. } while (0)
  560. #define emith_addf_r_r_r_lsl(d, s1, s2, simm) do { \
  561. if (simm) { \
  562. EMIT(PPC_LSLW_IMM(AT, s2, simm)); \
  563. EMIT(PPC_ADD_REG(FNZ, s1, AT)); \
  564. emith_set_arith_flags(d, s1, AT, 0, 0); \
  565. } else { \
  566. EMIT(PPC_ADD_REG(FNZ, s1, s2)); \
  567. emith_set_arith_flags(d, s1, s2, 0, 0); \
  568. } \
  569. } while (0)
  570. #define emith_addf_r_r_r_lsr(d, s1, s2, simm) do { \
  571. if (simm) { \
  572. EMIT(PPC_LSRW_IMM(AT, s2, simm)); \
  573. EMIT(PPC_ADD_REG(FNZ, s1, AT)); \
  574. emith_set_arith_flags(d, s1, AT, 0, 0); \
  575. } else { \
  576. EMIT(PPC_ADD_REG(FNZ, s1, s2)); \
  577. emith_set_arith_flags(d, s1, s2, 0, 0); \
  578. } \
  579. } while (0)
  580. #define emith_sub_r_r_r_lsl(d, s1, s2, simm) do { \
  581. if (simm) { \
  582. EMIT(PPC_LSLW_IMM(AT, s2, simm)); \
  583. EMIT(PPC_SUB_REG(d, s1, AT)); \
  584. } else EMIT(PPC_SUB_REG(d, s1, s2)); \
  585. } while (0)
  586. #define emith_subf_r_r_r_lsl(d, s1, s2, simm) do { \
  587. if (simm) { \
  588. EMIT(PPC_LSLW_IMM(AT, s2, simm)); \
  589. EMIT(PPC_SUB_REG(FNZ, s1, AT)); \
  590. emith_set_arith_flags(d, s1, AT, 0, 1); \
  591. } else { \
  592. EMIT(PPC_SUB_REG(FNZ, s1, s2)); \
  593. emith_set_arith_flags(d, s1, s2, 0, 1); \
  594. } \
  595. } while (0)
  596. #define emith_or_r_r_r_lsl(d, s1, s2, simm) do { \
  597. if (simm) { \
  598. EMIT(PPC_LSLW_IMM(AT, s2, simm)); \
  599. EMIT(PPC_OR_REG(d, s1, AT)); \
  600. } else EMIT(PPC_OR_REG(d, s1, s2)); \
  601. } while (0)
  602. #define emith_or_r_r_r_lsr(d, s1, s2, simm) do { \
  603. if (simm) { \
  604. EMIT(PPC_LSRW_IMM(AT, s2, simm)); \
  605. EMIT(PPC_OR_REG(d, s1, AT)); \
  606. } else EMIT(PPC_OR_REG(d, s1, s2)); \
  607. } while (0)
  608. #define emith_eor_r_r_r_lsl(d, s1, s2, simm) do { \
  609. if (simm) { \
  610. EMIT(PPC_LSLW_IMM(AT, s2, simm)); \
  611. EMIT(PPC_XOR_REG(d, s1, AT)); \
  612. } else EMIT(PPC_XOR_REG(d, s1, s2)); \
  613. } while (0)
  614. #define emith_eor_r_r_r_lsr(d, s1, s2, simm) do { \
  615. if (simm) { \
  616. EMIT(PPC_LSRW_IMM(AT, s2, simm)); \
  617. EMIT(PPC_XOR_REG(d, s1, AT)); \
  618. } else EMIT(PPC_XOR_REG(d, s1, s2)); \
  619. } while (0)
  620. #define emith_and_r_r_r_lsl(d, s1, s2, simm) do { \
  621. if (simm) { \
  622. EMIT(PPC_LSLW_IMM(AT, s2, simm)); \
  623. EMIT(PPC_AND_REG(d, s1, AT)); \
  624. } else EMIT(PPC_AND_REG(d, s1, s2)); \
  625. } while (0)
  626. #define emith_or_r_r_lsl(d, s, lslimm) \
  627. emith_or_r_r_r_lsl(d, d, s, lslimm)
  628. #define emith_or_r_r_lsr(d, s, lsrimm) \
  629. emith_or_r_r_r_lsr(d, d, s, lsrimm)
  630. #define emith_eor_r_r_lsl(d, s, lslimm) \
  631. emith_eor_r_r_r_lsl(d, d, s, lslimm)
  632. #define emith_eor_r_r_lsr(d, s, lsrimm) \
  633. emith_eor_r_r_r_lsr(d, d, s, lsrimm)
  634. #define emith_add_r_r_r(d, s1, s2) \
  635. emith_add_r_r_r_lsl(d, s1, s2, 0)
  636. #define emith_addf_r_r_r_ptr(d, s1, s2) \
  637. emith_addf_r_r_r_lsl_ptr(d, s1, s2, 0)
  638. #define emith_addf_r_r_r(d, s1, s2) \
  639. emith_addf_r_r_r_lsl(d, s1, s2, 0)
  640. #define emith_sub_r_r_r(d, s1, s2) \
  641. emith_sub_r_r_r_lsl(d, s1, s2, 0)
  642. #define emith_subf_r_r_r(d, s1, s2) \
  643. emith_subf_r_r_r_lsl(d, s1, s2, 0)
  644. #define emith_or_r_r_r(d, s1, s2) \
  645. emith_or_r_r_r_lsl(d, s1, s2, 0)
  646. #define emith_eor_r_r_r(d, s1, s2) \
  647. emith_eor_r_r_r_lsl(d, s1, s2, 0)
  648. #define emith_and_r_r_r(d, s1, s2) \
  649. emith_and_r_r_r_lsl(d, s1, s2, 0)
  650. #define emith_add_r_r_ptr(d, s) \
  651. emith_add_r_r_r_lsl_ptr(d, d, s, 0)
  652. #define emith_add_r_r(d, s) \
  653. emith_add_r_r_r(d, d, s)
  654. #define emith_sub_r_r(d, s) \
  655. emith_sub_r_r_r(d, d, s)
  656. #define emith_neg_r_r(d, s) \
  657. EMIT(PPC_NEG_REG(d, s))
  658. #define emith_adc_r_r_r(d, s1, s2) do { \
  659. emith_add_r_r_r(AT, s2, FC); \
  660. emith_add_r_r_r(d, s1, AT); \
  661. } while (0)
  662. #define emith_sbc_r_r_r(d, s1, s2) do { \
  663. emith_add_r_r_r(AT, s2, FC); \
  664. emith_sub_r_r_r(d, s1, AT); \
  665. } while (0)
  666. #define emith_adc_r_r(d, s) \
  667. emith_adc_r_r_r(d, d, s)
  668. #define emith_negc_r_r(d, s) do { \
  669. emith_neg_r_r(d, s); \
  670. emith_sub_r_r(d, FC); \
  671. } while (0)
  672. // NB: the incoming carry Cin can cause Cout if s2+Cin=0 (or s1+Cin=0 FWIW)
  673. // moreover, if s2+Cin=0 caused Cout, s1+s2+Cin=s1+0 can't cause another Cout
  674. #define emith_adcf_r_r_r(d, s1, s2) do { \
  675. emith_add_r_r_r(FNZ, s2, FC); \
  676. EMIT_PPC_SLTWU_REG(AT, FNZ, FC); \
  677. emith_add_r_r_r(FNZ, s1, FNZ); \
  678. emith_set_arith_flags(d, s1, s2, 0, 0); \
  679. emith_or_r_r(FC, AT); \
  680. } while (0)
  681. #define emith_sbcf_r_r_r(d, s1, s2) do { \
  682. emith_add_r_r_r(FNZ, s2, FC); \
  683. EMIT_PPC_SLTWU_REG(AT, FNZ, FC); \
  684. emith_sub_r_r_r(FNZ, s1, FNZ); \
  685. emith_set_arith_flags(d, s1, s2, 0, 1); \
  686. emith_or_r_r(FC, AT); \
  687. } while (0)
  688. #define emith_and_r_r(d, s) \
  689. emith_and_r_r_r(d, d, s)
  690. #define emith_and_r_r_c(cond, d, s) \
  691. emith_and_r_r(d, s)
  692. #define emith_or_r_r(d, s) \
  693. emith_or_r_r_r(d, d, s)
  694. #define emith_eor_r_r(d, s) \
  695. emith_eor_r_r_r(d, d, s)
  696. #define emith_tst_r_r_ptr(d, s) do { \
  697. if (d != s) { \
  698. emith_and_r_r_r(FNZ, d, s); \
  699. emith_cmp_ra = emith_cmp_rb = -1; \
  700. } else emith_cmp_ra = s, emith_cmp_rb = -1, emith_cmp_imm = 0; \
  701. } while (0)
  702. #define emith_tst_r_r(d, s) \
  703. emith_tst_r_r_ptr(d, s)
  704. #define emith_teq_r_r(d, s) do { \
  705. emith_eor_r_r_r(FNZ, d, s); \
  706. emith_cmp_ra = emith_cmp_rb = -1; \
  707. } while (0)
  708. #define emith_cmp_r_r(d, s) \
  709. emith_set_compare_flags(d, s, 0)
  710. // emith_subf_r_r_r(FNZ, d, s)
  711. #define emith_addf_r_r(d, s) \
  712. emith_addf_r_r_r(d, d, s)
  713. #define emith_subf_r_r(d, s) \
  714. emith_subf_r_r_r(d, d, s)
  715. #define emith_adcf_r_r(d, s) \
  716. emith_adcf_r_r_r(d, d, s)
  717. #define emith_sbcf_r_r(d, s) \
  718. emith_sbcf_r_r_r(d, d, s)
  719. #define emith_negcf_r_r(d, s) do { \
  720. emith_add_r_r_r(FNZ, s, FC); \
  721. EMIT_PPC_SLTWU_REG(AT, FNZ, FC); \
  722. emith_neg_r_r(FNZ, FNZ); \
  723. emith_set_arith_flags(d, Z0, s, 0, 1); \
  724. emith_or_r_r(FC, AT); \
  725. } while (0)
  726. // move immediate
  727. static void emith_move_imm(int r, int ptr, uintptr_t imm)
  728. {
  729. #ifdef __powerpc64__
  730. if (ptr && (s32)imm != imm) {
  731. emith_move_imm(r, 0, imm >> 32);
  732. if (imm >> 32)
  733. EMIT(PPC_LSL_IMM(r, r, 32));
  734. if (imm & 0x0000ffff)
  735. EMIT(PPC_OR_IMM(r, r, imm & 0x0000ffff));
  736. if (imm & 0xffff0000)
  737. EMIT(PPC_ORT_IMM(r, r, (imm & 0xffff0000) >> 16));
  738. } else
  739. #endif
  740. if ((s16)imm != (s32)imm) {
  741. EMIT(PPC_ADDT_IMM(r, Z0, (u16)(imm>>16)));
  742. if ((s16)imm)
  743. EMIT(PPC_OR_IMM(r, r, (u16)(imm)));
  744. } else EMIT(PPC_ADD_IMM(r, Z0, (u16)imm));
  745. }
  746. #define emith_move_r_ptr_imm(r, imm) \
  747. emith_move_imm(r, 1, (uintptr_t)(imm))
  748. #define emith_move_r_imm(r, imm) \
  749. emith_move_imm(r, 0, (u32)(imm))
  750. #define emith_move_r_imm_c(cond, r, imm) \
  751. emith_move_r_imm(r, imm)
  752. #define emith_move_r_imm_s8_patchable(r, imm) \
  753. EMIT(PPC_ADD_IMM(r, Z0, (s8)(imm)))
  754. #define emith_move_r_imm_s8_patch(ptr, imm) do { \
  755. u32 *ptr_ = (u32 *)ptr; \
  756. EMIT_PTR(ptr_, (*ptr_ & 0xffff0000) | (u16)(s8)(imm)); \
  757. } while (0)
  758. // arithmetic, immediate - can only be ADDI, since SUBI doesn't exist
  759. static void emith_add_imm(int rt, int ra, u32 imm)
  760. {
  761. int s = ra;
  762. if ((u16)imm) {
  763. EMIT(PPC_ADD_IMM(rt, s, (u16)imm));
  764. s = rt;
  765. }
  766. // adjust for sign extension in ADDI
  767. imm = (imm >> 16) + ((s16)imm < 0);
  768. if ((u16)imm || rt != s)
  769. EMIT(PPC_ADDT_IMM(rt, s, (u16)imm));
  770. }
  771. #define emith_add_r_imm(r, imm) \
  772. emith_add_r_r_imm(r, r, imm)
  773. #define emith_add_r_imm_c(cond, r, imm) \
  774. emith_add_r_imm(r, imm)
  775. #define emith_addf_r_imm(r, imm) \
  776. emith_addf_r_r_imm(r, imm)
  777. #define emith_sub_r_imm(r, imm) \
  778. emith_sub_r_r_imm(r, r, imm)
  779. #define emith_sub_r_imm_c(cond, r, imm) \
  780. emith_sub_r_imm(r, imm)
  781. #define emith_subf_r_imm(r, imm) \
  782. emith_subf_r_r_imm(r, r, imm)
  783. #define emith_adc_r_imm(r, imm) \
  784. emith_adc_r_r_imm(r, r, imm)
  785. #define emith_adcf_r_imm(r, imm) \
  786. emith_adcf_r_r_imm(r, r, imm)
  787. #define emith_cmp_r_imm(r, imm) \
  788. emith_set_compare_flags(r, -1, imm)
  789. // emith_subf_r_r_imm(FNZ, r, (s16)imm)
  790. #define emith_add_r_r_ptr_imm(d, s, imm) \
  791. emith_add_imm(d, s, imm)
  792. #define emith_add_r_r_imm(d, s, imm) \
  793. emith_add_r_r_ptr_imm(d, s, imm)
  794. #define emith_addf_r_r_imm(d, s, imm) do { \
  795. emith_add_r_r_imm(FNZ, s, imm); \
  796. emith_set_arith_flags(d, s, -1, imm, 0); \
  797. } while (0)
  798. #define emith_adc_r_r_imm(d, s, imm) do { \
  799. emith_add_r_r_r(AT, s, FC); \
  800. emith_add_r_r_imm(d, AT, imm); \
  801. } while (0)
  802. #define emith_adcf_r_r_imm(d, s, imm) do { \
  803. if (imm == 0) { \
  804. emith_add_r_r_r(FNZ, s, FC); \
  805. emith_set_arith_flags(d, s, -1, 1, 0); \
  806. } else { \
  807. emith_add_r_r_r(FNZ, s, FC); \
  808. EMIT_PPC_SLTWU_REG(AT, FNZ, FC); \
  809. emith_add_r_r_imm(FNZ, FNZ, imm); \
  810. emith_set_arith_flags(d, s, -1, imm, 0); \
  811. emith_or_r_r(FC, AT); \
  812. } \
  813. } while (0)
  814. // NB: no SUBI, since ADDI takes a signed imm
  815. #define emith_sub_r_r_imm(d, s, imm) \
  816. emith_add_r_r_imm(d, s, -(imm))
  817. #define emith_sub_r_r_imm_c(cond, d, s, imm) \
  818. emith_sub_r_r_imm(d, s, imm)
  819. #define emith_subf_r_r_imm(d, s, imm) do { \
  820. emith_sub_r_r_imm(FNZ, s, imm); \
  821. emith_set_arith_flags(d, s, -1, imm, 1); \
  822. } while (0)
  823. // logical, immediate
  824. #define emith_log_imm2(opi, opr, rt, ra, imm) do { \
  825. if ((imm) >> 16 || opi == OP_ANDI) { /* too big, or microcoded ANDI */ \
  826. emith_move_r_imm(AT, imm); \
  827. EMIT(PPC_OP_REG(OP__EXT, opr, ra, rt, AT)); \
  828. } else if (/*opi == OP_ANDI ||*/ imm || rt != ra) \
  829. EMIT(PPC_OP_IMM(opi, ra, rt, imm)); \
  830. } while (0)
  831. #define emith_log_imm(op, rt, ra, imm) \
  832. emith_log_imm2(OP_##op##I, OPE_##op, rt, ra, imm)
  833. #define emith_and_r_imm(r, imm) \
  834. emith_log_imm(AND, r, r, imm)
  835. #define emith_or_r_imm(r, imm) \
  836. emith_log_imm(OR, r, r, imm)
  837. #define emith_or_r_imm_c(cond, r, imm) \
  838. emith_or_r_imm(r, imm)
  839. #define emith_eor_r_imm_ptr(r, imm) \
  840. emith_log_imm(XOR, r, r, imm)
  841. #define emith_eor_r_imm_ptr_c(cond, r, imm) \
  842. emith_eor_r_imm_ptr(r, imm)
  843. #define emith_eor_r_imm(r, imm) \
  844. emith_eor_r_imm_ptr(r, imm)
  845. #define emith_eor_r_imm_c(cond, r, imm) \
  846. emith_eor_r_imm(r, imm)
  847. /* NB: BIC #imm not available; use AND #~imm instead */
  848. #define emith_bic_r_imm(r, imm) \
  849. emith_log_imm(AND, r, r, ~(imm))
  850. #define emith_bic_r_imm_c(cond, r, imm) \
  851. emith_bic_r_imm(r, imm)
  852. #define emith_tst_r_imm(r, imm) do { \
  853. emith_log_imm(AND, FNZ, r, imm); \
  854. emith_cmp_ra = emith_cmp_rb = -1; \
  855. } while (0)
  856. #define emith_tst_r_imm_c(cond, r, imm) \
  857. emith_tst_r_imm(r, imm)
  858. #define emith_and_r_r_imm(d, s, imm) \
  859. emith_log_imm(AND, d, s, imm)
  860. #define emith_or_r_r_imm(d, s, imm) \
  861. emith_log_imm(OR, d, s, imm)
  862. #define emith_eor_r_r_imm(d, s, imm) \
  863. emith_log_imm(XOR, d, s, imm)
  864. // shift
  865. #define emith_lsl(d, s, cnt) \
  866. EMIT(PPC_LSLW_IMM(d, s, cnt))
  867. #define emith_lsr(d, s, cnt) \
  868. EMIT(PPC_LSRW_IMM(d, s, cnt))
  869. #define emith_asr(d, s, cnt) \
  870. EMIT(PPC_ASRW_IMM(d, s, cnt))
  871. #define emith_ror(d, s, cnt) \
  872. EMIT(PPC_ROLW_IMM(d, s, 32-(cnt)))
  873. #define emith_ror_c(cond, d, s, cnt) \
  874. emith_ror(d, s, cnt)
  875. #define emith_rol(d, s, cnt) \
  876. EMIT(PPC_ROLW_IMM(d, s, cnt)); \
  877. #define emith_rorc(d) do { \
  878. emith_lsr(d, d, 1); \
  879. emith_lsl(AT, FC, 31); \
  880. emith_or_r_r(d, AT); \
  881. } while (0)
  882. #define emith_rolc(d) do { \
  883. emith_lsl(d, d, 1); \
  884. emith_or_r_r(d, FC); \
  885. } while (0)
  886. // NB: all flag setting shifts make V undefined
  887. #define emith_lslf(d, s, cnt) do { \
  888. int _s = s; \
  889. if ((cnt) > 1) { \
  890. emith_lsl(d, s, cnt-1); \
  891. _s = d; \
  892. } \
  893. if ((cnt) > 0) { \
  894. emith_lsr(FC, _s, 31); \
  895. emith_lsl(d, _s, 1); \
  896. } \
  897. emith_move_r_r(FNZ, d); \
  898. emith_cmp_ra = emith_cmp_rb = -1; \
  899. } while (0)
  900. #define emith_lsrf(d, s, cnt) do { \
  901. int _s = s; \
  902. if ((cnt) > 1) { \
  903. emith_lsr(d, s, cnt-1); \
  904. _s = d; \
  905. } \
  906. if ((cnt) > 0) { \
  907. emith_and_r_r_imm(FC, _s, 1); \
  908. emith_lsr(d, _s, 1); \
  909. } \
  910. emith_move_r_r(FNZ, d); \
  911. emith_cmp_ra = emith_cmp_rb = -1; \
  912. } while (0)
  913. #define emith_asrf(d, s, cnt) do { \
  914. int _s = s; \
  915. if ((cnt) > 1) { \
  916. emith_asr(d, s, cnt-1); \
  917. _s = d; \
  918. } \
  919. if ((cnt) > 0) { \
  920. emith_and_r_r_imm(FC, _s, 1); \
  921. emith_asr(d, _s, 1); \
  922. } \
  923. emith_move_r_r(FNZ, d); \
  924. emith_cmp_ra = emith_cmp_rb = -1; \
  925. } while (0)
  926. #define emith_rolf(d, s, cnt) do { \
  927. emith_rol(d, s, cnt); \
  928. emith_and_r_r_imm(FC, d, 1); \
  929. emith_move_r_r(FNZ, d); \
  930. emith_cmp_ra = emith_cmp_rb = -1; \
  931. } while (0)
  932. #define emith_rorf(d, s, cnt) do { \
  933. emith_ror(d, s, cnt); \
  934. emith_lsr(FC, d, 31); \
  935. emith_move_r_r(FNZ, d); \
  936. emith_cmp_ra = emith_cmp_rb = -1; \
  937. } while (0)
  938. #define emith_rolcf(d) do { \
  939. emith_lsr(AT, d, 31); \
  940. emith_lsl(d, d, 1); \
  941. emith_or_r_r(d, FC); \
  942. emith_move_r_r(FC, AT); \
  943. emith_move_r_r(FNZ, d); \
  944. emith_cmp_ra = emith_cmp_rb = -1; \
  945. } while (0)
  946. #define emith_rorcf(d) do { \
  947. emith_and_r_r_imm(AT, d, 1); \
  948. emith_lsr(d, d, 1); \
  949. emith_lsl(FC, FC, 31); \
  950. emith_or_r_r(d, FC); \
  951. emith_move_r_r(FC, AT); \
  952. emith_move_r_r(FNZ, d); \
  953. emith_cmp_ra = emith_cmp_rb = -1; \
  954. } while (0)
  955. // signed/unsigned extend
  956. #define emith_clear_msb(d, s, count) /* bits to clear */ \
  957. EMIT(PPC_BFXW_IMM(d, s, count, 32-(count)))
  958. #define emith_clear_msb_c(cond, d, s, count) \
  959. emith_clear_msb(d, s, count)
  960. #define emith_sext(d, s, count) /* bits to keep */ do { \
  961. if (count == 8) \
  962. EMIT(PPC_EXTSB_REG(d, s)); \
  963. else if (count == 16) \
  964. EMIT(PPC_EXTSH_REG(d, s)); \
  965. else { \
  966. emith_lsl(d, s, 32-(count)); \
  967. emith_asr(d, d, 32-(count)); \
  968. } \
  969. } while (0)
  970. // multiply Rd = Rn*Rm (+ Ra)
  971. #define emith_mul(d, s1, s2) \
  972. EMIT(PPC_MUL(d, s1, s2))
  973. #define emith_mul_u64(dlo, dhi, s1, s2) \
  974. EMIT_PPC_MULLU_REG(dlo, dhi, s1, s2)
  975. #define emith_mul_s64(dlo, dhi, s1, s2) \
  976. EMIT_PPC_MULLS_REG(dlo, dhi, s1, s2)
  977. #define emith_mula_s64(dlo, dhi, s1, s2) \
  978. EMIT_PPC_MACLS_REG(dlo, dhi, s1, s2)
  979. #define emith_mula_s64_c(cond, dlo, dhi, s1, s2) \
  980. emith_mula_s64(dlo, dhi, s1, s2)
  981. // load/store. offs has 16 bits signed, which is currently sufficient
  982. #define emith_read_r_r_offs_ptr(r, ra, offs) \
  983. EMIT(PPC_LDP_IMM(r, ra, offs))
  984. #define emith_read_r_r_offs_ptr_c(cond, r, ra, offs) \
  985. emith_read_r_r_offs_ptr(r, ra, offs)
  986. #define emith_read_r_r_offs(r, ra, offs) \
  987. EMIT(PPC_LDW_IMM(r, ra, offs))
  988. #define emith_read_r_r_offs_c(cond, r, ra, offs) \
  989. emith_read_r_r_offs(r, ra, offs)
  990. #define emith_read_r_r_r_ptr(r, ra, rm) \
  991. EMIT(PPC_LDP_REG(r, ra, rm))
  992. #define emith_read_r_r_r(r, ra, rm) \
  993. EMIT(PPC_LDW_REG(r, ra, rm))
  994. #define emith_read_r_r_r_c(cond, r, ra, rm) \
  995. emith_read_r_r_r(r, ra, rm)
  996. #define emith_read8_r_r_offs(r, ra, offs) \
  997. EMIT(PPC_LDB_IMM(r, ra, offs))
  998. #define emith_read8_r_r_offs_c(cond, r, ra, offs) \
  999. emith_read8_r_r_offs(r, ra, offs)
  1000. #define emith_read8_r_r_r(r, ra, rm) \
  1001. EMIT(PPC_LDB_REG(r, ra, rm))
  1002. #define emith_read8_r_r_r_c(cond, r, ra, rm) \
  1003. emith_read8_r_r_r(r, ra, rm)
  1004. #define emith_read16_r_r_offs(r, ra, offs) \
  1005. EMIT(PPC_LDH_IMM(r, ra, offs))
  1006. #define emith_read16_r_r_offs_c(cond, r, ra, offs) \
  1007. emith_read16_r_r_offs(r, ra, offs)
  1008. #define emith_read16_r_r_r(r, ra, rm) \
  1009. EMIT(PPC_LDH_REG(r, ra, rm))
  1010. #define emith_read16_r_r_r_c(cond, r, ra, rm) \
  1011. emith_read16_r_r_r(r, ra, rm)
  1012. #define emith_read8s_r_r_offs(r, ra, offs) do { \
  1013. EMIT(PPC_LDB_IMM(r, ra, offs)); \
  1014. EMIT(PPC_EXTSB_REG(r, r)); \
  1015. } while (0)
  1016. #define emith_read8s_r_r_offs_c(cond, r, ra, offs) \
  1017. emith_read8s_r_r_offs(r, ra, offs)
  1018. #define emith_read8s_r_r_r(r, ra, rm) do { \
  1019. EMIT(PPC_LDB_REG(r, ra, rm)); \
  1020. EMIT(PPC_EXTSB_REG(r, r)); \
  1021. } while (0)
  1022. #define emith_read8s_r_r_r_c(cond, r, ra, rm) \
  1023. emith_read8s_r_r_r(r, ra, rm)
  1024. #define emith_read16s_r_r_offs(r, ra, offs) do { \
  1025. EMIT(PPC_LDH_IMM(r, ra, offs)); \
  1026. EMIT(PPC_EXTSH_REG(r, r)); \
  1027. } while (0)
  1028. #define emith_read16s_r_r_offs_c(cond, r, ra, offs) \
  1029. emith_read16s_r_r_offs(r, ra, offs)
  1030. #define emith_read16s_r_r_r(r, ra, rm) do { \
  1031. EMIT(PPC_LDH_REG(r, ra, rm)); \
  1032. EMIT(PPC_EXTSH_REG(r, r)); \
  1033. } while (0)
  1034. #define emith_read16s_r_r_r_c(cond, r, ra, rm) \
  1035. emith_read16s_r_r_r(r, ra, rm)
  1036. #define emith_write_r_r_offs_ptr(r, ra, offs) \
  1037. EMIT(PPC_STP_IMM(r, ra, offs))
  1038. #define emith_write_r_r_offs_ptr_c(cond, r, ra, offs) \
  1039. emith_write_r_r_offs_ptr(r, ra, offs)
  1040. #define emith_write_r_r_r_ptr(r, ra, rm) \
  1041. EMIT(PPC_STP_REG(r, ra, rm))
  1042. #define emith_write_r_r_r_ptr_c(cond, r, ra, rm) \
  1043. emith_write_r_r_r_ptr(r, ra, rm)
  1044. #define emith_write_r_r_offs(r, ra, offs) \
  1045. EMIT(PPC_STW_IMM(r, ra, offs))
  1046. #define emith_write_r_r_offs_c(cond, r, ra, offs) \
  1047. emith_write_r_r_offs(r, ra, offs)
  1048. #define emith_write_r_r_r(r, ra, rm) \
  1049. EMIT(PPC_STW_REG(r, ra, rm))
  1050. #define emith_write_r_r_r_c(cond, r, ra, rm) \
  1051. emith_write_r_r_r(r, ra, rm)
  1052. #define emith_ctx_read_ptr(r, offs) \
  1053. emith_read_r_r_offs_ptr(r, CONTEXT_REG, offs)
  1054. #define emith_ctx_read(r, offs) \
  1055. emith_read_r_r_offs(r, CONTEXT_REG, offs)
  1056. #define emith_ctx_read_c(cond, r, offs) \
  1057. emith_ctx_read(r, offs)
  1058. #define emith_ctx_write_ptr(r, offs) \
  1059. emith_write_r_r_offs_ptr(r, CONTEXT_REG, offs)
  1060. #define emith_ctx_write(r, offs) \
  1061. emith_write_r_r_offs(r, CONTEXT_REG, offs)
  1062. #define emith_ctx_read_multiple(r, offs, cnt, tmpr) do { \
  1063. int r_ = r, offs_ = offs, cnt_ = cnt; \
  1064. for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
  1065. emith_ctx_read(r_, offs_); \
  1066. } while (0)
  1067. #define emith_ctx_write_multiple(r, offs, cnt, tmpr) do { \
  1068. int r_ = r, offs_ = offs, cnt_ = cnt; \
  1069. for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
  1070. emith_ctx_write(r_, offs_); \
  1071. } while (0)
  1072. // function call handling
  1073. #define emith_save_caller_regs(mask) do { \
  1074. int _c, _z = PTR_SIZE; u32 _m = mask & 0x1ff8; /* r3-r12 */ \
  1075. if (__builtin_parity(_m) == 1) _m |= 0x1; /* ABI align */ \
  1076. int _s = count_bits(_m) * _z, _o = _s; \
  1077. if (_s) emith_add_r_r_ptr_imm(SP, SP, -_s); \
  1078. for (_c = HOST_REGS-1; _m && _c >= 0; _m &= ~(1 << _c), _c--) \
  1079. if (_m & (1 << _c)) \
  1080. { _o -= _z; if (_c) emith_write_r_r_offs_ptr(_c, SP, _o); } \
  1081. } while (0)
  1082. #define emith_restore_caller_regs(mask) do { \
  1083. int _c, _z = PTR_SIZE; u32 _m = mask & 0x1ff8; \
  1084. if (__builtin_parity(_m) == 1) _m |= 0x1; \
  1085. int _s = count_bits(_m) * _z, _o = 0; \
  1086. for (_c = 0; _m && _c < HOST_REGS; _m &= ~(1 << _c), _c++) \
  1087. if (_m & (1 << _c)) \
  1088. { if (_c) emith_read_r_r_offs_ptr(_c, SP, _o); _o += _z; } \
  1089. if (_s) emith_add_r_r_ptr_imm(SP, SP, _s); \
  1090. } while (0)
  1091. #define host_arg2reg(rt, arg) \
  1092. rt = (arg+3)
  1093. #define emith_pass_arg_r(arg, reg) \
  1094. emith_move_r_r(arg, reg)
  1095. #define emith_pass_arg_imm(arg, imm) \
  1096. emith_move_r_imm(arg, imm)
  1097. // branching
  1098. #define emith_invert_branch(cond) /* inverted conditional branch */ \
  1099. ((cond) ^ 0x40)
  1100. // evaluate the emulated condition, returns a register/branch type pair
  1101. static int emith_cmpr_check(int rs, int rt, int cond, u32 *op)
  1102. {
  1103. int b = -1;
  1104. // condition check for comparing 2 registers
  1105. switch (cond) {
  1106. case DCOND_EQ: *op = PPC_CMPW_REG(rs, rt); b = BEQ; break;
  1107. case DCOND_NE: *op = PPC_CMPW_REG(rs, rt); b = BNE; break;
  1108. case DCOND_LO: *op = PPC_CMPLW_REG(rs, rt); b = BLT; break;
  1109. case DCOND_HS: *op = PPC_CMPLW_REG(rs, rt); b = BGE; break;
  1110. case DCOND_LS: *op = PPC_CMPLW_REG(rs, rt); b = BLE; break;
  1111. case DCOND_HI: *op = PPC_CMPLW_REG(rs, rt); b = BGT; break;
  1112. case DCOND_LT: *op = PPC_CMPW_REG(rs, rt); b = BLT; break;
  1113. case DCOND_GE: *op = PPC_CMPW_REG(rs, rt); b = BGE; break;
  1114. case DCOND_LE: *op = PPC_CMPW_REG(rs, rt); b = BLE; break;
  1115. case DCOND_GT: *op = PPC_CMPW_REG(rs, rt); b = BGT; break;
  1116. }
  1117. return b;
  1118. }
  1119. static int emith_cmpi_check(int rs, s32 imm, int cond, u32 *op)
  1120. {
  1121. int b = -1;
  1122. // condition check for comparing register with immediate
  1123. switch (cond) {
  1124. case DCOND_EQ: *op = PPC_CMPW_IMM(rs, (u16)imm), b = BEQ; break;
  1125. case DCOND_NE: *op = PPC_CMPW_IMM(rs, (u16)imm), b = BNE; break;
  1126. case DCOND_LO: *op = PPC_CMPLW_IMM(rs, (u16)imm), b = BLT; break;
  1127. case DCOND_HS: *op = PPC_CMPLW_IMM(rs, (u16)imm), b = BGE; break;
  1128. case DCOND_LS: *op = PPC_CMPLW_IMM(rs, (u16)imm), b = BLE; break;
  1129. case DCOND_HI: *op = PPC_CMPLW_IMM(rs, (u16)imm), b = BGT; break;
  1130. case DCOND_LT: *op = PPC_CMPW_IMM(rs, (u16)imm), b = BLT; break;
  1131. case DCOND_GE: *op = PPC_CMPW_IMM(rs, (u16)imm), b = BGE; break;
  1132. case DCOND_LE: *op = PPC_CMPW_IMM(rs, (u16)imm), b = BLE; break;
  1133. case DCOND_GT: *op = PPC_CMPW_IMM(rs, (u16)imm), b = BGT; break;
  1134. }
  1135. return b;
  1136. }
  1137. static int emith_cond_check(int cond)
  1138. {
  1139. int b = -1;
  1140. u32 op = 0;
  1141. if (emith_cmp_ra >= 0) {
  1142. if (emith_cmp_rb != -1)
  1143. b = emith_cmpr_check(emith_cmp_ra,emith_cmp_rb, cond,&op);
  1144. else b = emith_cmpi_check(emith_cmp_ra,emith_cmp_imm,cond,&op);
  1145. }
  1146. // shortcut for V known to be 0
  1147. if (b < 0 && emith_flg_noV) switch (cond) {
  1148. case DCOND_VS: /* no branch */ break; // never
  1149. case DCOND_VC: b = BXX; break; // always
  1150. case DCOND_LT: op = PPC_CMPW_IMM(FNZ, 0); b = BLT; break; // N
  1151. case DCOND_GE: op = PPC_CMPW_IMM(FNZ, 0); b = BGE; break; // !N
  1152. case DCOND_LE: op = PPC_CMPW_IMM(FNZ, 0); b = BLE; break; // N || Z
  1153. case DCOND_GT: op = PPC_CMPW_IMM(FNZ, 0); b = BGT; break; // !N && !Z
  1154. }
  1155. // the full monty if no shortcut
  1156. if (b < 0) switch (cond) {
  1157. // conditions using NZ
  1158. case DCOND_EQ: op = PPC_CMPW_IMM(FNZ, 0); b = BEQ; break; // Z
  1159. case DCOND_NE: op = PPC_CMPW_IMM(FNZ, 0); b = BNE; break; // !Z
  1160. case DCOND_MI: op = PPC_CMPW_IMM(FNZ, 0); b = BLT; break; // N
  1161. case DCOND_PL: op = PPC_CMPW_IMM(FNZ, 0); b = BGE; break; // !N
  1162. // conditions using C
  1163. case DCOND_LO: op = PPC_CMPW_IMM(FC , 0); b = BNE; break; // C
  1164. case DCOND_HS: op = PPC_CMPW_IMM(FC , 0); b = BEQ; break; // !C
  1165. // conditions using CZ
  1166. case DCOND_LS: // C || Z
  1167. case DCOND_HI: // !C && !Z
  1168. EMIT(PPC_ADD_IMM(AT, FC, -1)); // !C && !Z
  1169. EMIT(PPC_AND_REG(AT, FNZ, AT));
  1170. op = PPC_CMPW_IMM(AT , 0); b = (cond == DCOND_HI ? BNE : BEQ);
  1171. break;
  1172. // conditions using V
  1173. case DCOND_VS: // V
  1174. case DCOND_VC: // !V
  1175. EMIT(PPC_XOR_REG(AT, FV, FNZ)); // V = Nt^Ns^Nd^C
  1176. EMIT(PPC_LSRW_IMM(AT, AT, 31));
  1177. EMIT(PPC_XOR_REG(AT, AT, FC));
  1178. op = PPC_CMPW_IMM(AT , 0); b = (cond == DCOND_VS ? BNE : BEQ);
  1179. break;
  1180. // conditions using VNZ
  1181. case DCOND_LT: // N^V
  1182. case DCOND_GE: // !(N^V)
  1183. EMIT(PPC_LSRW_IMM(AT, FV, 31)); // Nd^V = Nt^Ns^C
  1184. EMIT(PPC_XOR_REG(AT, FC, AT));
  1185. op = PPC_CMPW_IMM(AT , 0); b = (cond == DCOND_LT ? BNE : BEQ);
  1186. break;
  1187. case DCOND_LE: // (N^V) || Z
  1188. case DCOND_GT: // !(N^V) && !Z
  1189. EMIT(PPC_LSRW_IMM(AT, FV, 31)); // Nd^V = Nt^Ns^C
  1190. EMIT(PPC_XOR_REG(AT, FC, AT));
  1191. EMIT(PPC_ADD_IMM(AT, AT, -1)); // !(Nd^V) && !Z
  1192. EMIT(PPC_AND_REG(AT, FNZ, AT));
  1193. op = PPC_CMPW_IMM(AT , 0); b = (cond == DCOND_GT ? BNE : BEQ);
  1194. break;
  1195. }
  1196. if (op) EMIT(op);
  1197. return b;
  1198. }
  1199. #define emith_jump(target) do { \
  1200. u32 disp_ = (u8 *)target - (u8 *)tcache_ptr; \
  1201. EMIT(PPC_B((uintptr_t)disp_ & 0x03ffffff)); \
  1202. } while (0)
  1203. #define emith_jump_patchable(target) \
  1204. emith_jump(target)
  1205. // NB: PPC conditional branches have only +/- 64KB range
  1206. #define emith_jump_cond(cond, target) do { \
  1207. int mcond_ = emith_cond_check(cond); \
  1208. u32 disp_ = (u8 *)target - (u8 *)tcache_ptr; \
  1209. if (mcond_ >= 0) EMIT(PPC_BCOND(mcond_,disp_ & 0x0000ffff)); \
  1210. } while (0)
  1211. #define emith_jump_cond_patchable(cond, target) \
  1212. emith_jump_cond(cond, target)
  1213. #define emith_jump_cond_inrange(target) \
  1214. ((u8 *)target - (u8 *)tcache_ptr < 0x8000 && \
  1215. (u8 *)target - (u8 *)tcache_ptr >= -0x8000+0x10) //mind cond_check
  1216. // NB: returns position of patch for cache maintenance
  1217. #define emith_jump_patch(ptr, target, pos) do { \
  1218. u32 *ptr_ = (u32 *)ptr; /* must skip condition check code */ \
  1219. u32 disp_, mask_; \
  1220. while (*ptr_>>26 != OP_BC && *ptr_>>26 != OP_B) ptr_ ++; \
  1221. disp_ = (u8 *)target - (u8 *)ptr_; \
  1222. mask_ = (*ptr_>>26 == OP_BC ? 0xffff0003 : 0xfc000003); \
  1223. EMIT_PTR(ptr_, (*ptr_ & mask_) | (disp_ & ~mask_)); \
  1224. if ((void *)(pos) != NULL) *(u8 **)(pos) = (u8 *)(ptr_-1); \
  1225. } while (0)
  1226. #define emith_jump_patch_inrange(ptr, target) \
  1227. ((u8 *)target - (u8 *)ptr < 0x8000 && \
  1228. (u8 *)target - (u8 *)ptr >= -0x8000+0x10) // mind cond_check
  1229. #define emith_jump_patch_size() 4
  1230. #define emith_jump_at(ptr, target) do { \
  1231. u32 disp_ = (u8 *)target - (u8 *)ptr; \
  1232. u32 *ptr_ = (u32 *)ptr; \
  1233. EMIT_PTR(ptr_, PPC_B((uintptr_t)disp_ & 0x03ffffff)); \
  1234. } while (0)
  1235. #define emith_jump_at_size() 4
  1236. #define emith_jump_reg(r) do { \
  1237. EMIT(PPC_MTSP_REG(r, CTR)); \
  1238. EMIT(PPC_BCTRCOND(BXX)); \
  1239. } while(0)
  1240. #define emith_jump_reg_c(cond, r) \
  1241. emith_jump_reg(r)
  1242. #define emith_jump_ctx(offs) do { \
  1243. emith_ctx_read_ptr(AT, offs); \
  1244. emith_jump_reg(AT); \
  1245. } while (0)
  1246. #define emith_jump_ctx_c(cond, offs) \
  1247. emith_jump_ctx(offs)
  1248. #define emith_call(target) do { \
  1249. u32 disp_ = (u8 *)target - (u8 *)tcache_ptr; \
  1250. EMIT(PPC_BL((uintptr_t)disp_ & 0x03ffffff)); \
  1251. } while(0)
  1252. #define emith_call_cond(cond, target) \
  1253. emith_call(target)
  1254. #define emith_call_reg(r) do { \
  1255. EMIT(PPC_MTSP_REG(r, CTR)); \
  1256. EMIT(PPC_BLCTRCOND(BXX)); \
  1257. } while(0)
  1258. #define emith_call_ctx(offs) do { \
  1259. emith_ctx_read_ptr(AT, offs); \
  1260. emith_call_reg(AT); \
  1261. } while (0)
  1262. #define emith_abijump_reg(r) \
  1263. emith_jump_reg(r)
  1264. #define emith_abijump_reg_c(cond, r) \
  1265. emith_abijump_reg(r)
  1266. #define emith_abicall(target) \
  1267. emith_call(target)
  1268. #define emith_abicall_cond(cond, target) \
  1269. emith_abicall(target)
  1270. #define emith_abicall_reg(r) \
  1271. emith_call_reg(r)
  1272. #define emith_call_cleanup() /**/
  1273. #define emith_ret() \
  1274. EMIT(PPC_RET())
  1275. #define emith_ret_c(cond) \
  1276. emith_ret()
  1277. #define emith_ret_to_ctx(offs) do { \
  1278. EMIT(PPC_MFSP_REG(AT, LR)); \
  1279. emith_ctx_write_ptr(AT, offs); \
  1280. } while (0)
  1281. #define emith_add_r_ret(r) do { \
  1282. EMIT(PPC_MFSP_REG(AT, LR)); \
  1283. emith_add_r_r_ptr(r, AT); \
  1284. } while (0)
  1285. // NB: ABI SP alignment is 16 in 64 bit mode
  1286. #define emith_push_ret(r) do { \
  1287. int offs_ = 16 - 2*PTR_SIZE; \
  1288. emith_add_r_r_ptr_imm(SP, SP, -16); \
  1289. EMIT(PPC_MFSP_REG(AT, LR)); \
  1290. emith_write_r_r_offs_ptr(AT, SP, offs_ + PTR_SIZE); \
  1291. if ((r) > 0) emith_write_r_r_offs(r, SP, offs_); \
  1292. } while (0)
  1293. #define emith_pop_and_ret(r) do { \
  1294. int offs_ = 16 - 2*PTR_SIZE; \
  1295. if ((r) > 0) emith_read_r_r_offs(r, SP, offs_); \
  1296. emith_read_r_r_offs_ptr(AT, SP, offs_ + PTR_SIZE); \
  1297. EMIT(PPC_MTSP_REG(AT, LR)); \
  1298. emith_add_r_r_ptr_imm(SP, SP, 16); \
  1299. emith_ret(); \
  1300. } while (0)
  1301. // emitter ABI stuff
  1302. #define emith_pool_check() /**/
  1303. #define emith_pool_commit(j) /**/
  1304. #define emith_insn_ptr() ((u8 *)tcache_ptr)
  1305. #define emith_flush() /**/
  1306. #define host_instructions_updated(base, end, force) __builtin___clear_cache(base, end)
  1307. #define emith_update_cache() /**/
  1308. #define emith_rw_offs_max() 0x7fff
  1309. // SH2 drc specific
  1310. #define STACK_EXTRA ((8+6)*PTR_SIZE) // Param, ABI (LR,CR,FP etc) save areas
  1311. #define emith_sh2_drc_entry() do { \
  1312. int _c, _z = PTR_SIZE; u32 _m = 0xffffc000; /* r14-r31 */ \
  1313. if (__builtin_parity(_m) == 1) _m |= 0x1; /* ABI align for SP is 16 */ \
  1314. int _s = count_bits(_m) * _z, _o = 0; \
  1315. for (_c = HOST_REGS-1; _m && _c >= 0; _m &= ~(1 << _c), _c--) \
  1316. if (_m & (1 << _c)) \
  1317. { _o -= _z; if (_c) emith_write_r_r_offs_ptr(_c, SP, _o); } \
  1318. EMIT(PPC_MFSP_REG(10, LR)); \
  1319. emith_write_r_r_offs_ptr(10, SP, 2*PTR_SIZE); \
  1320. emith_write_r_r_offs_ptr(SP, SP, -_s-STACK_EXTRA); /* XXX stdu */ \
  1321. emith_add_r_r_ptr_imm(SP, SP, -_s-STACK_EXTRA); \
  1322. } while (0)
  1323. #define emith_sh2_drc_exit() do { \
  1324. int _c, _z = PTR_SIZE; u32 _m = 0xffffc000; \
  1325. if (__builtin_parity(_m) == 1) _m |= 0x1; \
  1326. int _s = count_bits(_m) * _z, _o = STACK_EXTRA; \
  1327. for (_c = 0; _m && _c < HOST_REGS; _m &= ~(1 << _c), _c++) \
  1328. if (_m & (1 << _c)) \
  1329. { if (_c) emith_read_r_r_offs_ptr(_c, SP, _o); _o += _z; } \
  1330. emith_add_r_r_ptr_imm(SP, SP, _s+STACK_EXTRA); \
  1331. emith_read_r_r_offs_ptr(10, SP, 2*PTR_SIZE); \
  1332. EMIT(PPC_MTSP_REG(10, LR)); \
  1333. emith_ret(); \
  1334. } while (0)
  1335. // NB: assumes a is in arg0, tab, func and mask are temp
  1336. #define emith_sh2_rcall(a, tab, func, mask) do { \
  1337. emith_lsr(mask, a, SH2_READ_SHIFT); \
  1338. emith_add_r_r_r_lsl_ptr(tab, tab, mask, PTR_SCALE+1); \
  1339. emith_read_r_r_offs_ptr(func, tab, 0); \
  1340. emith_read_r_r_offs(mask, tab, PTR_SIZE); \
  1341. EMIT(PPC_BFXP_IMM(FC, func, 0, 1)); \
  1342. emith_add_r_r_ptr(func, func); \
  1343. emith_cmp_ra = emith_cmp_rb = -1; \
  1344. } while (0)
  1345. // NB: assumes a, val are in arg0 and arg1, tab and func are temp
  1346. #define emith_sh2_wcall(a, val, tab, func) do { \
  1347. emith_lsr(func, a, SH2_WRITE_SHIFT); \
  1348. emith_lsl(func, func, PTR_SCALE); \
  1349. emith_read_r_r_r_ptr(func, tab, func); \
  1350. emith_move_r_r_ptr(5, CONTEXT_REG); /* arg2 */ \
  1351. emith_jump_reg(func); \
  1352. } while (0)
  1353. #define emith_sh2_delay_loop(cycles, reg) do { \
  1354. int sr = rcache_get_reg(SHR_SR, RC_GR_RMW, NULL); \
  1355. int t1 = rcache_get_tmp(); \
  1356. int t2 = rcache_get_tmp(); \
  1357. int t3 = rcache_get_tmp(); \
  1358. /* if (sr < 0) return */ \
  1359. emith_cmp_r_imm(sr, 0); \
  1360. EMITH_JMP_START(DCOND_LE); \
  1361. /* turns = sr.cycles / cycles */ \
  1362. emith_asr(t2, sr, 12); \
  1363. emith_move_r_imm(t3, (u32)((1ULL<<32) / (cycles)) + 1); \
  1364. emith_mul_u64(t1, t2, t2, t3); /* multiply by 1/x */ \
  1365. rcache_free_tmp(t3); \
  1366. if (reg >= 0) { \
  1367. /* if (reg <= turns) turns = reg-1 */ \
  1368. t3 = rcache_get_reg(reg, RC_GR_RMW, NULL); \
  1369. emith_cmp_r_r(t3, t2); \
  1370. EMITH_SJMP_START(DCOND_HI); \
  1371. emith_sub_r_r_imm_c(DCOND_LS, t2, t3, 1); \
  1372. EMITH_SJMP_END(DCOND_HI); \
  1373. /* if (reg <= 1) turns = 0 */ \
  1374. emith_cmp_r_imm(t3, 1); \
  1375. EMITH_SJMP_START(DCOND_HI); \
  1376. emith_move_r_imm_c(DCOND_LS, t2, 0); \
  1377. EMITH_SJMP_END(DCOND_HI); \
  1378. /* reg -= turns */ \
  1379. emith_sub_r_r(t3, t2); \
  1380. } \
  1381. /* sr.cycles -= turns * cycles; */ \
  1382. emith_move_r_imm(t1, cycles); \
  1383. emith_mul(t1, t2, t1); \
  1384. emith_sub_r_r_r_lsl(sr, sr, t1, 12); \
  1385. EMITH_JMP_END(DCOND_LE); \
  1386. rcache_free_tmp(t1); \
  1387. rcache_free_tmp(t2); \
  1388. } while (0)
  1389. /*
  1390. * T = !carry(Rn = (Rn << 1) | T)
  1391. * if Q
  1392. * C = carry(Rn += Rm)
  1393. * else
  1394. * C = carry(Rn -= Rm)
  1395. * T ^= C
  1396. */
  1397. #define emith_sh2_div1_step(rn, rm, sr) do { \
  1398. int t_ = rcache_get_tmp(); \
  1399. emith_and_r_r_imm(AT, sr, T); \
  1400. emith_lsr(FC, rn, 31); /*Rn = (Rn<<1)+T*/ \
  1401. emith_lsl(t_, rn, 1); \
  1402. emith_or_r_r(t_, AT); \
  1403. emith_or_r_imm(sr, T); /* T = !carry */ \
  1404. emith_eor_r_r(sr, FC); \
  1405. emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
  1406. EMITH_JMP3_START(DCOND_EQ); \
  1407. emith_add_r_r_r(rn, t_, rm); \
  1408. EMIT(PPC_CMPLW_REG(rn, t_)); \
  1409. EMITH_JMP3_MID(DCOND_EQ); \
  1410. emith_sub_r_r_r(rn, t_, rm); \
  1411. EMIT(PPC_CMPLW_REG(t_, rn)); \
  1412. EMITH_JMP3_END(); \
  1413. EMIT(PPC_MFCR_REG(FC)); \
  1414. EMIT(PPC_BFXW_IMM(FC, FC, 0, 1)); \
  1415. emith_eor_r_r(sr, FC); /* T ^= carry */ \
  1416. rcache_free_tmp(t_); \
  1417. } while (0)
  1418. /* mh:ml += rn*rm, does saturation if required by S bit. rn, rm must be TEMP */
  1419. #define emith_sh2_macl(ml, mh, rn, rm, sr) do { \
  1420. emith_tst_r_imm(sr, S); \
  1421. EMITH_SJMP_START(DCOND_EQ); \
  1422. /* MACH top 16 bits unused if saturated. sign ext for overfl detect */ \
  1423. emith_sext(mh, mh, 16); \
  1424. EMITH_SJMP_END(DCOND_EQ); \
  1425. emith_mula_s64(ml, mh, rn, rm); \
  1426. emith_tst_r_imm(sr, S); \
  1427. EMITH_SJMP_START(DCOND_EQ); \
  1428. /* overflow if top 17 bits of MACH aren't all 1 or 0 */ \
  1429. /* to check: add MACH >> 31 to MACH >> 15. this is 0 if no overflow */ \
  1430. emith_asr(rn, mh, 15); \
  1431. emith_add_r_r_r_lsr(rn, rn, mh, 31); /* sum = (MACH>>31)+(MACH>>15) */ \
  1432. emith_tst_r_r(rn, rn); /* (need only N and Z flags) */ \
  1433. EMITH_SJMP_START(DCOND_EQ); /* sum != 0 -> ov */ \
  1434. emith_move_r_imm_c(DCOND_NE, ml, 0x0000); /* -overflow */ \
  1435. emith_move_r_imm_c(DCOND_NE, mh, 0x8000); \
  1436. EMITH_SJMP_START(DCOND_PL); /* sum > 0 -> +ovl */ \
  1437. emith_sub_r_imm_c(DCOND_MI, ml, 1); /* 0xffffffff */ \
  1438. emith_sub_r_imm_c(DCOND_MI, mh, 1); /* 0x00007fff */ \
  1439. EMITH_SJMP_END(DCOND_PL); \
  1440. EMITH_SJMP_END(DCOND_EQ); \
  1441. EMITH_SJMP_END(DCOND_EQ); \
  1442. } while (0)
  1443. /* mh:ml += rn*rm, does saturation if required by S bit. rn, rm must be TEMP */
  1444. #define emith_sh2_macw(ml, mh, rn, rm, sr) do { \
  1445. emith_tst_r_imm(sr, S); \
  1446. EMITH_SJMP_START(DCOND_EQ); \
  1447. /* XXX: MACH should be untouched when S is set? */ \
  1448. emith_asr(mh, ml, 31); /* sign ext MACL to MACH for ovrfl check */ \
  1449. EMITH_SJMP_END(DCOND_EQ); \
  1450. emith_mula_s64(ml, mh, rn, rm); \
  1451. emith_tst_r_imm(sr, S); \
  1452. EMITH_SJMP_START(DCOND_EQ); \
  1453. /* overflow if top 33 bits of MACH:MACL aren't all 1 or 0 */ \
  1454. /* to check: add MACL[31] to MACH. this is 0 if no overflow */ \
  1455. emith_lsr(rn, ml, 31); \
  1456. emith_add_r_r(rn, mh); /* sum = MACH + ((MACL>>31)&1) */ \
  1457. emith_tst_r_r(rn, rn); /* (need only N and Z flags) */ \
  1458. EMITH_SJMP_START(DCOND_EQ); /* sum != 0 -> overflow */ \
  1459. /* XXX: LSB signalling only in SH1, or in SH2 too? */ \
  1460. emith_move_r_imm_c(DCOND_NE, mh, 0x00000001); /* LSB of MACH */ \
  1461. emith_move_r_imm_c(DCOND_NE, ml, 0x80000000); /* negative ovrfl */ \
  1462. EMITH_SJMP_START(DCOND_PL); /* sum > 0 -> positive ovrfl */ \
  1463. emith_sub_r_imm_c(DCOND_MI, ml, 1); /* 0x7fffffff */ \
  1464. EMITH_SJMP_END(DCOND_PL); \
  1465. EMITH_SJMP_END(DCOND_EQ); \
  1466. EMITH_SJMP_END(DCOND_EQ); \
  1467. } while (0)
  1468. #define emith_write_sr(sr, srcr) \
  1469. EMIT(PPC_BFIW_IMM(sr, srcr, 22, 10))
  1470. #define emith_carry_to_t(sr, is_sub) \
  1471. EMIT(PPC_BFIW_IMM(sr, FC, 32-__builtin_ffs(T), 1))
  1472. #define emith_t_to_carry(sr, is_sub) \
  1473. emith_and_r_r_imm(FC, sr, 1)
  1474. #define emith_tpop_carry(sr, is_sub) do { \
  1475. emith_and_r_r_imm(FC, sr, 1); \
  1476. emith_eor_r_r(sr, FC); \
  1477. } while (0)
  1478. #define emith_tpush_carry(sr, is_sub) \
  1479. emith_or_r_r(sr, FC)
  1480. #ifdef T
  1481. #define emith_invert_cond(cond) \
  1482. ((cond) ^ 1)
  1483. // T bit handling
  1484. static void emith_set_t_cond(int sr, int cond)
  1485. {
  1486. int b;
  1487. // catch never and always cases
  1488. if ((b = emith_cond_check(cond)) < 0)
  1489. return;
  1490. else if (b == BXX) {
  1491. emith_or_r_imm(sr, T);
  1492. return;
  1493. }
  1494. // extract bit from CR and insert into T
  1495. EMIT(PPC_MFCR_REG(AT));
  1496. EMIT(PPC_BFXW_IMM(AT, AT, (b&7), 1));
  1497. if (!(b & 0x40)) EMIT(PPC_XOR_IMM(AT, AT, 1));
  1498. EMIT(PPC_BFIW_IMM(sr, AT, 32-__builtin_ffs(T), 1));
  1499. }
  1500. #define emith_clr_t_cond(sr) ((void)sr)
  1501. #define emith_get_t_cond() -1
  1502. #define emith_sync_t(sr) ((void)sr)
  1503. #define emith_invalidate_t()
  1504. static void emith_set_t(int sr, int val)
  1505. {
  1506. if (val)
  1507. emith_or_r_imm(sr, T);
  1508. else
  1509. emith_bic_r_imm(sr, T);
  1510. }
  1511. static int emith_tst_t(int sr, int tf)
  1512. {
  1513. emith_tst_r_imm(sr, T);
  1514. return tf ? DCOND_NE: DCOND_EQ;
  1515. }
  1516. #endif