32x.c 17 KB

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  1. /*
  2. * PicoDrive
  3. * (C) notaz, 2009,2010,2013
  4. *
  5. * This work is licensed under the terms of MAME license.
  6. * See COPYING file in the top-level directory.
  7. */
  8. #include "../pico_int.h"
  9. #include "../sound/ym2612.h"
  10. #include <cpu/sh2/compiler.h>
  11. struct Pico32x Pico32x;
  12. SH2 sh2s[2];
  13. #define SH2_IDLE_STATES (SH2_STATE_CPOLL|SH2_STATE_VPOLL|SH2_STATE_RPOLL|SH2_STATE_SLEEP)
  14. static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level)
  15. {
  16. if (sh2->pending_irl > sh2->pending_int_irq) {
  17. elprintf_sh2(sh2, EL_32X, "ack/irl %d @ %08x",
  18. level, sh2_pc(sh2));
  19. return 64 + sh2->pending_irl / 2;
  20. } else {
  21. elprintf_sh2(sh2, EL_32X, "ack/int %d/%d @ %08x",
  22. level, sh2->pending_int_vector, sh2_pc(sh2));
  23. sh2->pending_int_irq = 0; // auto-clear
  24. sh2->pending_level = sh2->pending_irl;
  25. return sh2->pending_int_vector;
  26. }
  27. }
  28. // MUST specify active_sh2 when called from sh2 memhandlers
  29. void p32x_update_irls(SH2 *active_sh2, unsigned int m68k_cycles)
  30. {
  31. int irqs, mlvl = 0, slvl = 0;
  32. int mrun, srun;
  33. if (active_sh2 != NULL)
  34. m68k_cycles = sh2_cycles_done_m68k(active_sh2);
  35. // find top bit = highest irq number (0 <= irl <= 14/2) by binary search
  36. // msh2
  37. irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[0];
  38. if (irqs >= 0x10) mlvl += 8, irqs >>= 4;
  39. if (irqs >= 0x04) mlvl += 4, irqs >>= 2;
  40. if (irqs >= 0x02) mlvl += 2, irqs >>= 1;
  41. // ssh2
  42. irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[1];
  43. if (irqs >= 0x10) slvl += 8, irqs >>= 4;
  44. if (irqs >= 0x04) slvl += 4, irqs >>= 2;
  45. if (irqs >= 0x02) slvl += 2, irqs >>= 1;
  46. mrun = sh2_irl_irq(&msh2, mlvl, msh2.state & SH2_STATE_RUN);
  47. if (mrun) {
  48. p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, m68k_cycles);
  49. if (msh2.state & SH2_STATE_RUN)
  50. sh2_end_run(&msh2, 1);
  51. }
  52. srun = sh2_irl_irq(&ssh2, slvl, ssh2.state & SH2_STATE_RUN);
  53. if (srun) {
  54. p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, m68k_cycles);
  55. if (ssh2.state & SH2_STATE_RUN)
  56. sh2_end_run(&ssh2, 1);
  57. }
  58. elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun);
  59. }
  60. // the mask register is inconsistent, CMD is supposed to be a mask,
  61. // while others are actually irq trigger enables?
  62. // TODO: test on hw..
  63. void p32x_trigger_irq(SH2 *sh2, unsigned int m68k_cycles, unsigned int mask)
  64. {
  65. Pico32x.sh2irqs |= mask & P32XI_VRES;
  66. Pico32x.sh2irqi[0] |= mask & (Pico32x.sh2irq_mask[0] << 3);
  67. Pico32x.sh2irqi[1] |= mask & (Pico32x.sh2irq_mask[1] << 3);
  68. p32x_update_irls(sh2, m68k_cycles);
  69. }
  70. void p32x_update_cmd_irq(SH2 *sh2, unsigned int m68k_cycles)
  71. {
  72. if ((Pico32x.sh2irq_mask[0] & 2) && (Pico32x.regs[2 / 2] & 1))
  73. Pico32x.sh2irqi[0] |= P32XI_CMD;
  74. else
  75. Pico32x.sh2irqi[0] &= ~P32XI_CMD;
  76. if ((Pico32x.sh2irq_mask[1] & 2) && (Pico32x.regs[2 / 2] & 2))
  77. Pico32x.sh2irqi[1] |= P32XI_CMD;
  78. else
  79. Pico32x.sh2irqi[1] &= ~P32XI_CMD;
  80. p32x_update_irls(sh2, m68k_cycles);
  81. }
  82. void Pico32xStartup(void)
  83. {
  84. elprintf(EL_STATUS|EL_32X, "32X startup");
  85. // TODO: OOM handling
  86. PicoIn.AHW |= PAHW_32X;
  87. sh2_init(&msh2, 0, &ssh2);
  88. msh2.irq_callback = sh2_irq_cb;
  89. sh2_init(&ssh2, 1, &msh2);
  90. ssh2.irq_callback = sh2_irq_cb;
  91. PicoMemSetup32x();
  92. p32x_pwm_ctl_changed();
  93. p32x_timers_recalc();
  94. Pico32x.sh2_regs[0] = P32XS2_ADEN;
  95. if (Pico.m.ncart_in)
  96. Pico32x.sh2_regs[0] |= P32XS_nCART;
  97. if (!Pico.m.pal)
  98. Pico32x.vdp_regs[0] |= P32XV_nPAL;
  99. rendstatus_old = -1;
  100. emu_32x_startup();
  101. }
  102. #define HWSWAP(x) (((x) << 16) | ((x) >> 16))
  103. void p32x_reset_sh2s(void)
  104. {
  105. elprintf(EL_32X, "sh2 reset");
  106. sh2_reset(&msh2);
  107. sh2_reset(&ssh2);
  108. sh2_peripheral_reset(&msh2);
  109. sh2_peripheral_reset(&ssh2);
  110. // if we don't have BIOS set, perform it's work here.
  111. // MSH2
  112. if (p32x_bios_m == NULL) {
  113. sh2_set_gbr(0, 0x20004000);
  114. if (!(PicoIn.AHW & PAHW_MCD)) {
  115. unsigned int idl_src, idl_dst, idl_size; // initial data load
  116. unsigned int vbr;
  117. // initial data
  118. idl_src = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d4)) & ~0xf0000000;
  119. idl_dst = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d8)) & ~0xf0000000;
  120. idl_size= HWSWAP(*(unsigned int *)(Pico.rom + 0x3dc));
  121. if (idl_size > Pico.romsize || idl_src + idl_size > Pico.romsize ||
  122. idl_size > 0x40000 || idl_dst + idl_size > 0x40000 || (idl_src & 3) || (idl_dst & 3)) {
  123. elprintf(EL_STATUS|EL_ANOMALY, "32x: invalid initial data ptrs: %06x -> %06x, %06x",
  124. idl_src, idl_dst, idl_size);
  125. }
  126. else
  127. memcpy(Pico32xMem->sdram + idl_dst, Pico.rom + idl_src, idl_size);
  128. // VBR
  129. vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3e8));
  130. sh2_set_vbr(0, vbr);
  131. // checksum and M_OK
  132. Pico32x.regs[0x28 / 2] = *(unsigned short *)(Pico.rom + 0x18e);
  133. }
  134. // program will set M_OK
  135. }
  136. // SSH2
  137. if (p32x_bios_s == NULL) {
  138. unsigned int vbr;
  139. // GBR/VBR
  140. vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3ec));
  141. sh2_set_gbr(1, 0x20004000);
  142. sh2_set_vbr(1, vbr);
  143. // program will set S_OK
  144. }
  145. msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDone();
  146. }
  147. void Pico32xInit(void)
  148. {
  149. if (msh2.mult_m68k_to_sh2 == 0 || msh2.mult_sh2_to_m68k == 0)
  150. Pico32xSetClocks(PICO_MSH2_HZ, 0);
  151. if (ssh2.mult_m68k_to_sh2 == 0 || ssh2.mult_sh2_to_m68k == 0)
  152. Pico32xSetClocks(0, PICO_MSH2_HZ);
  153. }
  154. void PicoPower32x(void)
  155. {
  156. memset(&Pico32x, 0, sizeof(Pico32x));
  157. Pico32x.regs[0] = P32XS_REN|P32XS_nRES; // verified
  158. Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_PEN;
  159. }
  160. void PicoUnload32x(void)
  161. {
  162. sh2_finish(&msh2);
  163. sh2_finish(&ssh2);
  164. if (Pico32xMem != NULL)
  165. plat_munmap(Pico32xMem, sizeof(*Pico32xMem));
  166. Pico32xMem = NULL;
  167. PicoIn.AHW &= ~PAHW_32X;
  168. }
  169. void PicoReset32x(void)
  170. {
  171. if (PicoIn.AHW & PAHW_32X) {
  172. p32x_trigger_irq(NULL, SekCyclesDone(), P32XI_VRES);
  173. p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, SekCyclesDone());
  174. p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, SekCyclesDone());
  175. p32x_pwm_ctl_changed();
  176. p32x_timers_recalc();
  177. }
  178. }
  179. static void p32x_start_blank(void)
  180. {
  181. if (Pico32xDrawMode != PDM32X_OFF && !PicoIn.skipFrame) {
  182. int offs, lines;
  183. pprof_start(draw);
  184. offs = 8; lines = 224;
  185. if ((Pico.video.reg[1] & 8) && !(PicoIn.opt & POPT_ALT_RENDERER)) {
  186. offs = 0;
  187. lines = 240;
  188. }
  189. // XXX: no proper handling of 32col mode..
  190. if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0 && // 32x not blanking
  191. (Pico.video.reg[12] & 1) && // 40col mode
  192. (!(Pico.video.debug_p & PVD_KILL_32X)))
  193. {
  194. int md_bg = Pico.video.reg[7] & 0x3f;
  195. // we draw full layer (not line-by-line)
  196. PicoDraw32xLayer(offs, lines, md_bg);
  197. }
  198. else if (Pico32xDrawMode != PDM32X_32X_ONLY)
  199. PicoDraw32xLayerMdOnly(offs, lines);
  200. pprof_end(draw);
  201. }
  202. // enter vblank
  203. Pico32x.vdp_regs[0x0a/2] |= P32XV_VBLK|P32XV_PEN;
  204. // FB swap waits until vblank
  205. if ((Pico32x.vdp_regs[0x0a/2] ^ Pico32x.pending_fb) & P32XV_FS) {
  206. Pico32x.vdp_regs[0x0a/2] &= ~P32XV_FS;
  207. Pico32x.vdp_regs[0x0a/2] |= Pico32x.pending_fb;
  208. Pico32xSwapDRAM(Pico32x.pending_fb ^ 1);
  209. }
  210. p32x_trigger_irq(NULL, SekCyclesDone(), P32XI_VINT);
  211. p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, SekCyclesDone());
  212. p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, SekCyclesDone());
  213. }
  214. void p32x_schedule_hint(SH2 *sh2, unsigned int m68k_cycles)
  215. {
  216. // rather rough, 32x hint is useless in practice
  217. int after;
  218. if (!((Pico32x.sh2irq_mask[0] | Pico32x.sh2irq_mask[1]) & 4))
  219. return; // nobody cares
  220. // note: when Pico.m.scanline is 224, SH2s might
  221. // still be at scanline 93 (or so)
  222. if (!(Pico32x.sh2_regs[0] & 0x80) &&
  223. Pico.m.scanline > (Pico.video.reg[1] & 0x08 ? 240 : 224))
  224. return;
  225. after = (Pico32x.sh2_regs[4 / 2] + 1) * 488;
  226. if (sh2 != NULL)
  227. p32x_event_schedule_sh2(sh2, P32X_EVENT_HINT, after);
  228. else
  229. p32x_event_schedule(m68k_cycles, P32X_EVENT_HINT, after);
  230. }
  231. /* events */
  232. static void fillend_event(unsigned int now)
  233. {
  234. Pico32x.vdp_regs[0x0a/2] &= ~P32XV_nFEN;
  235. p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, now);
  236. p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, now);
  237. }
  238. static void hint_event(unsigned int now)
  239. {
  240. p32x_trigger_irq(NULL, now, P32XI_HINT);
  241. p32x_schedule_hint(NULL, now);
  242. }
  243. typedef void (event_cb)(unsigned int now);
  244. /* times are in m68k (7.6MHz) cycles */
  245. unsigned int p32x_event_times[P32X_EVENT_COUNT];
  246. static unsigned int event_time_next;
  247. static event_cb *p32x_event_cbs[P32X_EVENT_COUNT] = {
  248. p32x_pwm_irq_event, // P32X_EVENT_PWM
  249. fillend_event, // P32X_EVENT_FILLEND
  250. hint_event, // P32X_EVENT_HINT
  251. };
  252. // schedule event at some time 'after', in m68k clocks
  253. void p32x_event_schedule(unsigned int now, enum p32x_event event, int after)
  254. {
  255. unsigned int when;
  256. when = (now + after) | 1;
  257. elprintf(EL_32X, "32x: new event #%u %u->%u", event, now, when);
  258. p32x_event_times[event] = when;
  259. if (event_time_next == 0 || CYCLES_GT(event_time_next, when))
  260. event_time_next = when;
  261. }
  262. void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after)
  263. {
  264. unsigned int now = sh2_cycles_done_m68k(sh2);
  265. int left_to_next;
  266. p32x_event_schedule(now, event, after);
  267. left_to_next = C_M68K_TO_SH2(sh2, (int)(event_time_next - now));
  268. if (sh2_cycles_left(sh2) > left_to_next) {
  269. if (left_to_next < 1)
  270. left_to_next = 1;
  271. sh2_end_run(sh2, left_to_next);
  272. }
  273. }
  274. static void p32x_run_events(unsigned int until)
  275. {
  276. int oldest, oldest_diff, time;
  277. int i, diff;
  278. while (1) {
  279. oldest = -1, oldest_diff = 0x7fffffff;
  280. for (i = 0; i < P32X_EVENT_COUNT; i++) {
  281. if (p32x_event_times[i]) {
  282. diff = p32x_event_times[i] - until;
  283. if (diff < oldest_diff) {
  284. oldest_diff = diff;
  285. oldest = i;
  286. }
  287. }
  288. }
  289. if (oldest_diff <= 0) {
  290. time = p32x_event_times[oldest];
  291. p32x_event_times[oldest] = 0;
  292. elprintf(EL_32X, "32x: run event #%d %u", oldest, time);
  293. p32x_event_cbs[oldest](time);
  294. }
  295. else if (oldest_diff < 0x7fffffff) {
  296. event_time_next = p32x_event_times[oldest];
  297. break;
  298. }
  299. else {
  300. event_time_next = 0;
  301. break;
  302. }
  303. }
  304. if (oldest != -1)
  305. elprintf(EL_32X, "32x: next event #%d at %u",
  306. oldest, event_time_next);
  307. }
  308. static void run_sh2(SH2 *sh2, unsigned int m68k_cycles)
  309. {
  310. unsigned int cycles, done;
  311. pevt_log_sh2_o(sh2, EVT_RUN_START);
  312. sh2->state |= SH2_STATE_RUN;
  313. cycles = C_M68K_TO_SH2(sh2, m68k_cycles);
  314. elprintf_sh2(sh2, EL_32X, "+run %u %d @%08x",
  315. sh2->m68krcycles_done, cycles, sh2->pc);
  316. done = sh2_execute(sh2, cycles);
  317. sh2->m68krcycles_done += C_SH2_TO_M68K(sh2, done);
  318. sh2->state &= ~SH2_STATE_RUN;
  319. pevt_log_sh2_o(sh2, EVT_RUN_END);
  320. elprintf_sh2(sh2, EL_32X, "-run %u %d",
  321. sh2->m68krcycles_done, done);
  322. }
  323. // sync other sh2 to this one
  324. // note: recursive call
  325. void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target)
  326. {
  327. SH2 *osh2 = sh2->other_sh2;
  328. int left_to_event;
  329. int m68k_cycles;
  330. if (osh2->state & SH2_STATE_RUN)
  331. return;
  332. m68k_cycles = m68k_target - osh2->m68krcycles_done;
  333. if (m68k_cycles < 200)
  334. return;
  335. if (osh2->state & SH2_IDLE_STATES) {
  336. osh2->m68krcycles_done = m68k_target;
  337. return;
  338. }
  339. elprintf_sh2(osh2, EL_32X, "sync to %u %d",
  340. m68k_target, m68k_cycles);
  341. run_sh2(osh2, m68k_cycles);
  342. // there might be new event to schedule current sh2 to
  343. if (event_time_next) {
  344. left_to_event = C_M68K_TO_SH2(sh2, (int)(event_time_next - m68k_target));
  345. if (sh2_cycles_left(sh2) > left_to_event) {
  346. if (left_to_event < 1)
  347. left_to_event = 1;
  348. sh2_end_run(sh2, left_to_event);
  349. }
  350. }
  351. }
  352. #define STEP_LS 24
  353. #define STEP_N 528 // at least one line (488)
  354. #define sync_sh2s_normal p32x_sync_sh2s
  355. //#define sync_sh2s_lockstep p32x_sync_sh2s
  356. /* most timing is in 68k clock */
  357. void sync_sh2s_normal(unsigned int m68k_target)
  358. {
  359. unsigned int now, target, next, timer_cycles;
  360. int cycles;
  361. elprintf(EL_32X, "sh2 sync to %u", m68k_target);
  362. if (!(Pico32x.regs[0] & P32XS_nRES)) {
  363. msh2.m68krcycles_done = ssh2.m68krcycles_done = m68k_target;
  364. return; // rare
  365. }
  366. now = msh2.m68krcycles_done;
  367. if (CYCLES_GT(now, ssh2.m68krcycles_done))
  368. now = ssh2.m68krcycles_done;
  369. timer_cycles = now;
  370. pprof_start(m68k);
  371. while (CYCLES_GT(m68k_target, now))
  372. {
  373. if (event_time_next && CYCLES_GE(now, event_time_next))
  374. p32x_run_events(now);
  375. target = m68k_target;
  376. if (event_time_next && CYCLES_GT(target, event_time_next))
  377. target = event_time_next;
  378. while (CYCLES_GT(target, now))
  379. {
  380. next = target;
  381. if (CYCLES_GT(target, now + STEP_N))
  382. next = now + STEP_N;
  383. elprintf(EL_32X, "sh2 exec to %u %d,%d/%d, flags %x", next,
  384. next - msh2.m68krcycles_done, next - ssh2.m68krcycles_done,
  385. m68k_target - now, Pico32x.emu_flags);
  386. pprof_start(ssh2);
  387. if (!(ssh2.state & SH2_IDLE_STATES)) {
  388. cycles = next - ssh2.m68krcycles_done;
  389. if (cycles > 0) {
  390. run_sh2(&ssh2, cycles > 20U ? cycles : 20U);
  391. if (event_time_next && CYCLES_GT(target, event_time_next))
  392. target = event_time_next;
  393. if (CYCLES_GT(next, target))
  394. next = target;
  395. }
  396. }
  397. pprof_end(ssh2);
  398. pprof_start(msh2);
  399. if (!(msh2.state & SH2_IDLE_STATES)) {
  400. cycles = next - msh2.m68krcycles_done;
  401. if (cycles > 0) {
  402. run_sh2(&msh2, cycles > 20U ? cycles : 20U);
  403. if (event_time_next && CYCLES_GT(target, event_time_next))
  404. target = event_time_next;
  405. if (CYCLES_GT(next, target))
  406. next = target;
  407. }
  408. }
  409. pprof_end(msh2);
  410. now = next;
  411. if (CYCLES_GT(now, msh2.m68krcycles_done)) {
  412. if (!(msh2.state & SH2_IDLE_STATES))
  413. now = msh2.m68krcycles_done;
  414. }
  415. if (CYCLES_GT(now, ssh2.m68krcycles_done)) {
  416. if (!(ssh2.state & SH2_IDLE_STATES))
  417. now = ssh2.m68krcycles_done;
  418. }
  419. if (CYCLES_GT(now, timer_cycles+STEP_N)) {
  420. if (msh2.state & SH2_TIMER_RUN)
  421. p32x_timer_do(&msh2, now - timer_cycles);
  422. if (ssh2.state & SH2_TIMER_RUN)
  423. p32x_timer_do(&ssh2, now - timer_cycles);
  424. timer_cycles = now;
  425. }
  426. }
  427. if (msh2.state & SH2_TIMER_RUN)
  428. p32x_timer_do(&msh2, now - timer_cycles);
  429. if (ssh2.state & SH2_TIMER_RUN)
  430. p32x_timer_do(&ssh2, now - timer_cycles);
  431. timer_cycles = now;
  432. }
  433. pprof_end_sub(m68k);
  434. // advance idle CPUs
  435. if (msh2.state & SH2_IDLE_STATES) {
  436. if (CYCLES_GT(m68k_target, msh2.m68krcycles_done))
  437. msh2.m68krcycles_done = m68k_target;
  438. }
  439. if (ssh2.state & SH2_IDLE_STATES) {
  440. if (CYCLES_GT(m68k_target, ssh2.m68krcycles_done))
  441. ssh2.m68krcycles_done = m68k_target;
  442. }
  443. // everyone is in sync now
  444. Pico32x.comm_dirty = 0;
  445. }
  446. void sync_sh2s_lockstep(unsigned int m68k_target)
  447. {
  448. unsigned int mcycles;
  449. mcycles = msh2.m68krcycles_done;
  450. if (ssh2.m68krcycles_done < mcycles)
  451. mcycles = ssh2.m68krcycles_done;
  452. while (mcycles < m68k_target) {
  453. mcycles += STEP_LS;
  454. sync_sh2s_normal(mcycles);
  455. }
  456. }
  457. #define CPUS_RUN(m68k_cycles) do { \
  458. if (PicoIn.AHW & PAHW_MCD) \
  459. pcd_run_cpus(m68k_cycles); \
  460. else \
  461. SekRunM68k(m68k_cycles); \
  462. \
  463. if ((Pico32x.emu_flags & P32XF_Z80_32X_IO) && Pico.m.z80Run \
  464. && !Pico.m.z80_reset && (PicoIn.opt & POPT_EN_Z80)) \
  465. PicoSyncZ80(SekCyclesDone()); \
  466. if (Pico32x.emu_flags & (P32XF_68KCPOLL|P32XF_68KVPOLL)) \
  467. p32x_sync_sh2s(SekCyclesDone()); \
  468. } while (0)
  469. #define PICO_32X
  470. #define PICO_CD
  471. #include "../pico_cmn.c"
  472. void PicoFrame32x(void)
  473. {
  474. sh2_execute_prepare(&msh2, PicoIn.opt & POPT_EN_DRC);
  475. sh2_execute_prepare(&ssh2, PicoIn.opt & POPT_EN_DRC);
  476. Pico.m.scanline = 0;
  477. Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank
  478. if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking
  479. Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access
  480. if (!(Pico32x.sh2_regs[0] & 0x80))
  481. p32x_schedule_hint(NULL, SekCyclesDone());
  482. p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, SekCyclesDone());
  483. p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, SekCyclesDone());
  484. if (PicoIn.AHW & PAHW_MCD)
  485. pcd_prepare_frame();
  486. PicoFrameStart();
  487. PicoFrameHints();
  488. elprintf(EL_32X, "poll: %02x %02x %02x",
  489. Pico32x.emu_flags & 3, msh2.state, ssh2.state);
  490. }
  491. // calculate multipliers against 68k clock (7670442)
  492. // normally * 3, but effectively slower due to high latencies everywhere
  493. // however using something lower breaks MK2 animations
  494. void Pico32xSetClocks(int msh2_hz, int ssh2_hz)
  495. {
  496. float m68k_clk = (float)(OSC_NTSC / 7);
  497. if (msh2_hz > 0) {
  498. msh2.mult_m68k_to_sh2 = (int)((float)msh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk);
  499. msh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)msh2_hz);
  500. }
  501. if (ssh2_hz > 0) {
  502. ssh2.mult_m68k_to_sh2 = (int)((float)ssh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk);
  503. ssh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)ssh2_hz);
  504. }
  505. }
  506. void Pico32xStateLoaded(int is_early)
  507. {
  508. if (is_early) {
  509. Pico32xMemStateLoaded();
  510. return;
  511. }
  512. sh2s[0].m68krcycles_done = sh2s[1].m68krcycles_done = SekCyclesDone();
  513. p32x_update_irls(NULL, SekCyclesDone());
  514. p32x_pwm_state_loaded();
  515. p32x_run_events(SekCyclesDone());
  516. }
  517. // vim:shiftwidth=2:ts=2:expandtab