videoport.c 35 KB

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  1. /*
  2. * PicoDrive
  3. * (c) Copyright Dave, 2004
  4. * (C) notaz, 2006-2009
  5. * (C) kub, 2020,2021
  6. *
  7. * This work is licensed under the terms of MAME license.
  8. * See COPYING file in the top-level directory.
  9. */
  10. #include "pico_int.h"
  11. #define NEED_DMA_SOURCE
  12. #include "memory.h"
  13. enum { clkdiv = 2 }; // CPU clock granularity: one of 1,2,4,8
  14. // VDP Slot timing, taken from http://gendev.spritesmind.net/
  15. // forum/viewtopic.php?f=22&t=851&sid=d5701a71396ee7f700c74fb7cd85cb09
  16. // Thank you very much for the great work, Nemesis!
  17. // 1 slot is 488/171 = 2.8538 68k cycles in h32, and 488/210 = 2.3238 in h40.
  18. // VDP has a slot counter running from 0x00 to 0xff every scanline, but it has
  19. // a gap depending on the video mode. The slot in which a horizontal interrupt
  20. // is generated also depends on the video mode.
  21. enum { hint32 = 0x84, gapstart32 = 0x94, gapend32 = 0xe9 };
  22. enum { hint40 = 0xa4, gapstart40 = 0xb7, gapend40 = 0xe5 };
  23. // number of slots in a scanline
  24. #define slots32 (0x100-(gapend32-gapstart32)) // 171
  25. #define slots40 (0x100-(gapend40-gapstart40)) // 210
  26. // In blanked display, all slots but the refresh slots are usable for transfers,
  27. // in active display only 16(h32) / 18(h40) slots can be used.
  28. // dma and refresh slots for active display, 16 for H32
  29. static u8 dmaslots32[] =
  30. { 145,243, 2,10,18, 34,42,50, 66,74,82, 98,106,114, 129,130 };
  31. static u8 refslots32[] =
  32. { 250, 26, 58, 90, 122 };
  33. // dma and refresh slots for active display, 18 for H40
  34. static u8 dmaslots40[] =
  35. { 232, 2,10,18, 34,42,50, 66,74,82, 98,106,114, 130,138,146, 161,162 };
  36. static u8 refslots40[] =
  37. { 250, 26, 58, 90, 122, 154 };
  38. // table sizes
  39. enum { cycsz = 488/clkdiv };
  40. enum { sl32blsz=slots32-sizeof(refslots32)+1, sl32acsz=sizeof(dmaslots32)+1 };
  41. enum { sl40blsz=slots40-sizeof(refslots40)+1, sl40acsz=sizeof(dmaslots40)+1 };
  42. // Tables must be considerably larger than one scanline, since 68k emulation
  43. // isn't stopping in the middle of an operation. If the last op is a 32 bit
  44. // VDP write 2 slots may need to be taken from the next scanline, which can be
  45. // more than 100 CPU cycles. For safety just cover 2 scanlines.
  46. // table for mapping hvcounter reads
  47. static u8 hcounts_32[2*cycsz], hcounts_40[2*cycsz];
  48. // tables mapping cycles to slots
  49. static u16 vdpcyc2sl_32_bl[2*cycsz],vdpcyc2sl_40_bl[2*cycsz];
  50. static u16 vdpcyc2sl_32_ac[2*cycsz],vdpcyc2sl_40_ac[2*cycsz];
  51. // tables mapping slots to cycles
  52. // NB the sl2cyc tables must cover all slots present in the cyc2sl tables.
  53. static u16 vdpsl2cyc_32_bl[2*sl32blsz],vdpsl2cyc_40_bl[2*sl40blsz];
  54. static u16 vdpsl2cyc_32_ac[2*sl32acsz],vdpsl2cyc_40_ac[2*sl40acsz];
  55. // calculate timing tables for one mode (H32 or H40)
  56. // NB tables aligned to HINT, since the main loop uses HINT as synchronization
  57. #define INITTABLES(s) { \
  58. float factor = 488./slots##s; \
  59. int ax, bx, rx, ac, bc; \
  60. int i, n; \
  61. \
  62. /* calculate internal VDP slot numbers */ \
  63. for (i = 0; i < cycsz; i++) { \
  64. n = hint##s + i*clkdiv/factor; \
  65. if (n >= gapstart##s) n += gapend##s-gapstart##s; \
  66. hcounts_##s[i] = n % 256; \
  67. } \
  68. memcpy(hcounts_##s+cycsz, hcounts_##s, ARRAY_SIZE(hcounts_##s)-cycsz);\
  69. \
  70. ax = bx = ac = bc = rx = 0; \
  71. for (i = 0; i < cycsz; i++) { \
  72. n = hcounts_##s[i]; \
  73. if (i == 0 || n != hcounts_##s[i-1]) { \
  74. /* fill slt <=> cycle tables, active scanline */ \
  75. if (ax < ARRAY_SIZE(dmaslots##s) && dmaslots##s[ax] == n) { \
  76. vdpsl2cyc_##s##_ac[++ax]=i; \
  77. while (ac < i) vdpcyc2sl_##s##_ac[ac++] = ax-1; \
  78. } \
  79. /* fill slt <=> cycle tables, scanline off */ \
  80. if (rx >= ARRAY_SIZE(refslots##s) || refslots##s[rx] != n) { \
  81. vdpsl2cyc_##s##_bl[++bx]=i; \
  82. while (bc < i) vdpcyc2sl_##s##_bl[bc++] = bx-1; \
  83. } else \
  84. ++rx; \
  85. } \
  86. } \
  87. /* fill up cycle to slot mappings for last slot */ \
  88. while (ac < cycsz) \
  89. vdpcyc2sl_##s##_ac[ac] = ARRAY_SIZE(dmaslots##s), ac++; \
  90. while (bc < cycsz) \
  91. vdpcyc2sl_##s##_bl[bc] = slots##s-ARRAY_SIZE(refslots##s), bc++; \
  92. /* extend tables for 2nd scanline */ \
  93. i = ARRAY_SIZE(dmaslots##s); \
  94. while (ac < ARRAY_SIZE(vdpcyc2sl_##s##_ac)) \
  95. vdpcyc2sl_##s##_ac[ac] = vdpcyc2sl_##s##_ac[ac-cycsz]+i, ac++; \
  96. while (ax < ARRAY_SIZE(vdpsl2cyc_##s##_ac)-1) ax++, \
  97. vdpsl2cyc_##s##_ac[ax] = vdpsl2cyc_##s##_ac[ax-i]+cycsz;\
  98. i = slots##s - ARRAY_SIZE(refslots##s); \
  99. while (bc < ARRAY_SIZE(vdpcyc2sl_##s##_bl)) \
  100. vdpcyc2sl_##s##_bl[bc] = vdpcyc2sl_##s##_bl[bc-cycsz]+i, bc++; \
  101. while (bx < ARRAY_SIZE(vdpsl2cyc_##s##_bl)-1) bx++, \
  102. vdpsl2cyc_##s##_bl[bx] = vdpsl2cyc_##s##_bl[bx-i]+cycsz; \
  103. }
  104. // initialize VDP timing tables
  105. void PicoVideoInit(void)
  106. {
  107. INITTABLES(32);
  108. INITTABLES(40);
  109. }
  110. static int blankline; // display disabled for this line
  111. u32 SATaddr, SATmask; // VRAM addr of sprite attribute table
  112. int (*PicoDmaHook)(u32 source, int len, unsigned short **base, u32 *mask) = NULL;
  113. /* VDP FIFO implementation
  114. *
  115. * fifo_slot: last slot executed in this scanline
  116. * fifo_cnt: #slots remaining for active FIFO write (#writes<<#bytep)
  117. * fifo_total: #total FIFO entries pending
  118. * fifo_data: last values transferred through fifo
  119. * fifo_queue: fifo transfer queue (#writes, flags)
  120. *
  121. * FIFO states: empty total=0
  122. * inuse total>0 && total<4
  123. * full total==4
  124. * wait total>4
  125. * Conditions:
  126. * fifo_slot is always behind slot2cyc[cycles]. Advancing it beyond cycles
  127. * implies blocking the 68k up to that slot.
  128. *
  129. * A FIFO write goes to the end of the FIFO queue, but DMA running in background
  130. * is always the last queue entry (transfers by CPU intervene and come 1st).
  131. * There can be more pending writes than FIFO slots, but the CPU will be blocked
  132. * until FIFO level (without background DMA) <= 4.
  133. * This is only about correct timing, data xfer must be handled by the caller.
  134. * Blocking the CPU means burning cycles via SekCyclesBurn*(), which is to be
  135. * executed by the caller.
  136. *
  137. * FIFOSync "executes" FIFO write slots up to the given cycle in the current
  138. * scanline. A queue entry completely executed is removed from the queue.
  139. * FIFOWrite pushes writes to the transfer queue. If it's a blocking write, 68k
  140. * is blocked if more than 4 FIFO writes are pending.
  141. * FIFORead executes a 68k read. 68k is blocked until the next transfer slot.
  142. */
  143. // NB code assumes fifo_* arrays have size 2^n
  144. static struct VdpFIFO { // XXX this must go into save file!
  145. // last transferred FIFO data, ...x = index XXX currently only CPU
  146. unsigned short fifo_data[4], fifo_dx;
  147. // queued FIFO transfers, ...x = index, ...l = queue length
  148. // each entry has 2 values: [n]>>3 = #writes, [n]&7 = flags (FQ_*)
  149. unsigned int fifo_queue[8], fifo_qx, fifo_ql;
  150. int fifo_total; // total# of pending FIFO entries (w/o BGDMA)
  151. unsigned short fifo_slot; // last executed slot in current scanline
  152. unsigned short fifo_maxslot;// #slots in scanline
  153. const unsigned short *fifo_cyc2sl;
  154. const unsigned short *fifo_sl2cyc;
  155. } VdpFIFO;
  156. enum { FQ_BYTE = 1, FQ_BGDMA = 2, FQ_FGDMA = 4 }; // queue flags, NB: BYTE = 1!
  157. // NB should limit cyc2sl to table size in case 68k overdraws its aim. That can
  158. // happen if the last op is a blocking acess to VDP, or for exceptions (e.g.irq)
  159. #define Cyc2Sl(vf,lc) (vf->fifo_cyc2sl[(lc)/clkdiv])
  160. #define Sl2Cyc(vf,sl) (vf->fifo_sl2cyc[sl]*clkdiv)
  161. // do the FIFO math
  162. static __inline int AdvanceFIFOEntry(struct VdpFIFO *vf, struct PicoVideo *pv, int slots)
  163. {
  164. int l = slots, b = vf->fifo_queue[vf->fifo_qx] & FQ_BYTE;
  165. int cnt = pv->fifo_cnt;
  166. // advance currently active FIFO entry
  167. if (l > cnt)
  168. l = cnt;
  169. if (!(vf->fifo_queue[vf->fifo_qx] & FQ_BGDMA))
  170. if ((vf->fifo_total -= ((cnt & b) + l) >> b) < 0) vf->fifo_total = 0;
  171. cnt -= l;
  172. // if entry has been processed...
  173. if (cnt == 0) {
  174. // remove entry from FIFO
  175. if (vf->fifo_ql) {
  176. vf->fifo_queue[vf->fifo_qx] = 0;
  177. vf->fifo_qx = (vf->fifo_qx+1) & 7, vf->fifo_ql --;
  178. }
  179. // start processing for next entry if there is one
  180. if (vf->fifo_ql) {
  181. b = vf->fifo_queue[vf->fifo_qx] & FQ_BYTE;
  182. cnt = (vf->fifo_queue[vf->fifo_qx] >> 3) << b;
  183. } else { // FIFO empty
  184. pv->status &= ~PVS_FIFORUN;
  185. vf->fifo_total = 0;
  186. }
  187. }
  188. pv->fifo_cnt = cnt;
  189. return l;
  190. }
  191. static __inline void SetFIFOState(struct VdpFIFO *vf, struct PicoVideo *pv)
  192. {
  193. unsigned int st = pv->status, cmd = pv->command;
  194. // release CPU and terminate DMA if FIFO isn't blocking the 68k anymore
  195. if (vf->fifo_total <= 4) {
  196. st &= ~PVS_CPUWR;
  197. if (!(st & (PVS_DMABG|PVS_DMAFILL))) {
  198. st &= ~SR_DMA;
  199. cmd &= ~0x80;
  200. }
  201. }
  202. if (pv->fifo_cnt == 0) {
  203. st &= ~PVS_CPURD;
  204. // terminate DMA if applicable
  205. if (!(st & (PVS_FIFORUN|PVS_DMAFILL))) {
  206. st &= ~(SR_DMA|PVS_DMABG);
  207. cmd &= ~0x80;
  208. }
  209. }
  210. pv->status = st;
  211. pv->command = cmd;
  212. }
  213. // sync FIFO to cycles
  214. void PicoVideoFIFOSync(int cycles)
  215. {
  216. struct VdpFIFO *vf = &VdpFIFO;
  217. struct PicoVideo *pv = &Pico.video;
  218. int slots, done;
  219. // calculate #slots since last executed slot
  220. slots = Cyc2Sl(vf, cycles) - vf->fifo_slot;
  221. // advance FIFO queue by #done slots
  222. done = slots;
  223. while (done > 0 && pv->fifo_cnt) {
  224. int l = AdvanceFIFOEntry(vf, pv, done);
  225. vf->fifo_slot += l;
  226. done -= l;
  227. }
  228. if (done != slots)
  229. SetFIFOState(vf, pv);
  230. }
  231. // drain FIFO, blocking 68k on the way. FIFO must be synced prior to drain.
  232. static int PicoVideoFIFODrain(int level, int cycles, int bgdma)
  233. {
  234. struct VdpFIFO *vf = &VdpFIFO;
  235. struct PicoVideo *pv = &Pico.video;
  236. unsigned ocyc = cycles;
  237. int burn = 0;
  238. // process FIFO entries until low level is reached
  239. while (vf->fifo_slot <= vf->fifo_maxslot && cycles < 488 &&
  240. ((vf->fifo_total > level) | (vf->fifo_queue[vf->fifo_qx] & bgdma))) {
  241. int b = vf->fifo_queue[vf->fifo_qx] & FQ_BYTE;
  242. int cnt = bgdma ? pv->fifo_cnt : ((vf->fifo_total-level)<<b) - (pv->fifo_cnt&b);
  243. int slot = (pv->fifo_cnt<cnt ? pv->fifo_cnt:cnt) + vf->fifo_slot;
  244. if (slot > vf->fifo_maxslot) {
  245. // target slot in later scanline, advance to eol
  246. slot = vf->fifo_maxslot;
  247. cycles = 488;
  248. } else {
  249. // advance FIFO to target slot and CPU to cycles at that slot
  250. cycles = Sl2Cyc(vf, slot);
  251. }
  252. if (slot > vf->fifo_slot) {
  253. AdvanceFIFOEntry(vf, pv, slot - vf->fifo_slot);
  254. vf->fifo_slot = slot;
  255. }
  256. }
  257. if (cycles > ocyc)
  258. burn = cycles - ocyc;
  259. SetFIFOState(vf, pv);
  260. return burn;
  261. }
  262. // read VDP data port
  263. static int PicoVideoFIFORead(void)
  264. {
  265. struct VdpFIFO *vf = &VdpFIFO;
  266. struct PicoVideo *pv = &Pico.video;
  267. int lc = SekCyclesDone()-Pico.t.m68c_line_start;
  268. int burn = 0;
  269. if (pv->fifo_cnt) {
  270. PicoVideoFIFOSync(lc);
  271. // advance FIFO and CPU until FIFO is empty
  272. burn = PicoVideoFIFODrain(0, lc, FQ_BGDMA);
  273. lc += burn;
  274. }
  275. if (pv->fifo_cnt)
  276. pv->status |= PVS_CPURD; // target slot is in later scanline
  277. else {
  278. // use next VDP access slot for reading, block 68k until then
  279. vf->fifo_slot = Cyc2Sl(vf, lc) + 1;
  280. burn += Sl2Cyc(vf, vf->fifo_slot) - lc;
  281. }
  282. return burn;
  283. }
  284. // write VDP data port
  285. int PicoVideoFIFOWrite(int count, int flags, unsigned sr_mask,unsigned sr_flags)
  286. {
  287. struct VdpFIFO *vf = &VdpFIFO;
  288. struct PicoVideo *pv = &Pico.video;
  289. int lc = SekCyclesDone()-Pico.t.m68c_line_start;
  290. int burn = 0;
  291. if (pv->fifo_cnt)
  292. PicoVideoFIFOSync(lc);
  293. pv->status = (pv->status & ~sr_mask) | sr_flags;
  294. if (count && vf->fifo_ql < 8) {
  295. // determine queue position for entry
  296. int x = (vf->fifo_qx + vf->fifo_ql - 1) & 7;
  297. if (unlikely(vf->fifo_queue[x] & FQ_BGDMA)) {
  298. // CPU FIFO writes have priority over a background DMA Fill/Copy
  299. // XXX if interrupting a DMA fill, fill data changes
  300. if (x == vf->fifo_qx) { // overtaking to queue head?
  301. int f = vf->fifo_queue[x] & 7;
  302. vf->fifo_queue[(x+1) & 7] = (pv->fifo_cnt >> (f & FQ_BYTE) << 3) | f;
  303. pv->status &= ~PVS_FIFORUN;
  304. } else
  305. // push background DMA back
  306. vf->fifo_queue[(x+1) & 7] = vf->fifo_queue[x];
  307. x = (x-1) & 7;
  308. }
  309. if ((pv->status & PVS_FIFORUN) && (vf->fifo_queue[x] & 7) == flags) {
  310. // amalgamate entries if of same type
  311. vf->fifo_queue[x] += (count << 3);
  312. if (x == vf->fifo_qx)
  313. pv->fifo_cnt += count << (flags & FQ_BYTE);
  314. } else {
  315. // create new xfer queue entry
  316. vf->fifo_ql ++;
  317. x = (x+1) & 7;
  318. vf->fifo_queue[x] = (count << 3) | flags;
  319. }
  320. // update FIFO state if it was empty
  321. if (!(pv->status & PVS_FIFORUN)) {
  322. vf->fifo_slot = Cyc2Sl(vf, lc+5); // FIFO latency ~3 vdp slots
  323. pv->status |= PVS_FIFORUN;
  324. pv->fifo_cnt = count << (flags & FQ_BYTE);
  325. }
  326. if (!(flags & FQ_BGDMA))
  327. vf->fifo_total += count;
  328. }
  329. // if CPU is waiting for the bus, advance CPU and FIFO until bus is free
  330. if (pv->status & PVS_CPUWR)
  331. burn = PicoVideoFIFODrain(4, lc, 0);
  332. return burn;
  333. }
  334. // at HINT, advance FIFO to new scanline
  335. int PicoVideoFIFOHint(void)
  336. {
  337. struct VdpFIFO *vf = &VdpFIFO;
  338. struct PicoVideo *pv = &Pico.video;
  339. int burn = 0;
  340. // reset slot to start of scanline
  341. vf->fifo_slot = 0;
  342. // if CPU is waiting for the bus, advance CPU and FIFO until bus is free
  343. if (pv->status & PVS_CPUWR)
  344. burn = PicoVideoFIFOWrite(0, 0, 0, 0);
  345. else if (pv->status & PVS_CPURD)
  346. burn = PicoVideoFIFORead();
  347. return burn;
  348. }
  349. // switch FIFO mode between active/inactive display
  350. void PicoVideoFIFOMode(int active, int h40)
  351. {
  352. static const unsigned short *vdpcyc2sl[2][2] =
  353. { {vdpcyc2sl_32_bl, vdpcyc2sl_40_bl},{vdpcyc2sl_32_ac, vdpcyc2sl_40_ac} };
  354. static const unsigned short *vdpsl2cyc[2][2] =
  355. { {vdpsl2cyc_32_bl, vdpsl2cyc_40_bl},{vdpsl2cyc_32_ac, vdpsl2cyc_40_ac} };
  356. struct VdpFIFO *vf = &VdpFIFO;
  357. struct PicoVideo *pv = &Pico.video;
  358. int lc = SekCyclesDone() - Pico.t.m68c_line_start;
  359. active = active && !(pv->status & PVS_VB2);
  360. if (vf->fifo_maxslot)
  361. PicoVideoFIFOSync(lc);
  362. vf->fifo_cyc2sl = vdpcyc2sl[active][h40];
  363. vf->fifo_sl2cyc = vdpsl2cyc[active][h40];
  364. // recalculate FIFO slot for new mode
  365. vf->fifo_slot = Cyc2Sl(vf, lc);
  366. vf->fifo_maxslot = Cyc2Sl(vf, 488);
  367. }
  368. // VDP memory rd/wr
  369. static __inline void AutoIncrement(void)
  370. {
  371. Pico.video.addr=(unsigned short)(Pico.video.addr+Pico.video.reg[0xf]);
  372. if (Pico.video.addr < Pico.video.reg[0xf]) Pico.video.addr_u ^= 1;
  373. }
  374. static NOINLINE void VideoWriteVRAM128(u32 a, u16 d)
  375. {
  376. // nasty
  377. u32 b = ((a & 2) >> 1) | ((a & 0x400) >> 9) | (a & 0x3FC) | ((a & 0x1F800) >> 1);
  378. ((u8 *)PicoMem.vram)[b] = d;
  379. if (!(u16)((b^SATaddr) & SATmask))
  380. Pico.est.rendstatus |= PDRAW_DIRTY_SPRITES;
  381. if (((a^SATaddr) & SATmask) == 0)
  382. UpdateSAT(a, d);
  383. }
  384. static void VideoWrite(u16 d)
  385. {
  386. unsigned int a = Pico.video.addr;
  387. switch (Pico.video.type)
  388. {
  389. case 1: if (a & 1)
  390. d = (u16)((d << 8) | (d >> 8));
  391. a |= Pico.video.addr_u << 16;
  392. VideoWriteVRAM(a, d);
  393. break;
  394. case 3: if (PicoMem.cram [(a >> 1) & 0x3f] != d) Pico.m.dirtyPal = 1;
  395. PicoMem.cram [(a >> 1) & 0x3f] = d & 0xeee; break;
  396. case 5: PicoMem.vsram[(a >> 1) & 0x3f] = d & 0x7ff; break;
  397. case 0x81:
  398. a |= Pico.video.addr_u << 16;
  399. VideoWriteVRAM128(a, d);
  400. break;
  401. //default:elprintf(EL_ANOMALY, "VDP write %04x with bad type %i", d, Pico.video.type); break;
  402. }
  403. AutoIncrement();
  404. }
  405. static unsigned int VideoRead(int is_from_z80)
  406. {
  407. unsigned int a, d = VdpFIFO.fifo_data[(VdpFIFO.fifo_dx+1)&3];
  408. a=Pico.video.addr; a>>=1;
  409. if (!is_from_z80)
  410. SekCyclesBurnRun(PicoVideoFIFORead());
  411. switch (Pico.video.type)
  412. {
  413. case 0: d=PicoMem.vram [a & 0x7fff]; break;
  414. case 8: d=PicoMem.cram [a & 0x003f] | (d & ~0x0eee); break;
  415. case 4: if ((a & 0x3f) >= 0x28) a = 0;
  416. d=PicoMem.vsram [a & 0x003f] | (d & ~0x07ff); break;
  417. case 12:a=PicoMem.vram [a & 0x7fff]; if (Pico.video.addr&1) a >>= 8;
  418. d=(a & 0x00ff) | (d & ~0x00ff); break;
  419. default:elprintf(EL_ANOMALY, "VDP read with bad type %i", Pico.video.type); break;
  420. }
  421. AutoIncrement();
  422. return d;
  423. }
  424. // VDP DMA
  425. static int GetDmaLength(void)
  426. {
  427. struct PicoVideo *pvid=&Pico.video;
  428. int len=0;
  429. // 16-bit words to transfer:
  430. len =pvid->reg[0x13];
  431. len|=pvid->reg[0x14]<<8;
  432. len = ((len - 1) & 0xffff) + 1;
  433. return len;
  434. }
  435. static void DmaSlow(int len, u32 source)
  436. {
  437. u32 inc = Pico.video.reg[0xf];
  438. u32 a = Pico.video.addr | (Pico.video.addr_u << 16);
  439. u16 *r, *base = NULL;
  440. u32 mask = 0x1ffff;
  441. elprintf(EL_VDPDMA, "DmaSlow[%i] %06x->%04x len %i inc=%i blank %i [%u] @ %06x",
  442. Pico.video.type, source, a, len, inc, (Pico.video.status&SR_VB)||!(Pico.video.reg[1]&0x40),
  443. SekCyclesDone(), SekPc);
  444. SekCyclesBurnRun(PicoVideoFIFOWrite(len, FQ_FGDMA | (Pico.video.type == 1),
  445. PVS_DMABG, SR_DMA | PVS_CPUWR));
  446. if ((source & 0xe00000) == 0xe00000) { // Ram
  447. base = (u16 *)PicoMem.ram;
  448. mask = 0xffff;
  449. }
  450. else if (PicoIn.AHW & PAHW_MCD)
  451. {
  452. u8 r3 = Pico_mcd->s68k_regs[3];
  453. elprintf(EL_VDPDMA, "DmaSlow CD, r3=%02x", r3);
  454. if (source < 0x20000) { // Bios area
  455. base = (u16 *)Pico_mcd->bios;
  456. } else if ((source & 0xfc0000) == 0x200000) { // Word Ram
  457. if (!(r3 & 4)) { // 2M mode
  458. base = (u16 *)(Pico_mcd->word_ram2M + (source & 0x20000));
  459. } else {
  460. if (source < 0x220000) { // 1M mode
  461. int bank = r3 & 1;
  462. base = (u16 *)(Pico_mcd->word_ram1M[bank]);
  463. } else {
  464. DmaSlowCell(source - 2, a, len, inc);
  465. return;
  466. }
  467. }
  468. source -= 2;
  469. } else if ((source & 0xfe0000) == 0x020000) { // Prg Ram
  470. base = (u16 *)Pico_mcd->prg_ram_b[r3 >> 6];
  471. source -= 2; // XXX: test
  472. }
  473. }
  474. else
  475. {
  476. // if we have DmaHook, let it handle ROM because of possible DMA delay
  477. u32 source2;
  478. if (PicoDmaHook && (source2 = PicoDmaHook(source, len, &base, &mask)))
  479. source = source2;
  480. else // Rom
  481. base = m68k_dma_source(source);
  482. }
  483. if (!base) {
  484. elprintf(EL_VDPDMA|EL_ANOMALY, "DmaSlow[%i] %06x->%04x: invalid src", Pico.video.type, source, a);
  485. return;
  486. }
  487. // operate in words
  488. source >>= 1;
  489. mask >>= 1;
  490. switch (Pico.video.type)
  491. {
  492. case 1: // vram
  493. r = PicoMem.vram;
  494. if (inc == 2 && !(a & 1) && (a & ~0xffff) == ((a + len*2-1) & ~0xffff) &&
  495. ((a >= SATaddr+0x280) | ((a + len*2-1) < SATaddr)) &&
  496. (source & ~mask) == ((source + len-1) & ~mask))
  497. {
  498. // most used DMA mode
  499. memcpy((char *)r + a, base + (source & mask), len * 2);
  500. a += len * 2;
  501. break;
  502. }
  503. for(; len; len--)
  504. {
  505. u16 d = base[source++ & mask];
  506. if(a & 1) d=(d<<8)|(d>>8);
  507. VideoWriteVRAM(a, d);
  508. // AutoIncrement
  509. a = (a+inc) & ~0x20000;
  510. }
  511. break;
  512. case 3: // cram
  513. Pico.m.dirtyPal = 1;
  514. r = PicoMem.cram;
  515. for (; len; len--)
  516. {
  517. r[(a / 2) & 0x3f] = base[source++ & mask] & 0xeee;
  518. // AutoIncrement
  519. a = (a+inc) & ~0x20000;
  520. }
  521. break;
  522. case 5: // vsram
  523. r = PicoMem.vsram;
  524. for (; len; len--)
  525. {
  526. r[(a / 2) & 0x3f] = base[source++ & mask] & 0x7ff;
  527. // AutoIncrement
  528. a = (a+inc) & ~0x20000;
  529. }
  530. break;
  531. case 0x81: // vram 128k
  532. for(; len; len--)
  533. {
  534. u16 d = base[source++ & mask];
  535. VideoWriteVRAM128(a, d);
  536. // AutoIncrement
  537. a = (a+inc) & ~0x20000;
  538. }
  539. break;
  540. default:
  541. if (Pico.video.type != 0 || (EL_LOGMASK & EL_VDPDMA))
  542. elprintf(EL_VDPDMA|EL_ANOMALY, "DMA with bad type %i", Pico.video.type);
  543. break;
  544. }
  545. // remember addr
  546. Pico.video.addr = a;
  547. Pico.video.addr_u = a >> 16;
  548. }
  549. static void DmaCopy(int len)
  550. {
  551. u32 a = Pico.video.addr | (Pico.video.addr_u << 16);
  552. u8 *vr = (u8 *)PicoMem.vram;
  553. u8 inc = Pico.video.reg[0xf];
  554. int source;
  555. elprintf(EL_VDPDMA, "DmaCopy len %i [%u]", len, SekCyclesDone());
  556. // XXX implement VRAM 128k? Is this even working? xfer/count still FQ_BYTE?
  557. SekCyclesBurnRun(PicoVideoFIFOWrite(len, FQ_BGDMA | FQ_BYTE,
  558. PVS_CPUWR, SR_DMA | PVS_DMABG));
  559. source =Pico.video.reg[0x15];
  560. source|=Pico.video.reg[0x16]<<8;
  561. for (; len; len--)
  562. {
  563. vr[(u16)a] = vr[(u16)(source++)];
  564. if (((a^SATaddr) & SATmask) == 0)
  565. UpdateSAT(a, ((u16 *)vr)[(u16)a >> 1]);
  566. // AutoIncrement
  567. a = (a+inc) & ~0x20000;
  568. }
  569. // remember addr
  570. Pico.video.addr = a;
  571. Pico.video.addr_u = a >> 16;
  572. }
  573. static NOINLINE void DmaFill(int data)
  574. {
  575. u32 a = Pico.video.addr | (Pico.video.addr_u << 16);
  576. u8 *vr = (u8 *)PicoMem.vram;
  577. u8 high = (u8)(data >> 8);
  578. u8 inc = Pico.video.reg[0xf];
  579. int source;
  580. int len, l;
  581. len = GetDmaLength();
  582. elprintf(EL_VDPDMA, "DmaFill len %i inc %i [%u]", len, inc, SekCyclesDone());
  583. SekCyclesBurnRun(PicoVideoFIFOWrite(len, FQ_BGDMA | (Pico.video.type == 1),
  584. PVS_CPUWR | PVS_DMAFILL, SR_DMA | PVS_DMABG));
  585. switch (Pico.video.type)
  586. {
  587. case 1: // vram
  588. if (inc == 1 && (a & ~0xffff) == ((a + len-1) & ~0xffff) &&
  589. ((a >= SATaddr+0x280) | ((a + len-1) < SATaddr)))
  590. {
  591. // most used DMA mode
  592. memset(vr + (u16)a, high, len);
  593. a += len;
  594. break;
  595. }
  596. for (l = len; l; l--) {
  597. // Write upper byte to adjacent address
  598. // (here we are byteswapped, so address is already 'adjacent')
  599. vr[(u16)a] = high;
  600. if (((a^SATaddr) & SATmask) == 0)
  601. UpdateSAT(a, ((u16 *)vr)[(u16)a >> 1]);
  602. // Increment address register
  603. a = (a+inc) & ~0x20000;
  604. }
  605. break;
  606. case 3: // cram
  607. Pico.m.dirtyPal = 1;
  608. data &= 0xeee;
  609. for (l = len; l; l--) {
  610. PicoMem.cram[(a/2) & 0x3f] = data;
  611. // Increment address register
  612. a = (a+inc) & ~0x20000;
  613. }
  614. break;
  615. case 5: { // vsram
  616. data &= 0x7ff;
  617. for (l = len; l; l--) {
  618. PicoMem.vsram[(a/2) & 0x3f] = data;
  619. // Increment address register
  620. a = (a+inc) & ~0x20000;
  621. }
  622. break;
  623. }
  624. case 0x81: // vram 128k
  625. for (l = len; l; l--) {
  626. VideoWriteVRAM128(a, data);
  627. // Increment address register
  628. a = (a+inc) & ~0x20000;
  629. }
  630. break;
  631. default:
  632. a += len * inc;
  633. break;
  634. }
  635. // remember addr
  636. Pico.video.addr = a;
  637. Pico.video.addr_u = a >> 16;
  638. // register update
  639. Pico.video.reg[0x13] = Pico.video.reg[0x14] = 0;
  640. source = Pico.video.reg[0x15];
  641. source |= Pico.video.reg[0x16] << 8;
  642. source += len;
  643. Pico.video.reg[0x15] = source;
  644. Pico.video.reg[0x16] = source >> 8;
  645. }
  646. // VDP command handling
  647. static NOINLINE void CommandDma(void)
  648. {
  649. struct PicoVideo *pvid=&Pico.video;
  650. u32 len, method;
  651. u32 source;
  652. PicoVideoFIFOSync(SekCyclesDone()-Pico.t.m68c_line_start);
  653. if (pvid->status & SR_DMA) {
  654. elprintf(EL_VDPDMA, "Dma overlap, left=%d @ %06x",
  655. VdpFIFO.fifo_total, SekPc);
  656. pvid->fifo_cnt = VdpFIFO.fifo_total = VdpFIFO.fifo_ql = 0;
  657. pvid->status &= ~(PVS_FIFORUN|PVS_DMAFILL);
  658. }
  659. len = GetDmaLength();
  660. source =Pico.video.reg[0x15];
  661. source|=Pico.video.reg[0x16] << 8;
  662. source|=Pico.video.reg[0x17] << 16;
  663. method=pvid->reg[0x17]>>6;
  664. if (method < 2)
  665. DmaSlow(len, source << 1); // 68000 to VDP
  666. else if (method == 3)
  667. DmaCopy(len); // VRAM Copy
  668. else {
  669. pvid->status |= SR_DMA|PVS_DMAFILL;
  670. return;
  671. }
  672. source += len;
  673. Pico.video.reg[0x13] = Pico.video.reg[0x14] = 0;
  674. Pico.video.reg[0x15] = source;
  675. Pico.video.reg[0x16] = source >> 8;
  676. }
  677. static NOINLINE void CommandChange(struct PicoVideo *pvid)
  678. {
  679. unsigned int cmd, addr;
  680. cmd = pvid->command;
  681. // Get type of transfer 0xc0000030 (v/c/vsram read/write)
  682. pvid->type = (u8)(((cmd >> 2) & 0xc) | (cmd >> 30));
  683. if (pvid->type == 1) // vram
  684. pvid->type |= pvid->reg[1] & 0x80; // 128k
  685. // Get address 0x3fff0003
  686. addr = (cmd >> 16) & 0x3fff;
  687. addr |= (cmd << 14) & 0xc000;
  688. pvid->addr = (u16)addr;
  689. pvid->addr_u = (u8)((cmd >> 2) & 1);
  690. }
  691. // VDP interface
  692. static void DrawSync(int skip)
  693. {
  694. int lines = Pico.video.reg[1]&0x08 ? 240 : 224;
  695. int last = Pico.m.scanline - (skip || blankline == Pico.m.scanline);
  696. if (last < lines && !(PicoIn.opt & POPT_ALT_RENDERER) &&
  697. !PicoIn.skipFrame && Pico.est.DrawScanline <= last) {
  698. //elprintf(EL_ANOMALY, "sync");
  699. if (blankline >= 0 && blankline < last) {
  700. PicoDrawSync(blankline, 1);
  701. blankline = -1;
  702. }
  703. PicoDrawSync(last, 0);
  704. }
  705. }
  706. PICO_INTERNAL_ASM void PicoVideoWrite(u32 a,unsigned short d)
  707. {
  708. struct PicoVideo *pvid=&Pico.video;
  709. //elprintf(EL_STATUS, "PicoVideoWrite [%06x] %04x [%u] @ %06x",
  710. // a, d, SekCyclesDone(), SekPc);
  711. a &= 0x1c;
  712. switch (a)
  713. {
  714. case 0x00: // Data port 0 or 2
  715. // try avoiding the sync..
  716. if (Pico.m.scanline < (pvid->reg[1]&0x08 ? 240 : 224) && (pvid->reg[1]&0x40) &&
  717. !(!pvid->pending &&
  718. ((pvid->command & 0xc00000f0) == 0x40000010 && PicoMem.vsram[pvid->addr>>1] == (d & 0x7ff)))
  719. )
  720. DrawSync(0); // XXX it's unclear when vscroll data is fetched from vsram?
  721. if (pvid->pending) {
  722. CommandChange(pvid);
  723. pvid->pending=0;
  724. }
  725. if (!(PicoIn.opt&POPT_DIS_VDP_FIFO))
  726. {
  727. VdpFIFO.fifo_data[++VdpFIFO.fifo_dx&3] = d;
  728. SekCyclesBurnRun(PicoVideoFIFOWrite(1, pvid->type == 1, 0, PVS_CPUWR));
  729. elprintf(EL_ASVDP, "VDP data write: [%04x] %04x [%u] {%i} @ %06x",
  730. Pico.video.addr, d, SekCyclesDone(), Pico.video.type, SekPc);
  731. }
  732. VideoWrite(d);
  733. // start DMA fill on write. NB VSRAM and CRAM fills use wrong FIFO data.
  734. if (pvid->status & PVS_DMAFILL)
  735. DmaFill(VdpFIFO.fifo_data[(VdpFIFO.fifo_dx + !!(pvid->type&~0x81))&3]);
  736. break;
  737. case 0x04: // Control (command) port 4 or 6
  738. if (pvid->status & SR_DMA)
  739. SekCyclesBurnRun(PicoVideoFIFORead()); // kludge, flush out running DMA
  740. if (pvid->pending)
  741. {
  742. // Low word of command:
  743. if (!(pvid->reg[1]&0x10))
  744. d = (d&~0x80)|(pvid->command&0x80);
  745. pvid->command &= 0xffff0000;
  746. pvid->command |= d;
  747. pvid->pending = 0;
  748. CommandChange(pvid);
  749. // Check for dma:
  750. if (d & 0x80) {
  751. DrawSync(SekCyclesDone() - Pico.t.m68c_line_start <= 488-390);
  752. CommandDma();
  753. }
  754. }
  755. else
  756. {
  757. if ((d&0xc000)==0x8000)
  758. {
  759. // Register write:
  760. int num=(d>>8)&0x1f;
  761. int dold=pvid->reg[num];
  762. pvid->type=0; // register writes clear command (else no Sega logo in Golden Axe II)
  763. if (num > 0x0a && !(pvid->reg[1]&4)) {
  764. elprintf(EL_ANOMALY, "%02x written to reg %02x in SMS mode @ %06x", d, num, SekPc);
  765. return;
  766. }
  767. if (num == 0 && !(pvid->reg[0]&2) && (d&2))
  768. pvid->hv_latch = PicoVideoRead(0x08);
  769. if (num == 1 && ((pvid->reg[1]^d)&0x40)) {
  770. PicoVideoFIFOMode(d & 0x40, pvid->reg[12]&1);
  771. // handle line blanking before line rendering
  772. if (SekCyclesDone() - Pico.t.m68c_line_start <= 488-390)
  773. blankline = d&0x40 ? -1 : Pico.m.scanline;
  774. }
  775. if (num == 12 && ((pvid->reg[12]^d)&0x01))
  776. PicoVideoFIFOMode(pvid->reg[1]&0x40, d & 1);
  777. DrawSync(SekCyclesDone() - Pico.t.m68c_line_start <= 488-390);
  778. pvid->reg[num]=(unsigned char)d;
  779. switch (num)
  780. {
  781. case 0x00:
  782. elprintf(EL_INTSW, "hint_onoff: %i->%i [%u] pend=%i @ %06x", (dold&0x10)>>4,
  783. (d&0x10)>>4, SekCyclesDone(), (pvid->pending_ints&0x10)>>4, SekPc);
  784. goto update_irq;
  785. case 0x01:
  786. elprintf(EL_INTSW, "vint_onoff: %i->%i [%u] pend=%i @ %06x", (dold&0x20)>>5,
  787. (d&0x20)>>5, SekCyclesDone(), (pvid->pending_ints&0x20)>>5, SekPc);
  788. if (!(pvid->status & PVS_VB2))
  789. pvid->status &= ~SR_VB;
  790. pvid->status |= ((d >> 3) ^ SR_VB) & SR_VB; // forced blanking
  791. goto update_irq;
  792. case 0x05:
  793. case 0x06:
  794. if (d^dold) Pico.est.rendstatus |= PDRAW_SPRITES_MOVED;
  795. break;
  796. case 0x0c:
  797. // renderers should update their palettes if sh/hi mode is changed
  798. if ((d^dold)&8) Pico.m.dirtyPal = 1;
  799. break;
  800. default:
  801. return;
  802. }
  803. SATaddr = ((pvid->reg[5]&0x7f) << 9) | ((pvid->reg[6]&0x20) << 11);
  804. SATmask = ~0x1ff;
  805. if (Pico.video.reg[12]&1)
  806. SATaddr &= ~0x200, SATmask &= ~0x200; // H40, zero lowest SAT bit
  807. //elprintf(EL_STATUS, "spritep moved to %04x", SATaddr);
  808. return;
  809. update_irq:
  810. #ifndef EMU_CORE_DEBUG
  811. // update IRQ level
  812. if (!SekShouldInterrupt()) // hack
  813. {
  814. int lines, pints, irq = 0;
  815. lines = (pvid->reg[1] & 0x20) | (pvid->reg[0] & 0x10);
  816. pints = pvid->pending_ints & lines;
  817. if (pints & 0x20) irq = 6;
  818. else if (pints & 0x10) irq = 4;
  819. SekInterrupt(irq); // update line
  820. // this is broken because cost of current insn isn't known here
  821. if (irq) SekEndRun(21); // make it delayed
  822. }
  823. #endif
  824. }
  825. else
  826. {
  827. // High word of command:
  828. pvid->command&=0x0000ffff;
  829. pvid->command|=d<<16;
  830. pvid->pending=1;
  831. }
  832. }
  833. break;
  834. // case 0x08: // 08 0a - HV counter - lock up
  835. // case 0x0c: // 0c 0e - HV counter - lock up
  836. // case 0x10: // 10 12 - PSG - handled by caller
  837. // case 0x14: // 14 16 - PSG - handled by caller
  838. // case 0x18: // 18 1a - no effect?
  839. case 0x1c: // 1c 1e - debug
  840. pvid->debug = d;
  841. pvid->debug_p = 0;
  842. if (d & (1 << 6)) {
  843. pvid->debug_p |= PVD_KILL_A | PVD_KILL_B;
  844. pvid->debug_p |= PVD_KILL_S_LO | PVD_KILL_S_HI;
  845. }
  846. switch ((d >> 7) & 3) {
  847. case 1:
  848. pvid->debug_p &= ~(PVD_KILL_S_LO | PVD_KILL_S_HI);
  849. pvid->debug_p |= PVD_FORCE_S;
  850. break;
  851. case 2:
  852. pvid->debug_p &= ~PVD_KILL_A;
  853. pvid->debug_p |= PVD_FORCE_A;
  854. break;
  855. case 3:
  856. pvid->debug_p &= ~PVD_KILL_B;
  857. pvid->debug_p |= PVD_FORCE_B;
  858. break;
  859. }
  860. break;
  861. }
  862. }
  863. static u32 VideoSr(const struct PicoVideo *pv)
  864. {
  865. unsigned int hp = pv->reg[12]&1 ? 15*488/210+1 : 15*488/171+1; // HBLANK start
  866. unsigned int hl = pv->reg[12]&1 ? 37*488/210+1 : 28*488/171+1; // HBLANK len
  867. unsigned int c;
  868. u32 d = pv->status;
  869. c = SekCyclesDone() - Pico.t.m68c_line_start;
  870. if (c - hp < hl)
  871. d |= SR_HB;
  872. PicoVideoFIFOSync(c);
  873. if (VdpFIFO.fifo_total >= 4)
  874. d |= SR_FULL;
  875. else if (!VdpFIFO.fifo_total)
  876. d |= SR_EMPT;
  877. return d;
  878. }
  879. PICO_INTERNAL_ASM u32 PicoVideoRead(u32 a)
  880. {
  881. a &= 0x1c;
  882. if (a == 0x04) // control port
  883. {
  884. struct PicoVideo *pv = &Pico.video;
  885. u32 d = VideoSr(pv);
  886. if (pv->pending) {
  887. CommandChange(pv);
  888. pv->pending = 0;
  889. }
  890. elprintf(EL_SR, "SR read: %04x [%u] @ %06x", d, SekCyclesDone(), SekPc);
  891. return d;
  892. }
  893. // H-counter info (based on Generator):
  894. // frame:
  895. // | <- hblank? -> |
  896. // start <416> hint <36> hdisplay <38> end // CPU cycles
  897. // |---------...---------|------------|-------------|
  898. // 0 B6 E4 FF // 40 cells
  899. // 0 93 E8 FF // 32 cells
  900. // Gens (?) v-render
  901. // start <hblank=84> hint hdisplay <404> |
  902. // |---------------------|--------------------------|
  903. // E4 (hc[0x43]==0) 07 B1 // 40
  904. // E8 (hc[0x45]==0) 05 91 // 32
  905. // check: Sonic 3D Blast bonus, Cannon Fodder, Chase HQ II, 3 Ninjas kick back, Road Rash 3, Skitchin', Wheel of Fortune
  906. if ((a&0x1c)==0x08)
  907. {
  908. unsigned int c;
  909. u32 d;
  910. c = (SekCyclesDone() - Pico.t.m68c_line_start) & 0x1ff; // FIXME
  911. if (Pico.video.reg[0]&2)
  912. d = Pico.video.hv_latch;
  913. else if (Pico.video.reg[12]&1)
  914. d = hcounts_40[c/2] | (Pico.video.v_counter << 8);
  915. else d = hcounts_32[c/2] | (Pico.video.v_counter << 8);
  916. elprintf(EL_HVCNT, "hv: %02x %02x [%u] @ %06x", d, Pico.video.v_counter, SekCyclesDone(), SekPc);
  917. return d;
  918. }
  919. if (a==0x00) // data port
  920. {
  921. return VideoRead(0);
  922. }
  923. return 0;
  924. }
  925. unsigned char PicoVideoRead8DataH(int is_from_z80)
  926. {
  927. return VideoRead(is_from_z80) >> 8;
  928. }
  929. unsigned char PicoVideoRead8DataL(int is_from_z80)
  930. {
  931. return VideoRead(is_from_z80);
  932. }
  933. unsigned char PicoVideoRead8CtlH(int is_from_z80)
  934. {
  935. struct PicoVideo *pv = &Pico.video;
  936. u8 d = VideoSr(pv) >> 8;
  937. if (pv->pending) {
  938. CommandChange(pv);
  939. pv->pending = 0;
  940. }
  941. elprintf(EL_SR, "SR read (h): %02x @ %06x", d, SekPc);
  942. return d;
  943. }
  944. unsigned char PicoVideoRead8CtlL(int is_from_z80)
  945. {
  946. struct PicoVideo *pv = &Pico.video;
  947. u8 d = VideoSr(pv);
  948. if (pv->pending) {
  949. CommandChange(pv);
  950. pv->pending = 0;
  951. }
  952. elprintf(EL_SR, "SR read (l): %02x @ %06x", d, SekPc);
  953. return d;
  954. }
  955. unsigned char PicoVideoRead8HV_H(int is_from_z80)
  956. {
  957. elprintf(EL_HVCNT, "vcounter: %02x [%u] @ %06x", Pico.video.v_counter, SekCyclesDone(), SekPc);
  958. return Pico.video.v_counter;
  959. }
  960. // FIXME: broken
  961. unsigned char PicoVideoRead8HV_L(int is_from_z80)
  962. {
  963. u32 d = (SekCyclesDone() - Pico.t.m68c_line_start) & 0x1ff; // FIXME
  964. if (Pico.video.reg[0]&2)
  965. d = Pico.video.hv_latch;
  966. else if (Pico.video.reg[12]&1)
  967. d = hcounts_40[d/2];
  968. else d = hcounts_32[d/2];
  969. elprintf(EL_HVCNT, "hcounter: %02x [%u] @ %06x", d, SekCyclesDone(), SekPc);
  970. return d;
  971. }
  972. void PicoVideoCacheSAT(void)
  973. {
  974. struct PicoVideo *pv = &Pico.video;
  975. int l;
  976. SATaddr = ((pv->reg[5]&0x7f) << 9) | ((pv->reg[6]&0x20) << 11);
  977. SATmask = ~0x1ff;
  978. if (pv->reg[12]&1)
  979. SATaddr &= ~0x200, SATmask &= ~0x200; // H40, zero lowest SAT bit
  980. // rebuild SAT cache XXX wrong since cache and memory can differ
  981. for (l = 0; l < 80; l++) {
  982. ((u16 *)VdpSATCache)[l*2 ] = PicoMem.vram[(SATaddr>>1) + l*4 ];
  983. ((u16 *)VdpSATCache)[l*2 + 1] = PicoMem.vram[(SATaddr>>1) + l*4 + 1];
  984. }
  985. Pico.est.rendstatus |= PDRAW_SPRITES_MOVED;
  986. }
  987. void PicoVideoSave(void)
  988. {
  989. struct VdpFIFO *vf = &VdpFIFO;
  990. struct PicoVideo *pv = &Pico.video;
  991. int l, x;
  992. // account for all outstanding xfers XXX kludge, entry attr's not saved
  993. for (l = vf->fifo_ql, x = vf->fifo_qx + l-1; l > 1; l--, x--)
  994. pv->fifo_cnt += (vf->fifo_queue[x&7] >> 3) << (vf->fifo_queue[x&7] & FQ_BYTE);
  995. }
  996. void PicoVideoLoad(void)
  997. {
  998. struct VdpFIFO *vf = &VdpFIFO;
  999. struct PicoVideo *pv = &Pico.video;
  1000. // convert former dma_xfers (why was this in PicoMisc anyway?)
  1001. if (Pico.m.dma_xfers) {
  1002. pv->status |= SR_DMA|PVS_FIFORUN;
  1003. pv->fifo_cnt = Pico.m.dma_xfers * (pv->type == 1 ? 2 : 1);
  1004. vf->fifo_total = Pico.m.dma_xfers;
  1005. Pico.m.dma_xfers = 0;
  1006. }
  1007. PicoVideoCacheSAT();
  1008. }
  1009. // vim:shiftwidth=2:ts=2:expandtab