m68k_in.c 239 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921392239233924392539263927392839293930393139323933393439353936393739383939394039413942394339443945394639473948394939503951395239533954395539563957395839593960396139623963396439653966396739683969397039713972397339743975397639773978397939803981398239833984398539863987398839893990399139923993399439953996399739983999400040014002400340044005400640074008400940104011401240134014401540164017401840194020402140224023402440254026402740284029403040314032403340344035403640374038403940404041404240434044404540464047404840494050405140524053405440554056405740584059406040614062406340644065406640674068406940704071407240734074407540764077407840794080408140824083408440854086408740884089409040914092409340944095409640974098409941004101410241034104410541064107410841094110411141124113411441154116411741184119412041214122412341244125412641274128412941304131413241334134413541364137413841394140414141424143414441454146414741484149415041514152415341544155415641574158415941604161416241634164416541664167416841694170417141724173417441754176417741784179418041814182418341844185418641874188418941904191419241934194419541964197419841994200420142024203420442054206420742084209421042114212421342144215421642174218421942204221422242234224422542264227422842294230423142324233423442354236423742384239424042414242424342444245424642474248424942504251425242534254425542564257425842594260426142624263426442654266426742684269427042714272427342744275427642774278427942804281428242834284428542864287428842894290429142924293429442954296429742984299430043014302430343044305430643074308430943104311431243134314431543164317431843194320432143224323432443254326432743284329433043314332433343344335433643374338433943404341434243434344434543464347434843494350435143524353435443554356435743584359436043614362436343644365436643674368436943704371437243734374437543764377437843794380438143824383438443854386438743884389439043914392439343944395439643974398439944004401440244034404440544064407440844094410441144124413441444154416441744184419442044214422442344244425442644274428442944304431443244334434443544364437443844394440444144424443444444454446444744484449445044514452445344544455445644574458445944604461446244634464446544664467446844694470447144724473447444754476447744784479448044814482448344844485448644874488448944904491449244934494449544964497449844994500450145024503450445054506450745084509451045114512451345144515451645174518451945204521452245234524452545264527452845294530453145324533453445354536453745384539454045414542454345444545454645474548454945504551455245534554455545564557455845594560456145624563456445654566456745684569457045714572457345744575457645774578457945804581458245834584458545864587458845894590459145924593459445954596459745984599460046014602460346044605460646074608460946104611461246134614461546164617461846194620462146224623462446254626462746284629463046314632463346344635463646374638463946404641464246434644464546464647464846494650465146524653465446554656465746584659466046614662466346644665466646674668466946704671467246734674467546764677467846794680468146824683468446854686468746884689469046914692469346944695469646974698469947004701470247034704470547064707470847094710471147124713471447154716471747184719472047214722472347244725472647274728472947304731473247334734473547364737473847394740474147424743474447454746474747484749475047514752475347544755475647574758475947604761476247634764476547664767476847694770477147724773477447754776477747784779478047814782478347844785478647874788478947904791479247934794479547964797479847994800480148024803480448054806480748084809481048114812481348144815481648174818481948204821482248234824482548264827482848294830483148324833483448354836483748384839484048414842484348444845484648474848484948504851485248534854485548564857485848594860486148624863486448654866486748684869487048714872487348744875487648774878487948804881488248834884488548864887488848894890489148924893489448954896489748984899490049014902490349044905490649074908490949104911491249134914491549164917491849194920492149224923492449254926492749284929493049314932493349344935493649374938493949404941494249434944494549464947494849494950495149524953495449554956495749584959496049614962496349644965496649674968496949704971497249734974497549764977497849794980498149824983498449854986498749884989499049914992499349944995499649974998499950005001500250035004500550065007500850095010501150125013501450155016501750185019502050215022502350245025502650275028502950305031503250335034503550365037503850395040504150425043504450455046504750485049505050515052505350545055505650575058505950605061506250635064506550665067506850695070507150725073507450755076507750785079508050815082508350845085508650875088508950905091509250935094509550965097509850995100510151025103510451055106510751085109511051115112511351145115511651175118511951205121512251235124512551265127512851295130513151325133513451355136513751385139514051415142514351445145514651475148514951505151515251535154515551565157515851595160516151625163516451655166516751685169517051715172517351745175517651775178517951805181518251835184518551865187518851895190519151925193519451955196519751985199520052015202520352045205520652075208520952105211521252135214521552165217521852195220522152225223522452255226522752285229523052315232523352345235523652375238523952405241524252435244524552465247524852495250525152525253525452555256525752585259526052615262526352645265526652675268526952705271527252735274527552765277527852795280528152825283528452855286528752885289529052915292529352945295529652975298529953005301530253035304530553065307530853095310531153125313531453155316531753185319532053215322532353245325532653275328532953305331533253335334533553365337533853395340534153425343534453455346534753485349535053515352535353545355535653575358535953605361536253635364536553665367536853695370537153725373537453755376537753785379538053815382538353845385538653875388538953905391539253935394539553965397539853995400540154025403540454055406540754085409541054115412541354145415541654175418541954205421542254235424542554265427542854295430543154325433543454355436543754385439544054415442544354445445544654475448544954505451545254535454545554565457545854595460546154625463546454655466546754685469547054715472547354745475547654775478547954805481548254835484548554865487548854895490549154925493549454955496549754985499550055015502550355045505550655075508550955105511551255135514551555165517551855195520552155225523552455255526552755285529553055315532553355345535553655375538553955405541554255435544554555465547554855495550555155525553555455555556555755585559556055615562556355645565556655675568556955705571557255735574557555765577557855795580558155825583558455855586558755885589559055915592559355945595559655975598559956005601560256035604560556065607560856095610561156125613561456155616561756185619562056215622562356245625562656275628562956305631563256335634563556365637563856395640564156425643564456455646564756485649565056515652565356545655565656575658565956605661566256635664566556665667566856695670567156725673567456755676567756785679568056815682568356845685568656875688568956905691569256935694569556965697569856995700570157025703570457055706570757085709571057115712571357145715571657175718571957205721572257235724572557265727572857295730573157325733573457355736573757385739574057415742574357445745574657475748574957505751575257535754575557565757575857595760576157625763576457655766576757685769577057715772577357745775577657775778577957805781578257835784578557865787578857895790579157925793579457955796579757985799580058015802580358045805580658075808580958105811581258135814581558165817581858195820582158225823582458255826582758285829583058315832583358345835583658375838583958405841584258435844584558465847584858495850585158525853585458555856585758585859586058615862586358645865586658675868586958705871587258735874587558765877587858795880588158825883588458855886588758885889589058915892589358945895589658975898589959005901590259035904590559065907590859095910591159125913591459155916591759185919592059215922592359245925592659275928592959305931593259335934593559365937593859395940594159425943594459455946594759485949595059515952595359545955595659575958595959605961596259635964596559665967596859695970597159725973597459755976597759785979598059815982598359845985598659875988598959905991599259935994599559965997599859996000600160026003600460056006600760086009601060116012601360146015601660176018601960206021602260236024602560266027602860296030603160326033603460356036603760386039604060416042604360446045604660476048604960506051605260536054605560566057605860596060606160626063606460656066606760686069607060716072607360746075607660776078607960806081608260836084608560866087608860896090609160926093609460956096609760986099610061016102610361046105610661076108610961106111611261136114611561166117611861196120612161226123612461256126612761286129613061316132613361346135613661376138613961406141614261436144614561466147614861496150615161526153615461556156615761586159616061616162616361646165616661676168616961706171617261736174617561766177617861796180618161826183618461856186618761886189619061916192619361946195619661976198619962006201620262036204620562066207620862096210621162126213621462156216621762186219622062216222622362246225622662276228622962306231623262336234623562366237623862396240624162426243624462456246624762486249625062516252625362546255625662576258625962606261626262636264626562666267626862696270627162726273627462756276627762786279628062816282628362846285628662876288628962906291629262936294629562966297629862996300630163026303630463056306630763086309631063116312631363146315631663176318631963206321632263236324632563266327632863296330633163326333633463356336633763386339634063416342634363446345634663476348634963506351635263536354635563566357635863596360636163626363636463656366636763686369637063716372637363746375637663776378637963806381638263836384638563866387638863896390639163926393639463956396639763986399640064016402640364046405640664076408640964106411641264136414641564166417641864196420642164226423642464256426642764286429643064316432643364346435643664376438643964406441644264436444644564466447644864496450645164526453645464556456645764586459646064616462646364646465646664676468646964706471647264736474647564766477647864796480648164826483648464856486648764886489649064916492649364946495649664976498649965006501650265036504650565066507650865096510651165126513651465156516651765186519652065216522652365246525652665276528652965306531653265336534653565366537653865396540654165426543654465456546654765486549655065516552655365546555655665576558655965606561656265636564656565666567656865696570657165726573657465756576657765786579658065816582658365846585658665876588658965906591659265936594659565966597659865996600660166026603660466056606660766086609661066116612661366146615661666176618661966206621662266236624662566266627662866296630663166326633663466356636663766386639664066416642664366446645664666476648664966506651665266536654665566566657665866596660666166626663666466656666666766686669667066716672667366746675667666776678667966806681668266836684668566866687668866896690669166926693669466956696669766986699670067016702670367046705670667076708670967106711671267136714671567166717671867196720672167226723672467256726672767286729673067316732673367346735673667376738673967406741674267436744674567466747674867496750675167526753675467556756675767586759676067616762676367646765676667676768676967706771677267736774677567766777677867796780678167826783678467856786678767886789679067916792679367946795679667976798679968006801680268036804680568066807680868096810681168126813681468156816681768186819682068216822682368246825682668276828682968306831683268336834683568366837683868396840684168426843684468456846684768486849685068516852685368546855685668576858685968606861686268636864686568666867686868696870687168726873687468756876687768786879688068816882688368846885688668876888688968906891689268936894689568966897689868996900690169026903690469056906690769086909691069116912691369146915691669176918691969206921692269236924692569266927692869296930693169326933693469356936693769386939694069416942694369446945694669476948694969506951695269536954695569566957695869596960696169626963696469656966696769686969697069716972697369746975697669776978697969806981698269836984698569866987698869896990699169926993699469956996699769986999700070017002700370047005700670077008700970107011701270137014701570167017701870197020702170227023702470257026702770287029703070317032703370347035703670377038703970407041704270437044704570467047704870497050705170527053705470557056705770587059706070617062706370647065706670677068706970707071707270737074707570767077707870797080708170827083708470857086708770887089709070917092709370947095709670977098709971007101710271037104710571067107710871097110711171127113711471157116711771187119712071217122712371247125712671277128712971307131713271337134713571367137713871397140714171427143714471457146714771487149715071517152715371547155715671577158715971607161716271637164716571667167716871697170717171727173717471757176717771787179718071817182718371847185718671877188718971907191719271937194719571967197719871997200720172027203720472057206720772087209721072117212721372147215721672177218721972207221722272237224722572267227722872297230723172327233723472357236723772387239724072417242724372447245724672477248724972507251725272537254725572567257725872597260726172627263726472657266726772687269727072717272727372747275727672777278727972807281728272837284728572867287728872897290729172927293729472957296729772987299730073017302730373047305730673077308730973107311731273137314731573167317731873197320732173227323732473257326732773287329733073317332733373347335733673377338733973407341734273437344734573467347734873497350735173527353735473557356735773587359736073617362736373647365736673677368736973707371737273737374737573767377737873797380738173827383738473857386738773887389739073917392739373947395739673977398739974007401740274037404740574067407740874097410741174127413741474157416741774187419742074217422742374247425742674277428742974307431743274337434743574367437743874397440744174427443744474457446744774487449745074517452745374547455745674577458745974607461746274637464746574667467746874697470747174727473747474757476747774787479748074817482748374847485748674877488748974907491749274937494749574967497749874997500750175027503750475057506750775087509751075117512751375147515751675177518751975207521752275237524752575267527752875297530753175327533753475357536753775387539754075417542754375447545754675477548754975507551755275537554755575567557755875597560756175627563756475657566756775687569757075717572757375747575757675777578757975807581758275837584758575867587758875897590759175927593759475957596759775987599760076017602760376047605760676077608760976107611761276137614761576167617761876197620762176227623762476257626762776287629763076317632763376347635763676377638763976407641764276437644764576467647764876497650765176527653765476557656765776587659766076617662766376647665766676677668766976707671767276737674767576767677767876797680768176827683768476857686768776887689769076917692769376947695769676977698769977007701770277037704770577067707770877097710771177127713771477157716771777187719772077217722772377247725772677277728772977307731773277337734773577367737773877397740774177427743774477457746774777487749775077517752775377547755775677577758775977607761776277637764776577667767776877697770777177727773777477757776777777787779778077817782778377847785778677877788778977907791779277937794779577967797779877997800780178027803780478057806780778087809781078117812781378147815781678177818781978207821782278237824782578267827782878297830783178327833783478357836783778387839784078417842784378447845784678477848784978507851785278537854785578567857785878597860786178627863786478657866786778687869787078717872787378747875787678777878787978807881788278837884788578867887788878897890789178927893789478957896789778987899790079017902790379047905790679077908790979107911791279137914791579167917791879197920792179227923792479257926792779287929793079317932793379347935793679377938793979407941794279437944794579467947794879497950795179527953795479557956795779587959796079617962796379647965796679677968796979707971797279737974797579767977797879797980798179827983798479857986798779887989799079917992799379947995799679977998799980008001800280038004800580068007800880098010801180128013801480158016801780188019802080218022802380248025802680278028802980308031803280338034803580368037803880398040804180428043804480458046804780488049805080518052805380548055805680578058805980608061806280638064806580668067806880698070807180728073807480758076807780788079808080818082808380848085808680878088808980908091809280938094809580968097809880998100810181028103810481058106810781088109811081118112811381148115811681178118811981208121812281238124812581268127812881298130813181328133813481358136813781388139814081418142814381448145814681478148814981508151815281538154815581568157815881598160816181628163816481658166816781688169817081718172817381748175817681778178817981808181818281838184818581868187818881898190819181928193819481958196819781988199820082018202820382048205820682078208820982108211821282138214821582168217821882198220822182228223822482258226822782288229823082318232823382348235823682378238823982408241824282438244824582468247824882498250825182528253825482558256825782588259826082618262826382648265826682678268826982708271827282738274827582768277827882798280828182828283828482858286828782888289829082918292829382948295829682978298829983008301830283038304830583068307830883098310831183128313831483158316831783188319832083218322832383248325832683278328832983308331833283338334833583368337833883398340834183428343834483458346834783488349835083518352835383548355835683578358835983608361836283638364836583668367836883698370837183728373837483758376837783788379838083818382838383848385838683878388838983908391839283938394839583968397839883998400840184028403840484058406840784088409841084118412841384148415841684178418841984208421842284238424842584268427842884298430843184328433843484358436843784388439844084418442844384448445844684478448844984508451845284538454845584568457845884598460846184628463846484658466846784688469847084718472847384748475847684778478847984808481848284838484848584868487848884898490849184928493849484958496849784988499850085018502850385048505850685078508850985108511851285138514851585168517851885198520852185228523852485258526852785288529853085318532853385348535853685378538853985408541854285438544854585468547854885498550855185528553855485558556855785588559856085618562856385648565856685678568856985708571857285738574857585768577857885798580858185828583858485858586858785888589859085918592859385948595859685978598859986008601860286038604860586068607860886098610861186128613861486158616861786188619862086218622862386248625862686278628862986308631863286338634863586368637863886398640864186428643864486458646864786488649865086518652865386548655865686578658865986608661866286638664866586668667866886698670867186728673867486758676867786788679868086818682868386848685868686878688868986908691869286938694869586968697869886998700870187028703870487058706870787088709871087118712871387148715871687178718871987208721872287238724872587268727872887298730873187328733873487358736873787388739874087418742874387448745874687478748874987508751875287538754875587568757875887598760876187628763876487658766876787688769877087718772877387748775877687778778877987808781878287838784878587868787878887898790879187928793879487958796879787988799880088018802880388048805880688078808880988108811881288138814881588168817881888198820882188228823882488258826882788288829883088318832883388348835883688378838883988408841884288438844884588468847884888498850885188528853885488558856885788588859886088618862886388648865886688678868886988708871887288738874887588768877887888798880888188828883888488858886888788888889889088918892889388948895889688978898889989008901890289038904890589068907890889098910891189128913891489158916891789188919892089218922892389248925892689278928892989308931893289338934893589368937893889398940894189428943894489458946894789488949895089518952895389548955895689578958895989608961896289638964896589668967896889698970897189728973897489758976897789788979898089818982898389848985898689878988898989908991899289938994899589968997899889999000900190029003900490059006900790089009901090119012901390149015901690179018901990209021902290239024902590269027902890299030903190329033903490359036903790389039904090419042904390449045904690479048904990509051905290539054905590569057905890599060906190629063906490659066906790689069907090719072907390749075907690779078907990809081908290839084908590869087908890899090909190929093909490959096909790989099910091019102910391049105910691079108910991109111911291139114911591169117911891199120912191229123912491259126912791289129913091319132913391349135913691379138913991409141914291439144914591469147914891499150915191529153915491559156915791589159916091619162916391649165916691679168916991709171917291739174917591769177917891799180918191829183918491859186918791889189919091919192919391949195919691979198919992009201920292039204920592069207920892099210921192129213921492159216921792189219922092219222922392249225922692279228922992309231923292339234923592369237923892399240924192429243924492459246924792489249925092519252925392549255925692579258925992609261926292639264926592669267926892699270927192729273927492759276927792789279928092819282928392849285928692879288928992909291929292939294929592969297929892999300930193029303930493059306930793089309931093119312931393149315931693179318931993209321932293239324932593269327932893299330933193329333933493359336933793389339934093419342934393449345934693479348934993509351935293539354935593569357935893599360936193629363936493659366936793689369937093719372937393749375937693779378937993809381938293839384938593869387938893899390939193929393939493959396939793989399940094019402940394049405940694079408940994109411941294139414941594169417941894199420942194229423942494259426942794289429943094319432943394349435943694379438943994409441944294439444944594469447944894499450945194529453945494559456945794589459946094619462946394649465946694679468946994709471947294739474947594769477947894799480948194829483948494859486948794889489949094919492949394949495949694979498949995009501950295039504950595069507950895099510951195129513951495159516951795189519952095219522952395249525952695279528952995309531953295339534953595369537953895399540954195429543954495459546954795489549955095519552955395549555955695579558955995609561956295639564956595669567956895699570957195729573957495759576957795789579958095819582958395849585958695879588958995909591959295939594959595969597959895999600960196029603960496059606960796089609961096119612961396149615961696179618961996209621962296239624962596269627962896299630963196329633963496359636963796389639964096419642964396449645964696479648964996509651965296539654965596569657965896599660966196629663966496659666966796689669967096719672967396749675967696779678967996809681968296839684968596869687968896899690969196929693969496959696969796989699970097019702970397049705970697079708970997109711971297139714971597169717971897199720972197229723972497259726972797289729973097319732973397349735973697379738973997409741974297439744974597469747974897499750975197529753975497559756975797589759976097619762976397649765976697679768976997709771977297739774977597769777977897799780978197829783978497859786978797889789979097919792979397949795979697979798979998009801980298039804980598069807980898099810981198129813981498159816981798189819982098219822982398249825982698279828982998309831983298339834983598369837983898399840984198429843984498459846984798489849985098519852985398549855985698579858985998609861986298639864986598669867986898699870987198729873987498759876987798789879988098819882988398849885988698879888988998909891989298939894989598969897989898999900990199029903990499059906990799089909991099119912991399149915991699179918991999209921992299239924992599269927992899299930993199329933993499359936993799389939994099419942994399449945994699479948994999509951995299539954995599569957995899599960996199629963996499659966996799689969997099719972997399749975997699779978997999809981998299839984998599869987998899899990999199929993999499959996999799989999100001000110002100031000410005100061000710008100091001010011100121001310014100151001610017100181001910020100211002210023100241002510026100271002810029100301003110032100331003410035100361003710038100391004010041100421004310044100451004610047100481004910050100511005210053100541005510056100571005810059100601006110062100631006410065100661006710068100691007010071100721007310074100751007610077100781007910080100811008210083100841008510086100871008810089100901009110092100931009410095100961009710098100991010010101101021010310104101051010610107101081010910110101111011210113101141011510116101171011810119101201012110122101231012410125101261012710128101291013010131101321013310134101351013610137101381013910140101411014210143101441014510146101471014810149101501015110152101531015410155101561015710158101591016010161101621016310164101651016610167101681016910170101711017210173101741017510176101771017810179101801018110182101831018410185101861018710188101891019010191101921019310194101951019610197101981019910200102011020210203102041020510206102071020810209102101021110212102131021410215102161021710218102191022010221102221022310224102251022610227102281022910230102311023210233102341023510236102371023810239102401024110242102431024410245102461024710248102491025010251102521025310254102551025610257102581025910260102611026210263102641026510266102671026810269102701027110272102731027410275102761027710278102791028010281102821028310284102851028610287102881028910290102911029210293102941029510296102971029810299103001030110302103031030410305103061030710308103091031010311103121031310314103151031610317103181031910320103211032210323103241032510326103271032810329103301033110332103331033410335103361033710338103391034010341103421034310344103451034610347103481034910350103511035210353103541035510356103571035810359103601036110362103631036410365103661036710368103691037010371103721037310374103751037610377103781037910380103811038210383103841038510386103871038810389103901039110392103931039410395103961039710398103991040010401104021040310404104051040610407104081040910410104111041210413104141041510416104171041810419104201042110422104231042410425104261042710428104291043010431104321043310434104351043610437104381043910440104411044210443104441044510446104471044810449104501045110452104531045410455104561045710458104591046010461104621046310464104651046610467104681046910470104711047210473104741047510476104771047810479104801048110482104831048410485104861048710488104891049010491104921049310494104951049610497104981049910500105011050210503105041050510506105071050810509105101051110512105131051410515105161051710518105191052010521105221052310524105251052610527105281052910530105311053210533105341053510536105371053810539105401054110542105431054410545105461054710548105491055010551105521055310554105551055610557105581055910560105611056210563105641056510566105671056810569105701057110572105731057410575105761057710578105791058010581105821058310584105851058610587105881058910590105911059210593105941059510596105971059810599106001060110602106031060410605106061060710608106091061010611106121061310614106151061610617106181061910620106211062210623106241062510626106271062810629106301063110632106331063410635106361063710638106391064010641106421064310644106451064610647106481064910650106511065210653106541065510656106571065810659106601066110662106631066410665106661066710668106691067010671106721067310674106751067610677106781067910680106811068210683106841068510686106871068810689106901069110692106931069410695106961069710698106991070010701
  1. /*
  2. must fix:
  3. callm
  4. chk
  5. */
  6. /* ======================================================================== */
  7. /* ========================= LICENSING & COPYRIGHT ======================== */
  8. /* ======================================================================== */
  9. /*
  10. * MUSASHI
  11. * Version 3.31
  12. *
  13. * A portable Motorola M680x0 processor emulation engine.
  14. * Copyright 1998-2007 Karl Stenerud. All rights reserved.
  15. *
  16. * This code may be freely used for non-commercial purposes as long as this
  17. * copyright notice remains unaltered in the source code and any binary files
  18. * containing this code in compiled form.
  19. *
  20. * All other lisencing terms must be negotiated with the author
  21. * (Karl Stenerud).
  22. *
  23. * The latest version of this code can be obtained at:
  24. * http://kstenerud.cjb.net
  25. */
  26. /* Special thanks to Bart Trzynadlowski for his insight into the
  27. * undocumented features of this chip:
  28. *
  29. * http://dynarec.com/~bart/files/68knotes.txt
  30. */
  31. /* Input file for m68kmake
  32. * -----------------------
  33. *
  34. * All sections begin with 80 X's in a row followed by an end-of-line
  35. * sequence.
  36. * After this, m68kmake will expect to find one of the following section
  37. * identifiers:
  38. * M68KMAKE_PROTOTYPE_HEADER - header for opcode handler prototypes
  39. * M68KMAKE_PROTOTYPE_FOOTER - footer for opcode handler prototypes
  40. * M68KMAKE_TABLE_HEADER - header for opcode handler jumptable
  41. * M68KMAKE_TABLE_FOOTER - footer for opcode handler jumptable
  42. * M68KMAKE_TABLE_BODY - the table itself
  43. * M68KMAKE_OPCODE_HANDLER_HEADER - header for opcode handler implementation
  44. * M68KMAKE_OPCODE_HANDLER_FOOTER - footer for opcode handler implementation
  45. * M68KMAKE_OPCODE_HANDLER_BODY - body section for opcode handler implementation
  46. *
  47. * NOTE: M68KMAKE_OPCODE_HANDLER_BODY must be last in the file and
  48. * M68KMAKE_TABLE_BODY must be second last in the file.
  49. *
  50. * The M68KMAKE_OPHANDLER_BODY section contains the opcode handler
  51. * primitives themselves. Each opcode handler begins with:
  52. * M68KMAKE_OP(A, B, C, D)
  53. *
  54. * where A is the opcode handler name, B is the size of the operation,
  55. * C denotes any special processing mode, and D denotes a specific
  56. * addressing mode.
  57. * For C and D where nothing is specified, use "."
  58. *
  59. * Example:
  60. * M68KMAKE_OP(abcd, 8, rr, .) abcd, size 8, register to register, default EA
  61. * M68KMAKE_OP(abcd, 8, mm, ax7) abcd, size 8, memory to memory, register X is A7
  62. * M68KMAKE_OP(tst, 16, ., pcix) tst, size 16, PCIX addressing
  63. *
  64. * All opcode handler primitives end with a closing curly brace "}" at column 1
  65. *
  66. * NOTE: Do not place a M68KMAKE_OP() directive inside the opcode handler,
  67. * and do not put a closing curly brace at column 1 unless it is
  68. * marking the end of the handler!
  69. *
  70. * Inside the handler, m68kmake will recognize M68KMAKE_GET_OPER_xx_xx,
  71. * M68KMAKE_GET_EA_xx_xx, and M68KMAKE_CC directives, and create multiple
  72. * opcode handlers to handle variations in the opcode handler.
  73. * Note: M68KMAKE_CC will only be interpreted in condition code opcodes.
  74. * As well, M68KMAKE_GET_EA_xx_xx and M68KMAKE_GET_OPER_xx_xx will only
  75. * be interpreted on instructions where the corresponding table entry
  76. * specifies multiple effective addressing modes.
  77. * Example:
  78. * clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4
  79. *
  80. * This table entry says that the clr.l opcde has 7 variations (A+-DXWL).
  81. * It is run in user or supervisor mode for all CPUs, and uses 12 cycles for
  82. * 68000, 6 cycles for 68010, and 4 cycles for 68020.
  83. */
  84. XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  85. M68KMAKE_PROTOTYPE_HEADER
  86. #ifndef M68KOPS__HEADER
  87. #define M68KOPS__HEADER
  88. /* ======================================================================== */
  89. /* ============================ OPCODE HANDLERS =========================== */
  90. /* ======================================================================== */
  91. XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  92. M68KMAKE_PROTOTYPE_FOOTER
  93. /* Build the opcode handler table */
  94. void m68ki_build_opcode_table(void);
  95. extern void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
  96. extern unsigned char m68ki_cycles[][0x10000];
  97. /* ======================================================================== */
  98. /* ============================== END OF FILE ============================= */
  99. /* ======================================================================== */
  100. #endif /* M68KOPS__HEADER */
  101. XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  102. M68KMAKE_TABLE_HEADER
  103. /* ======================================================================== */
  104. /* ========================= OPCODE TABLE BUILDER ========================= */
  105. /* ======================================================================== */
  106. #include "m68kops.h"
  107. #define NUM_CPU_TYPES 4
  108. void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
  109. unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */
  110. /* This is used to generate the opcode handler jump table */
  111. typedef struct
  112. {
  113. void (*opcode_handler)(void); /* handler function */
  114. unsigned int mask; /* mask on opcode */
  115. unsigned int match; /* what to match after masking */
  116. unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */
  117. } opcode_handler_struct;
  118. /* Opcode handler table */
  119. static opcode_handler_struct m68k_opcode_handler_table[] =
  120. {
  121. /* function mask match 000 010 020 040 */
  122. XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  123. M68KMAKE_TABLE_FOOTER
  124. {0, 0, 0, {0, 0, 0, 0}}
  125. };
  126. /* Build the opcode handler jump table */
  127. void m68ki_build_opcode_table(void)
  128. {
  129. opcode_handler_struct *ostruct;
  130. int instr;
  131. int i;
  132. int j;
  133. int k;
  134. for(i = 0; i < 0x10000; i++)
  135. {
  136. /* default to illegal */
  137. m68ki_instruction_jump_table[i] = m68k_op_illegal;
  138. for(k=0;k<NUM_CPU_TYPES;k++)
  139. m68ki_cycles[k][i] = 0;
  140. }
  141. ostruct = m68k_opcode_handler_table;
  142. while(ostruct->mask != 0xff00)
  143. {
  144. for(i = 0;i < 0x10000;i++)
  145. {
  146. if((i & ostruct->mask) == ostruct->match)
  147. {
  148. m68ki_instruction_jump_table[i] = ostruct->opcode_handler;
  149. for(k=0;k<NUM_CPU_TYPES;k++)
  150. m68ki_cycles[k][i] = ostruct->cycles[k];
  151. }
  152. }
  153. ostruct++;
  154. }
  155. while(ostruct->mask == 0xff00)
  156. {
  157. for(i = 0;i <= 0xff;i++)
  158. {
  159. m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
  160. for(k=0;k<NUM_CPU_TYPES;k++)
  161. m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
  162. }
  163. ostruct++;
  164. }
  165. while(ostruct->mask == 0xf1f8)
  166. {
  167. for(i = 0;i < 8;i++)
  168. {
  169. for(j = 0;j < 8;j++)
  170. {
  171. instr = ostruct->match | (i << 9) | j;
  172. m68ki_instruction_jump_table[instr] = ostruct->opcode_handler;
  173. for(k=0;k<NUM_CPU_TYPES;k++)
  174. m68ki_cycles[k][instr] = ostruct->cycles[k];
  175. }
  176. }
  177. ostruct++;
  178. }
  179. while(ostruct->mask == 0xfff0)
  180. {
  181. for(i = 0;i <= 0x0f;i++)
  182. {
  183. m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
  184. for(k=0;k<NUM_CPU_TYPES;k++)
  185. m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
  186. }
  187. ostruct++;
  188. }
  189. while(ostruct->mask == 0xf1ff)
  190. {
  191. for(i = 0;i <= 0x07;i++)
  192. {
  193. m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler;
  194. for(k=0;k<NUM_CPU_TYPES;k++)
  195. m68ki_cycles[k][ostruct->match | (i << 9)] = ostruct->cycles[k];
  196. }
  197. ostruct++;
  198. }
  199. while(ostruct->mask == 0xfff8)
  200. {
  201. for(i = 0;i <= 0x07;i++)
  202. {
  203. m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
  204. for(k=0;k<NUM_CPU_TYPES;k++)
  205. m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
  206. }
  207. ostruct++;
  208. }
  209. while(ostruct->mask == 0xffff)
  210. {
  211. m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler;
  212. for(k=0;k<NUM_CPU_TYPES;k++)
  213. m68ki_cycles[k][ostruct->match] = ostruct->cycles[k];
  214. ostruct++;
  215. }
  216. }
  217. /* ======================================================================== */
  218. /* ============================== END OF FILE ============================= */
  219. /* ======================================================================== */
  220. XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  221. M68KMAKE_OPCODE_HANDLER_HEADER
  222. #include "m68kcpu.h"
  223. extern void m68040_fpu_op0(void);
  224. extern void m68040_fpu_op1(void);
  225. /* ======================================================================== */
  226. /* ========================= INSTRUCTION HANDLERS ========================= */
  227. /* ======================================================================== */
  228. XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  229. M68KMAKE_OPCODE_HANDLER_FOOTER
  230. /* ======================================================================== */
  231. /* ============================== END OF FILE ============================= */
  232. /* ======================================================================== */
  233. XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  234. M68KMAKE_TABLE_BODY
  235. The following table is arranged as follows:
  236. name: Opcode mnemonic
  237. size: Operation size
  238. spec proc: Special processing mode:
  239. .: normal
  240. s: static operand
  241. r: register operand
  242. rr: register to register
  243. mm: memory to memory
  244. er: effective address to register
  245. re: register to effective address
  246. dd: data register to data register
  247. da: data register to address register
  248. aa: address register to address register
  249. cr: control register to register
  250. rc: register to control register
  251. toc: to condition code register
  252. tos: to status register
  253. tou: to user stack pointer
  254. frc: from condition code register
  255. frs: from status register
  256. fru: from user stack pointer
  257. * for move.x, the special processing mode is a specific
  258. destination effective addressing mode.
  259. spec ea: Specific effective addressing mode:
  260. .: normal
  261. i: immediate
  262. d: data register
  263. a: address register
  264. ai: address register indirect
  265. pi: address register indirect with postincrement
  266. pd: address register indirect with predecrement
  267. di: address register indirect with displacement
  268. ix: address register indirect with index
  269. aw: absolute word address
  270. al: absolute long address
  271. pcdi: program counter relative with displacement
  272. pcix: program counter relative with index
  273. a7: register specified in instruction is A7
  274. ax7: register field X of instruction is A7
  275. ay7: register field Y of instruction is A7
  276. axy7: register fields X and Y of instruction are A7
  277. bit pattern: Pattern to recognize this opcode. "." means don't care.
  278. allowed ea: List of allowed addressing modes:
  279. .: not present
  280. A: address register indirect
  281. +: ARI (address register indirect) with postincrement
  282. -: ARI with predecrement
  283. D: ARI with displacement
  284. X: ARI with index
  285. W: absolute word address
  286. L: absolute long address
  287. d: program counter indirect with displacement
  288. x: program counter indirect with index
  289. I: immediate
  290. mode: CPU operating mode for each cpu type. U = user or supervisor,
  291. S = supervisor only, "." = opcode not present.
  292. cpu cycles: Base number of cycles required to execute this opcode on the
  293. specified CPU type.
  294. Use "." if CPU does not have this opcode.
  295. spec spec allowed ea mode cpu cycles
  296. name size proc ea bit pattern A+-DXWLdxI 0 1 2 4 000 010 020 040 comments
  297. ====== ==== ==== ==== ================ ========== = = = = === === === === =============
  298. M68KMAKE_TABLE_START
  299. 1010 0 . . 1010............ .......... U U U U 4 4 4 4
  300. 1111 0 . . 1111............ .......... U U U U 4 4 4 4
  301. 040fpu0 32 . . 11110010........ .......... . . . U . . . 0
  302. 040fpu1 32 . . 11110011........ .......... . . . U . . . 0
  303. abcd 8 rr . 1100...100000... .......... U U U U 6 6 4 4
  304. abcd 8 mm ax7 1100111100001... .......... U U U U 18 18 16 16
  305. abcd 8 mm ay7 1100...100001111 .......... U U U U 18 18 16 16
  306. abcd 8 mm axy7 1100111100001111 .......... U U U U 18 18 16 16
  307. abcd 8 mm . 1100...100001... .......... U U U U 18 18 16 16
  308. add 8 er d 1101...000000... .......... U U U U 4 4 2 2
  309. add 8 er . 1101...000...... A+-DXWLdxI U U U U 4 4 2 2
  310. add 16 er d 1101...001000... .......... U U U U 4 4 2 2
  311. add 16 er a 1101...001001... .......... U U U U 4 4 2 2
  312. add 16 er . 1101...001...... A+-DXWLdxI U U U U 4 4 2 2
  313. add 32 er d 1101...010000... .......... U U U U 6 6 2 2
  314. add 32 er a 1101...010001... .......... U U U U 6 6 2 2
  315. add 32 er . 1101...010...... A+-DXWLdxI U U U U 6 6 2 2
  316. add 8 re . 1101...100...... A+-DXWL... U U U U 8 8 4 4
  317. add 16 re . 1101...101...... A+-DXWL... U U U U 8 8 4 4
  318. add 32 re . 1101...110...... A+-DXWL... U U U U 12 12 4 4
  319. adda 16 . d 1101...011000... .......... U U U U 8 8 2 2
  320. adda 16 . a 1101...011001... .......... U U U U 8 8 2 2
  321. adda 16 . . 1101...011...... A+-DXWLdxI U U U U 8 8 2 2
  322. adda 32 . d 1101...111000... .......... U U U U 6 6 2 2
  323. adda 32 . a 1101...111001... .......... U U U U 6 6 2 2
  324. adda 32 . . 1101...111...... A+-DXWLdxI U U U U 6 6 2 2
  325. addi 8 . d 0000011000000... .......... U U U U 8 8 2 2
  326. addi 8 . . 0000011000...... A+-DXWL... U U U U 12 12 4 4
  327. addi 16 . d 0000011001000... .......... U U U U 8 8 2 2
  328. addi 16 . . 0000011001...... A+-DXWL... U U U U 12 12 4 4
  329. addi 32 . d 0000011010000... .......... U U U U 16 14 2 2
  330. addi 32 . . 0000011010...... A+-DXWL... U U U U 20 20 4 4
  331. addq 8 . d 0101...000000... .......... U U U U 4 4 2 2
  332. addq 8 . . 0101...000...... A+-DXWL... U U U U 8 8 4 4
  333. addq 16 . d 0101...001000... .......... U U U U 4 4 2 2
  334. addq 16 . a 0101...001001... .......... U U U U 8 8 2 2
  335. addq 16 . . 0101...001...... A+-DXWL... U U U U 8 8 4 4
  336. addq 32 . d 0101...010000... .......... U U U U 8 8 2 2
  337. addq 32 . a 0101...010001... .......... U U U U 8 8 2 2
  338. addq 32 . . 0101...010...... A+-DXWL... U U U U 12 12 4 4
  339. addx 8 rr . 1101...100000... .......... U U U U 4 4 2 2
  340. addx 16 rr . 1101...101000... .......... U U U U 4 4 2 2
  341. addx 32 rr . 1101...110000... .......... U U U U 8 6 2 2
  342. addx 8 mm ax7 1101111100001... .......... U U U U 18 18 12 12
  343. addx 8 mm ay7 1101...100001111 .......... U U U U 18 18 12 12
  344. addx 8 mm axy7 1101111100001111 .......... U U U U 18 18 12 12
  345. addx 8 mm . 1101...100001... .......... U U U U 18 18 12 12
  346. addx 16 mm . 1101...101001... .......... U U U U 18 18 12 12
  347. addx 32 mm . 1101...110001... .......... U U U U 30 30 12 12
  348. and 8 er d 1100...000000... .......... U U U U 4 4 2 2
  349. and 8 er . 1100...000...... A+-DXWLdxI U U U U 4 4 2 2
  350. and 16 er d 1100...001000... .......... U U U U 4 4 2 2
  351. and 16 er . 1100...001...... A+-DXWLdxI U U U U 4 4 2 2
  352. and 32 er d 1100...010000... .......... U U U U 6 6 2 2
  353. and 32 er . 1100...010...... A+-DXWLdxI U U U U 6 6 2 2
  354. and 8 re . 1100...100...... A+-DXWL... U U U U 8 8 4 4
  355. and 16 re . 1100...101...... A+-DXWL... U U U U 8 8 4 4
  356. and 32 re . 1100...110...... A+-DXWL... U U U U 12 12 4 4
  357. andi 16 toc . 0000001000111100 .......... U U U U 20 16 12 12
  358. andi 16 tos . 0000001001111100 .......... S S S S 20 16 12 12
  359. andi 8 . d 0000001000000... .......... U U U U 8 8 2 2
  360. andi 8 . . 0000001000...... A+-DXWL... U U U U 12 12 4 4
  361. andi 16 . d 0000001001000... .......... U U U U 8 8 2 2
  362. andi 16 . . 0000001001...... A+-DXWL... U U U U 12 12 4 4
  363. andi 32 . d 0000001010000... .......... U U U U 14 14 2 2
  364. andi 32 . . 0000001010...... A+-DXWL... U U U U 20 20 4 4
  365. asr 8 s . 1110...000000... .......... U U U U 6 6 6 6
  366. asr 16 s . 1110...001000... .......... U U U U 6 6 6 6
  367. asr 32 s . 1110...010000... .......... U U U U 8 8 6 6
  368. asr 8 r . 1110...000100... .......... U U U U 6 6 6 6
  369. asr 16 r . 1110...001100... .......... U U U U 6 6 6 6
  370. asr 32 r . 1110...010100... .......... U U U U 8 8 6 6
  371. asr 16 . . 1110000011...... A+-DXWL... U U U U 8 8 5 5
  372. asl 8 s . 1110...100000... .......... U U U U 6 6 8 8
  373. asl 16 s . 1110...101000... .......... U U U U 6 6 8 8
  374. asl 32 s . 1110...110000... .......... U U U U 8 8 8 8
  375. asl 8 r . 1110...100100... .......... U U U U 6 6 8 8
  376. asl 16 r . 1110...101100... .......... U U U U 6 6 8 8
  377. asl 32 r . 1110...110100... .......... U U U U 8 8 8 8
  378. asl 16 . . 1110000111...... A+-DXWL... U U U U 8 8 6 6
  379. bcc 8 . . 0110............ .......... U U U U 10 10 6 6
  380. bcc 16 . . 0110....00000000 .......... U U U U 10 10 6 6
  381. bcc 32 . . 0110....11111111 .......... U U U U 10 10 6 6
  382. bchg 8 r . 0000...101...... A+-DXWL... U U U U 8 8 4 4
  383. bchg 32 r d 0000...101000... .......... U U U U 8 8 4 4
  384. bchg 8 s . 0000100001...... A+-DXWL... U U U U 12 12 4 4
  385. bchg 32 s d 0000100001000... .......... U U U U 12 12 4 4
  386. bclr 8 r . 0000...110...... A+-DXWL... U U U U 8 10 4 4
  387. bclr 32 r d 0000...110000... .......... U U U U 10 10 4 4
  388. bclr 8 s . 0000100010...... A+-DXWL... U U U U 12 12 4 4
  389. bclr 32 s d 0000100010000... .......... U U U U 14 14 4 4
  390. bfchg 32 . d 1110101011000... .......... . . U U . . 12 12 timing not quite correct
  391. bfchg 32 . . 1110101011...... A..DXWL... . . U U . . 20 20
  392. bfclr 32 . d 1110110011000... .......... . . U U . . 12 12
  393. bfclr 32 . . 1110110011...... A..DXWL... . . U U . . 20 20
  394. bfexts 32 . d 1110101111000... .......... . . U U . . 8 8
  395. bfexts 32 . . 1110101111...... A..DXWLdx. . . U U . . 15 15
  396. bfextu 32 . d 1110100111000... .......... . . U U . . 8 8
  397. bfextu 32 . . 1110100111...... A..DXWLdx. . . U U . . 15 15
  398. bfffo 32 . d 1110110111000... .......... . . U U . . 18 18
  399. bfffo 32 . . 1110110111...... A..DXWLdx. . . U U . . 28 28
  400. bfins 32 . d 1110111111000... .......... . . U U . . 10 10
  401. bfins 32 . . 1110111111...... A..DXWL... . . U U . . 17 17
  402. bfset 32 . d 1110111011000... .......... . . U U . . 12 12
  403. bfset 32 . . 1110111011...... A..DXWL... . . U U . . 20 20
  404. bftst 32 . d 1110100011000... .......... . . U U . . 6 6
  405. bftst 32 . . 1110100011...... A..DXWLdx. . . U U . . 13 13
  406. bkpt 0 . . 0100100001001... .......... . U U U . 10 10 10
  407. bra 8 . . 01100000........ .......... U U U U 10 10 10 10
  408. bra 16 . . 0110000000000000 .......... U U U U 10 10 10 10
  409. bra 32 . . 0110000011111111 .......... U U U U 10 10 10 10
  410. bset 32 r d 0000...111000... .......... U U U U 8 8 4 4
  411. bset 8 r . 0000...111...... A+-DXWL... U U U U 8 8 4 4
  412. bset 8 s . 0000100011...... A+-DXWL... U U U U 12 12 4 4
  413. bset 32 s d 0000100011000... .......... U U U U 12 12 4 4
  414. bsr 8 . . 01100001........ .......... U U U U 18 18 7 7
  415. bsr 16 . . 0110000100000000 .......... U U U U 18 18 7 7
  416. bsr 32 . . 0110000111111111 .......... U U U U 18 18 7 7
  417. btst 8 r . 0000...100...... A+-DXWLdxI U U U U 4 4 4 4
  418. btst 32 r d 0000...100000... .......... U U U U 6 6 4 4
  419. btst 8 s . 0000100000...... A+-DXWLdx. U U U U 8 8 4 4
  420. btst 32 s d 0000100000000... .......... U U U U 10 10 4 4
  421. callm 32 . . 0000011011...... A..DXWLdx. . . U U . . 60 60 not properly emulated
  422. cas 8 . . 0000101011...... A+-DXWL... . . U U . . 12 12
  423. cas 16 . . 0000110011...... A+-DXWL... . . U U . . 12 12
  424. cas 32 . . 0000111011...... A+-DXWL... . . U U . . 12 12
  425. cas2 16 . . 0000110011111100 .......... . . U U . . 12 12
  426. cas2 32 . . 0000111011111100 .......... . . U U . . 12 12
  427. chk 16 . d 0100...110000... .......... U U U U 10 8 8 8
  428. chk 16 . . 0100...110...... A+-DXWLdxI U U U U 10 8 8 8
  429. chk 32 . d 0100...100000... .......... . . U U . . 8 8
  430. chk 32 . . 0100...100...... A+-DXWLdxI . . U U . . 8 8
  431. chk2cmp2 8 . pcdi 0000000011111010 .......... . . U U . . 23 23
  432. chk2cmp2 8 . pcix 0000000011111011 .......... . . U U . . 23 23
  433. chk2cmp2 8 . . 0000000011...... A..DXWL... . . U U . . 18 18
  434. chk2cmp2 16 . pcdi 0000001011111010 .......... . . U U . . 23 23
  435. chk2cmp2 16 . pcix 0000001011111011 .......... . . U U . . 23 23
  436. chk2cmp2 16 . . 0000001011...... A..DXWL... . . U U . . 18 18
  437. chk2cmp2 32 . pcdi 0000010011111010 .......... . . U U . . 23 23
  438. chk2cmp2 32 . pcix 0000010011111011 .......... . . U U . . 23 23
  439. chk2cmp2 32 . . 0000010011...... A..DXWL... . . U U . . 18 18
  440. clr 8 . d 0100001000000... .......... U U U U 4 4 2 2
  441. clr 8 . . 0100001000...... A+-DXWL... U U U U 8 4 4 4
  442. clr 16 . d 0100001001000... .......... U U U U 4 4 2 2
  443. clr 16 . . 0100001001...... A+-DXWL... U U U U 8 4 4 4
  444. clr 32 . d 0100001010000... .......... U U U U 6 6 2 2
  445. clr 32 . . 0100001010...... A+-DXWL... U U U U 12 6 4 4
  446. cmp 8 . d 1011...000000... .......... U U U U 4 4 2 2
  447. cmp 8 . . 1011...000...... A+-DXWLdxI U U U U 4 4 2 2
  448. cmp 16 . d 1011...001000... .......... U U U U 4 4 2 2
  449. cmp 16 . a 1011...001001... .......... U U U U 4 4 2 2
  450. cmp 16 . . 1011...001...... A+-DXWLdxI U U U U 4 4 2 2
  451. cmp 32 . d 1011...010000... .......... U U U U 6 6 2 2
  452. cmp 32 . a 1011...010001... .......... U U U U 6 6 2 2
  453. cmp 32 . . 1011...010...... A+-DXWLdxI U U U U 6 6 2 2
  454. cmpa 16 . d 1011...011000... .......... U U U U 6 6 4 4
  455. cmpa 16 . a 1011...011001... .......... U U U U 6 6 4 4
  456. cmpa 16 . . 1011...011...... A+-DXWLdxI U U U U 6 6 4 4
  457. cmpa 32 . d 1011...111000... .......... U U U U 6 6 4 4
  458. cmpa 32 . a 1011...111001... .......... U U U U 6 6 4 4
  459. cmpa 32 . . 1011...111...... A+-DXWLdxI U U U U 6 6 4 4
  460. cmpi 8 . d 0000110000000... .......... U U U U 8 8 2 2
  461. cmpi 8 . . 0000110000...... A+-DXWL... U U U U 8 8 2 2
  462. cmpi 8 . pcdi 0000110000111010 .......... . . U U . . 7 7
  463. cmpi 8 . pcix 0000110000111011 .......... . . U U . . 9 9
  464. cmpi 16 . d 0000110001000... .......... U U U U 8 8 2 2
  465. cmpi 16 . . 0000110001...... A+-DXWL... U U U U 8 8 2 2
  466. cmpi 16 . pcdi 0000110001111010 .......... . . U U . . 7 7
  467. cmpi 16 . pcix 0000110001111011 .......... . . U U . . 9 9
  468. cmpi 32 . d 0000110010000... .......... U U U U 14 12 2 2
  469. cmpi 32 . . 0000110010...... A+-DXWL... U U U U 12 12 2 2
  470. cmpi 32 . pcdi 0000110010111010 .......... . . U U . . 7 7
  471. cmpi 32 . pcix 0000110010111011 .......... . . U U . . 9 9
  472. cmpm 8 . ax7 1011111100001... .......... U U U U 12 12 9 9
  473. cmpm 8 . ay7 1011...100001111 .......... U U U U 12 12 9 9
  474. cmpm 8 . axy7 1011111100001111 .......... U U U U 12 12 9 9
  475. cmpm 8 . . 1011...100001... .......... U U U U 12 12 9 9
  476. cmpm 16 . . 1011...101001... .......... U U U U 12 12 9 9
  477. cmpm 32 . . 1011...110001... .......... U U U U 20 20 9 9
  478. cpbcc 32 . . 1111...01....... .......... . . U . . . 4 . unemulated
  479. cpdbcc 32 . . 1111...001001... .......... . . U . . . 4 . unemulated
  480. cpgen 32 . . 1111...000...... .......... . . U . . . 4 . unemulated
  481. cpscc 32 . . 1111...001...... .......... . . U . . . 4 . unemulated
  482. cptrapcc 32 . . 1111...001111... .......... . . U . . . 4 . unemulated
  483. dbt 16 . . 0101000011001... .......... U U U U 12 12 6 6
  484. dbf 16 . . 0101000111001... .......... U U U U 12 12 6 6
  485. dbcc 16 . . 0101....11001... .......... U U U U 12 12 6 6
  486. divs 16 . d 1000...111000... .......... U U U U 158 122 56 56
  487. divs 16 . . 1000...111...... A+-DXWLdxI U U U U 158 122 56 56
  488. divu 16 . d 1000...011000... .......... U U U U 140 108 44 44
  489. divu 16 . . 1000...011...... A+-DXWLdxI U U U U 140 108 44 44
  490. divl 32 . d 0100110001000... .......... . . U U . . 84 84
  491. divl 32 . . 0100110001...... A+-DXWLdxI . . U U . . 84 84
  492. eor 8 . d 1011...100000... .......... U U U U 4 4 2 2
  493. eor 8 . . 1011...100...... A+-DXWL... U U U U 8 8 4 4
  494. eor 16 . d 1011...101000... .......... U U U U 4 4 2 2
  495. eor 16 . . 1011...101...... A+-DXWL... U U U U 8 8 4 4
  496. eor 32 . d 1011...110000... .......... U U U U 8 6 2 2
  497. eor 32 . . 1011...110...... A+-DXWL... U U U U 12 12 4 4
  498. eori 16 toc . 0000101000111100 .......... U U U U 20 16 12 12
  499. eori 16 tos . 0000101001111100 .......... S S S S 20 16 12 12
  500. eori 8 . d 0000101000000... .......... U U U U 8 8 2 2
  501. eori 8 . . 0000101000...... A+-DXWL... U U U U 12 12 4 4
  502. eori 16 . d 0000101001000... .......... U U U U 8 8 2 2
  503. eori 16 . . 0000101001...... A+-DXWL... U U U U 12 12 4 4
  504. eori 32 . d 0000101010000... .......... U U U U 16 14 2 2
  505. eori 32 . . 0000101010...... A+-DXWL... U U U U 20 20 4 4
  506. exg 32 dd . 1100...101000... .......... U U U U 6 6 2 2
  507. exg 32 aa . 1100...101001... .......... U U U U 6 6 2 2
  508. exg 32 da . 1100...110001... .......... U U U U 6 6 2 2
  509. ext 16 . . 0100100010000... .......... U U U U 4 4 4 4
  510. ext 32 . . 0100100011000... .......... U U U U 4 4 4 4
  511. extb 32 . . 0100100111000... .......... . . U U . . 4 4
  512. illegal 0 . . 0100101011111100 .......... U U U U 4 4 4 4
  513. jmp 32 . . 0100111011...... A..DXWLdx. U U U U 4 4 0 0
  514. jsr 32 . . 0100111010...... A..DXWLdx. U U U U 12 12 0 0
  515. lea 32 . . 0100...111...... A..DXWLdx. U U U U 0 0 2 2
  516. link 16 . a7 0100111001010111 .......... U U U U 16 16 5 5
  517. link 16 . . 0100111001010... .......... U U U U 16 16 5 5
  518. link 32 . a7 0100100000001111 .......... . . U U . . 6 6
  519. link 32 . . 0100100000001... .......... . . U U . . 6 6
  520. lsr 8 s . 1110...000001... .......... U U U U 6 6 4 4
  521. lsr 16 s . 1110...001001... .......... U U U U 6 6 4 4
  522. lsr 32 s . 1110...010001... .......... U U U U 8 8 4 4
  523. lsr 8 r . 1110...000101... .......... U U U U 6 6 6 6
  524. lsr 16 r . 1110...001101... .......... U U U U 6 6 6 6
  525. lsr 32 r . 1110...010101... .......... U U U U 8 8 6 6
  526. lsr 16 . . 1110001011...... A+-DXWL... U U U U 8 8 5 5
  527. lsl 8 s . 1110...100001... .......... U U U U 6 6 4 4
  528. lsl 16 s . 1110...101001... .......... U U U U 6 6 4 4
  529. lsl 32 s . 1110...110001... .......... U U U U 8 8 4 4
  530. lsl 8 r . 1110...100101... .......... U U U U 6 6 6 6
  531. lsl 16 r . 1110...101101... .......... U U U U 6 6 6 6
  532. lsl 32 r . 1110...110101... .......... U U U U 8 8 6 6
  533. lsl 16 . . 1110001111...... A+-DXWL... U U U U 8 8 5 5
  534. move 8 d d 0001...000000... .......... U U U U 4 4 2 2
  535. move 8 d . 0001...000...... A+-DXWLdxI U U U U 4 4 2 2
  536. move 8 ai d 0001...010000... .......... U U U U 8 8 4 4
  537. move 8 ai . 0001...010...... A+-DXWLdxI U U U U 8 8 4 4
  538. move 8 pi d 0001...011000... .......... U U U U 8 8 4 4
  539. move 8 pi . 0001...011...... A+-DXWLdxI U U U U 8 8 4 4
  540. move 8 pi7 d 0001111011000... .......... U U U U 8 8 4 4
  541. move 8 pi7 . 0001111011...... A+-DXWLdxI U U U U 8 8 4 4
  542. move 8 pd d 0001...100000... .......... U U U U 8 8 5 5
  543. move 8 pd . 0001...100...... A+-DXWLdxI U U U U 8 8 5 5
  544. move 8 pd7 d 0001111100000... .......... U U U U 8 8 5 5
  545. move 8 pd7 . 0001111100...... A+-DXWLdxI U U U U 8 8 5 5
  546. move 8 di d 0001...101000... .......... U U U U 12 12 5 5
  547. move 8 di . 0001...101...... A+-DXWLdxI U U U U 12 12 5 5
  548. move 8 ix d 0001...110000... .......... U U U U 14 14 7 7
  549. move 8 ix . 0001...110...... A+-DXWLdxI U U U U 14 14 7 7
  550. move 8 aw d 0001000111000... .......... U U U U 12 12 4 4
  551. move 8 aw . 0001000111...... A+-DXWLdxI U U U U 12 12 4 4
  552. move 8 al d 0001001111000... .......... U U U U 16 16 6 6
  553. move 8 al . 0001001111...... A+-DXWLdxI U U U U 16 16 6 6
  554. move 16 d d 0011...000000... .......... U U U U 4 4 2 2
  555. move 16 d a 0011...000001... .......... U U U U 4 4 2 2
  556. move 16 d . 0011...000...... A+-DXWLdxI U U U U 4 4 2 2
  557. move 16 ai d 0011...010000... .......... U U U U 8 8 4 4
  558. move 16 ai a 0011...010001... .......... U U U U 8 8 4 4
  559. move 16 ai . 0011...010...... A+-DXWLdxI U U U U 8 8 4 4
  560. move 16 pi d 0011...011000... .......... U U U U 8 8 4 4
  561. move 16 pi a 0011...011001... .......... U U U U 8 8 4 4
  562. move 16 pi . 0011...011...... A+-DXWLdxI U U U U 8 8 4 4
  563. move 16 pd d 0011...100000... .......... U U U U 8 8 5 5
  564. move 16 pd a 0011...100001... .......... U U U U 8 8 5 5
  565. move 16 pd . 0011...100...... A+-DXWLdxI U U U U 8 8 5 5
  566. move 16 di d 0011...101000... .......... U U U U 12 12 5 5
  567. move 16 di a 0011...101001... .......... U U U U 12 12 5 5
  568. move 16 di . 0011...101...... A+-DXWLdxI U U U U 12 12 5 5
  569. move 16 ix d 0011...110000... .......... U U U U 14 14 7 7
  570. move 16 ix a 0011...110001... .......... U U U U 14 14 7 7
  571. move 16 ix . 0011...110...... A+-DXWLdxI U U U U 14 14 7 7
  572. move 16 aw d 0011000111000... .......... U U U U 12 12 4 4
  573. move 16 aw a 0011000111001... .......... U U U U 12 12 4 4
  574. move 16 aw . 0011000111...... A+-DXWLdxI U U U U 12 12 4 4
  575. move 16 al d 0011001111000... .......... U U U U 16 16 6 6
  576. move 16 al a 0011001111001... .......... U U U U 16 16 6 6
  577. move 16 al . 0011001111...... A+-DXWLdxI U U U U 16 16 6 6
  578. move 32 d d 0010...000000... .......... U U U U 4 4 2 2
  579. move 32 d a 0010...000001... .......... U U U U 4 4 2 2
  580. move 32 d . 0010...000...... A+-DXWLdxI U U U U 4 4 2 2
  581. move 32 ai d 0010...010000... .......... U U U U 12 12 4 4
  582. move 32 ai a 0010...010001... .......... U U U U 12 12 4 4
  583. move 32 ai . 0010...010...... A+-DXWLdxI U U U U 12 12 4 4
  584. move 32 pi d 0010...011000... .......... U U U U 12 12 4 4
  585. move 32 pi a 0010...011001... .......... U U U U 12 12 4 4
  586. move 32 pi . 0010...011...... A+-DXWLdxI U U U U 12 12 4 4
  587. move 32 pd d 0010...100000... .......... U U U U 12 14 5 5
  588. move 32 pd a 0010...100001... .......... U U U U 12 14 5 5
  589. move 32 pd . 0010...100...... A+-DXWLdxI U U U U 12 14 5 5
  590. move 32 di d 0010...101000... .......... U U U U 16 16 5 5
  591. move 32 di a 0010...101001... .......... U U U U 16 16 5 5
  592. move 32 di . 0010...101...... A+-DXWLdxI U U U U 16 16 5 5
  593. move 32 ix d 0010...110000... .......... U U U U 18 18 7 7
  594. move 32 ix a 0010...110001... .......... U U U U 18 18 7 7
  595. move 32 ix . 0010...110...... A+-DXWLdxI U U U U 18 18 7 7
  596. move 32 aw d 0010000111000... .......... U U U U 16 16 4 4
  597. move 32 aw a 0010000111001... .......... U U U U 16 16 4 4
  598. move 32 aw . 0010000111...... A+-DXWLdxI U U U U 16 16 4 4
  599. move 32 al d 0010001111000... .......... U U U U 20 20 6 6
  600. move 32 al a 0010001111001... .......... U U U U 20 20 6 6
  601. move 32 al . 0010001111...... A+-DXWLdxI U U U U 20 20 6 6
  602. movea 16 . d 0011...001000... .......... U U U U 4 4 2 2
  603. movea 16 . a 0011...001001... .......... U U U U 4 4 2 2
  604. movea 16 . . 0011...001...... A+-DXWLdxI U U U U 4 4 2 2
  605. movea 32 . d 0010...001000... .......... U U U U 4 4 2 2
  606. movea 32 . a 0010...001001... .......... U U U U 4 4 2 2
  607. movea 32 . . 0010...001...... A+-DXWLdxI U U U U 4 4 2 2
  608. move 16 frc d 0100001011000... .......... . U U U . 4 4 4
  609. move 16 frc . 0100001011...... A+-DXWL... . U U U . 8 4 4
  610. move 16 toc d 0100010011000... .......... U U U U 12 12 4 4
  611. move 16 toc . 0100010011...... A+-DXWLdxI U U U U 12 12 4 4
  612. move 16 frs d 0100000011000... .......... U S S S 6 4 8 8 U only for 000
  613. move 16 frs . 0100000011...... A+-DXWL... U S S S 8 8 8 8 U only for 000
  614. move 16 tos d 0100011011000... .......... S S S S 12 12 8 8
  615. move 16 tos . 0100011011...... A+-DXWLdxI S S S S 12 12 8 8
  616. move 32 fru . 0100111001101... .......... S S S S 4 6 2 2
  617. move 32 tou . 0100111001100... .......... S S S S 4 6 2 2
  618. movec 32 cr . 0100111001111010 .......... . S S S . 12 6 6
  619. movec 32 rc . 0100111001111011 .......... . S S S . 10 12 12
  620. movem 16 re pd 0100100010100... .......... U U U U 8 8 4 4
  621. movem 16 re . 0100100010...... A..DXWL... U U U U 8 8 4 4
  622. movem 32 re pd 0100100011100... .......... U U U U 8 8 4 4
  623. movem 32 re . 0100100011...... A..DXWL... U U U U 8 8 4 4
  624. movem 16 er pi 0100110010011... .......... U U U U 12 12 8 8
  625. movem 16 er pcdi 0100110010111010 .......... U U U U 16 16 9 9
  626. movem 16 er pcix 0100110010111011 .......... U U U U 18 18 11 11
  627. movem 16 er . 0100110010...... A..DXWL... U U U U 12 12 8 8
  628. movem 32 er pi 0100110011011... .......... U U U U 12 12 8 8
  629. movem 32 er pcdi 0100110011111010 .......... U U U U 16 16 9 9
  630. movem 32 er pcix 0100110011111011 .......... U U U U 18 18 11 11
  631. movem 32 er . 0100110011...... A..DXWL... U U U U 12 12 8 8
  632. movep 16 er . 0000...100001... .......... U U U U 16 16 12 12
  633. movep 32 er . 0000...101001... .......... U U U U 24 24 18 18
  634. movep 16 re . 0000...110001... .......... U U U U 16 16 11 11
  635. movep 32 re . 0000...111001... .......... U U U U 24 24 17 17
  636. moveq 32 . . 0111...0........ .......... U U U U 4 4 2 2
  637. moves 8 . . 0000111000...... A+-DXWL... . S S S . 14 5 5
  638. moves 16 . . 0000111001...... A+-DXWL... . S S S . 14 5 5
  639. moves 32 . . 0000111010...... A+-DXWL... . S S S . 16 5 5
  640. move16 32 . . 1111011000100... .......... . . . U . . . 4 TODO: correct timing
  641. muls 16 . d 1100...111000... .......... U U U U 54 32 27 27
  642. muls 16 . . 1100...111...... A+-DXWLdxI U U U U 54 32 27 27
  643. mulu 16 . d 1100...011000... .......... U U U U 54 30 27 27
  644. mulu 16 . . 1100...011...... A+-DXWLdxI U U U U 54 30 27 27
  645. mull 32 . d 0100110000000... .......... . . U U . . 43 43
  646. mull 32 . . 0100110000...... A+-DXWLdxI . . U U . . 43 43
  647. nbcd 8 . d 0100100000000... .......... U U U U 6 6 6 6
  648. nbcd 8 . . 0100100000...... A+-DXWL... U U U U 8 8 6 6
  649. neg 8 . d 0100010000000... .......... U U U U 4 4 2 2
  650. neg 8 . . 0100010000...... A+-DXWL... U U U U 8 8 4 4
  651. neg 16 . d 0100010001000... .......... U U U U 4 4 2 2
  652. neg 16 . . 0100010001...... A+-DXWL... U U U U 8 8 4 4
  653. neg 32 . d 0100010010000... .......... U U U U 6 6 2 2
  654. neg 32 . . 0100010010...... A+-DXWL... U U U U 12 12 4 4
  655. negx 8 . d 0100000000000... .......... U U U U 4 4 2 2
  656. negx 8 . . 0100000000...... A+-DXWL... U U U U 8 8 4 4
  657. negx 16 . d 0100000001000... .......... U U U U 4 4 2 2
  658. negx 16 . . 0100000001...... A+-DXWL... U U U U 8 8 4 4
  659. negx 32 . d 0100000010000... .......... U U U U 6 6 2 2
  660. negx 32 . . 0100000010...... A+-DXWL... U U U U 12 12 4 4
  661. nop 0 . . 0100111001110001 .......... U U U U 4 4 2 2
  662. not 8 . d 0100011000000... .......... U U U U 4 4 2 2
  663. not 8 . . 0100011000...... A+-DXWL... U U U U 8 8 4 4
  664. not 16 . d 0100011001000... .......... U U U U 4 4 2 2
  665. not 16 . . 0100011001...... A+-DXWL... U U U U 8 8 4 4
  666. not 32 . d 0100011010000... .......... U U U U 6 6 2 2
  667. not 32 . . 0100011010...... A+-DXWL... U U U U 12 12 4 4
  668. or 8 er d 1000...000000... .......... U U U U 4 4 2 2
  669. or 8 er . 1000...000...... A+-DXWLdxI U U U U 4 4 2 2
  670. or 16 er d 1000...001000... .......... U U U U 4 4 2 2
  671. or 16 er . 1000...001...... A+-DXWLdxI U U U U 4 4 2 2
  672. or 32 er d 1000...010000... .......... U U U U 6 6 2 2
  673. or 32 er . 1000...010...... A+-DXWLdxI U U U U 6 6 2 2
  674. or 8 re . 1000...100...... A+-DXWL... U U U U 8 8 4 4
  675. or 16 re . 1000...101...... A+-DXWL... U U U U 8 8 4 4
  676. or 32 re . 1000...110...... A+-DXWL... U U U U 12 12 4 4
  677. ori 16 toc . 0000000000111100 .......... U U U U 20 16 12 12
  678. ori 16 tos . 0000000001111100 .......... S S S S 20 16 12 12
  679. ori 8 . d 0000000000000... .......... U U U U 8 8 2 2
  680. ori 8 . . 0000000000...... A+-DXWL... U U U U 12 12 4 4
  681. ori 16 . d 0000000001000... .......... U U U U 8 8 2 2
  682. ori 16 . . 0000000001...... A+-DXWL... U U U U 12 12 4 4
  683. ori 32 . d 0000000010000... .......... U U U U 16 14 2 2
  684. ori 32 . . 0000000010...... A+-DXWL... U U U U 20 20 4 4
  685. pack 16 rr . 1000...101000... .......... . . U U . . 6 6
  686. pack 16 mm ax7 1000111101001... .......... . . U U . . 13 13
  687. pack 16 mm ay7 1000...101001111 .......... . . U U . . 13 13
  688. pack 16 mm axy7 1000111101001111 .......... . . U U . . 13 13
  689. pack 16 mm . 1000...101001... .......... . . U U . . 13 13
  690. pea 32 . . 0100100001...... A..DXWLdx. U U U U 6 6 5 5
  691. pflush 32 . . 1111010100011000 .......... . . . S . . . 4 TODO: correct timing
  692. reset 0 . . 0100111001110000 .......... S S S S 0 0 0 0
  693. ror 8 s . 1110...000011... .......... U U U U 6 6 8 8
  694. ror 16 s . 1110...001011... .......... U U U U 6 6 8 8
  695. ror 32 s . 1110...010011... .......... U U U U 8 8 8 8
  696. ror 8 r . 1110...000111... .......... U U U U 6 6 8 8
  697. ror 16 r . 1110...001111... .......... U U U U 6 6 8 8
  698. ror 32 r . 1110...010111... .......... U U U U 8 8 8 8
  699. ror 16 . . 1110011011...... A+-DXWL... U U U U 8 8 7 7
  700. rol 8 s . 1110...100011... .......... U U U U 6 6 8 8
  701. rol 16 s . 1110...101011... .......... U U U U 6 6 8 8
  702. rol 32 s . 1110...110011... .......... U U U U 8 8 8 8
  703. rol 8 r . 1110...100111... .......... U U U U 6 6 8 8
  704. rol 16 r . 1110...101111... .......... U U U U 6 6 8 8
  705. rol 32 r . 1110...110111... .......... U U U U 8 8 8 8
  706. rol 16 . . 1110011111...... A+-DXWL... U U U U 8 8 7 7
  707. roxr 8 s . 1110...000010... .......... U U U U 6 6 12 12
  708. roxr 16 s . 1110...001010... .......... U U U U 6 6 12 12
  709. roxr 32 s . 1110...010010... .......... U U U U 8 8 12 12
  710. roxr 8 r . 1110...000110... .......... U U U U 6 6 12 12
  711. roxr 16 r . 1110...001110... .......... U U U U 6 6 12 12
  712. roxr 32 r . 1110...010110... .......... U U U U 8 8 12 12
  713. roxr 16 . . 1110010011...... A+-DXWL... U U U U 8 8 5 5
  714. roxl 8 s . 1110...100010... .......... U U U U 6 6 12 12
  715. roxl 16 s . 1110...101010... .......... U U U U 6 6 12 12
  716. roxl 32 s . 1110...110010... .......... U U U U 8 8 12 12
  717. roxl 8 r . 1110...100110... .......... U U U U 6 6 12 12
  718. roxl 16 r . 1110...101110... .......... U U U U 6 6 12 12
  719. roxl 32 r . 1110...110110... .......... U U U U 8 8 12 12
  720. roxl 16 . . 1110010111...... A+-DXWL... U U U U 8 8 5 5
  721. rtd 32 . . 0100111001110100 .......... . U U U . 16 10 10
  722. rte 32 . . 0100111001110011 .......... S S S S 20 24 20 20 bus fault not emulated
  723. rtm 32 . . 000001101100.... .......... . . U U . . 19 19 not properly emulated
  724. rtr 32 . . 0100111001110111 .......... U U U U 20 20 14 14
  725. rts 32 . . 0100111001110101 .......... U U U U 16 16 10 10
  726. sbcd 8 rr . 1000...100000... .......... U U U U 6 6 4 4
  727. sbcd 8 mm ax7 1000111100001... .......... U U U U 18 18 16 16
  728. sbcd 8 mm ay7 1000...100001111 .......... U U U U 18 18 16 16
  729. sbcd 8 mm axy7 1000111100001111 .......... U U U U 18 18 16 16
  730. sbcd 8 mm . 1000...100001... .......... U U U U 18 18 16 16
  731. st 8 . d 0101000011000... .......... U U U U 6 4 4 4
  732. st 8 . . 0101000011...... A+-DXWL... U U U U 8 8 6 6
  733. sf 8 . d 0101000111000... .......... U U U U 4 4 4 4
  734. sf 8 . . 0101000111...... A+-DXWL... U U U U 8 8 6 6
  735. scc 8 . d 0101....11000... .......... U U U U 4 4 4 4
  736. scc 8 . . 0101....11...... A+-DXWL... U U U U 8 8 6 6
  737. stop 0 . . 0100111001110010 .......... S S S S 4 4 8 8
  738. sub 8 er d 1001...000000... .......... U U U U 4 4 2 2
  739. sub 8 er . 1001...000...... A+-DXWLdxI U U U U 4 4 2 2
  740. sub 16 er d 1001...001000... .......... U U U U 4 4 2 2
  741. sub 16 er a 1001...001001... .......... U U U U 4 4 2 2
  742. sub 16 er . 1001...001...... A+-DXWLdxI U U U U 4 4 2 2
  743. sub 32 er d 1001...010000... .......... U U U U 6 6 2 2
  744. sub 32 er a 1001...010001... .......... U U U U 6 6 2 2
  745. sub 32 er . 1001...010...... A+-DXWLdxI U U U U 6 6 2 2
  746. sub 8 re . 1001...100...... A+-DXWL... U U U U 8 8 4 4
  747. sub 16 re . 1001...101...... A+-DXWL... U U U U 8 8 4 4
  748. sub 32 re . 1001...110...... A+-DXWL... U U U U 12 12 4 4
  749. suba 16 . d 1001...011000... .......... U U U U 8 8 2 2
  750. suba 16 . a 1001...011001... .......... U U U U 8 8 2 2
  751. suba 16 . . 1001...011...... A+-DXWLdxI U U U U 8 8 2 2
  752. suba 32 . d 1001...111000... .......... U U U U 6 6 2 2
  753. suba 32 . a 1001...111001... .......... U U U U 6 6 2 2
  754. suba 32 . . 1001...111...... A+-DXWLdxI U U U U 6 6 2 2
  755. subi 8 . d 0000010000000... .......... U U U U 8 8 2 2
  756. subi 8 . . 0000010000...... A+-DXWL... U U U U 12 12 4 4
  757. subi 16 . d 0000010001000... .......... U U U U 8 8 2 2
  758. subi 16 . . 0000010001...... A+-DXWL... U U U U 12 12 4 4
  759. subi 32 . d 0000010010000... .......... U U U U 16 14 2 2
  760. subi 32 . . 0000010010...... A+-DXWL... U U U U 20 20 4 4
  761. subq 8 . d 0101...100000... .......... U U U U 4 4 2 2
  762. subq 8 . . 0101...100...... A+-DXWL... U U U U 8 8 4 4
  763. subq 16 . d 0101...101000... .......... U U U U 4 4 2 2
  764. subq 16 . a 0101...101001... .......... U U U U 8 4 2 2
  765. subq 16 . . 0101...101...... A+-DXWL... U U U U 8 8 4 4
  766. subq 32 . d 0101...110000... .......... U U U U 8 8 2 2
  767. subq 32 . a 0101...110001... .......... U U U U 8 8 2 2
  768. subq 32 . . 0101...110...... A+-DXWL... U U U U 12 12 4 4
  769. subx 8 rr . 1001...100000... .......... U U U U 4 4 2 2
  770. subx 16 rr . 1001...101000... .......... U U U U 4 4 2 2
  771. subx 32 rr . 1001...110000... .......... U U U U 8 6 2 2
  772. subx 8 mm ax7 1001111100001... .......... U U U U 18 18 12 12
  773. subx 8 mm ay7 1001...100001111 .......... U U U U 18 18 12 12
  774. subx 8 mm axy7 1001111100001111 .......... U U U U 18 18 12 12
  775. subx 8 mm . 1001...100001... .......... U U U U 18 18 12 12
  776. subx 16 mm . 1001...101001... .......... U U U U 18 18 12 12
  777. subx 32 mm . 1001...110001... .......... U U U U 30 30 12 12
  778. swap 32 . . 0100100001000... .......... U U U U 4 4 4 4
  779. tas 8 . d 0100101011000... .......... U U U U 4 4 4 4
  780. tas 8 . . 0100101011...... A+-DXWL... U U U U 14 14 12 12
  781. trap 0 . . 010011100100.... .......... U U U U 4 4 4 4
  782. trapt 0 . . 0101000011111100 .......... . . U U . . 4 4
  783. trapt 16 . . 0101000011111010 .......... . . U U . . 6 6
  784. trapt 32 . . 0101000011111011 .......... . . U U . . 8 8
  785. trapf 0 . . 0101000111111100 .......... . . U U . . 4 4
  786. trapf 16 . . 0101000111111010 .......... . . U U . . 6 6
  787. trapf 32 . . 0101000111111011 .......... . . U U . . 8 8
  788. trapcc 0 . . 0101....11111100 .......... . . U U . . 4 4
  789. trapcc 16 . . 0101....11111010 .......... . . U U . . 6 6
  790. trapcc 32 . . 0101....11111011 .......... . . U U . . 8 8
  791. trapv 0 . . 0100111001110110 .......... U U U U 4 4 4 4
  792. tst 8 . d 0100101000000... .......... U U U U 4 4 2 2
  793. tst 8 . . 0100101000...... A+-DXWL... U U U U 4 4 2 2
  794. tst 8 . pcdi 0100101000111010 .......... . . U U . . 7 7
  795. tst 8 . pcix 0100101000111011 .......... . . U U . . 9 9
  796. tst 8 . i 0100101000111100 .......... . . U U . . 6 6
  797. tst 16 . d 0100101001000... .......... U U U U 4 4 2 2
  798. tst 16 . a 0100101001001... .......... . . U U . . 2 2
  799. tst 16 . . 0100101001...... A+-DXWL... U U U U 4 4 2 2
  800. tst 16 . pcdi 0100101001111010 .......... . . U U . . 7 7
  801. tst 16 . pcix 0100101001111011 .......... . . U U . . 9 9
  802. tst 16 . i 0100101001111100 .......... . . U U . . 6 6
  803. tst 32 . d 0100101010000... .......... U U U U 4 4 2 2
  804. tst 32 . a 0100101010001... .......... . . U U . . 2 2
  805. tst 32 . . 0100101010...... A+-DXWL... U U U U 4 4 2 2
  806. tst 32 . pcdi 0100101010111010 .......... . . U U . . 7 7
  807. tst 32 . pcix 0100101010111011 .......... . . U U . . 9 9
  808. tst 32 . i 0100101010111100 .......... . . U U . . 6 6
  809. unlk 32 . a7 0100111001011111 .......... U U U U 12 12 6 6
  810. unlk 32 . . 0100111001011... .......... U U U U 12 12 6 6
  811. unpk 16 rr . 1000...110000... .......... . . U U . . 8 8
  812. unpk 16 mm ax7 1000111110001... .......... . . U U . . 13 13
  813. unpk 16 mm ay7 1000...110001111 .......... . . U U . . 13 13
  814. unpk 16 mm axy7 1000111110001111 .......... . . U U . . 13 13
  815. unpk 16 mm . 1000...110001... .......... . . U U . . 13 13
  816. XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  817. M68KMAKE_OPCODE_HANDLER_BODY
  818. M68KMAKE_OP(1010, 0, ., .)
  819. {
  820. m68ki_exception_1010();
  821. }
  822. M68KMAKE_OP(1111, 0, ., .)
  823. {
  824. m68ki_exception_1111();
  825. }
  826. M68KMAKE_OP(040fpu0, 32, ., .)
  827. {
  828. if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  829. {
  830. m68040_fpu_op0();
  831. return;
  832. }
  833. m68ki_exception_1111();
  834. }
  835. M68KMAKE_OP(040fpu1, 32, ., .)
  836. {
  837. if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  838. {
  839. m68040_fpu_op1();
  840. return;
  841. }
  842. m68ki_exception_1111();
  843. }
  844. M68KMAKE_OP(abcd, 8, rr, .)
  845. {
  846. uint* r_dst = &DX;
  847. uint src = DY;
  848. uint dst = *r_dst;
  849. uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
  850. uint corf = 0;
  851. if(res > 9)
  852. corf = 6;
  853. res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
  854. FLAG_V = ~res; /* Undefined V behavior */
  855. res += corf;
  856. FLAG_X = FLAG_C = (res > 0x9f) << 8;
  857. if(FLAG_C)
  858. res -= 0xa0;
  859. FLAG_V &= res; /* Undefined V behavior part II */
  860. FLAG_N = NFLAG_8(res); /* Undefined N behavior */
  861. res = MASK_OUT_ABOVE_8(res);
  862. FLAG_Z |= res;
  863. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  864. }
  865. M68KMAKE_OP(abcd, 8, mm, ax7)
  866. {
  867. uint src = OPER_AY_PD_8();
  868. uint ea = EA_A7_PD_8();
  869. uint dst = m68ki_read_8(ea);
  870. uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
  871. uint corf = 0;
  872. if(res > 9)
  873. corf = 6;
  874. res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
  875. FLAG_V = ~res; /* Undefined V behavior */
  876. res += corf;
  877. FLAG_X = FLAG_C = (res > 0x9f) << 8;
  878. if(FLAG_C)
  879. res -= 0xa0;
  880. FLAG_V &= res; /* Undefined V behavior part II */
  881. FLAG_N = NFLAG_8(res); /* Undefined N behavior */
  882. res = MASK_OUT_ABOVE_8(res);
  883. FLAG_Z |= res;
  884. m68ki_write_8(ea, res);
  885. }
  886. M68KMAKE_OP(abcd, 8, mm, ay7)
  887. {
  888. uint src = OPER_A7_PD_8();
  889. uint ea = EA_AX_PD_8();
  890. uint dst = m68ki_read_8(ea);
  891. uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
  892. uint corf = 0;
  893. if(res > 9)
  894. corf = 6;
  895. res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
  896. FLAG_V = ~res; /* Undefined V behavior */
  897. res += corf;
  898. FLAG_X = FLAG_C = (res > 0x9f) << 8;
  899. if(FLAG_C)
  900. res -= 0xa0;
  901. FLAG_V &= res; /* Undefined V behavior part II */
  902. FLAG_N = NFLAG_8(res); /* Undefined N behavior */
  903. res = MASK_OUT_ABOVE_8(res);
  904. FLAG_Z |= res;
  905. m68ki_write_8(ea, res);
  906. }
  907. M68KMAKE_OP(abcd, 8, mm, axy7)
  908. {
  909. uint src = OPER_A7_PD_8();
  910. uint ea = EA_A7_PD_8();
  911. uint dst = m68ki_read_8(ea);
  912. uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
  913. uint corf = 0;
  914. if(res > 9)
  915. corf = 6;
  916. res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
  917. FLAG_V = ~res; /* Undefined V behavior */
  918. res += corf;
  919. FLAG_X = FLAG_C = (res > 0x9f) << 8;
  920. if(FLAG_C)
  921. res -= 0xa0;
  922. FLAG_V &= res; /* Undefined V behavior part II */
  923. FLAG_N = NFLAG_8(res); /* Undefined N behavior */
  924. res = MASK_OUT_ABOVE_8(res);
  925. FLAG_Z |= res;
  926. m68ki_write_8(ea, res);
  927. }
  928. M68KMAKE_OP(abcd, 8, mm, .)
  929. {
  930. uint src = OPER_AY_PD_8();
  931. uint ea = EA_AX_PD_8();
  932. uint dst = m68ki_read_8(ea);
  933. uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
  934. uint corf = 0;
  935. if(res > 9)
  936. corf = 6;
  937. res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
  938. FLAG_V = ~res; /* Undefined V behavior */
  939. res += corf;
  940. FLAG_X = FLAG_C = (res > 0x9f) << 8;
  941. if(FLAG_C)
  942. res -= 0xa0;
  943. FLAG_V &= res; /* Undefined V behavior part II */
  944. FLAG_N = NFLAG_8(res); /* Undefined N behavior */
  945. res = MASK_OUT_ABOVE_8(res);
  946. FLAG_Z |= res;
  947. m68ki_write_8(ea, res);
  948. }
  949. M68KMAKE_OP(add, 8, er, d)
  950. {
  951. uint* r_dst = &DX;
  952. uint src = MASK_OUT_ABOVE_8(DY);
  953. uint dst = MASK_OUT_ABOVE_8(*r_dst);
  954. uint res = src + dst;
  955. FLAG_N = NFLAG_8(res);
  956. FLAG_V = VFLAG_ADD_8(src, dst, res);
  957. FLAG_X = FLAG_C = CFLAG_8(res);
  958. FLAG_Z = MASK_OUT_ABOVE_8(res);
  959. *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
  960. }
  961. M68KMAKE_OP(add, 8, er, .)
  962. {
  963. uint* r_dst = &DX;
  964. uint src = M68KMAKE_GET_OPER_AY_8;
  965. uint dst = MASK_OUT_ABOVE_8(*r_dst);
  966. uint res = src + dst;
  967. FLAG_N = NFLAG_8(res);
  968. FLAG_V = VFLAG_ADD_8(src, dst, res);
  969. FLAG_X = FLAG_C = CFLAG_8(res);
  970. FLAG_Z = MASK_OUT_ABOVE_8(res);
  971. *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
  972. }
  973. M68KMAKE_OP(add, 16, er, d)
  974. {
  975. uint* r_dst = &DX;
  976. uint src = MASK_OUT_ABOVE_16(DY);
  977. uint dst = MASK_OUT_ABOVE_16(*r_dst);
  978. uint res = src + dst;
  979. FLAG_N = NFLAG_16(res);
  980. FLAG_V = VFLAG_ADD_16(src, dst, res);
  981. FLAG_X = FLAG_C = CFLAG_16(res);
  982. FLAG_Z = MASK_OUT_ABOVE_16(res);
  983. *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
  984. }
  985. M68KMAKE_OP(add, 16, er, a)
  986. {
  987. uint* r_dst = &DX;
  988. uint src = MASK_OUT_ABOVE_16(AY);
  989. uint dst = MASK_OUT_ABOVE_16(*r_dst);
  990. uint res = src + dst;
  991. FLAG_N = NFLAG_16(res);
  992. FLAG_V = VFLAG_ADD_16(src, dst, res);
  993. FLAG_X = FLAG_C = CFLAG_16(res);
  994. FLAG_Z = MASK_OUT_ABOVE_16(res);
  995. *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
  996. }
  997. M68KMAKE_OP(add, 16, er, .)
  998. {
  999. uint* r_dst = &DX;
  1000. uint src = M68KMAKE_GET_OPER_AY_16;
  1001. uint dst = MASK_OUT_ABOVE_16(*r_dst);
  1002. uint res = src + dst;
  1003. FLAG_N = NFLAG_16(res);
  1004. FLAG_V = VFLAG_ADD_16(src, dst, res);
  1005. FLAG_X = FLAG_C = CFLAG_16(res);
  1006. FLAG_Z = MASK_OUT_ABOVE_16(res);
  1007. *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
  1008. }
  1009. M68KMAKE_OP(add, 32, er, d)
  1010. {
  1011. uint* r_dst = &DX;
  1012. uint src = DY;
  1013. uint dst = *r_dst;
  1014. uint res = src + dst;
  1015. FLAG_N = NFLAG_32(res);
  1016. FLAG_V = VFLAG_ADD_32(src, dst, res);
  1017. FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
  1018. FLAG_Z = MASK_OUT_ABOVE_32(res);
  1019. *r_dst = FLAG_Z;
  1020. }
  1021. M68KMAKE_OP(add, 32, er, a)
  1022. {
  1023. uint* r_dst = &DX;
  1024. uint src = AY;
  1025. uint dst = *r_dst;
  1026. uint res = src + dst;
  1027. FLAG_N = NFLAG_32(res);
  1028. FLAG_V = VFLAG_ADD_32(src, dst, res);
  1029. FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
  1030. FLAG_Z = MASK_OUT_ABOVE_32(res);
  1031. *r_dst = FLAG_Z;
  1032. }
  1033. M68KMAKE_OP(add, 32, er, .)
  1034. {
  1035. uint* r_dst = &DX;
  1036. uint src = M68KMAKE_GET_OPER_AY_32;
  1037. uint dst = *r_dst;
  1038. uint res = src + dst;
  1039. FLAG_N = NFLAG_32(res);
  1040. FLAG_V = VFLAG_ADD_32(src, dst, res);
  1041. FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
  1042. FLAG_Z = MASK_OUT_ABOVE_32(res);
  1043. *r_dst = FLAG_Z;
  1044. }
  1045. M68KMAKE_OP(add, 8, re, .)
  1046. {
  1047. uint ea = M68KMAKE_GET_EA_AY_8;
  1048. uint src = MASK_OUT_ABOVE_8(DX);
  1049. uint dst = m68ki_read_8(ea);
  1050. uint res = src + dst;
  1051. FLAG_N = NFLAG_8(res);
  1052. FLAG_V = VFLAG_ADD_8(src, dst, res);
  1053. FLAG_X = FLAG_C = CFLAG_8(res);
  1054. FLAG_Z = MASK_OUT_ABOVE_8(res);
  1055. m68ki_write_8(ea, FLAG_Z);
  1056. }
  1057. M68KMAKE_OP(add, 16, re, .)
  1058. {
  1059. uint ea = M68KMAKE_GET_EA_AY_16;
  1060. uint src = MASK_OUT_ABOVE_16(DX);
  1061. uint dst = m68ki_read_16(ea);
  1062. uint res = src + dst;
  1063. FLAG_N = NFLAG_16(res);
  1064. FLAG_V = VFLAG_ADD_16(src, dst, res);
  1065. FLAG_X = FLAG_C = CFLAG_16(res);
  1066. FLAG_Z = MASK_OUT_ABOVE_16(res);
  1067. m68ki_write_16(ea, FLAG_Z);
  1068. }
  1069. M68KMAKE_OP(add, 32, re, .)
  1070. {
  1071. uint ea = M68KMAKE_GET_EA_AY_32;
  1072. uint src = DX;
  1073. uint dst = m68ki_read_32(ea);
  1074. uint res = src + dst;
  1075. FLAG_N = NFLAG_32(res);
  1076. FLAG_V = VFLAG_ADD_32(src, dst, res);
  1077. FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
  1078. FLAG_Z = MASK_OUT_ABOVE_32(res);
  1079. m68ki_write_32(ea, FLAG_Z);
  1080. }
  1081. M68KMAKE_OP(adda, 16, ., d)
  1082. {
  1083. uint* r_dst = &AX;
  1084. *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY));
  1085. }
  1086. M68KMAKE_OP(adda, 16, ., a)
  1087. {
  1088. uint* r_dst = &AX;
  1089. *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY));
  1090. }
  1091. M68KMAKE_OP(adda, 16, ., .)
  1092. {
  1093. uint* r_dst = &AX;
  1094. uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
  1095. *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
  1096. }
  1097. M68KMAKE_OP(adda, 32, ., d)
  1098. {
  1099. uint* r_dst = &AX;
  1100. *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY);
  1101. }
  1102. M68KMAKE_OP(adda, 32, ., a)
  1103. {
  1104. uint* r_dst = &AX;
  1105. *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY);
  1106. }
  1107. M68KMAKE_OP(adda, 32, ., .)
  1108. {
  1109. uint* r_dst = &AX;
  1110. uint src = M68KMAKE_GET_OPER_AY_32; // notaz
  1111. *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
  1112. }
  1113. M68KMAKE_OP(addi, 8, ., d)
  1114. {
  1115. uint* r_dst = &DY;
  1116. uint src = OPER_I_8();
  1117. uint dst = MASK_OUT_ABOVE_8(*r_dst);
  1118. uint res = src + dst;
  1119. FLAG_N = NFLAG_8(res);
  1120. FLAG_V = VFLAG_ADD_8(src, dst, res);
  1121. FLAG_X = FLAG_C = CFLAG_8(res);
  1122. FLAG_Z = MASK_OUT_ABOVE_8(res);
  1123. *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
  1124. }
  1125. M68KMAKE_OP(addi, 8, ., .)
  1126. {
  1127. uint src = OPER_I_8();
  1128. uint ea = M68KMAKE_GET_EA_AY_8;
  1129. uint dst = m68ki_read_8(ea);
  1130. uint res = src + dst;
  1131. FLAG_N = NFLAG_8(res);
  1132. FLAG_V = VFLAG_ADD_8(src, dst, res);
  1133. FLAG_X = FLAG_C = CFLAG_8(res);
  1134. FLAG_Z = MASK_OUT_ABOVE_8(res);
  1135. m68ki_write_8(ea, FLAG_Z);
  1136. }
  1137. M68KMAKE_OP(addi, 16, ., d)
  1138. {
  1139. uint* r_dst = &DY;
  1140. uint src = OPER_I_16();
  1141. uint dst = MASK_OUT_ABOVE_16(*r_dst);
  1142. uint res = src + dst;
  1143. FLAG_N = NFLAG_16(res);
  1144. FLAG_V = VFLAG_ADD_16(src, dst, res);
  1145. FLAG_X = FLAG_C = CFLAG_16(res);
  1146. FLAG_Z = MASK_OUT_ABOVE_16(res);
  1147. *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
  1148. }
  1149. M68KMAKE_OP(addi, 16, ., .)
  1150. {
  1151. uint src = OPER_I_16();
  1152. uint ea = M68KMAKE_GET_EA_AY_16;
  1153. uint dst = m68ki_read_16(ea);
  1154. uint res = src + dst;
  1155. FLAG_N = NFLAG_16(res);
  1156. FLAG_V = VFLAG_ADD_16(src, dst, res);
  1157. FLAG_X = FLAG_C = CFLAG_16(res);
  1158. FLAG_Z = MASK_OUT_ABOVE_16(res);
  1159. m68ki_write_16(ea, FLAG_Z);
  1160. }
  1161. M68KMAKE_OP(addi, 32, ., d)
  1162. {
  1163. uint* r_dst = &DY;
  1164. uint src = OPER_I_32();
  1165. uint dst = *r_dst;
  1166. uint res = src + dst;
  1167. FLAG_N = NFLAG_32(res);
  1168. FLAG_V = VFLAG_ADD_32(src, dst, res);
  1169. FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
  1170. FLAG_Z = MASK_OUT_ABOVE_32(res);
  1171. *r_dst = FLAG_Z;
  1172. }
  1173. M68KMAKE_OP(addi, 32, ., .)
  1174. {
  1175. uint src = OPER_I_32();
  1176. uint ea = M68KMAKE_GET_EA_AY_32;
  1177. uint dst = m68ki_read_32(ea);
  1178. uint res = src + dst;
  1179. FLAG_N = NFLAG_32(res);
  1180. FLAG_V = VFLAG_ADD_32(src, dst, res);
  1181. FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
  1182. FLAG_Z = MASK_OUT_ABOVE_32(res);
  1183. m68ki_write_32(ea, FLAG_Z);
  1184. }
  1185. M68KMAKE_OP(addq, 8, ., d)
  1186. {
  1187. uint* r_dst = &DY;
  1188. uint src = (((REG_IR >> 9) - 1) & 7) + 1;
  1189. uint dst = MASK_OUT_ABOVE_8(*r_dst);
  1190. uint res = src + dst;
  1191. FLAG_N = NFLAG_8(res);
  1192. FLAG_V = VFLAG_ADD_8(src, dst, res);
  1193. FLAG_X = FLAG_C = CFLAG_8(res);
  1194. FLAG_Z = MASK_OUT_ABOVE_8(res);
  1195. *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
  1196. }
  1197. M68KMAKE_OP(addq, 8, ., .)
  1198. {
  1199. uint src = (((REG_IR >> 9) - 1) & 7) + 1;
  1200. uint ea = M68KMAKE_GET_EA_AY_8;
  1201. uint dst = m68ki_read_8(ea);
  1202. uint res = src + dst;
  1203. FLAG_N = NFLAG_8(res);
  1204. FLAG_V = VFLAG_ADD_8(src, dst, res);
  1205. FLAG_X = FLAG_C = CFLAG_8(res);
  1206. FLAG_Z = MASK_OUT_ABOVE_8(res);
  1207. m68ki_write_8(ea, FLAG_Z);
  1208. }
  1209. M68KMAKE_OP(addq, 16, ., d)
  1210. {
  1211. uint* r_dst = &DY;
  1212. uint src = (((REG_IR >> 9) - 1) & 7) + 1;
  1213. uint dst = MASK_OUT_ABOVE_16(*r_dst);
  1214. uint res = src + dst;
  1215. FLAG_N = NFLAG_16(res);
  1216. FLAG_V = VFLAG_ADD_16(src, dst, res);
  1217. FLAG_X = FLAG_C = CFLAG_16(res);
  1218. FLAG_Z = MASK_OUT_ABOVE_16(res);
  1219. *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
  1220. }
  1221. M68KMAKE_OP(addq, 16, ., a)
  1222. {
  1223. uint* r_dst = &AY;
  1224. *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
  1225. }
  1226. M68KMAKE_OP(addq, 16, ., .)
  1227. {
  1228. uint src = (((REG_IR >> 9) - 1) & 7) + 1;
  1229. uint ea = M68KMAKE_GET_EA_AY_16;
  1230. uint dst = m68ki_read_16(ea);
  1231. uint res = src + dst;
  1232. FLAG_N = NFLAG_16(res);
  1233. FLAG_V = VFLAG_ADD_16(src, dst, res);
  1234. FLAG_X = FLAG_C = CFLAG_16(res);
  1235. FLAG_Z = MASK_OUT_ABOVE_16(res);
  1236. m68ki_write_16(ea, FLAG_Z);
  1237. }
  1238. M68KMAKE_OP(addq, 32, ., d)
  1239. {
  1240. uint* r_dst = &DY;
  1241. uint src = (((REG_IR >> 9) - 1) & 7) + 1;
  1242. uint dst = *r_dst;
  1243. uint res = src + dst;
  1244. FLAG_N = NFLAG_32(res);
  1245. FLAG_V = VFLAG_ADD_32(src, dst, res);
  1246. FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
  1247. FLAG_Z = MASK_OUT_ABOVE_32(res);
  1248. *r_dst = FLAG_Z;
  1249. }
  1250. M68KMAKE_OP(addq, 32, ., a)
  1251. {
  1252. uint* r_dst = &AY;
  1253. *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
  1254. }
  1255. M68KMAKE_OP(addq, 32, ., .)
  1256. {
  1257. uint src = (((REG_IR >> 9) - 1) & 7) + 1;
  1258. uint ea = M68KMAKE_GET_EA_AY_32;
  1259. uint dst = m68ki_read_32(ea);
  1260. uint res = src + dst;
  1261. FLAG_N = NFLAG_32(res);
  1262. FLAG_V = VFLAG_ADD_32(src, dst, res);
  1263. FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
  1264. FLAG_Z = MASK_OUT_ABOVE_32(res);
  1265. m68ki_write_32(ea, FLAG_Z);
  1266. }
  1267. M68KMAKE_OP(addx, 8, rr, .)
  1268. {
  1269. uint* r_dst = &DX;
  1270. uint src = MASK_OUT_ABOVE_8(DY);
  1271. uint dst = MASK_OUT_ABOVE_8(*r_dst);
  1272. uint res = src + dst + XFLAG_AS_1();
  1273. FLAG_N = NFLAG_8(res);
  1274. FLAG_V = VFLAG_ADD_8(src, dst, res);
  1275. FLAG_X = FLAG_C = CFLAG_8(res);
  1276. res = MASK_OUT_ABOVE_8(res);
  1277. FLAG_Z |= res;
  1278. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  1279. }
  1280. M68KMAKE_OP(addx, 16, rr, .)
  1281. {
  1282. uint* r_dst = &DX;
  1283. uint src = MASK_OUT_ABOVE_16(DY);
  1284. uint dst = MASK_OUT_ABOVE_16(*r_dst);
  1285. uint res = src + dst + XFLAG_AS_1();
  1286. FLAG_N = NFLAG_16(res);
  1287. FLAG_V = VFLAG_ADD_16(src, dst, res);
  1288. FLAG_X = FLAG_C = CFLAG_16(res);
  1289. res = MASK_OUT_ABOVE_16(res);
  1290. FLAG_Z |= res;
  1291. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  1292. }
  1293. M68KMAKE_OP(addx, 32, rr, .)
  1294. {
  1295. uint* r_dst = &DX;
  1296. uint src = DY;
  1297. uint dst = *r_dst;
  1298. uint res = src + dst + XFLAG_AS_1();
  1299. FLAG_N = NFLAG_32(res);
  1300. FLAG_V = VFLAG_ADD_32(src, dst, res);
  1301. FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
  1302. res = MASK_OUT_ABOVE_32(res);
  1303. FLAG_Z |= res;
  1304. *r_dst = res;
  1305. }
  1306. M68KMAKE_OP(addx, 8, mm, ax7)
  1307. {
  1308. uint src = OPER_AY_PD_8();
  1309. uint ea = EA_A7_PD_8();
  1310. uint dst = m68ki_read_8(ea);
  1311. uint res = src + dst + XFLAG_AS_1();
  1312. FLAG_N = NFLAG_8(res);
  1313. FLAG_V = VFLAG_ADD_8(src, dst, res);
  1314. FLAG_X = FLAG_C = CFLAG_8(res);
  1315. res = MASK_OUT_ABOVE_8(res);
  1316. FLAG_Z |= res;
  1317. m68ki_write_8(ea, res);
  1318. }
  1319. M68KMAKE_OP(addx, 8, mm, ay7)
  1320. {
  1321. uint src = OPER_A7_PD_8();
  1322. uint ea = EA_AX_PD_8();
  1323. uint dst = m68ki_read_8(ea);
  1324. uint res = src + dst + XFLAG_AS_1();
  1325. FLAG_N = NFLAG_8(res);
  1326. FLAG_V = VFLAG_ADD_8(src, dst, res);
  1327. FLAG_X = FLAG_C = CFLAG_8(res);
  1328. res = MASK_OUT_ABOVE_8(res);
  1329. FLAG_Z |= res;
  1330. m68ki_write_8(ea, res);
  1331. }
  1332. M68KMAKE_OP(addx, 8, mm, axy7)
  1333. {
  1334. uint src = OPER_A7_PD_8();
  1335. uint ea = EA_A7_PD_8();
  1336. uint dst = m68ki_read_8(ea);
  1337. uint res = src + dst + XFLAG_AS_1();
  1338. FLAG_N = NFLAG_8(res);
  1339. FLAG_V = VFLAG_ADD_8(src, dst, res);
  1340. FLAG_X = FLAG_C = CFLAG_8(res);
  1341. res = MASK_OUT_ABOVE_8(res);
  1342. FLAG_Z |= res;
  1343. m68ki_write_8(ea, res);
  1344. }
  1345. M68KMAKE_OP(addx, 8, mm, .)
  1346. {
  1347. uint src = OPER_AY_PD_8();
  1348. uint ea = EA_AX_PD_8();
  1349. uint dst = m68ki_read_8(ea);
  1350. uint res = src + dst + XFLAG_AS_1();
  1351. FLAG_N = NFLAG_8(res);
  1352. FLAG_V = VFLAG_ADD_8(src, dst, res);
  1353. FLAG_X = FLAG_C = CFLAG_8(res);
  1354. res = MASK_OUT_ABOVE_8(res);
  1355. FLAG_Z |= res;
  1356. m68ki_write_8(ea, res);
  1357. }
  1358. M68KMAKE_OP(addx, 16, mm, .)
  1359. {
  1360. uint src = OPER_AY_PD_16();
  1361. uint ea = EA_AX_PD_16();
  1362. uint dst = m68ki_read_16(ea);
  1363. uint res = src + dst + XFLAG_AS_1();
  1364. FLAG_N = NFLAG_16(res);
  1365. FLAG_V = VFLAG_ADD_16(src, dst, res);
  1366. FLAG_X = FLAG_C = CFLAG_16(res);
  1367. res = MASK_OUT_ABOVE_16(res);
  1368. FLAG_Z |= res;
  1369. m68ki_write_16(ea, res);
  1370. }
  1371. M68KMAKE_OP(addx, 32, mm, .)
  1372. {
  1373. uint src = OPER_AY_PD_32();
  1374. uint ea = EA_AX_PD_32();
  1375. uint dst = m68ki_read_32(ea);
  1376. uint res = src + dst + XFLAG_AS_1();
  1377. FLAG_N = NFLAG_32(res);
  1378. FLAG_V = VFLAG_ADD_32(src, dst, res);
  1379. FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
  1380. res = MASK_OUT_ABOVE_32(res);
  1381. FLAG_Z |= res;
  1382. m68ki_write_32(ea, res);
  1383. }
  1384. M68KMAKE_OP(and, 8, er, d)
  1385. {
  1386. FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00));
  1387. FLAG_N = NFLAG_8(FLAG_Z);
  1388. FLAG_C = CFLAG_CLEAR;
  1389. FLAG_V = VFLAG_CLEAR;
  1390. }
  1391. M68KMAKE_OP(and, 8, er, .)
  1392. {
  1393. FLAG_Z = MASK_OUT_ABOVE_8(DX &= (M68KMAKE_GET_OPER_AY_8 | 0xffffff00));
  1394. FLAG_N = NFLAG_8(FLAG_Z);
  1395. FLAG_C = CFLAG_CLEAR;
  1396. FLAG_V = VFLAG_CLEAR;
  1397. }
  1398. M68KMAKE_OP(and, 16, er, d)
  1399. {
  1400. FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000));
  1401. FLAG_N = NFLAG_16(FLAG_Z);
  1402. FLAG_C = CFLAG_CLEAR;
  1403. FLAG_V = VFLAG_CLEAR;
  1404. }
  1405. M68KMAKE_OP(and, 16, er, .)
  1406. {
  1407. FLAG_Z = MASK_OUT_ABOVE_16(DX &= (M68KMAKE_GET_OPER_AY_16 | 0xffff0000));
  1408. FLAG_N = NFLAG_16(FLAG_Z);
  1409. FLAG_C = CFLAG_CLEAR;
  1410. FLAG_V = VFLAG_CLEAR;
  1411. }
  1412. M68KMAKE_OP(and, 32, er, d)
  1413. {
  1414. FLAG_Z = DX &= DY;
  1415. FLAG_N = NFLAG_32(FLAG_Z);
  1416. FLAG_C = CFLAG_CLEAR;
  1417. FLAG_V = VFLAG_CLEAR;
  1418. }
  1419. M68KMAKE_OP(and, 32, er, .)
  1420. {
  1421. FLAG_Z = DX &= M68KMAKE_GET_OPER_AY_32;
  1422. FLAG_N = NFLAG_32(FLAG_Z);
  1423. FLAG_C = CFLAG_CLEAR;
  1424. FLAG_V = VFLAG_CLEAR;
  1425. }
  1426. M68KMAKE_OP(and, 8, re, .)
  1427. {
  1428. uint ea = M68KMAKE_GET_EA_AY_8;
  1429. uint res = DX & m68ki_read_8(ea);
  1430. FLAG_N = NFLAG_8(res);
  1431. FLAG_C = CFLAG_CLEAR;
  1432. FLAG_V = VFLAG_CLEAR;
  1433. FLAG_Z = MASK_OUT_ABOVE_8(res);
  1434. m68ki_write_8(ea, FLAG_Z);
  1435. }
  1436. M68KMAKE_OP(and, 16, re, .)
  1437. {
  1438. uint ea = M68KMAKE_GET_EA_AY_16;
  1439. uint res = DX & m68ki_read_16(ea);
  1440. FLAG_N = NFLAG_16(res);
  1441. FLAG_C = CFLAG_CLEAR;
  1442. FLAG_V = VFLAG_CLEAR;
  1443. FLAG_Z = MASK_OUT_ABOVE_16(res);
  1444. m68ki_write_16(ea, FLAG_Z);
  1445. }
  1446. M68KMAKE_OP(and, 32, re, .)
  1447. {
  1448. uint ea = M68KMAKE_GET_EA_AY_32;
  1449. uint res = DX & m68ki_read_32(ea);
  1450. FLAG_N = NFLAG_32(res);
  1451. FLAG_Z = res;
  1452. FLAG_C = CFLAG_CLEAR;
  1453. FLAG_V = VFLAG_CLEAR;
  1454. m68ki_write_32(ea, res);
  1455. }
  1456. M68KMAKE_OP(andi, 8, ., d)
  1457. {
  1458. FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00));
  1459. FLAG_N = NFLAG_8(FLAG_Z);
  1460. FLAG_C = CFLAG_CLEAR;
  1461. FLAG_V = VFLAG_CLEAR;
  1462. }
  1463. M68KMAKE_OP(andi, 8, ., .)
  1464. {
  1465. uint src = OPER_I_8();
  1466. uint ea = M68KMAKE_GET_EA_AY_8;
  1467. uint res = src & m68ki_read_8(ea);
  1468. FLAG_N = NFLAG_8(res);
  1469. FLAG_Z = res;
  1470. FLAG_C = CFLAG_CLEAR;
  1471. FLAG_V = VFLAG_CLEAR;
  1472. m68ki_write_8(ea, res);
  1473. }
  1474. M68KMAKE_OP(andi, 16, ., d)
  1475. {
  1476. FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000));
  1477. FLAG_N = NFLAG_16(FLAG_Z);
  1478. FLAG_C = CFLAG_CLEAR;
  1479. FLAG_V = VFLAG_CLEAR;
  1480. }
  1481. M68KMAKE_OP(andi, 16, ., .)
  1482. {
  1483. uint src = OPER_I_16();
  1484. uint ea = M68KMAKE_GET_EA_AY_16;
  1485. uint res = src & m68ki_read_16(ea);
  1486. FLAG_N = NFLAG_16(res);
  1487. FLAG_Z = res;
  1488. FLAG_C = CFLAG_CLEAR;
  1489. FLAG_V = VFLAG_CLEAR;
  1490. m68ki_write_16(ea, res);
  1491. }
  1492. M68KMAKE_OP(andi, 32, ., d)
  1493. {
  1494. FLAG_Z = DY &= (OPER_I_32());
  1495. FLAG_N = NFLAG_32(FLAG_Z);
  1496. FLAG_C = CFLAG_CLEAR;
  1497. FLAG_V = VFLAG_CLEAR;
  1498. }
  1499. M68KMAKE_OP(andi, 32, ., .)
  1500. {
  1501. uint src = OPER_I_32();
  1502. uint ea = M68KMAKE_GET_EA_AY_32;
  1503. uint res = src & m68ki_read_32(ea);
  1504. FLAG_N = NFLAG_32(res);
  1505. FLAG_Z = res;
  1506. FLAG_C = CFLAG_CLEAR;
  1507. FLAG_V = VFLAG_CLEAR;
  1508. m68ki_write_32(ea, res);
  1509. }
  1510. M68KMAKE_OP(andi, 16, toc, .)
  1511. {
  1512. m68ki_set_ccr(m68ki_get_ccr() & OPER_I_16());
  1513. }
  1514. M68KMAKE_OP(andi, 16, tos, .)
  1515. {
  1516. if(FLAG_S)
  1517. {
  1518. uint src = OPER_I_16();
  1519. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  1520. m68ki_set_sr(m68ki_get_sr() & src);
  1521. return;
  1522. }
  1523. m68ki_exception_privilege_violation();
  1524. }
  1525. M68KMAKE_OP(asr, 8, s, .)
  1526. {
  1527. uint* r_dst = &DY;
  1528. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  1529. uint src = MASK_OUT_ABOVE_8(*r_dst);
  1530. uint res = src >> shift;
  1531. if(shift != 0)
  1532. USE_CYCLES(shift<<CYC_SHIFT);
  1533. if(GET_MSB_8(src))
  1534. res |= m68ki_shift_8_table[shift];
  1535. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  1536. FLAG_N = NFLAG_8(res);
  1537. FLAG_Z = res;
  1538. FLAG_V = VFLAG_CLEAR;
  1539. FLAG_X = FLAG_C = src << (9-shift);
  1540. }
  1541. M68KMAKE_OP(asr, 16, s, .)
  1542. {
  1543. uint* r_dst = &DY;
  1544. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  1545. uint src = MASK_OUT_ABOVE_16(*r_dst);
  1546. uint res = src >> shift;
  1547. if(shift != 0)
  1548. USE_CYCLES(shift<<CYC_SHIFT);
  1549. if(GET_MSB_16(src))
  1550. res |= m68ki_shift_16_table[shift];
  1551. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  1552. FLAG_N = NFLAG_16(res);
  1553. FLAG_Z = res;
  1554. FLAG_V = VFLAG_CLEAR;
  1555. FLAG_X = FLAG_C = src << (9-shift);
  1556. }
  1557. M68KMAKE_OP(asr, 32, s, .)
  1558. {
  1559. uint* r_dst = &DY;
  1560. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  1561. uint src = *r_dst;
  1562. uint res = src >> shift;
  1563. if(shift != 0)
  1564. USE_CYCLES(shift<<CYC_SHIFT);
  1565. if(GET_MSB_32(src))
  1566. res |= m68ki_shift_32_table[shift];
  1567. *r_dst = res;
  1568. FLAG_N = NFLAG_32(res);
  1569. FLAG_Z = res;
  1570. FLAG_V = VFLAG_CLEAR;
  1571. FLAG_X = FLAG_C = src << (9-shift);
  1572. }
  1573. M68KMAKE_OP(asr, 8, r, .)
  1574. {
  1575. uint* r_dst = &DY;
  1576. uint shift = DX & 0x3f;
  1577. uint src = MASK_OUT_ABOVE_8(*r_dst);
  1578. uint res = src >> shift;
  1579. if(shift != 0)
  1580. {
  1581. USE_CYCLES(shift<<CYC_SHIFT);
  1582. if(shift < 8)
  1583. {
  1584. if(GET_MSB_8(src))
  1585. res |= m68ki_shift_8_table[shift];
  1586. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  1587. FLAG_X = FLAG_C = src << (9-shift);
  1588. FLAG_N = NFLAG_8(res);
  1589. FLAG_Z = res;
  1590. FLAG_V = VFLAG_CLEAR;
  1591. return;
  1592. }
  1593. if(GET_MSB_8(src))
  1594. {
  1595. *r_dst |= 0xff;
  1596. FLAG_C = CFLAG_SET;
  1597. FLAG_X = XFLAG_SET;
  1598. FLAG_N = NFLAG_SET;
  1599. FLAG_Z = ZFLAG_CLEAR;
  1600. FLAG_V = VFLAG_CLEAR;
  1601. return;
  1602. }
  1603. *r_dst &= 0xffffff00;
  1604. FLAG_C = CFLAG_CLEAR;
  1605. FLAG_X = XFLAG_CLEAR;
  1606. FLAG_N = NFLAG_CLEAR;
  1607. FLAG_Z = ZFLAG_SET;
  1608. FLAG_V = VFLAG_CLEAR;
  1609. return;
  1610. }
  1611. FLAG_C = CFLAG_CLEAR;
  1612. FLAG_N = NFLAG_8(src);
  1613. FLAG_Z = src;
  1614. FLAG_V = VFLAG_CLEAR;
  1615. }
  1616. M68KMAKE_OP(asr, 16, r, .)
  1617. {
  1618. uint* r_dst = &DY;
  1619. uint shift = DX & 0x3f;
  1620. uint src = MASK_OUT_ABOVE_16(*r_dst);
  1621. uint res = src >> shift;
  1622. if(shift != 0)
  1623. {
  1624. USE_CYCLES(shift<<CYC_SHIFT);
  1625. if(shift < 16)
  1626. {
  1627. if(GET_MSB_16(src))
  1628. res |= m68ki_shift_16_table[shift];
  1629. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  1630. FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
  1631. FLAG_N = NFLAG_16(res);
  1632. FLAG_Z = res;
  1633. FLAG_V = VFLAG_CLEAR;
  1634. return;
  1635. }
  1636. if(GET_MSB_16(src))
  1637. {
  1638. *r_dst |= 0xffff;
  1639. FLAG_C = CFLAG_SET;
  1640. FLAG_X = XFLAG_SET;
  1641. FLAG_N = NFLAG_SET;
  1642. FLAG_Z = ZFLAG_CLEAR;
  1643. FLAG_V = VFLAG_CLEAR;
  1644. return;
  1645. }
  1646. *r_dst &= 0xffff0000;
  1647. FLAG_C = CFLAG_CLEAR;
  1648. FLAG_X = XFLAG_CLEAR;
  1649. FLAG_N = NFLAG_CLEAR;
  1650. FLAG_Z = ZFLAG_SET;
  1651. FLAG_V = VFLAG_CLEAR;
  1652. return;
  1653. }
  1654. FLAG_C = CFLAG_CLEAR;
  1655. FLAG_N = NFLAG_16(src);
  1656. FLAG_Z = src;
  1657. FLAG_V = VFLAG_CLEAR;
  1658. }
  1659. M68KMAKE_OP(asr, 32, r, .)
  1660. {
  1661. uint* r_dst = &DY;
  1662. uint shift = DX & 0x3f;
  1663. uint src = *r_dst;
  1664. uint res = src >> shift;
  1665. if(shift != 0)
  1666. {
  1667. USE_CYCLES(shift<<CYC_SHIFT);
  1668. if(shift < 32)
  1669. {
  1670. if(GET_MSB_32(src))
  1671. res |= m68ki_shift_32_table[shift];
  1672. *r_dst = res;
  1673. FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
  1674. FLAG_N = NFLAG_32(res);
  1675. FLAG_Z = res;
  1676. FLAG_V = VFLAG_CLEAR;
  1677. return;
  1678. }
  1679. if(GET_MSB_32(src))
  1680. {
  1681. *r_dst = 0xffffffff;
  1682. FLAG_C = CFLAG_SET;
  1683. FLAG_X = XFLAG_SET;
  1684. FLAG_N = NFLAG_SET;
  1685. FLAG_Z = ZFLAG_CLEAR;
  1686. FLAG_V = VFLAG_CLEAR;
  1687. return;
  1688. }
  1689. *r_dst = 0;
  1690. FLAG_C = CFLAG_CLEAR;
  1691. FLAG_X = XFLAG_CLEAR;
  1692. FLAG_N = NFLAG_CLEAR;
  1693. FLAG_Z = ZFLAG_SET;
  1694. FLAG_V = VFLAG_CLEAR;
  1695. return;
  1696. }
  1697. FLAG_C = CFLAG_CLEAR;
  1698. FLAG_N = NFLAG_32(src);
  1699. FLAG_Z = src;
  1700. FLAG_V = VFLAG_CLEAR;
  1701. }
  1702. M68KMAKE_OP(asr, 16, ., .)
  1703. {
  1704. uint ea = M68KMAKE_GET_EA_AY_16;
  1705. uint src = m68ki_read_16(ea);
  1706. uint res = src >> 1;
  1707. if(GET_MSB_16(src))
  1708. res |= 0x8000;
  1709. m68ki_write_16(ea, res);
  1710. FLAG_N = NFLAG_16(res);
  1711. FLAG_Z = res;
  1712. FLAG_V = VFLAG_CLEAR;
  1713. FLAG_C = FLAG_X = src << 8;
  1714. }
  1715. M68KMAKE_OP(asl, 8, s, .)
  1716. {
  1717. uint* r_dst = &DY;
  1718. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  1719. uint src = MASK_OUT_ABOVE_8(*r_dst);
  1720. uint res = MASK_OUT_ABOVE_8(src << shift);
  1721. if(shift != 0)
  1722. USE_CYCLES(shift<<CYC_SHIFT);
  1723. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  1724. FLAG_X = FLAG_C = src << shift;
  1725. FLAG_N = NFLAG_8(res);
  1726. FLAG_Z = res;
  1727. src &= m68ki_shift_8_table[shift + 1];
  1728. FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7;
  1729. }
  1730. M68KMAKE_OP(asl, 16, s, .)
  1731. {
  1732. uint* r_dst = &DY;
  1733. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  1734. uint src = MASK_OUT_ABOVE_16(*r_dst);
  1735. uint res = MASK_OUT_ABOVE_16(src << shift);
  1736. if(shift != 0)
  1737. USE_CYCLES(shift<<CYC_SHIFT);
  1738. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  1739. FLAG_N = NFLAG_16(res);
  1740. FLAG_Z = res;
  1741. FLAG_X = FLAG_C = src >> (8-shift);
  1742. src &= m68ki_shift_16_table[shift + 1];
  1743. FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
  1744. }
  1745. M68KMAKE_OP(asl, 32, s, .)
  1746. {
  1747. uint* r_dst = &DY;
  1748. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  1749. uint src = *r_dst;
  1750. uint res = MASK_OUT_ABOVE_32(src << shift);
  1751. if(shift != 0)
  1752. USE_CYCLES(shift<<CYC_SHIFT);
  1753. *r_dst = res;
  1754. FLAG_N = NFLAG_32(res);
  1755. FLAG_Z = res;
  1756. FLAG_X = FLAG_C = src >> (24-shift);
  1757. src &= m68ki_shift_32_table[shift + 1];
  1758. FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
  1759. }
  1760. M68KMAKE_OP(asl, 8, r, .)
  1761. {
  1762. uint* r_dst = &DY;
  1763. uint shift = DX & 0x3f;
  1764. uint src = MASK_OUT_ABOVE_8(*r_dst);
  1765. uint res = MASK_OUT_ABOVE_8(src << shift);
  1766. if(shift != 0)
  1767. {
  1768. USE_CYCLES(shift<<CYC_SHIFT);
  1769. if(shift < 8)
  1770. {
  1771. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  1772. FLAG_X = FLAG_C = src << shift;
  1773. FLAG_N = NFLAG_8(res);
  1774. FLAG_Z = res;
  1775. src &= m68ki_shift_8_table[shift + 1];
  1776. FLAG_V = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7;
  1777. return;
  1778. }
  1779. *r_dst &= 0xffffff00;
  1780. FLAG_X = FLAG_C = ((shift == 8 ? src & 1 : 0))<<8;
  1781. FLAG_N = NFLAG_CLEAR;
  1782. FLAG_Z = ZFLAG_SET;
  1783. FLAG_V = (!(src == 0))<<7;
  1784. return;
  1785. }
  1786. FLAG_C = CFLAG_CLEAR;
  1787. FLAG_N = NFLAG_8(src);
  1788. FLAG_Z = src;
  1789. FLAG_V = VFLAG_CLEAR;
  1790. }
  1791. M68KMAKE_OP(asl, 16, r, .)
  1792. {
  1793. uint* r_dst = &DY;
  1794. uint shift = DX & 0x3f;
  1795. uint src = MASK_OUT_ABOVE_16(*r_dst);
  1796. uint res = MASK_OUT_ABOVE_16(src << shift);
  1797. if(shift != 0)
  1798. {
  1799. USE_CYCLES(shift<<CYC_SHIFT);
  1800. if(shift < 16)
  1801. {
  1802. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  1803. FLAG_X = FLAG_C = (src << shift) >> 8;
  1804. FLAG_N = NFLAG_16(res);
  1805. FLAG_Z = res;
  1806. src &= m68ki_shift_16_table[shift + 1];
  1807. FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
  1808. return;
  1809. }
  1810. *r_dst &= 0xffff0000;
  1811. FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8;
  1812. FLAG_N = NFLAG_CLEAR;
  1813. FLAG_Z = ZFLAG_SET;
  1814. FLAG_V = (!(src == 0))<<7;
  1815. return;
  1816. }
  1817. FLAG_C = CFLAG_CLEAR;
  1818. FLAG_N = NFLAG_16(src);
  1819. FLAG_Z = src;
  1820. FLAG_V = VFLAG_CLEAR;
  1821. }
  1822. M68KMAKE_OP(asl, 32, r, .)
  1823. {
  1824. uint* r_dst = &DY;
  1825. uint shift = DX & 0x3f;
  1826. uint src = *r_dst;
  1827. uint res = MASK_OUT_ABOVE_32(src << shift);
  1828. if(shift != 0)
  1829. {
  1830. USE_CYCLES(shift<<CYC_SHIFT);
  1831. if(shift < 32)
  1832. {
  1833. *r_dst = res;
  1834. FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
  1835. FLAG_N = NFLAG_32(res);
  1836. FLAG_Z = res;
  1837. src &= m68ki_shift_32_table[shift + 1];
  1838. FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
  1839. return;
  1840. }
  1841. *r_dst = 0;
  1842. FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
  1843. FLAG_N = NFLAG_CLEAR;
  1844. FLAG_Z = ZFLAG_SET;
  1845. FLAG_V = (!(src == 0))<<7;
  1846. return;
  1847. }
  1848. FLAG_C = CFLAG_CLEAR;
  1849. FLAG_N = NFLAG_32(src);
  1850. FLAG_Z = src;
  1851. FLAG_V = VFLAG_CLEAR;
  1852. }
  1853. M68KMAKE_OP(asl, 16, ., .)
  1854. {
  1855. uint ea = M68KMAKE_GET_EA_AY_16;
  1856. uint src = m68ki_read_16(ea);
  1857. uint res = MASK_OUT_ABOVE_16(src << 1);
  1858. m68ki_write_16(ea, res);
  1859. FLAG_N = NFLAG_16(res);
  1860. FLAG_Z = res;
  1861. FLAG_X = FLAG_C = src >> 7;
  1862. src &= 0xc000;
  1863. FLAG_V = (!(src == 0 || src == 0xc000))<<7;
  1864. }
  1865. M68KMAKE_OP(bcc, 8, ., .)
  1866. {
  1867. if(M68KMAKE_CC)
  1868. {
  1869. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  1870. m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
  1871. return;
  1872. }
  1873. USE_CYCLES(CYC_BCC_NOTAKE_B);
  1874. }
  1875. M68KMAKE_OP(bcc, 16, ., .)
  1876. {
  1877. if(M68KMAKE_CC)
  1878. {
  1879. uint offset = OPER_I_16();
  1880. REG_PC -= 2;
  1881. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  1882. m68ki_branch_16(offset);
  1883. return;
  1884. }
  1885. REG_PC += 2;
  1886. USE_CYCLES(CYC_BCC_NOTAKE_W);
  1887. }
  1888. M68KMAKE_OP(bcc, 32, ., .)
  1889. {
  1890. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  1891. {
  1892. if(M68KMAKE_CC)
  1893. {
  1894. uint offset = OPER_I_32();
  1895. REG_PC -= 4;
  1896. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  1897. m68ki_branch_32(offset);
  1898. return;
  1899. }
  1900. REG_PC += 4;
  1901. return;
  1902. }
  1903. else
  1904. {
  1905. if(M68KMAKE_CC)
  1906. {
  1907. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  1908. m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
  1909. return;
  1910. }
  1911. USE_CYCLES(CYC_BCC_NOTAKE_B);
  1912. }
  1913. }
  1914. M68KMAKE_OP(bchg, 32, r, d)
  1915. {
  1916. uint* r_dst = &DY;
  1917. uint mask = 1 << (DX & 0x1f);
  1918. FLAG_Z = *r_dst & mask;
  1919. *r_dst ^= mask;
  1920. }
  1921. M68KMAKE_OP(bchg, 8, r, .)
  1922. {
  1923. uint ea = M68KMAKE_GET_EA_AY_8;
  1924. uint src = m68ki_read_8(ea);
  1925. uint mask = 1 << (DX & 7);
  1926. FLAG_Z = src & mask;
  1927. m68ki_write_8(ea, src ^ mask);
  1928. }
  1929. M68KMAKE_OP(bchg, 32, s, d)
  1930. {
  1931. uint* r_dst = &DY;
  1932. uint mask = 1 << (OPER_I_8() & 0x1f);
  1933. FLAG_Z = *r_dst & mask;
  1934. *r_dst ^= mask;
  1935. }
  1936. M68KMAKE_OP(bchg, 8, s, .)
  1937. {
  1938. uint mask = 1 << (OPER_I_8() & 7);
  1939. uint ea = M68KMAKE_GET_EA_AY_8;
  1940. uint src = m68ki_read_8(ea);
  1941. FLAG_Z = src & mask;
  1942. m68ki_write_8(ea, src ^ mask);
  1943. }
  1944. M68KMAKE_OP(bclr, 32, r, d)
  1945. {
  1946. uint* r_dst = &DY;
  1947. uint mask = 1 << (DX & 0x1f);
  1948. FLAG_Z = *r_dst & mask;
  1949. *r_dst &= ~mask;
  1950. }
  1951. M68KMAKE_OP(bclr, 8, r, .)
  1952. {
  1953. uint ea = M68KMAKE_GET_EA_AY_8;
  1954. uint src = m68ki_read_8(ea);
  1955. uint mask = 1 << (DX & 7);
  1956. FLAG_Z = src & mask;
  1957. m68ki_write_8(ea, src & ~mask);
  1958. }
  1959. M68KMAKE_OP(bclr, 32, s, d)
  1960. {
  1961. uint* r_dst = &DY;
  1962. uint mask = 1 << (OPER_I_8() & 0x1f);
  1963. FLAG_Z = *r_dst & mask;
  1964. *r_dst &= ~mask;
  1965. }
  1966. M68KMAKE_OP(bclr, 8, s, .)
  1967. {
  1968. uint mask = 1 << (OPER_I_8() & 7);
  1969. uint ea = M68KMAKE_GET_EA_AY_8;
  1970. uint src = m68ki_read_8(ea);
  1971. FLAG_Z = src & mask;
  1972. m68ki_write_8(ea, src & ~mask);
  1973. }
  1974. M68KMAKE_OP(bfchg, 32, ., d)
  1975. {
  1976. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  1977. {
  1978. uint word2 = OPER_I_16();
  1979. uint offset = (word2>>6)&31;
  1980. uint width = word2;
  1981. uint* data = &DY;
  1982. uint64 mask;
  1983. if(BIT_B(word2))
  1984. offset = REG_D[offset&7];
  1985. if(BIT_5(word2))
  1986. width = REG_D[width&7];
  1987. offset &= 31;
  1988. width = ((width-1) & 31) + 1;
  1989. mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
  1990. mask = ROR_32(mask, offset);
  1991. FLAG_N = NFLAG_32(*data<<offset);
  1992. FLAG_Z = *data & mask;
  1993. FLAG_V = VFLAG_CLEAR;
  1994. FLAG_C = CFLAG_CLEAR;
  1995. *data ^= mask;
  1996. return;
  1997. }
  1998. m68ki_exception_illegal();
  1999. }
  2000. M68KMAKE_OP(bfchg, 32, ., .)
  2001. {
  2002. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2003. {
  2004. uint word2 = OPER_I_16();
  2005. sint offset = (word2>>6)&31;
  2006. uint width = word2;
  2007. uint mask_base;
  2008. uint data_long;
  2009. uint mask_long;
  2010. uint data_byte = 0;
  2011. uint mask_byte = 0;
  2012. uint ea = M68KMAKE_GET_EA_AY_8;
  2013. if(BIT_B(word2))
  2014. offset = MAKE_INT_32(REG_D[offset&7]);
  2015. if(BIT_5(word2))
  2016. width = REG_D[width&7];
  2017. /* Offset is signed so we have to use ugly math =( */
  2018. ea += offset / 8;
  2019. offset %= 8;
  2020. if(offset < 0)
  2021. {
  2022. offset += 8;
  2023. ea--;
  2024. }
  2025. width = ((width-1) & 31) + 1;
  2026. mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
  2027. mask_long = mask_base >> offset;
  2028. data_long = m68ki_read_32(ea);
  2029. FLAG_N = NFLAG_32(data_long << offset);
  2030. FLAG_Z = data_long & mask_long;
  2031. FLAG_V = VFLAG_CLEAR;
  2032. FLAG_C = CFLAG_CLEAR;
  2033. m68ki_write_32(ea, data_long ^ mask_long);
  2034. if((width + offset) > 32)
  2035. {
  2036. mask_byte = MASK_OUT_ABOVE_8(mask_base);
  2037. data_byte = m68ki_read_8(ea+4);
  2038. FLAG_Z |= (data_byte & mask_byte);
  2039. m68ki_write_8(ea+4, data_byte ^ mask_byte);
  2040. }
  2041. return;
  2042. }
  2043. m68ki_exception_illegal();
  2044. }
  2045. M68KMAKE_OP(bfclr, 32, ., d)
  2046. {
  2047. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2048. {
  2049. uint word2 = OPER_I_16();
  2050. uint offset = (word2>>6)&31;
  2051. uint width = word2;
  2052. uint* data = &DY;
  2053. uint64 mask;
  2054. if(BIT_B(word2))
  2055. offset = REG_D[offset&7];
  2056. if(BIT_5(word2))
  2057. width = REG_D[width&7];
  2058. offset &= 31;
  2059. width = ((width-1) & 31) + 1;
  2060. mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
  2061. mask = ROR_32(mask, offset);
  2062. FLAG_N = NFLAG_32(*data<<offset);
  2063. FLAG_Z = *data & mask;
  2064. FLAG_V = VFLAG_CLEAR;
  2065. FLAG_C = CFLAG_CLEAR;
  2066. *data &= ~mask;
  2067. return;
  2068. }
  2069. m68ki_exception_illegal();
  2070. }
  2071. M68KMAKE_OP(bfclr, 32, ., .)
  2072. {
  2073. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2074. {
  2075. uint word2 = OPER_I_16();
  2076. sint offset = (word2>>6)&31;
  2077. uint width = word2;
  2078. uint mask_base;
  2079. uint data_long;
  2080. uint mask_long;
  2081. uint data_byte = 0;
  2082. uint mask_byte = 0;
  2083. uint ea = M68KMAKE_GET_EA_AY_8;
  2084. if(BIT_B(word2))
  2085. offset = MAKE_INT_32(REG_D[offset&7]);
  2086. if(BIT_5(word2))
  2087. width = REG_D[width&7];
  2088. /* Offset is signed so we have to use ugly math =( */
  2089. ea += offset / 8;
  2090. offset %= 8;
  2091. if(offset < 0)
  2092. {
  2093. offset += 8;
  2094. ea--;
  2095. }
  2096. width = ((width-1) & 31) + 1;
  2097. mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
  2098. mask_long = mask_base >> offset;
  2099. data_long = m68ki_read_32(ea);
  2100. FLAG_N = NFLAG_32(data_long << offset);
  2101. FLAG_Z = data_long & mask_long;
  2102. FLAG_V = VFLAG_CLEAR;
  2103. FLAG_C = CFLAG_CLEAR;
  2104. m68ki_write_32(ea, data_long & ~mask_long);
  2105. if((width + offset) > 32)
  2106. {
  2107. mask_byte = MASK_OUT_ABOVE_8(mask_base);
  2108. data_byte = m68ki_read_8(ea+4);
  2109. FLAG_Z |= (data_byte & mask_byte);
  2110. m68ki_write_8(ea+4, data_byte & ~mask_byte);
  2111. }
  2112. return;
  2113. }
  2114. m68ki_exception_illegal();
  2115. }
  2116. M68KMAKE_OP(bfexts, 32, ., d)
  2117. {
  2118. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2119. {
  2120. uint word2 = OPER_I_16();
  2121. uint offset = (word2>>6)&31;
  2122. uint width = word2;
  2123. uint64 data = DY;
  2124. if(BIT_B(word2))
  2125. offset = REG_D[offset&7];
  2126. if(BIT_5(word2))
  2127. width = REG_D[width&7];
  2128. offset &= 31;
  2129. width = ((width-1) & 31) + 1;
  2130. data = ROL_32(data, offset);
  2131. FLAG_N = NFLAG_32(data);
  2132. data = MAKE_INT_32(data) >> (32 - width);
  2133. FLAG_Z = data;
  2134. FLAG_V = VFLAG_CLEAR;
  2135. FLAG_C = CFLAG_CLEAR;
  2136. REG_D[(word2>>12)&7] = data;
  2137. return;
  2138. }
  2139. m68ki_exception_illegal();
  2140. }
  2141. M68KMAKE_OP(bfexts, 32, ., .)
  2142. {
  2143. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2144. {
  2145. uint word2 = OPER_I_16();
  2146. sint offset = (word2>>6)&31;
  2147. uint width = word2;
  2148. uint data;
  2149. uint ea = M68KMAKE_GET_EA_AY_8;
  2150. if(BIT_B(word2))
  2151. offset = MAKE_INT_32(REG_D[offset&7]);
  2152. if(BIT_5(word2))
  2153. width = REG_D[width&7];
  2154. /* Offset is signed so we have to use ugly math =( */
  2155. ea += offset / 8;
  2156. offset %= 8;
  2157. if(offset < 0)
  2158. {
  2159. offset += 8;
  2160. ea--;
  2161. }
  2162. width = ((width-1) & 31) + 1;
  2163. data = m68ki_read_32(ea);
  2164. data = MASK_OUT_ABOVE_32(data<<offset);
  2165. if((offset+width) > 32)
  2166. data |= (m68ki_read_8(ea+4) << offset) >> 8;
  2167. FLAG_N = NFLAG_32(data);
  2168. data = MAKE_INT_32(data) >> (32 - width);
  2169. FLAG_Z = data;
  2170. FLAG_V = VFLAG_CLEAR;
  2171. FLAG_C = CFLAG_CLEAR;
  2172. REG_D[(word2 >> 12) & 7] = data;
  2173. return;
  2174. }
  2175. m68ki_exception_illegal();
  2176. }
  2177. M68KMAKE_OP(bfextu, 32, ., d)
  2178. {
  2179. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2180. {
  2181. uint word2 = OPER_I_16();
  2182. uint offset = (word2>>6)&31;
  2183. uint width = word2;
  2184. uint64 data = DY;
  2185. if(BIT_B(word2))
  2186. offset = REG_D[offset&7];
  2187. if(BIT_5(word2))
  2188. width = REG_D[width&7];
  2189. offset &= 31;
  2190. width = ((width-1) & 31) + 1;
  2191. data = ROL_32(data, offset);
  2192. FLAG_N = NFLAG_32(data);
  2193. data >>= 32 - width;
  2194. FLAG_Z = data;
  2195. FLAG_V = VFLAG_CLEAR;
  2196. FLAG_C = CFLAG_CLEAR;
  2197. REG_D[(word2>>12)&7] = data;
  2198. return;
  2199. }
  2200. m68ki_exception_illegal();
  2201. }
  2202. M68KMAKE_OP(bfextu, 32, ., .)
  2203. {
  2204. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2205. {
  2206. uint word2 = OPER_I_16();
  2207. sint offset = (word2>>6)&31;
  2208. uint width = word2;
  2209. uint data;
  2210. uint ea = M68KMAKE_GET_EA_AY_8;
  2211. if(BIT_B(word2))
  2212. offset = MAKE_INT_32(REG_D[offset&7]);
  2213. if(BIT_5(word2))
  2214. width = REG_D[width&7];
  2215. /* Offset is signed so we have to use ugly math =( */
  2216. ea += offset / 8;
  2217. offset %= 8;
  2218. if(offset < 0)
  2219. {
  2220. offset += 8;
  2221. ea--;
  2222. }
  2223. width = ((width-1) & 31) + 1;
  2224. data = m68ki_read_32(ea);
  2225. data = MASK_OUT_ABOVE_32(data<<offset);
  2226. if((offset+width) > 32)
  2227. data |= (m68ki_read_8(ea+4) << offset) >> 8;
  2228. FLAG_N = NFLAG_32(data);
  2229. data >>= (32 - width);
  2230. FLAG_Z = data;
  2231. FLAG_V = VFLAG_CLEAR;
  2232. FLAG_C = CFLAG_CLEAR;
  2233. REG_D[(word2 >> 12) & 7] = data;
  2234. return;
  2235. }
  2236. m68ki_exception_illegal();
  2237. }
  2238. M68KMAKE_OP(bfffo, 32, ., d)
  2239. {
  2240. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2241. {
  2242. uint word2 = OPER_I_16();
  2243. uint offset = (word2>>6)&31;
  2244. uint width = word2;
  2245. uint64 data = DY;
  2246. uint bit;
  2247. if(BIT_B(word2))
  2248. offset = REG_D[offset&7];
  2249. if(BIT_5(word2))
  2250. width = REG_D[width&7];
  2251. offset &= 31;
  2252. width = ((width-1) & 31) + 1;
  2253. data = ROL_32(data, offset);
  2254. FLAG_N = NFLAG_32(data);
  2255. data >>= 32 - width;
  2256. FLAG_Z = data;
  2257. FLAG_V = VFLAG_CLEAR;
  2258. FLAG_C = CFLAG_CLEAR;
  2259. for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
  2260. offset++;
  2261. REG_D[(word2>>12)&7] = offset;
  2262. return;
  2263. }
  2264. m68ki_exception_illegal();
  2265. }
  2266. M68KMAKE_OP(bfffo, 32, ., .)
  2267. {
  2268. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2269. {
  2270. uint word2 = OPER_I_16();
  2271. sint offset = (word2>>6)&31;
  2272. sint local_offset;
  2273. uint width = word2;
  2274. uint data;
  2275. uint bit;
  2276. uint ea = M68KMAKE_GET_EA_AY_8;
  2277. if(BIT_B(word2))
  2278. offset = MAKE_INT_32(REG_D[offset&7]);
  2279. if(BIT_5(word2))
  2280. width = REG_D[width&7];
  2281. /* Offset is signed so we have to use ugly math =( */
  2282. ea += offset / 8;
  2283. local_offset = offset % 8;
  2284. if(local_offset < 0)
  2285. {
  2286. local_offset += 8;
  2287. ea--;
  2288. }
  2289. width = ((width-1) & 31) + 1;
  2290. data = m68ki_read_32(ea);
  2291. data = MASK_OUT_ABOVE_32(data<<local_offset);
  2292. if((local_offset+width) > 32)
  2293. data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
  2294. FLAG_N = NFLAG_32(data);
  2295. data >>= (32 - width);
  2296. FLAG_Z = data;
  2297. FLAG_V = VFLAG_CLEAR;
  2298. FLAG_C = CFLAG_CLEAR;
  2299. for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
  2300. offset++;
  2301. REG_D[(word2>>12)&7] = offset;
  2302. return;
  2303. }
  2304. m68ki_exception_illegal();
  2305. }
  2306. M68KMAKE_OP(bfins, 32, ., d)
  2307. {
  2308. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2309. {
  2310. uint word2 = OPER_I_16();
  2311. uint offset = (word2>>6)&31;
  2312. uint width = word2;
  2313. uint* data = &DY;
  2314. uint64 mask;
  2315. uint64 insert = REG_D[(word2>>12)&7];
  2316. if(BIT_B(word2))
  2317. offset = REG_D[offset&7];
  2318. if(BIT_5(word2))
  2319. width = REG_D[width&7];
  2320. offset &= 31;
  2321. width = ((width-1) & 31) + 1;
  2322. mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
  2323. mask = ROR_32(mask, offset);
  2324. insert = MASK_OUT_ABOVE_32(insert << (32 - width));
  2325. FLAG_N = NFLAG_32(insert);
  2326. FLAG_Z = insert;
  2327. insert = ROR_32(insert, offset);
  2328. FLAG_V = VFLAG_CLEAR;
  2329. FLAG_C = CFLAG_CLEAR;
  2330. *data &= ~mask;
  2331. *data |= insert;
  2332. return;
  2333. }
  2334. m68ki_exception_illegal();
  2335. }
  2336. M68KMAKE_OP(bfins, 32, ., .)
  2337. {
  2338. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2339. {
  2340. uint word2 = OPER_I_16();
  2341. sint offset = (word2>>6)&31;
  2342. uint width = word2;
  2343. uint insert_base = REG_D[(word2>>12)&7];
  2344. uint insert_long;
  2345. uint insert_byte;
  2346. uint mask_base;
  2347. uint data_long;
  2348. uint mask_long;
  2349. uint data_byte = 0;
  2350. uint mask_byte = 0;
  2351. uint ea = M68KMAKE_GET_EA_AY_8;
  2352. if(BIT_B(word2))
  2353. offset = MAKE_INT_32(REG_D[offset&7]);
  2354. if(BIT_5(word2))
  2355. width = REG_D[width&7];
  2356. /* Offset is signed so we have to use ugly math =( */
  2357. ea += offset / 8;
  2358. offset %= 8;
  2359. if(offset < 0)
  2360. {
  2361. offset += 8;
  2362. ea--;
  2363. }
  2364. width = ((width-1) & 31) + 1;
  2365. mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
  2366. mask_long = mask_base >> offset;
  2367. insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));
  2368. FLAG_N = NFLAG_32(insert_base);
  2369. FLAG_Z = insert_base;
  2370. insert_long = insert_base >> offset;
  2371. data_long = m68ki_read_32(ea);
  2372. FLAG_V = VFLAG_CLEAR;
  2373. FLAG_C = CFLAG_CLEAR;
  2374. m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);
  2375. if((width + offset) > 32)
  2376. {
  2377. mask_byte = MASK_OUT_ABOVE_8(mask_base);
  2378. insert_byte = MASK_OUT_ABOVE_8(insert_base);
  2379. data_byte = m68ki_read_8(ea+4);
  2380. FLAG_Z |= (data_byte & mask_byte);
  2381. m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);
  2382. }
  2383. return;
  2384. }
  2385. m68ki_exception_illegal();
  2386. }
  2387. M68KMAKE_OP(bfset, 32, ., d)
  2388. {
  2389. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2390. {
  2391. uint word2 = OPER_I_16();
  2392. uint offset = (word2>>6)&31;
  2393. uint width = word2;
  2394. uint* data = &DY;
  2395. uint64 mask;
  2396. if(BIT_B(word2))
  2397. offset = REG_D[offset&7];
  2398. if(BIT_5(word2))
  2399. width = REG_D[width&7];
  2400. offset &= 31;
  2401. width = ((width-1) & 31) + 1;
  2402. mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
  2403. mask = ROR_32(mask, offset);
  2404. FLAG_N = NFLAG_32(*data<<offset);
  2405. FLAG_Z = *data & mask;
  2406. FLAG_V = VFLAG_CLEAR;
  2407. FLAG_C = CFLAG_CLEAR;
  2408. *data |= mask;
  2409. return;
  2410. }
  2411. m68ki_exception_illegal();
  2412. }
  2413. M68KMAKE_OP(bfset, 32, ., .)
  2414. {
  2415. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2416. {
  2417. uint word2 = OPER_I_16();
  2418. sint offset = (word2>>6)&31;
  2419. uint width = word2;
  2420. uint mask_base;
  2421. uint data_long;
  2422. uint mask_long;
  2423. uint data_byte = 0;
  2424. uint mask_byte = 0;
  2425. uint ea = M68KMAKE_GET_EA_AY_8;
  2426. if(BIT_B(word2))
  2427. offset = MAKE_INT_32(REG_D[offset&7]);
  2428. if(BIT_5(word2))
  2429. width = REG_D[width&7];
  2430. /* Offset is signed so we have to use ugly math =( */
  2431. ea += offset / 8;
  2432. offset %= 8;
  2433. if(offset < 0)
  2434. {
  2435. offset += 8;
  2436. ea--;
  2437. }
  2438. width = ((width-1) & 31) + 1;
  2439. mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
  2440. mask_long = mask_base >> offset;
  2441. data_long = m68ki_read_32(ea);
  2442. FLAG_N = NFLAG_32(data_long << offset);
  2443. FLAG_Z = data_long & mask_long;
  2444. FLAG_V = VFLAG_CLEAR;
  2445. FLAG_C = CFLAG_CLEAR;
  2446. m68ki_write_32(ea, data_long | mask_long);
  2447. if((width + offset) > 32)
  2448. {
  2449. mask_byte = MASK_OUT_ABOVE_8(mask_base);
  2450. data_byte = m68ki_read_8(ea+4);
  2451. FLAG_Z |= (data_byte & mask_byte);
  2452. m68ki_write_8(ea+4, data_byte | mask_byte);
  2453. }
  2454. return;
  2455. }
  2456. m68ki_exception_illegal();
  2457. }
  2458. M68KMAKE_OP(bftst, 32, ., d)
  2459. {
  2460. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2461. {
  2462. uint word2 = OPER_I_16();
  2463. uint offset = (word2>>6)&31;
  2464. uint width = word2;
  2465. uint* data = &DY;
  2466. uint64 mask;
  2467. if(BIT_B(word2))
  2468. offset = REG_D[offset&7];
  2469. if(BIT_5(word2))
  2470. width = REG_D[width&7];
  2471. offset &= 31;
  2472. width = ((width-1) & 31) + 1;
  2473. mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
  2474. mask = ROR_32(mask, offset);
  2475. FLAG_N = NFLAG_32(*data<<offset);
  2476. FLAG_Z = *data & mask;
  2477. FLAG_V = VFLAG_CLEAR;
  2478. FLAG_C = CFLAG_CLEAR;
  2479. return;
  2480. }
  2481. m68ki_exception_illegal();
  2482. }
  2483. M68KMAKE_OP(bftst, 32, ., .)
  2484. {
  2485. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2486. {
  2487. uint word2 = OPER_I_16();
  2488. sint offset = (word2>>6)&31;
  2489. uint width = word2;
  2490. uint mask_base;
  2491. uint data_long;
  2492. uint mask_long;
  2493. uint data_byte = 0;
  2494. uint mask_byte = 0;
  2495. uint ea = M68KMAKE_GET_EA_AY_8;
  2496. if(BIT_B(word2))
  2497. offset = MAKE_INT_32(REG_D[offset&7]);
  2498. if(BIT_5(word2))
  2499. width = REG_D[width&7];
  2500. /* Offset is signed so we have to use ugly math =( */
  2501. ea += offset / 8;
  2502. offset %= 8;
  2503. if(offset < 0)
  2504. {
  2505. offset += 8;
  2506. ea--;
  2507. }
  2508. width = ((width-1) & 31) + 1;
  2509. mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
  2510. mask_long = mask_base >> offset;
  2511. data_long = m68ki_read_32(ea);
  2512. FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
  2513. FLAG_Z = data_long & mask_long;
  2514. FLAG_V = VFLAG_CLEAR;
  2515. FLAG_C = CFLAG_CLEAR;
  2516. if((width + offset) > 32)
  2517. {
  2518. mask_byte = MASK_OUT_ABOVE_8(mask_base);
  2519. data_byte = m68ki_read_8(ea+4);
  2520. FLAG_Z |= (data_byte & mask_byte);
  2521. }
  2522. return;
  2523. }
  2524. m68ki_exception_illegal();
  2525. }
  2526. M68KMAKE_OP(bkpt, 0, ., .)
  2527. {
  2528. if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
  2529. {
  2530. m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0); /* auto-disable (see m68kcpu.h) */
  2531. }
  2532. m68ki_exception_illegal();
  2533. }
  2534. M68KMAKE_OP(bra, 8, ., .)
  2535. {
  2536. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  2537. m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
  2538. if(REG_PC == REG_PPC)
  2539. USE_ALL_CYCLES();
  2540. }
  2541. M68KMAKE_OP(bra, 16, ., .)
  2542. {
  2543. uint offset = OPER_I_16();
  2544. REG_PC -= 2;
  2545. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  2546. m68ki_branch_16(offset);
  2547. if(REG_PC == REG_PPC)
  2548. USE_ALL_CYCLES();
  2549. }
  2550. M68KMAKE_OP(bra, 32, ., .)
  2551. {
  2552. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2553. {
  2554. uint offset = OPER_I_32();
  2555. REG_PC -= 4;
  2556. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  2557. m68ki_branch_32(offset);
  2558. if(REG_PC == REG_PPC)
  2559. USE_ALL_CYCLES();
  2560. return;
  2561. }
  2562. else
  2563. {
  2564. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  2565. m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
  2566. if(REG_PC == REG_PPC)
  2567. USE_ALL_CYCLES();
  2568. }
  2569. }
  2570. M68KMAKE_OP(bset, 32, r, d)
  2571. {
  2572. uint* r_dst = &DY;
  2573. uint mask = 1 << (DX & 0x1f);
  2574. FLAG_Z = *r_dst & mask;
  2575. *r_dst |= mask;
  2576. }
  2577. M68KMAKE_OP(bset, 8, r, .)
  2578. {
  2579. uint ea = M68KMAKE_GET_EA_AY_8;
  2580. uint src = m68ki_read_8(ea);
  2581. uint mask = 1 << (DX & 7);
  2582. FLAG_Z = src & mask;
  2583. m68ki_write_8(ea, src | mask);
  2584. }
  2585. M68KMAKE_OP(bset, 32, s, d)
  2586. {
  2587. uint* r_dst = &DY;
  2588. uint mask = 1 << (OPER_I_8() & 0x1f);
  2589. FLAG_Z = *r_dst & mask;
  2590. *r_dst |= mask;
  2591. }
  2592. M68KMAKE_OP(bset, 8, s, .)
  2593. {
  2594. uint mask = 1 << (OPER_I_8() & 7);
  2595. uint ea = M68KMAKE_GET_EA_AY_8;
  2596. uint src = m68ki_read_8(ea);
  2597. FLAG_Z = src & mask;
  2598. m68ki_write_8(ea, src | mask);
  2599. }
  2600. M68KMAKE_OP(bsr, 8, ., .)
  2601. {
  2602. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  2603. m68ki_push_32(REG_PC);
  2604. m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
  2605. }
  2606. M68KMAKE_OP(bsr, 16, ., .)
  2607. {
  2608. uint offset = OPER_I_16();
  2609. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  2610. m68ki_push_32(REG_PC);
  2611. REG_PC -= 2;
  2612. m68ki_branch_16(offset);
  2613. }
  2614. M68KMAKE_OP(bsr, 32, ., .)
  2615. {
  2616. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2617. {
  2618. uint offset = OPER_I_32();
  2619. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  2620. m68ki_push_32(REG_PC);
  2621. REG_PC -= 4;
  2622. m68ki_branch_32(offset);
  2623. return;
  2624. }
  2625. else
  2626. {
  2627. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  2628. m68ki_push_32(REG_PC);
  2629. m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
  2630. }
  2631. }
  2632. M68KMAKE_OP(btst, 32, r, d)
  2633. {
  2634. FLAG_Z = DY & (1 << (DX & 0x1f));
  2635. }
  2636. M68KMAKE_OP(btst, 8, r, .)
  2637. {
  2638. FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << (DX & 7));
  2639. }
  2640. M68KMAKE_OP(btst, 32, s, d)
  2641. {
  2642. FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f));
  2643. }
  2644. M68KMAKE_OP(btst, 8, s, .)
  2645. {
  2646. uint bit = OPER_I_8() & 7;
  2647. FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << bit);
  2648. }
  2649. M68KMAKE_OP(callm, 32, ., .)
  2650. {
  2651. /* note: watch out for pcrelative modes */
  2652. if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
  2653. {
  2654. uint ea = M68KMAKE_GET_EA_AY_32;
  2655. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  2656. REG_PC += 2;
  2657. (void)ea; /* just to avoid an 'unused variable' warning */
  2658. M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
  2659. m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
  2660. m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
  2661. return;
  2662. }
  2663. m68ki_exception_illegal();
  2664. }
  2665. M68KMAKE_OP(cas, 8, ., .)
  2666. {
  2667. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2668. {
  2669. uint word2 = OPER_I_16();
  2670. uint ea = M68KMAKE_GET_EA_AY_8;
  2671. uint dest = m68ki_read_8(ea);
  2672. uint* compare = &REG_D[word2 & 7];
  2673. uint res = dest - MASK_OUT_ABOVE_8(*compare);
  2674. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  2675. FLAG_N = NFLAG_8(res);
  2676. FLAG_Z = MASK_OUT_ABOVE_8(res);
  2677. FLAG_V = VFLAG_SUB_8(*compare, dest, res);
  2678. FLAG_C = CFLAG_8(res);
  2679. if(COND_NE())
  2680. *compare = MASK_OUT_BELOW_8(*compare) | dest;
  2681. else
  2682. {
  2683. USE_CYCLES(3);
  2684. m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
  2685. }
  2686. return;
  2687. }
  2688. m68ki_exception_illegal();
  2689. }
  2690. M68KMAKE_OP(cas, 16, ., .)
  2691. {
  2692. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2693. {
  2694. uint word2 = OPER_I_16();
  2695. uint ea = M68KMAKE_GET_EA_AY_16;
  2696. uint dest = m68ki_read_16(ea);
  2697. uint* compare = &REG_D[word2 & 7];
  2698. uint res = dest - MASK_OUT_ABOVE_16(*compare);
  2699. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  2700. FLAG_N = NFLAG_16(res);
  2701. FLAG_Z = MASK_OUT_ABOVE_16(res);
  2702. FLAG_V = VFLAG_SUB_16(*compare, dest, res);
  2703. FLAG_C = CFLAG_16(res);
  2704. if(COND_NE())
  2705. *compare = MASK_OUT_BELOW_16(*compare) | dest;
  2706. else
  2707. {
  2708. USE_CYCLES(3);
  2709. m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
  2710. }
  2711. return;
  2712. }
  2713. m68ki_exception_illegal();
  2714. }
  2715. M68KMAKE_OP(cas, 32, ., .)
  2716. {
  2717. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2718. {
  2719. uint word2 = OPER_I_16();
  2720. uint ea = M68KMAKE_GET_EA_AY_32;
  2721. uint dest = m68ki_read_32(ea);
  2722. uint* compare = &REG_D[word2 & 7];
  2723. uint res = dest - *compare;
  2724. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  2725. FLAG_N = NFLAG_32(res);
  2726. FLAG_Z = MASK_OUT_ABOVE_32(res);
  2727. FLAG_V = VFLAG_SUB_32(*compare, dest, res);
  2728. FLAG_C = CFLAG_SUB_32(*compare, dest, res);
  2729. if(COND_NE())
  2730. *compare = dest;
  2731. else
  2732. {
  2733. USE_CYCLES(3);
  2734. m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
  2735. }
  2736. return;
  2737. }
  2738. m68ki_exception_illegal();
  2739. }
  2740. M68KMAKE_OP(cas2, 16, ., .)
  2741. {
  2742. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2743. {
  2744. uint word2 = OPER_I_32();
  2745. uint* compare1 = &REG_D[(word2 >> 16) & 7];
  2746. uint ea1 = REG_DA[(word2 >> 28) & 15];
  2747. uint dest1 = m68ki_read_16(ea1);
  2748. uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1);
  2749. uint* compare2 = &REG_D[word2 & 7];
  2750. uint ea2 = REG_DA[(word2 >> 12) & 15];
  2751. uint dest2 = m68ki_read_16(ea2);
  2752. uint res2;
  2753. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  2754. FLAG_N = NFLAG_16(res1);
  2755. FLAG_Z = MASK_OUT_ABOVE_16(res1);
  2756. FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1);
  2757. FLAG_C = CFLAG_16(res1);
  2758. if(COND_EQ())
  2759. {
  2760. res2 = dest2 - MASK_OUT_ABOVE_16(*compare2);
  2761. FLAG_N = NFLAG_16(res2);
  2762. FLAG_Z = MASK_OUT_ABOVE_16(res2);
  2763. FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2);
  2764. FLAG_C = CFLAG_16(res2);
  2765. if(COND_EQ())
  2766. {
  2767. USE_CYCLES(3);
  2768. m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]);
  2769. m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]);
  2770. return;
  2771. }
  2772. }
  2773. *compare1 = BIT_1F(word2) ? MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1;
  2774. *compare2 = BIT_F(word2) ? MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2;
  2775. return;
  2776. }
  2777. m68ki_exception_illegal();
  2778. }
  2779. M68KMAKE_OP(cas2, 32, ., .)
  2780. {
  2781. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2782. {
  2783. uint word2 = OPER_I_32();
  2784. uint* compare1 = &REG_D[(word2 >> 16) & 7];
  2785. uint ea1 = REG_DA[(word2 >> 28) & 15];
  2786. uint dest1 = m68ki_read_32(ea1);
  2787. uint res1 = dest1 - *compare1;
  2788. uint* compare2 = &REG_D[word2 & 7];
  2789. uint ea2 = REG_DA[(word2 >> 12) & 15];
  2790. uint dest2 = m68ki_read_32(ea2);
  2791. uint res2;
  2792. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  2793. FLAG_N = NFLAG_32(res1);
  2794. FLAG_Z = MASK_OUT_ABOVE_32(res1);
  2795. FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1);
  2796. FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1);
  2797. if(COND_EQ())
  2798. {
  2799. res2 = dest2 - *compare2;
  2800. FLAG_N = NFLAG_32(res2);
  2801. FLAG_Z = MASK_OUT_ABOVE_32(res2);
  2802. FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2);
  2803. FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2);
  2804. if(COND_EQ())
  2805. {
  2806. USE_CYCLES(3);
  2807. m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]);
  2808. m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]);
  2809. return;
  2810. }
  2811. }
  2812. *compare1 = dest1;
  2813. *compare2 = dest2;
  2814. return;
  2815. }
  2816. m68ki_exception_illegal();
  2817. }
  2818. M68KMAKE_OP(chk, 16, ., d)
  2819. {
  2820. sint src = MAKE_INT_16(DX);
  2821. sint bound = MAKE_INT_16(DY);
  2822. FLAG_Z = ZFLAG_16(src); /* Undocumented */
  2823. FLAG_V = VFLAG_CLEAR; /* Undocumented */
  2824. FLAG_C = CFLAG_CLEAR; /* Undocumented */
  2825. if(src >= 0 && src <= bound)
  2826. {
  2827. return;
  2828. }
  2829. FLAG_N = (src < 0)<<7;
  2830. m68ki_exception_trap(EXCEPTION_CHK);
  2831. }
  2832. M68KMAKE_OP(chk, 16, ., .)
  2833. {
  2834. sint src = MAKE_INT_16(DX);
  2835. sint bound = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
  2836. FLAG_Z = ZFLAG_16(src); /* Undocumented */
  2837. FLAG_V = VFLAG_CLEAR; /* Undocumented */
  2838. FLAG_C = CFLAG_CLEAR; /* Undocumented */
  2839. if(src >= 0 && src <= bound)
  2840. {
  2841. return;
  2842. }
  2843. FLAG_N = (src < 0)<<7;
  2844. m68ki_exception_trap(EXCEPTION_CHK);
  2845. }
  2846. M68KMAKE_OP(chk, 32, ., d)
  2847. {
  2848. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2849. {
  2850. sint src = MAKE_INT_32(DX);
  2851. sint bound = MAKE_INT_32(DY);
  2852. FLAG_Z = ZFLAG_32(src); /* Undocumented */
  2853. FLAG_V = VFLAG_CLEAR; /* Undocumented */
  2854. FLAG_C = CFLAG_CLEAR; /* Undocumented */
  2855. if(src >= 0 && src <= bound)
  2856. {
  2857. return;
  2858. }
  2859. FLAG_N = (src < 0)<<7;
  2860. m68ki_exception_trap(EXCEPTION_CHK);
  2861. return;
  2862. }
  2863. m68ki_exception_illegal();
  2864. }
  2865. M68KMAKE_OP(chk, 32, ., .)
  2866. {
  2867. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2868. {
  2869. sint src = MAKE_INT_32(DX);
  2870. sint bound = MAKE_INT_32(M68KMAKE_GET_OPER_AY_32);
  2871. FLAG_Z = ZFLAG_32(src); /* Undocumented */
  2872. FLAG_V = VFLAG_CLEAR; /* Undocumented */
  2873. FLAG_C = CFLAG_CLEAR; /* Undocumented */
  2874. if(src >= 0 && src <= bound)
  2875. {
  2876. return;
  2877. }
  2878. FLAG_N = (src < 0)<<7;
  2879. m68ki_exception_trap(EXCEPTION_CHK);
  2880. return;
  2881. }
  2882. m68ki_exception_illegal();
  2883. }
  2884. M68KMAKE_OP(chk2cmp2, 8, ., pcdi)
  2885. {
  2886. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2887. {
  2888. uint word2 = OPER_I_16();
  2889. uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
  2890. uint ea = EA_PCDI_8();
  2891. uint lower_bound = m68ki_read_pcrel_8(ea);
  2892. uint upper_bound = m68ki_read_pcrel_8(ea + 1);
  2893. if(!BIT_F(word2))
  2894. FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
  2895. else
  2896. FLAG_C = compare - lower_bound;
  2897. FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
  2898. if(COND_CS())
  2899. {
  2900. if(BIT_B(word2))
  2901. m68ki_exception_trap(EXCEPTION_CHK);
  2902. return;
  2903. }
  2904. FLAG_C = upper_bound - compare;
  2905. if(COND_CS() && BIT_B(word2))
  2906. m68ki_exception_trap(EXCEPTION_CHK);
  2907. return;
  2908. }
  2909. m68ki_exception_illegal();
  2910. }
  2911. M68KMAKE_OP(chk2cmp2, 8, ., pcix)
  2912. {
  2913. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2914. {
  2915. uint word2 = OPER_I_16();
  2916. uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
  2917. uint ea = EA_PCIX_8();
  2918. uint lower_bound = m68ki_read_pcrel_8(ea);
  2919. uint upper_bound = m68ki_read_pcrel_8(ea + 1);
  2920. if(!BIT_F(word2))
  2921. FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
  2922. else
  2923. FLAG_C = compare - lower_bound;
  2924. FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
  2925. if(COND_CS())
  2926. {
  2927. if(BIT_B(word2))
  2928. m68ki_exception_trap(EXCEPTION_CHK);
  2929. return;
  2930. }
  2931. FLAG_C = upper_bound - compare;
  2932. if(COND_CS() && BIT_B(word2))
  2933. m68ki_exception_trap(EXCEPTION_CHK);
  2934. return;
  2935. }
  2936. m68ki_exception_illegal();
  2937. }
  2938. M68KMAKE_OP(chk2cmp2, 8, ., .)
  2939. {
  2940. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2941. {
  2942. uint word2 = OPER_I_16();
  2943. uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
  2944. uint ea = M68KMAKE_GET_EA_AY_8;
  2945. uint lower_bound = m68ki_read_8(ea);
  2946. uint upper_bound = m68ki_read_8(ea + 1);
  2947. if(!BIT_F(word2))
  2948. FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
  2949. else
  2950. FLAG_C = compare - lower_bound;
  2951. FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
  2952. if(COND_CS())
  2953. {
  2954. if(BIT_B(word2))
  2955. m68ki_exception_trap(EXCEPTION_CHK);
  2956. return;
  2957. }
  2958. FLAG_C = upper_bound - compare;
  2959. if(COND_CS() && BIT_B(word2))
  2960. m68ki_exception_trap(EXCEPTION_CHK);
  2961. return;
  2962. }
  2963. m68ki_exception_illegal();
  2964. }
  2965. M68KMAKE_OP(chk2cmp2, 16, ., pcdi)
  2966. {
  2967. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2968. {
  2969. uint word2 = OPER_I_16();
  2970. uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
  2971. uint ea = EA_PCDI_16();
  2972. uint lower_bound = m68ki_read_pcrel_16(ea);
  2973. uint upper_bound = m68ki_read_pcrel_16(ea + 2);
  2974. if(!BIT_F(word2))
  2975. FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
  2976. else
  2977. FLAG_C = compare - lower_bound;
  2978. FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
  2979. FLAG_C = CFLAG_16(FLAG_C);
  2980. if(COND_CS())
  2981. {
  2982. if(BIT_B(word2))
  2983. m68ki_exception_trap(EXCEPTION_CHK);
  2984. return;
  2985. }
  2986. if(!BIT_F(word2))
  2987. FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
  2988. else
  2989. FLAG_C = upper_bound - compare;
  2990. FLAG_C = CFLAG_16(FLAG_C);
  2991. if(COND_CS() && BIT_B(word2))
  2992. m68ki_exception_trap(EXCEPTION_CHK);
  2993. return;
  2994. }
  2995. m68ki_exception_illegal();
  2996. }
  2997. M68KMAKE_OP(chk2cmp2, 16, ., pcix)
  2998. {
  2999. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3000. {
  3001. uint word2 = OPER_I_16();
  3002. uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
  3003. uint ea = EA_PCIX_16();
  3004. uint lower_bound = m68ki_read_pcrel_16(ea);
  3005. uint upper_bound = m68ki_read_pcrel_16(ea + 2);
  3006. if(!BIT_F(word2))
  3007. FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
  3008. else
  3009. FLAG_C = compare - lower_bound;
  3010. FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
  3011. FLAG_C = CFLAG_16(FLAG_C);
  3012. if(COND_CS())
  3013. {
  3014. if(BIT_B(word2))
  3015. m68ki_exception_trap(EXCEPTION_CHK);
  3016. return;
  3017. }
  3018. if(!BIT_F(word2))
  3019. FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
  3020. else
  3021. FLAG_C = upper_bound - compare;
  3022. FLAG_C = CFLAG_16(FLAG_C);
  3023. if(COND_CS() && BIT_B(word2))
  3024. m68ki_exception_trap(EXCEPTION_CHK);
  3025. return;
  3026. }
  3027. m68ki_exception_illegal();
  3028. }
  3029. M68KMAKE_OP(chk2cmp2, 16, ., .)
  3030. {
  3031. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3032. {
  3033. uint word2 = OPER_I_16();
  3034. uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
  3035. uint ea = M68KMAKE_GET_EA_AY_16;
  3036. uint lower_bound = m68ki_read_16(ea);
  3037. uint upper_bound = m68ki_read_16(ea + 2);
  3038. if(!BIT_F(word2))
  3039. FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
  3040. else
  3041. FLAG_C = compare - lower_bound;
  3042. FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
  3043. FLAG_C = CFLAG_16(FLAG_C);
  3044. if(COND_CS())
  3045. {
  3046. if(BIT_B(word2))
  3047. m68ki_exception_trap(EXCEPTION_CHK);
  3048. return;
  3049. }
  3050. if(!BIT_F(word2))
  3051. FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
  3052. else
  3053. FLAG_C = upper_bound - compare;
  3054. FLAG_C = CFLAG_16(FLAG_C);
  3055. if(COND_CS() && BIT_B(word2))
  3056. m68ki_exception_trap(EXCEPTION_CHK);
  3057. return;
  3058. }
  3059. m68ki_exception_illegal();
  3060. }
  3061. M68KMAKE_OP(chk2cmp2, 32, ., pcdi)
  3062. {
  3063. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3064. {
  3065. uint word2 = OPER_I_16();
  3066. uint compare = REG_DA[(word2 >> 12) & 15];
  3067. uint ea = EA_PCDI_32();
  3068. uint lower_bound = m68ki_read_pcrel_32(ea);
  3069. uint upper_bound = m68ki_read_pcrel_32(ea + 4);
  3070. FLAG_C = compare - lower_bound;
  3071. FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
  3072. FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
  3073. if(COND_CS())
  3074. {
  3075. if(BIT_B(word2))
  3076. m68ki_exception_trap(EXCEPTION_CHK);
  3077. return;
  3078. }
  3079. FLAG_C = upper_bound - compare;
  3080. FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
  3081. if(COND_CS() && BIT_B(word2))
  3082. m68ki_exception_trap(EXCEPTION_CHK);
  3083. return;
  3084. }
  3085. m68ki_exception_illegal();
  3086. }
  3087. M68KMAKE_OP(chk2cmp2, 32, ., pcix)
  3088. {
  3089. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3090. {
  3091. uint word2 = OPER_I_16();
  3092. uint compare = REG_DA[(word2 >> 12) & 15];
  3093. uint ea = EA_PCIX_32();
  3094. uint lower_bound = m68ki_read_pcrel_32(ea);
  3095. uint upper_bound = m68ki_read_pcrel_32(ea + 4);
  3096. FLAG_C = compare - lower_bound;
  3097. FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
  3098. FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
  3099. if(COND_CS())
  3100. {
  3101. if(BIT_B(word2))
  3102. m68ki_exception_trap(EXCEPTION_CHK);
  3103. return;
  3104. }
  3105. FLAG_C = upper_bound - compare;
  3106. FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
  3107. if(COND_CS() && BIT_B(word2))
  3108. m68ki_exception_trap(EXCEPTION_CHK);
  3109. return;
  3110. }
  3111. m68ki_exception_illegal();
  3112. }
  3113. M68KMAKE_OP(chk2cmp2, 32, ., .)
  3114. {
  3115. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3116. {
  3117. uint word2 = OPER_I_16();
  3118. uint compare = REG_DA[(word2 >> 12) & 15];
  3119. uint ea = M68KMAKE_GET_EA_AY_32;
  3120. uint lower_bound = m68ki_read_32(ea);
  3121. uint upper_bound = m68ki_read_32(ea + 4);
  3122. FLAG_C = compare - lower_bound;
  3123. FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
  3124. FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
  3125. if(COND_CS())
  3126. {
  3127. if(BIT_B(word2))
  3128. m68ki_exception_trap(EXCEPTION_CHK);
  3129. return;
  3130. }
  3131. FLAG_C = upper_bound - compare;
  3132. FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
  3133. if(COND_CS() && BIT_B(word2))
  3134. m68ki_exception_trap(EXCEPTION_CHK);
  3135. return;
  3136. }
  3137. m68ki_exception_illegal();
  3138. }
  3139. M68KMAKE_OP(clr, 8, ., d)
  3140. {
  3141. DY &= 0xffffff00;
  3142. FLAG_N = NFLAG_CLEAR;
  3143. FLAG_V = VFLAG_CLEAR;
  3144. FLAG_C = CFLAG_CLEAR;
  3145. FLAG_Z = ZFLAG_SET;
  3146. }
  3147. M68KMAKE_OP(clr, 8, ., .)
  3148. {
  3149. m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
  3150. FLAG_N = NFLAG_CLEAR;
  3151. FLAG_V = VFLAG_CLEAR;
  3152. FLAG_C = CFLAG_CLEAR;
  3153. FLAG_Z = ZFLAG_SET;
  3154. }
  3155. M68KMAKE_OP(clr, 16, ., d)
  3156. {
  3157. DY &= 0xffff0000;
  3158. FLAG_N = NFLAG_CLEAR;
  3159. FLAG_V = VFLAG_CLEAR;
  3160. FLAG_C = CFLAG_CLEAR;
  3161. FLAG_Z = ZFLAG_SET;
  3162. }
  3163. M68KMAKE_OP(clr, 16, ., .)
  3164. {
  3165. m68ki_write_16(M68KMAKE_GET_EA_AY_16, 0);
  3166. FLAG_N = NFLAG_CLEAR;
  3167. FLAG_V = VFLAG_CLEAR;
  3168. FLAG_C = CFLAG_CLEAR;
  3169. FLAG_Z = ZFLAG_SET;
  3170. }
  3171. M68KMAKE_OP(clr, 32, ., d)
  3172. {
  3173. DY = 0;
  3174. FLAG_N = NFLAG_CLEAR;
  3175. FLAG_V = VFLAG_CLEAR;
  3176. FLAG_C = CFLAG_CLEAR;
  3177. FLAG_Z = ZFLAG_SET;
  3178. }
  3179. M68KMAKE_OP(clr, 32, ., .)
  3180. {
  3181. m68ki_write_32(M68KMAKE_GET_EA_AY_32, 0);
  3182. FLAG_N = NFLAG_CLEAR;
  3183. FLAG_V = VFLAG_CLEAR;
  3184. FLAG_C = CFLAG_CLEAR;
  3185. FLAG_Z = ZFLAG_SET;
  3186. }
  3187. M68KMAKE_OP(cmp, 8, ., d)
  3188. {
  3189. uint src = MASK_OUT_ABOVE_8(DY);
  3190. uint dst = MASK_OUT_ABOVE_8(DX);
  3191. uint res = dst - src;
  3192. FLAG_N = NFLAG_8(res);
  3193. FLAG_Z = MASK_OUT_ABOVE_8(res);
  3194. FLAG_V = VFLAG_SUB_8(src, dst, res);
  3195. FLAG_C = CFLAG_8(res);
  3196. }
  3197. M68KMAKE_OP(cmp, 8, ., .)
  3198. {
  3199. uint src = M68KMAKE_GET_OPER_AY_8;
  3200. uint dst = MASK_OUT_ABOVE_8(DX);
  3201. uint res = dst - src;
  3202. FLAG_N = NFLAG_8(res);
  3203. FLAG_Z = MASK_OUT_ABOVE_8(res);
  3204. FLAG_V = VFLAG_SUB_8(src, dst, res);
  3205. FLAG_C = CFLAG_8(res);
  3206. }
  3207. M68KMAKE_OP(cmp, 16, ., d)
  3208. {
  3209. uint src = MASK_OUT_ABOVE_16(DY);
  3210. uint dst = MASK_OUT_ABOVE_16(DX);
  3211. uint res = dst - src;
  3212. FLAG_N = NFLAG_16(res);
  3213. FLAG_Z = MASK_OUT_ABOVE_16(res);
  3214. FLAG_V = VFLAG_SUB_16(src, dst, res);
  3215. FLAG_C = CFLAG_16(res);
  3216. }
  3217. M68KMAKE_OP(cmp, 16, ., a)
  3218. {
  3219. uint src = MASK_OUT_ABOVE_16(AY);
  3220. uint dst = MASK_OUT_ABOVE_16(DX);
  3221. uint res = dst - src;
  3222. FLAG_N = NFLAG_16(res);
  3223. FLAG_Z = MASK_OUT_ABOVE_16(res);
  3224. FLAG_V = VFLAG_SUB_16(src, dst, res);
  3225. FLAG_C = CFLAG_16(res);
  3226. }
  3227. M68KMAKE_OP(cmp, 16, ., .)
  3228. {
  3229. uint src = M68KMAKE_GET_OPER_AY_16;
  3230. uint dst = MASK_OUT_ABOVE_16(DX);
  3231. uint res = dst - src;
  3232. FLAG_N = NFLAG_16(res);
  3233. FLAG_Z = MASK_OUT_ABOVE_16(res);
  3234. FLAG_V = VFLAG_SUB_16(src, dst, res);
  3235. FLAG_C = CFLAG_16(res);
  3236. }
  3237. M68KMAKE_OP(cmp, 32, ., d)
  3238. {
  3239. uint src = DY;
  3240. uint dst = DX;
  3241. uint res = dst - src;
  3242. FLAG_N = NFLAG_32(res);
  3243. FLAG_Z = MASK_OUT_ABOVE_32(res);
  3244. FLAG_V = VFLAG_SUB_32(src, dst, res);
  3245. FLAG_C = CFLAG_SUB_32(src, dst, res);
  3246. }
  3247. M68KMAKE_OP(cmp, 32, ., a)
  3248. {
  3249. uint src = AY;
  3250. uint dst = DX;
  3251. uint res = dst - src;
  3252. FLAG_N = NFLAG_32(res);
  3253. FLAG_Z = MASK_OUT_ABOVE_32(res);
  3254. FLAG_V = VFLAG_SUB_32(src, dst, res);
  3255. FLAG_C = CFLAG_SUB_32(src, dst, res);
  3256. }
  3257. M68KMAKE_OP(cmp, 32, ., .)
  3258. {
  3259. uint src = M68KMAKE_GET_OPER_AY_32;
  3260. uint dst = DX;
  3261. uint res = dst - src;
  3262. FLAG_N = NFLAG_32(res);
  3263. FLAG_Z = MASK_OUT_ABOVE_32(res);
  3264. FLAG_V = VFLAG_SUB_32(src, dst, res);
  3265. FLAG_C = CFLAG_SUB_32(src, dst, res);
  3266. }
  3267. M68KMAKE_OP(cmpa, 16, ., d)
  3268. {
  3269. uint src = MAKE_INT_16(DY);
  3270. uint dst = AX;
  3271. uint res = dst - src;
  3272. FLAG_N = NFLAG_32(res);
  3273. FLAG_Z = MASK_OUT_ABOVE_32(res);
  3274. FLAG_V = VFLAG_SUB_32(src, dst, res);
  3275. FLAG_C = CFLAG_SUB_32(src, dst, res);
  3276. }
  3277. M68KMAKE_OP(cmpa, 16, ., a)
  3278. {
  3279. uint src = MAKE_INT_16(AY);
  3280. uint dst = AX;
  3281. uint res = dst - src;
  3282. FLAG_N = NFLAG_32(res);
  3283. FLAG_Z = MASK_OUT_ABOVE_32(res);
  3284. FLAG_V = VFLAG_SUB_32(src, dst, res);
  3285. FLAG_C = CFLAG_SUB_32(src, dst, res);
  3286. }
  3287. M68KMAKE_OP(cmpa, 16, ., .)
  3288. {
  3289. uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
  3290. uint dst = AX;
  3291. uint res = dst - src;
  3292. FLAG_N = NFLAG_32(res);
  3293. FLAG_Z = MASK_OUT_ABOVE_32(res);
  3294. FLAG_V = VFLAG_SUB_32(src, dst, res);
  3295. FLAG_C = CFLAG_SUB_32(src, dst, res);
  3296. }
  3297. M68KMAKE_OP(cmpa, 32, ., d)
  3298. {
  3299. uint src = DY;
  3300. uint dst = AX;
  3301. uint res = dst - src;
  3302. FLAG_N = NFLAG_32(res);
  3303. FLAG_Z = MASK_OUT_ABOVE_32(res);
  3304. FLAG_V = VFLAG_SUB_32(src, dst, res);
  3305. FLAG_C = CFLAG_SUB_32(src, dst, res);
  3306. }
  3307. M68KMAKE_OP(cmpa, 32, ., a)
  3308. {
  3309. uint src = AY;
  3310. uint dst = AX;
  3311. uint res = dst - src;
  3312. FLAG_N = NFLAG_32(res);
  3313. FLAG_Z = MASK_OUT_ABOVE_32(res);
  3314. FLAG_V = VFLAG_SUB_32(src, dst, res);
  3315. FLAG_C = CFLAG_SUB_32(src, dst, res);
  3316. }
  3317. M68KMAKE_OP(cmpa, 32, ., .)
  3318. {
  3319. uint src = M68KMAKE_GET_OPER_AY_32;
  3320. uint dst = AX;
  3321. uint res = dst - src;
  3322. FLAG_N = NFLAG_32(res);
  3323. FLAG_Z = MASK_OUT_ABOVE_32(res);
  3324. FLAG_V = VFLAG_SUB_32(src, dst, res);
  3325. FLAG_C = CFLAG_SUB_32(src, dst, res);
  3326. }
  3327. M68KMAKE_OP(cmpi, 8, ., d)
  3328. {
  3329. uint src = OPER_I_8();
  3330. uint dst = MASK_OUT_ABOVE_8(DY);
  3331. uint res = dst - src;
  3332. FLAG_N = NFLAG_8(res);
  3333. FLAG_Z = MASK_OUT_ABOVE_8(res);
  3334. FLAG_V = VFLAG_SUB_8(src, dst, res);
  3335. FLAG_C = CFLAG_8(res);
  3336. }
  3337. M68KMAKE_OP(cmpi, 8, ., .)
  3338. {
  3339. uint src = OPER_I_8();
  3340. uint dst = M68KMAKE_GET_OPER_AY_8;
  3341. uint res = dst - src;
  3342. FLAG_N = NFLAG_8(res);
  3343. FLAG_Z = MASK_OUT_ABOVE_8(res);
  3344. FLAG_V = VFLAG_SUB_8(src, dst, res);
  3345. FLAG_C = CFLAG_8(res);
  3346. }
  3347. M68KMAKE_OP(cmpi, 8, ., pcdi)
  3348. {
  3349. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3350. {
  3351. uint src = OPER_I_8();
  3352. uint dst = OPER_PCDI_8();
  3353. uint res = dst - src;
  3354. FLAG_N = NFLAG_8(res);
  3355. FLAG_Z = MASK_OUT_ABOVE_8(res);
  3356. FLAG_V = VFLAG_SUB_8(src, dst, res);
  3357. FLAG_C = CFLAG_8(res);
  3358. return;
  3359. }
  3360. m68ki_exception_illegal();
  3361. }
  3362. M68KMAKE_OP(cmpi, 8, ., pcix)
  3363. {
  3364. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3365. {
  3366. uint src = OPER_I_8();
  3367. uint dst = OPER_PCIX_8();
  3368. uint res = dst - src;
  3369. FLAG_N = NFLAG_8(res);
  3370. FLAG_Z = MASK_OUT_ABOVE_8(res);
  3371. FLAG_V = VFLAG_SUB_8(src, dst, res);
  3372. FLAG_C = CFLAG_8(res);
  3373. return;
  3374. }
  3375. m68ki_exception_illegal();
  3376. }
  3377. M68KMAKE_OP(cmpi, 16, ., d)
  3378. {
  3379. uint src = OPER_I_16();
  3380. uint dst = MASK_OUT_ABOVE_16(DY);
  3381. uint res = dst - src;
  3382. FLAG_N = NFLAG_16(res);
  3383. FLAG_Z = MASK_OUT_ABOVE_16(res);
  3384. FLAG_V = VFLAG_SUB_16(src, dst, res);
  3385. FLAG_C = CFLAG_16(res);
  3386. }
  3387. M68KMAKE_OP(cmpi, 16, ., .)
  3388. {
  3389. uint src = OPER_I_16();
  3390. uint dst = M68KMAKE_GET_OPER_AY_16;
  3391. uint res = dst - src;
  3392. FLAG_N = NFLAG_16(res);
  3393. FLAG_Z = MASK_OUT_ABOVE_16(res);
  3394. FLAG_V = VFLAG_SUB_16(src, dst, res);
  3395. FLAG_C = CFLAG_16(res);
  3396. }
  3397. M68KMAKE_OP(cmpi, 16, ., pcdi)
  3398. {
  3399. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3400. {
  3401. uint src = OPER_I_16();
  3402. uint dst = OPER_PCDI_16();
  3403. uint res = dst - src;
  3404. FLAG_N = NFLAG_16(res);
  3405. FLAG_Z = MASK_OUT_ABOVE_16(res);
  3406. FLAG_V = VFLAG_SUB_16(src, dst, res);
  3407. FLAG_C = CFLAG_16(res);
  3408. return;
  3409. }
  3410. m68ki_exception_illegal();
  3411. }
  3412. M68KMAKE_OP(cmpi, 16, ., pcix)
  3413. {
  3414. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3415. {
  3416. uint src = OPER_I_16();
  3417. uint dst = OPER_PCIX_16();
  3418. uint res = dst - src;
  3419. FLAG_N = NFLAG_16(res);
  3420. FLAG_Z = MASK_OUT_ABOVE_16(res);
  3421. FLAG_V = VFLAG_SUB_16(src, dst, res);
  3422. FLAG_C = CFLAG_16(res);
  3423. return;
  3424. }
  3425. m68ki_exception_illegal();
  3426. }
  3427. M68KMAKE_OP(cmpi, 32, ., d)
  3428. {
  3429. uint src = OPER_I_32();
  3430. uint dst = DY;
  3431. uint res = dst - src;
  3432. m68ki_cmpild_callback(src, REG_IR & 7); /* auto-disable (see m68kcpu.h) */
  3433. FLAG_N = NFLAG_32(res);
  3434. FLAG_Z = MASK_OUT_ABOVE_32(res);
  3435. FLAG_V = VFLAG_SUB_32(src, dst, res);
  3436. FLAG_C = CFLAG_SUB_32(src, dst, res);
  3437. }
  3438. M68KMAKE_OP(cmpi, 32, ., .)
  3439. {
  3440. uint src = OPER_I_32();
  3441. uint dst = M68KMAKE_GET_OPER_AY_32;
  3442. uint res = dst - src;
  3443. FLAG_N = NFLAG_32(res);
  3444. FLAG_Z = MASK_OUT_ABOVE_32(res);
  3445. FLAG_V = VFLAG_SUB_32(src, dst, res);
  3446. FLAG_C = CFLAG_SUB_32(src, dst, res);
  3447. }
  3448. M68KMAKE_OP(cmpi, 32, ., pcdi)
  3449. {
  3450. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3451. {
  3452. uint src = OPER_I_32();
  3453. uint dst = OPER_PCDI_32();
  3454. uint res = dst - src;
  3455. FLAG_N = NFLAG_32(res);
  3456. FLAG_Z = MASK_OUT_ABOVE_32(res);
  3457. FLAG_V = VFLAG_SUB_32(src, dst, res);
  3458. FLAG_C = CFLAG_SUB_32(src, dst, res);
  3459. return;
  3460. }
  3461. m68ki_exception_illegal();
  3462. }
  3463. M68KMAKE_OP(cmpi, 32, ., pcix)
  3464. {
  3465. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3466. {
  3467. uint src = OPER_I_32();
  3468. uint dst = OPER_PCIX_32();
  3469. uint res = dst - src;
  3470. FLAG_N = NFLAG_32(res);
  3471. FLAG_Z = MASK_OUT_ABOVE_32(res);
  3472. FLAG_V = VFLAG_SUB_32(src, dst, res);
  3473. FLAG_C = CFLAG_SUB_32(src, dst, res);
  3474. return;
  3475. }
  3476. m68ki_exception_illegal();
  3477. }
  3478. M68KMAKE_OP(cmpm, 8, ., ax7)
  3479. {
  3480. uint src = OPER_AY_PI_8();
  3481. uint dst = OPER_A7_PI_8();
  3482. uint res = dst - src;
  3483. FLAG_N = NFLAG_8(res);
  3484. FLAG_Z = MASK_OUT_ABOVE_8(res);
  3485. FLAG_V = VFLAG_SUB_8(src, dst, res);
  3486. FLAG_C = CFLAG_8(res);
  3487. }
  3488. M68KMAKE_OP(cmpm, 8, ., ay7)
  3489. {
  3490. uint src = OPER_A7_PI_8();
  3491. uint dst = OPER_AX_PI_8();
  3492. uint res = dst - src;
  3493. FLAG_N = NFLAG_8(res);
  3494. FLAG_Z = MASK_OUT_ABOVE_8(res);
  3495. FLAG_V = VFLAG_SUB_8(src, dst, res);
  3496. FLAG_C = CFLAG_8(res);
  3497. }
  3498. M68KMAKE_OP(cmpm, 8, ., axy7)
  3499. {
  3500. uint src = OPER_A7_PI_8();
  3501. uint dst = OPER_A7_PI_8();
  3502. uint res = dst - src;
  3503. FLAG_N = NFLAG_8(res);
  3504. FLAG_Z = MASK_OUT_ABOVE_8(res);
  3505. FLAG_V = VFLAG_SUB_8(src, dst, res);
  3506. FLAG_C = CFLAG_8(res);
  3507. }
  3508. M68KMAKE_OP(cmpm, 8, ., .)
  3509. {
  3510. uint src = OPER_AY_PI_8();
  3511. uint dst = OPER_AX_PI_8();
  3512. uint res = dst - src;
  3513. FLAG_N = NFLAG_8(res);
  3514. FLAG_Z = MASK_OUT_ABOVE_8(res);
  3515. FLAG_V = VFLAG_SUB_8(src, dst, res);
  3516. FLAG_C = CFLAG_8(res);
  3517. }
  3518. M68KMAKE_OP(cmpm, 16, ., .)
  3519. {
  3520. uint src = OPER_AY_PI_16();
  3521. uint dst = OPER_AX_PI_16();
  3522. uint res = dst - src;
  3523. FLAG_N = NFLAG_16(res);
  3524. FLAG_Z = MASK_OUT_ABOVE_16(res);
  3525. FLAG_V = VFLAG_SUB_16(src, dst, res);
  3526. FLAG_C = CFLAG_16(res);
  3527. }
  3528. M68KMAKE_OP(cmpm, 32, ., .)
  3529. {
  3530. uint src = OPER_AY_PI_32();
  3531. uint dst = OPER_AX_PI_32();
  3532. uint res = dst - src;
  3533. FLAG_N = NFLAG_32(res);
  3534. FLAG_Z = MASK_OUT_ABOVE_32(res);
  3535. FLAG_V = VFLAG_SUB_32(src, dst, res);
  3536. FLAG_C = CFLAG_SUB_32(src, dst, res);
  3537. }
  3538. M68KMAKE_OP(cpbcc, 32, ., .)
  3539. {
  3540. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3541. {
  3542. M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
  3543. m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
  3544. m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
  3545. return;
  3546. }
  3547. m68ki_exception_1111();
  3548. }
  3549. M68KMAKE_OP(cpdbcc, 32, ., .)
  3550. {
  3551. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3552. {
  3553. M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
  3554. m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
  3555. m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
  3556. return;
  3557. }
  3558. m68ki_exception_1111();
  3559. }
  3560. M68KMAKE_OP(cpgen, 32, ., .)
  3561. {
  3562. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3563. {
  3564. M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
  3565. m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
  3566. m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
  3567. return;
  3568. }
  3569. m68ki_exception_1111();
  3570. }
  3571. M68KMAKE_OP(cpscc, 32, ., .)
  3572. {
  3573. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3574. {
  3575. M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
  3576. m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
  3577. m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
  3578. return;
  3579. }
  3580. m68ki_exception_1111();
  3581. }
  3582. M68KMAKE_OP(cptrapcc, 32, ., .)
  3583. {
  3584. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3585. {
  3586. M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
  3587. m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
  3588. m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
  3589. return;
  3590. }
  3591. m68ki_exception_1111();
  3592. }
  3593. M68KMAKE_OP(dbt, 16, ., .)
  3594. {
  3595. REG_PC += 2;
  3596. }
  3597. M68KMAKE_OP(dbf, 16, ., .)
  3598. {
  3599. uint* r_dst = &DY;
  3600. uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
  3601. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  3602. if(res != 0xffff)
  3603. {
  3604. uint offset = OPER_I_16();
  3605. REG_PC -= 2;
  3606. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  3607. m68ki_branch_16(offset);
  3608. USE_CYCLES(CYC_DBCC_F_NOEXP);
  3609. return;
  3610. }
  3611. REG_PC += 2;
  3612. USE_CYCLES(CYC_DBCC_F_EXP);
  3613. }
  3614. M68KMAKE_OP(dbcc, 16, ., .)
  3615. {
  3616. if(M68KMAKE_NOT_CC)
  3617. {
  3618. uint* r_dst = &DY;
  3619. uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
  3620. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  3621. if(res != 0xffff)
  3622. {
  3623. uint offset = OPER_I_16();
  3624. REG_PC -= 2;
  3625. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  3626. m68ki_branch_16(offset);
  3627. USE_CYCLES(CYC_DBCC_F_NOEXP);
  3628. return;
  3629. }
  3630. REG_PC += 2;
  3631. USE_CYCLES(CYC_DBCC_F_EXP);
  3632. return;
  3633. }
  3634. REG_PC += 2;
  3635. }
  3636. M68KMAKE_OP(divs, 16, ., d)
  3637. {
  3638. uint* r_dst = &DX;
  3639. sint src = MAKE_INT_16(DY);
  3640. sint quotient;
  3641. sint remainder;
  3642. if(src != 0)
  3643. {
  3644. if((uint32)*r_dst == 0x80000000 && src == -1)
  3645. {
  3646. FLAG_Z = 0;
  3647. FLAG_N = NFLAG_CLEAR;
  3648. FLAG_V = VFLAG_CLEAR;
  3649. FLAG_C = CFLAG_CLEAR;
  3650. *r_dst = 0;
  3651. return;
  3652. }
  3653. quotient = MAKE_INT_32(*r_dst) / src;
  3654. remainder = MAKE_INT_32(*r_dst) % src;
  3655. if(quotient == MAKE_INT_16(quotient))
  3656. {
  3657. FLAG_Z = quotient;
  3658. FLAG_N = NFLAG_16(quotient);
  3659. FLAG_V = VFLAG_CLEAR;
  3660. FLAG_C = CFLAG_CLEAR;
  3661. *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
  3662. return;
  3663. }
  3664. FLAG_V = VFLAG_SET;
  3665. return;
  3666. }
  3667. m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
  3668. }
  3669. M68KMAKE_OP(divs, 16, ., .)
  3670. {
  3671. uint* r_dst = &DX;
  3672. sint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
  3673. sint quotient;
  3674. sint remainder;
  3675. if(src != 0)
  3676. {
  3677. if((uint32)*r_dst == 0x80000000 && src == -1)
  3678. {
  3679. FLAG_Z = 0;
  3680. FLAG_N = NFLAG_CLEAR;
  3681. FLAG_V = VFLAG_CLEAR;
  3682. FLAG_C = CFLAG_CLEAR;
  3683. *r_dst = 0;
  3684. return;
  3685. }
  3686. quotient = MAKE_INT_32(*r_dst) / src;
  3687. remainder = MAKE_INT_32(*r_dst) % src;
  3688. if(quotient == MAKE_INT_16(quotient))
  3689. {
  3690. FLAG_Z = quotient;
  3691. FLAG_N = NFLAG_16(quotient);
  3692. FLAG_V = VFLAG_CLEAR;
  3693. FLAG_C = CFLAG_CLEAR;
  3694. *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
  3695. return;
  3696. }
  3697. FLAG_V = VFLAG_SET;
  3698. return;
  3699. }
  3700. m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
  3701. }
  3702. M68KMAKE_OP(divu, 16, ., d)
  3703. {
  3704. uint* r_dst = &DX;
  3705. uint src = MASK_OUT_ABOVE_16(DY);
  3706. if(src != 0)
  3707. {
  3708. uint quotient = *r_dst / src;
  3709. uint remainder = *r_dst % src;
  3710. if(quotient < 0x10000)
  3711. {
  3712. FLAG_Z = quotient;
  3713. FLAG_N = NFLAG_16(quotient);
  3714. FLAG_V = VFLAG_CLEAR;
  3715. FLAG_C = CFLAG_CLEAR;
  3716. *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
  3717. return;
  3718. }
  3719. FLAG_V = VFLAG_SET;
  3720. return;
  3721. }
  3722. m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
  3723. }
  3724. M68KMAKE_OP(divu, 16, ., .)
  3725. {
  3726. uint* r_dst = &DX;
  3727. uint src = M68KMAKE_GET_OPER_AY_16;
  3728. if(src != 0)
  3729. {
  3730. uint quotient = *r_dst / src;
  3731. uint remainder = *r_dst % src;
  3732. if(quotient < 0x10000)
  3733. {
  3734. FLAG_Z = quotient;
  3735. FLAG_N = NFLAG_16(quotient);
  3736. FLAG_V = VFLAG_CLEAR;
  3737. FLAG_C = CFLAG_CLEAR;
  3738. *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
  3739. return;
  3740. }
  3741. FLAG_V = VFLAG_SET;
  3742. return;
  3743. }
  3744. m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
  3745. }
  3746. M68KMAKE_OP(divl, 32, ., d)
  3747. {
  3748. #if M68K_USE_64_BIT
  3749. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3750. {
  3751. uint word2 = OPER_I_16();
  3752. uint64 divisor = DY;
  3753. uint64 dividend = 0;
  3754. uint64 quotient = 0;
  3755. uint64 remainder = 0;
  3756. if(divisor != 0)
  3757. {
  3758. if(BIT_A(word2)) /* 64 bit */
  3759. {
  3760. dividend = REG_D[word2 & 7];
  3761. dividend <<= 32;
  3762. dividend |= REG_D[(word2 >> 12) & 7];
  3763. if(BIT_B(word2)) /* signed */
  3764. {
  3765. quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
  3766. remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
  3767. if((sint64)quotient != (sint64)((sint32)quotient))
  3768. {
  3769. FLAG_V = VFLAG_SET;
  3770. return;
  3771. }
  3772. }
  3773. else /* unsigned */
  3774. {
  3775. quotient = dividend / divisor;
  3776. if(quotient > 0xffffffff)
  3777. {
  3778. FLAG_V = VFLAG_SET;
  3779. return;
  3780. }
  3781. remainder = dividend % divisor;
  3782. }
  3783. }
  3784. else /* 32 bit */
  3785. {
  3786. dividend = REG_D[(word2 >> 12) & 7];
  3787. if(BIT_B(word2)) /* signed */
  3788. {
  3789. quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
  3790. remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
  3791. }
  3792. else /* unsigned */
  3793. {
  3794. quotient = dividend / divisor;
  3795. remainder = dividend % divisor;
  3796. }
  3797. }
  3798. REG_D[word2 & 7] = remainder;
  3799. REG_D[(word2 >> 12) & 7] = quotient;
  3800. FLAG_N = NFLAG_32(quotient);
  3801. FLAG_Z = quotient;
  3802. FLAG_V = VFLAG_CLEAR;
  3803. FLAG_C = CFLAG_CLEAR;
  3804. return;
  3805. }
  3806. m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
  3807. return;
  3808. }
  3809. m68ki_exception_illegal();
  3810. #else
  3811. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3812. {
  3813. uint word2 = OPER_I_16();
  3814. uint divisor = DY;
  3815. uint dividend_hi = REG_D[word2 & 7];
  3816. uint dividend_lo = REG_D[(word2 >> 12) & 7];
  3817. uint quotient = 0;
  3818. uint remainder = 0;
  3819. uint dividend_neg = 0;
  3820. uint divisor_neg = 0;
  3821. sint i;
  3822. uint overflow;
  3823. if(divisor != 0)
  3824. {
  3825. /* quad / long : long quotient, long remainder */
  3826. if(BIT_A(word2))
  3827. {
  3828. if(BIT_B(word2)) /* signed */
  3829. {
  3830. /* special case in signed divide */
  3831. if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
  3832. {
  3833. REG_D[word2 & 7] = 0;
  3834. REG_D[(word2 >> 12) & 7] = 0x80000000;
  3835. FLAG_N = NFLAG_SET;
  3836. FLAG_Z = ZFLAG_CLEAR;
  3837. FLAG_V = VFLAG_CLEAR;
  3838. FLAG_C = CFLAG_CLEAR;
  3839. return;
  3840. }
  3841. if(GET_MSB_32(dividend_hi))
  3842. {
  3843. dividend_neg = 1;
  3844. dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
  3845. dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
  3846. }
  3847. if(GET_MSB_32(divisor))
  3848. {
  3849. divisor_neg = 1;
  3850. divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
  3851. }
  3852. }
  3853. /* if the upper long is greater than the divisor, we're overflowing. */
  3854. if(dividend_hi >= divisor)
  3855. {
  3856. FLAG_V = VFLAG_SET;
  3857. return;
  3858. }
  3859. for(i = 31; i >= 0; i--)
  3860. {
  3861. quotient <<= 1;
  3862. remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
  3863. if(remainder >= divisor)
  3864. {
  3865. remainder -= divisor;
  3866. quotient++;
  3867. }
  3868. }
  3869. for(i = 31; i >= 0; i--)
  3870. {
  3871. quotient <<= 1;
  3872. overflow = GET_MSB_32(remainder);
  3873. remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
  3874. if(remainder >= divisor || overflow)
  3875. {
  3876. remainder -= divisor;
  3877. quotient++;
  3878. }
  3879. }
  3880. if(BIT_B(word2)) /* signed */
  3881. {
  3882. if(quotient > 0x7fffffff)
  3883. {
  3884. FLAG_V = VFLAG_SET;
  3885. return;
  3886. }
  3887. if(dividend_neg)
  3888. {
  3889. remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
  3890. quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
  3891. }
  3892. if(divisor_neg)
  3893. quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
  3894. }
  3895. REG_D[word2 & 7] = remainder;
  3896. REG_D[(word2 >> 12) & 7] = quotient;
  3897. FLAG_N = NFLAG_32(quotient);
  3898. FLAG_Z = quotient;
  3899. FLAG_V = VFLAG_CLEAR;
  3900. FLAG_C = CFLAG_CLEAR;
  3901. return;
  3902. }
  3903. /* long / long: long quotient, maybe long remainder */
  3904. if(BIT_B(word2)) /* signed */
  3905. {
  3906. /* Special case in divide */
  3907. if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
  3908. {
  3909. FLAG_N = NFLAG_SET;
  3910. FLAG_Z = ZFLAG_CLEAR;
  3911. FLAG_V = VFLAG_CLEAR;
  3912. FLAG_C = CFLAG_CLEAR;
  3913. REG_D[(word2 >> 12) & 7] = 0x80000000;
  3914. REG_D[word2 & 7] = 0;
  3915. return;
  3916. }
  3917. REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
  3918. quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
  3919. }
  3920. else
  3921. {
  3922. REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
  3923. quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
  3924. }
  3925. FLAG_N = NFLAG_32(quotient);
  3926. FLAG_Z = quotient;
  3927. FLAG_V = VFLAG_CLEAR;
  3928. FLAG_C = CFLAG_CLEAR;
  3929. return;
  3930. }
  3931. m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
  3932. return;
  3933. }
  3934. m68ki_exception_illegal();
  3935. #endif
  3936. }
  3937. M68KMAKE_OP(divl, 32, ., .)
  3938. {
  3939. #if M68K_USE_64_BIT
  3940. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3941. {
  3942. uint word2 = OPER_I_16();
  3943. uint64 divisor = M68KMAKE_GET_OPER_AY_32;
  3944. uint64 dividend = 0;
  3945. uint64 quotient = 0;
  3946. uint64 remainder = 0;
  3947. if(divisor != 0)
  3948. {
  3949. if(BIT_A(word2)) /* 64 bit */
  3950. {
  3951. dividend = REG_D[word2 & 7];
  3952. dividend <<= 32;
  3953. dividend |= REG_D[(word2 >> 12) & 7];
  3954. if(BIT_B(word2)) /* signed */
  3955. {
  3956. quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
  3957. remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
  3958. if((sint64)quotient != (sint64)((sint32)quotient))
  3959. {
  3960. FLAG_V = VFLAG_SET;
  3961. return;
  3962. }
  3963. }
  3964. else /* unsigned */
  3965. {
  3966. quotient = dividend / divisor;
  3967. if(quotient > 0xffffffff)
  3968. {
  3969. FLAG_V = VFLAG_SET;
  3970. return;
  3971. }
  3972. remainder = dividend % divisor;
  3973. }
  3974. }
  3975. else /* 32 bit */
  3976. {
  3977. dividend = REG_D[(word2 >> 12) & 7];
  3978. if(BIT_B(word2)) /* signed */
  3979. {
  3980. quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
  3981. remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
  3982. }
  3983. else /* unsigned */
  3984. {
  3985. quotient = dividend / divisor;
  3986. remainder = dividend % divisor;
  3987. }
  3988. }
  3989. REG_D[word2 & 7] = remainder;
  3990. REG_D[(word2 >> 12) & 7] = quotient;
  3991. FLAG_N = NFLAG_32(quotient);
  3992. FLAG_Z = quotient;
  3993. FLAG_V = VFLAG_CLEAR;
  3994. FLAG_C = CFLAG_CLEAR;
  3995. return;
  3996. }
  3997. m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
  3998. return;
  3999. }
  4000. m68ki_exception_illegal();
  4001. #else
  4002. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  4003. {
  4004. uint word2 = OPER_I_16();
  4005. uint divisor = M68KMAKE_GET_OPER_AY_32;
  4006. uint dividend_hi = REG_D[word2 & 7];
  4007. uint dividend_lo = REG_D[(word2 >> 12) & 7];
  4008. uint quotient = 0;
  4009. uint remainder = 0;
  4010. uint dividend_neg = 0;
  4011. uint divisor_neg = 0;
  4012. sint i;
  4013. uint overflow;
  4014. if(divisor != 0)
  4015. {
  4016. /* quad / long : long quotient, long remainder */
  4017. if(BIT_A(word2))
  4018. {
  4019. if(BIT_B(word2)) /* signed */
  4020. {
  4021. /* special case in signed divide */
  4022. if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
  4023. {
  4024. REG_D[word2 & 7] = 0;
  4025. REG_D[(word2 >> 12) & 7] = 0x80000000;
  4026. FLAG_N = NFLAG_SET;
  4027. FLAG_Z = ZFLAG_CLEAR;
  4028. FLAG_V = VFLAG_CLEAR;
  4029. FLAG_C = CFLAG_CLEAR;
  4030. return;
  4031. }
  4032. if(GET_MSB_32(dividend_hi))
  4033. {
  4034. dividend_neg = 1;
  4035. dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
  4036. dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
  4037. }
  4038. if(GET_MSB_32(divisor))
  4039. {
  4040. divisor_neg = 1;
  4041. divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
  4042. }
  4043. }
  4044. /* if the upper long is greater than the divisor, we're overflowing. */
  4045. if(dividend_hi >= divisor)
  4046. {
  4047. FLAG_V = VFLAG_SET;
  4048. return;
  4049. }
  4050. for(i = 31; i >= 0; i--)
  4051. {
  4052. quotient <<= 1;
  4053. remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
  4054. if(remainder >= divisor)
  4055. {
  4056. remainder -= divisor;
  4057. quotient++;
  4058. }
  4059. }
  4060. for(i = 31; i >= 0; i--)
  4061. {
  4062. quotient <<= 1;
  4063. overflow = GET_MSB_32(remainder);
  4064. remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
  4065. if(remainder >= divisor || overflow)
  4066. {
  4067. remainder -= divisor;
  4068. quotient++;
  4069. }
  4070. }
  4071. if(BIT_B(word2)) /* signed */
  4072. {
  4073. if(quotient > 0x7fffffff)
  4074. {
  4075. FLAG_V = VFLAG_SET;
  4076. return;
  4077. }
  4078. if(dividend_neg)
  4079. {
  4080. remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
  4081. quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
  4082. }
  4083. if(divisor_neg)
  4084. quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
  4085. }
  4086. REG_D[word2 & 7] = remainder;
  4087. REG_D[(word2 >> 12) & 7] = quotient;
  4088. FLAG_N = NFLAG_32(quotient);
  4089. FLAG_Z = quotient;
  4090. FLAG_V = VFLAG_CLEAR;
  4091. FLAG_C = CFLAG_CLEAR;
  4092. return;
  4093. }
  4094. /* long / long: long quotient, maybe long remainder */
  4095. if(BIT_B(word2)) /* signed */
  4096. {
  4097. /* Special case in divide */
  4098. if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
  4099. {
  4100. FLAG_N = NFLAG_SET;
  4101. FLAG_Z = ZFLAG_CLEAR;
  4102. FLAG_V = VFLAG_CLEAR;
  4103. FLAG_C = CFLAG_CLEAR;
  4104. REG_D[(word2 >> 12) & 7] = 0x80000000;
  4105. REG_D[word2 & 7] = 0;
  4106. return;
  4107. }
  4108. REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
  4109. quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
  4110. }
  4111. else
  4112. {
  4113. REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
  4114. quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
  4115. }
  4116. FLAG_N = NFLAG_32(quotient);
  4117. FLAG_Z = quotient;
  4118. FLAG_V = VFLAG_CLEAR;
  4119. FLAG_C = CFLAG_CLEAR;
  4120. return;
  4121. }
  4122. m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
  4123. return;
  4124. }
  4125. m68ki_exception_illegal();
  4126. #endif
  4127. }
  4128. M68KMAKE_OP(eor, 8, ., d)
  4129. {
  4130. uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX));
  4131. FLAG_N = NFLAG_8(res);
  4132. FLAG_Z = res;
  4133. FLAG_C = CFLAG_CLEAR;
  4134. FLAG_V = VFLAG_CLEAR;
  4135. }
  4136. M68KMAKE_OP(eor, 8, ., .)
  4137. {
  4138. uint ea = M68KMAKE_GET_EA_AY_8;
  4139. uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
  4140. m68ki_write_8(ea, res);
  4141. FLAG_N = NFLAG_8(res);
  4142. FLAG_Z = res;
  4143. FLAG_C = CFLAG_CLEAR;
  4144. FLAG_V = VFLAG_CLEAR;
  4145. }
  4146. M68KMAKE_OP(eor, 16, ., d)
  4147. {
  4148. uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX));
  4149. FLAG_N = NFLAG_16(res);
  4150. FLAG_Z = res;
  4151. FLAG_C = CFLAG_CLEAR;
  4152. FLAG_V = VFLAG_CLEAR;
  4153. }
  4154. M68KMAKE_OP(eor, 16, ., .)
  4155. {
  4156. uint ea = M68KMAKE_GET_EA_AY_16;
  4157. uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
  4158. m68ki_write_16(ea, res);
  4159. FLAG_N = NFLAG_16(res);
  4160. FLAG_Z = res;
  4161. FLAG_C = CFLAG_CLEAR;
  4162. FLAG_V = VFLAG_CLEAR;
  4163. }
  4164. M68KMAKE_OP(eor, 32, ., d)
  4165. {
  4166. uint res = DY ^= DX;
  4167. FLAG_N = NFLAG_32(res);
  4168. FLAG_Z = res;
  4169. FLAG_C = CFLAG_CLEAR;
  4170. FLAG_V = VFLAG_CLEAR;
  4171. }
  4172. M68KMAKE_OP(eor, 32, ., .)
  4173. {
  4174. uint ea = M68KMAKE_GET_EA_AY_32;
  4175. uint res = DX ^ m68ki_read_32(ea);
  4176. m68ki_write_32(ea, res);
  4177. FLAG_N = NFLAG_32(res);
  4178. FLAG_Z = res;
  4179. FLAG_C = CFLAG_CLEAR;
  4180. FLAG_V = VFLAG_CLEAR;
  4181. }
  4182. M68KMAKE_OP(eori, 8, ., d)
  4183. {
  4184. uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8());
  4185. FLAG_N = NFLAG_8(res);
  4186. FLAG_Z = res;
  4187. FLAG_C = CFLAG_CLEAR;
  4188. FLAG_V = VFLAG_CLEAR;
  4189. }
  4190. M68KMAKE_OP(eori, 8, ., .)
  4191. {
  4192. uint src = OPER_I_8();
  4193. uint ea = M68KMAKE_GET_EA_AY_8;
  4194. uint res = src ^ m68ki_read_8(ea);
  4195. m68ki_write_8(ea, res);
  4196. FLAG_N = NFLAG_8(res);
  4197. FLAG_Z = res;
  4198. FLAG_C = CFLAG_CLEAR;
  4199. FLAG_V = VFLAG_CLEAR;
  4200. }
  4201. M68KMAKE_OP(eori, 16, ., d)
  4202. {
  4203. uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16());
  4204. FLAG_N = NFLAG_16(res);
  4205. FLAG_Z = res;
  4206. FLAG_C = CFLAG_CLEAR;
  4207. FLAG_V = VFLAG_CLEAR;
  4208. }
  4209. M68KMAKE_OP(eori, 16, ., .)
  4210. {
  4211. uint src = OPER_I_16();
  4212. uint ea = M68KMAKE_GET_EA_AY_16;
  4213. uint res = src ^ m68ki_read_16(ea);
  4214. m68ki_write_16(ea, res);
  4215. FLAG_N = NFLAG_16(res);
  4216. FLAG_Z = res;
  4217. FLAG_C = CFLAG_CLEAR;
  4218. FLAG_V = VFLAG_CLEAR;
  4219. }
  4220. M68KMAKE_OP(eori, 32, ., d)
  4221. {
  4222. uint res = DY ^= OPER_I_32();
  4223. FLAG_N = NFLAG_32(res);
  4224. FLAG_Z = res;
  4225. FLAG_C = CFLAG_CLEAR;
  4226. FLAG_V = VFLAG_CLEAR;
  4227. }
  4228. M68KMAKE_OP(eori, 32, ., .)
  4229. {
  4230. uint src = OPER_I_32();
  4231. uint ea = M68KMAKE_GET_EA_AY_32;
  4232. uint res = src ^ m68ki_read_32(ea);
  4233. m68ki_write_32(ea, res);
  4234. FLAG_N = NFLAG_32(res);
  4235. FLAG_Z = res;
  4236. FLAG_C = CFLAG_CLEAR;
  4237. FLAG_V = VFLAG_CLEAR;
  4238. }
  4239. M68KMAKE_OP(eori, 16, toc, .)
  4240. {
  4241. m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_16());
  4242. }
  4243. M68KMAKE_OP(eori, 16, tos, .)
  4244. {
  4245. if(FLAG_S)
  4246. {
  4247. uint src = OPER_I_16();
  4248. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  4249. m68ki_set_sr(m68ki_get_sr() ^ src);
  4250. return;
  4251. }
  4252. m68ki_exception_privilege_violation();
  4253. }
  4254. M68KMAKE_OP(exg, 32, dd, .)
  4255. {
  4256. uint* reg_a = &DX;
  4257. uint* reg_b = &DY;
  4258. uint tmp = *reg_a;
  4259. *reg_a = *reg_b;
  4260. *reg_b = tmp;
  4261. }
  4262. M68KMAKE_OP(exg, 32, aa, .)
  4263. {
  4264. uint* reg_a = &AX;
  4265. uint* reg_b = &AY;
  4266. uint tmp = *reg_a;
  4267. *reg_a = *reg_b;
  4268. *reg_b = tmp;
  4269. }
  4270. M68KMAKE_OP(exg, 32, da, .)
  4271. {
  4272. uint* reg_a = &DX;
  4273. uint* reg_b = &AY;
  4274. uint tmp = *reg_a;
  4275. *reg_a = *reg_b;
  4276. *reg_b = tmp;
  4277. }
  4278. M68KMAKE_OP(ext, 16, ., .)
  4279. {
  4280. uint* r_dst = &DY;
  4281. *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0);
  4282. FLAG_N = NFLAG_16(*r_dst);
  4283. FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
  4284. FLAG_V = VFLAG_CLEAR;
  4285. FLAG_C = CFLAG_CLEAR;
  4286. }
  4287. M68KMAKE_OP(ext, 32, ., .)
  4288. {
  4289. uint* r_dst = &DY;
  4290. *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0);
  4291. FLAG_N = NFLAG_32(*r_dst);
  4292. FLAG_Z = *r_dst;
  4293. FLAG_V = VFLAG_CLEAR;
  4294. FLAG_C = CFLAG_CLEAR;
  4295. }
  4296. M68KMAKE_OP(extb, 32, ., .)
  4297. {
  4298. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  4299. {
  4300. uint* r_dst = &DY;
  4301. *r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0);
  4302. FLAG_N = NFLAG_32(*r_dst);
  4303. FLAG_Z = *r_dst;
  4304. FLAG_V = VFLAG_CLEAR;
  4305. FLAG_C = CFLAG_CLEAR;
  4306. return;
  4307. }
  4308. m68ki_exception_illegal();
  4309. }
  4310. M68KMAKE_OP(illegal, 0, ., .)
  4311. {
  4312. m68ki_exception_illegal();
  4313. }
  4314. M68KMAKE_OP(jmp, 32, ., .)
  4315. {
  4316. m68ki_jump(M68KMAKE_GET_EA_AY_32);
  4317. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  4318. if(REG_PC == REG_PPC)
  4319. USE_ALL_CYCLES();
  4320. }
  4321. M68KMAKE_OP(jsr, 32, ., .)
  4322. {
  4323. uint ea = M68KMAKE_GET_EA_AY_32;
  4324. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  4325. m68ki_push_32(REG_PC);
  4326. m68ki_jump(ea);
  4327. }
  4328. M68KMAKE_OP(lea, 32, ., .)
  4329. {
  4330. AX = M68KMAKE_GET_EA_AY_32;
  4331. }
  4332. M68KMAKE_OP(link, 16, ., a7)
  4333. {
  4334. REG_A[7] -= 4;
  4335. m68ki_write_32(REG_A[7], REG_A[7]);
  4336. REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
  4337. }
  4338. M68KMAKE_OP(link, 16, ., .)
  4339. {
  4340. uint* r_dst = &AY;
  4341. m68ki_push_32(*r_dst);
  4342. *r_dst = REG_A[7];
  4343. REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
  4344. }
  4345. M68KMAKE_OP(link, 32, ., a7)
  4346. {
  4347. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  4348. {
  4349. REG_A[7] -= 4;
  4350. m68ki_write_32(REG_A[7], REG_A[7]);
  4351. REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
  4352. return;
  4353. }
  4354. m68ki_exception_illegal();
  4355. }
  4356. M68KMAKE_OP(link, 32, ., .)
  4357. {
  4358. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  4359. {
  4360. uint* r_dst = &AY;
  4361. m68ki_push_32(*r_dst);
  4362. *r_dst = REG_A[7];
  4363. REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
  4364. return;
  4365. }
  4366. m68ki_exception_illegal();
  4367. }
  4368. M68KMAKE_OP(lsr, 8, s, .)
  4369. {
  4370. uint* r_dst = &DY;
  4371. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  4372. uint src = MASK_OUT_ABOVE_8(*r_dst);
  4373. uint res = src >> shift;
  4374. if(shift != 0)
  4375. USE_CYCLES(shift<<CYC_SHIFT);
  4376. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  4377. FLAG_N = NFLAG_CLEAR;
  4378. FLAG_Z = res;
  4379. FLAG_X = FLAG_C = src << (9-shift);
  4380. FLAG_V = VFLAG_CLEAR;
  4381. }
  4382. M68KMAKE_OP(lsr, 16, s, .)
  4383. {
  4384. uint* r_dst = &DY;
  4385. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  4386. uint src = MASK_OUT_ABOVE_16(*r_dst);
  4387. uint res = src >> shift;
  4388. if(shift != 0)
  4389. USE_CYCLES(shift<<CYC_SHIFT);
  4390. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  4391. FLAG_N = NFLAG_CLEAR;
  4392. FLAG_Z = res;
  4393. FLAG_X = FLAG_C = src << (9-shift);
  4394. FLAG_V = VFLAG_CLEAR;
  4395. }
  4396. M68KMAKE_OP(lsr, 32, s, .)
  4397. {
  4398. uint* r_dst = &DY;
  4399. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  4400. uint src = *r_dst;
  4401. uint res = src >> shift;
  4402. if(shift != 0)
  4403. USE_CYCLES(shift<<CYC_SHIFT);
  4404. *r_dst = res;
  4405. FLAG_N = NFLAG_CLEAR;
  4406. FLAG_Z = res;
  4407. FLAG_X = FLAG_C = src << (9-shift);
  4408. FLAG_V = VFLAG_CLEAR;
  4409. }
  4410. M68KMAKE_OP(lsr, 8, r, .)
  4411. {
  4412. uint* r_dst = &DY;
  4413. uint shift = DX & 0x3f;
  4414. uint src = MASK_OUT_ABOVE_8(*r_dst);
  4415. uint res = src >> shift;
  4416. if(shift != 0)
  4417. {
  4418. USE_CYCLES(shift<<CYC_SHIFT);
  4419. if(shift <= 8)
  4420. {
  4421. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  4422. FLAG_X = FLAG_C = src << (9-shift);
  4423. FLAG_N = NFLAG_CLEAR;
  4424. FLAG_Z = res;
  4425. FLAG_V = VFLAG_CLEAR;
  4426. return;
  4427. }
  4428. *r_dst &= 0xffffff00;
  4429. FLAG_X = XFLAG_CLEAR;
  4430. FLAG_C = CFLAG_CLEAR;
  4431. FLAG_N = NFLAG_CLEAR;
  4432. FLAG_Z = ZFLAG_SET;
  4433. FLAG_V = VFLAG_CLEAR;
  4434. return;
  4435. }
  4436. FLAG_C = CFLAG_CLEAR;
  4437. FLAG_N = NFLAG_8(src);
  4438. FLAG_Z = src;
  4439. FLAG_V = VFLAG_CLEAR;
  4440. }
  4441. M68KMAKE_OP(lsr, 16, r, .)
  4442. {
  4443. uint* r_dst = &DY;
  4444. uint shift = DX & 0x3f;
  4445. uint src = MASK_OUT_ABOVE_16(*r_dst);
  4446. uint res = src >> shift;
  4447. if(shift != 0)
  4448. {
  4449. USE_CYCLES(shift<<CYC_SHIFT);
  4450. if(shift <= 16)
  4451. {
  4452. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  4453. FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
  4454. FLAG_N = NFLAG_CLEAR;
  4455. FLAG_Z = res;
  4456. FLAG_V = VFLAG_CLEAR;
  4457. return;
  4458. }
  4459. *r_dst &= 0xffff0000;
  4460. FLAG_X = XFLAG_CLEAR;
  4461. FLAG_C = CFLAG_CLEAR;
  4462. FLAG_N = NFLAG_CLEAR;
  4463. FLAG_Z = ZFLAG_SET;
  4464. FLAG_V = VFLAG_CLEAR;
  4465. return;
  4466. }
  4467. FLAG_C = CFLAG_CLEAR;
  4468. FLAG_N = NFLAG_16(src);
  4469. FLAG_Z = src;
  4470. FLAG_V = VFLAG_CLEAR;
  4471. }
  4472. M68KMAKE_OP(lsr, 32, r, .)
  4473. {
  4474. uint* r_dst = &DY;
  4475. uint shift = DX & 0x3f;
  4476. uint src = *r_dst;
  4477. uint res = src >> shift;
  4478. if(shift != 0)
  4479. {
  4480. USE_CYCLES(shift<<CYC_SHIFT);
  4481. if(shift < 32)
  4482. {
  4483. *r_dst = res;
  4484. FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
  4485. FLAG_N = NFLAG_CLEAR;
  4486. FLAG_Z = res;
  4487. FLAG_V = VFLAG_CLEAR;
  4488. return;
  4489. }
  4490. *r_dst = 0;
  4491. FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0);
  4492. FLAG_N = NFLAG_CLEAR;
  4493. FLAG_Z = ZFLAG_SET;
  4494. FLAG_V = VFLAG_CLEAR;
  4495. return;
  4496. }
  4497. FLAG_C = CFLAG_CLEAR;
  4498. FLAG_N = NFLAG_32(src);
  4499. FLAG_Z = src;
  4500. FLAG_V = VFLAG_CLEAR;
  4501. }
  4502. M68KMAKE_OP(lsr, 16, ., .)
  4503. {
  4504. uint ea = M68KMAKE_GET_EA_AY_16;
  4505. uint src = m68ki_read_16(ea);
  4506. uint res = src >> 1;
  4507. m68ki_write_16(ea, res);
  4508. FLAG_N = NFLAG_CLEAR;
  4509. FLAG_Z = res;
  4510. FLAG_C = FLAG_X = src << 8;
  4511. FLAG_V = VFLAG_CLEAR;
  4512. }
  4513. M68KMAKE_OP(lsl, 8, s, .)
  4514. {
  4515. uint* r_dst = &DY;
  4516. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  4517. uint src = MASK_OUT_ABOVE_8(*r_dst);
  4518. uint res = MASK_OUT_ABOVE_8(src << shift);
  4519. if(shift != 0)
  4520. USE_CYCLES(shift<<CYC_SHIFT);
  4521. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  4522. FLAG_N = NFLAG_8(res);
  4523. FLAG_Z = res;
  4524. FLAG_X = FLAG_C = src << shift;
  4525. FLAG_V = VFLAG_CLEAR;
  4526. }
  4527. M68KMAKE_OP(lsl, 16, s, .)
  4528. {
  4529. uint* r_dst = &DY;
  4530. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  4531. uint src = MASK_OUT_ABOVE_16(*r_dst);
  4532. uint res = MASK_OUT_ABOVE_16(src << shift);
  4533. if(shift != 0)
  4534. USE_CYCLES(shift<<CYC_SHIFT);
  4535. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  4536. FLAG_N = NFLAG_16(res);
  4537. FLAG_Z = res;
  4538. FLAG_X = FLAG_C = src >> (8-shift);
  4539. FLAG_V = VFLAG_CLEAR;
  4540. }
  4541. M68KMAKE_OP(lsl, 32, s, .)
  4542. {
  4543. uint* r_dst = &DY;
  4544. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  4545. uint src = *r_dst;
  4546. uint res = MASK_OUT_ABOVE_32(src << shift);
  4547. if(shift != 0)
  4548. USE_CYCLES(shift<<CYC_SHIFT);
  4549. *r_dst = res;
  4550. FLAG_N = NFLAG_32(res);
  4551. FLAG_Z = res;
  4552. FLAG_X = FLAG_C = src >> (24-shift);
  4553. FLAG_V = VFLAG_CLEAR;
  4554. }
  4555. M68KMAKE_OP(lsl, 8, r, .)
  4556. {
  4557. uint* r_dst = &DY;
  4558. uint shift = DX & 0x3f;
  4559. uint src = MASK_OUT_ABOVE_8(*r_dst);
  4560. uint res = MASK_OUT_ABOVE_8(src << shift);
  4561. if(shift != 0)
  4562. {
  4563. USE_CYCLES(shift<<CYC_SHIFT);
  4564. if(shift <= 8)
  4565. {
  4566. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  4567. FLAG_X = FLAG_C = src << shift;
  4568. FLAG_N = NFLAG_8(res);
  4569. FLAG_Z = res;
  4570. FLAG_V = VFLAG_CLEAR;
  4571. return;
  4572. }
  4573. *r_dst &= 0xffffff00;
  4574. FLAG_X = XFLAG_CLEAR;
  4575. FLAG_C = CFLAG_CLEAR;
  4576. FLAG_N = NFLAG_CLEAR;
  4577. FLAG_Z = ZFLAG_SET;
  4578. FLAG_V = VFLAG_CLEAR;
  4579. return;
  4580. }
  4581. FLAG_C = CFLAG_CLEAR;
  4582. FLAG_N = NFLAG_8(src);
  4583. FLAG_Z = src;
  4584. FLAG_V = VFLAG_CLEAR;
  4585. }
  4586. M68KMAKE_OP(lsl, 16, r, .)
  4587. {
  4588. uint* r_dst = &DY;
  4589. uint shift = DX & 0x3f;
  4590. uint src = MASK_OUT_ABOVE_16(*r_dst);
  4591. uint res = MASK_OUT_ABOVE_16(src << shift);
  4592. if(shift != 0)
  4593. {
  4594. USE_CYCLES(shift<<CYC_SHIFT);
  4595. if(shift <= 16)
  4596. {
  4597. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  4598. FLAG_X = FLAG_C = (src << shift) >> 8;
  4599. FLAG_N = NFLAG_16(res);
  4600. FLAG_Z = res;
  4601. FLAG_V = VFLAG_CLEAR;
  4602. return;
  4603. }
  4604. *r_dst &= 0xffff0000;
  4605. FLAG_X = XFLAG_CLEAR;
  4606. FLAG_C = CFLAG_CLEAR;
  4607. FLAG_N = NFLAG_CLEAR;
  4608. FLAG_Z = ZFLAG_SET;
  4609. FLAG_V = VFLAG_CLEAR;
  4610. return;
  4611. }
  4612. FLAG_C = CFLAG_CLEAR;
  4613. FLAG_N = NFLAG_16(src);
  4614. FLAG_Z = src;
  4615. FLAG_V = VFLAG_CLEAR;
  4616. }
  4617. M68KMAKE_OP(lsl, 32, r, .)
  4618. {
  4619. uint* r_dst = &DY;
  4620. uint shift = DX & 0x3f;
  4621. uint src = *r_dst;
  4622. uint res = MASK_OUT_ABOVE_32(src << shift);
  4623. if(shift != 0)
  4624. {
  4625. USE_CYCLES(shift<<CYC_SHIFT);
  4626. if(shift < 32)
  4627. {
  4628. *r_dst = res;
  4629. FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
  4630. FLAG_N = NFLAG_32(res);
  4631. FLAG_Z = res;
  4632. FLAG_V = VFLAG_CLEAR;
  4633. return;
  4634. }
  4635. *r_dst = 0;
  4636. FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
  4637. FLAG_N = NFLAG_CLEAR;
  4638. FLAG_Z = ZFLAG_SET;
  4639. FLAG_V = VFLAG_CLEAR;
  4640. return;
  4641. }
  4642. FLAG_C = CFLAG_CLEAR;
  4643. FLAG_N = NFLAG_32(src);
  4644. FLAG_Z = src;
  4645. FLAG_V = VFLAG_CLEAR;
  4646. }
  4647. M68KMAKE_OP(lsl, 16, ., .)
  4648. {
  4649. uint ea = M68KMAKE_GET_EA_AY_16;
  4650. uint src = m68ki_read_16(ea);
  4651. uint res = MASK_OUT_ABOVE_16(src << 1);
  4652. m68ki_write_16(ea, res);
  4653. FLAG_N = NFLAG_16(res);
  4654. FLAG_Z = res;
  4655. FLAG_X = FLAG_C = src >> 7;
  4656. FLAG_V = VFLAG_CLEAR;
  4657. }
  4658. M68KMAKE_OP(move, 8, d, d)
  4659. {
  4660. uint res = MASK_OUT_ABOVE_8(DY);
  4661. uint* r_dst = &DX;
  4662. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  4663. FLAG_N = NFLAG_8(res);
  4664. FLAG_Z = res;
  4665. FLAG_V = VFLAG_CLEAR;
  4666. FLAG_C = CFLAG_CLEAR;
  4667. }
  4668. M68KMAKE_OP(move, 8, d, .)
  4669. {
  4670. uint res = M68KMAKE_GET_OPER_AY_8;
  4671. uint* r_dst = &DX;
  4672. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  4673. FLAG_N = NFLAG_8(res);
  4674. FLAG_Z = res;
  4675. FLAG_V = VFLAG_CLEAR;
  4676. FLAG_C = CFLAG_CLEAR;
  4677. }
  4678. M68KMAKE_OP(move, 8, ai, d)
  4679. {
  4680. uint res = MASK_OUT_ABOVE_8(DY);
  4681. uint ea = EA_AX_AI_8();
  4682. m68ki_write_8(ea, res);
  4683. FLAG_N = NFLAG_8(res);
  4684. FLAG_Z = res;
  4685. FLAG_V = VFLAG_CLEAR;
  4686. FLAG_C = CFLAG_CLEAR;
  4687. }
  4688. M68KMAKE_OP(move, 8, ai, .)
  4689. {
  4690. uint res = M68KMAKE_GET_OPER_AY_8;
  4691. uint ea = EA_AX_AI_8();
  4692. m68ki_write_8(ea, res);
  4693. FLAG_N = NFLAG_8(res);
  4694. FLAG_Z = res;
  4695. FLAG_V = VFLAG_CLEAR;
  4696. FLAG_C = CFLAG_CLEAR;
  4697. }
  4698. M68KMAKE_OP(move, 8, pi7, d)
  4699. {
  4700. uint res = MASK_OUT_ABOVE_8(DY);
  4701. uint ea = EA_A7_PI_8();
  4702. m68ki_write_8(ea, res);
  4703. FLAG_N = NFLAG_8(res);
  4704. FLAG_Z = res;
  4705. FLAG_V = VFLAG_CLEAR;
  4706. FLAG_C = CFLAG_CLEAR;
  4707. }
  4708. M68KMAKE_OP(move, 8, pi, d)
  4709. {
  4710. uint res = MASK_OUT_ABOVE_8(DY);
  4711. uint ea = EA_AX_PI_8();
  4712. m68ki_write_8(ea, res);
  4713. FLAG_N = NFLAG_8(res);
  4714. FLAG_Z = res;
  4715. FLAG_V = VFLAG_CLEAR;
  4716. FLAG_C = CFLAG_CLEAR;
  4717. }
  4718. M68KMAKE_OP(move, 8, pi7, .)
  4719. {
  4720. uint res = M68KMAKE_GET_OPER_AY_8;
  4721. uint ea = EA_A7_PI_8();
  4722. m68ki_write_8(ea, res);
  4723. FLAG_N = NFLAG_8(res);
  4724. FLAG_Z = res;
  4725. FLAG_V = VFLAG_CLEAR;
  4726. FLAG_C = CFLAG_CLEAR;
  4727. }
  4728. M68KMAKE_OP(move, 8, pi, .)
  4729. {
  4730. uint res = M68KMAKE_GET_OPER_AY_8;
  4731. uint ea = EA_AX_PI_8();
  4732. m68ki_write_8(ea, res);
  4733. FLAG_N = NFLAG_8(res);
  4734. FLAG_Z = res;
  4735. FLAG_V = VFLAG_CLEAR;
  4736. FLAG_C = CFLAG_CLEAR;
  4737. }
  4738. M68KMAKE_OP(move, 8, pd7, d)
  4739. {
  4740. uint res = MASK_OUT_ABOVE_8(DY);
  4741. uint ea = EA_A7_PD_8();
  4742. m68ki_write_8(ea, res);
  4743. FLAG_N = NFLAG_8(res);
  4744. FLAG_Z = res;
  4745. FLAG_V = VFLAG_CLEAR;
  4746. FLAG_C = CFLAG_CLEAR;
  4747. }
  4748. M68KMAKE_OP(move, 8, pd, d)
  4749. {
  4750. uint res = MASK_OUT_ABOVE_8(DY);
  4751. uint ea = EA_AX_PD_8();
  4752. m68ki_write_8(ea, res);
  4753. FLAG_N = NFLAG_8(res);
  4754. FLAG_Z = res;
  4755. FLAG_V = VFLAG_CLEAR;
  4756. FLAG_C = CFLAG_CLEAR;
  4757. }
  4758. M68KMAKE_OP(move, 8, pd7, .)
  4759. {
  4760. uint res = M68KMAKE_GET_OPER_AY_8;
  4761. uint ea = EA_A7_PD_8();
  4762. m68ki_write_8(ea, res);
  4763. FLAG_N = NFLAG_8(res);
  4764. FLAG_Z = res;
  4765. FLAG_V = VFLAG_CLEAR;
  4766. FLAG_C = CFLAG_CLEAR;
  4767. }
  4768. M68KMAKE_OP(move, 8, pd, .)
  4769. {
  4770. uint res = M68KMAKE_GET_OPER_AY_8;
  4771. uint ea = EA_AX_PD_8();
  4772. m68ki_write_8(ea, res);
  4773. FLAG_N = NFLAG_8(res);
  4774. FLAG_Z = res;
  4775. FLAG_V = VFLAG_CLEAR;
  4776. FLAG_C = CFLAG_CLEAR;
  4777. }
  4778. M68KMAKE_OP(move, 8, di, d)
  4779. {
  4780. uint res = MASK_OUT_ABOVE_8(DY);
  4781. uint ea = EA_AX_DI_8();
  4782. m68ki_write_8(ea, res);
  4783. FLAG_N = NFLAG_8(res);
  4784. FLAG_Z = res;
  4785. FLAG_V = VFLAG_CLEAR;
  4786. FLAG_C = CFLAG_CLEAR;
  4787. }
  4788. M68KMAKE_OP(move, 8, di, .)
  4789. {
  4790. uint res = M68KMAKE_GET_OPER_AY_8;
  4791. uint ea = EA_AX_DI_8();
  4792. m68ki_write_8(ea, res);
  4793. FLAG_N = NFLAG_8(res);
  4794. FLAG_Z = res;
  4795. FLAG_V = VFLAG_CLEAR;
  4796. FLAG_C = CFLAG_CLEAR;
  4797. }
  4798. M68KMAKE_OP(move, 8, ix, d)
  4799. {
  4800. uint res = MASK_OUT_ABOVE_8(DY);
  4801. uint ea = EA_AX_IX_8();
  4802. m68ki_write_8(ea, res);
  4803. FLAG_N = NFLAG_8(res);
  4804. FLAG_Z = res;
  4805. FLAG_V = VFLAG_CLEAR;
  4806. FLAG_C = CFLAG_CLEAR;
  4807. }
  4808. M68KMAKE_OP(move, 8, ix, .)
  4809. {
  4810. uint res = M68KMAKE_GET_OPER_AY_8;
  4811. uint ea = EA_AX_IX_8();
  4812. m68ki_write_8(ea, res);
  4813. FLAG_N = NFLAG_8(res);
  4814. FLAG_Z = res;
  4815. FLAG_V = VFLAG_CLEAR;
  4816. FLAG_C = CFLAG_CLEAR;
  4817. }
  4818. M68KMAKE_OP(move, 8, aw, d)
  4819. {
  4820. uint res = MASK_OUT_ABOVE_8(DY);
  4821. uint ea = EA_AW_8();
  4822. m68ki_write_8(ea, res);
  4823. FLAG_N = NFLAG_8(res);
  4824. FLAG_Z = res;
  4825. FLAG_V = VFLAG_CLEAR;
  4826. FLAG_C = CFLAG_CLEAR;
  4827. }
  4828. M68KMAKE_OP(move, 8, aw, .)
  4829. {
  4830. uint res = M68KMAKE_GET_OPER_AY_8;
  4831. uint ea = EA_AW_8();
  4832. m68ki_write_8(ea, res);
  4833. FLAG_N = NFLAG_8(res);
  4834. FLAG_Z = res;
  4835. FLAG_V = VFLAG_CLEAR;
  4836. FLAG_C = CFLAG_CLEAR;
  4837. }
  4838. M68KMAKE_OP(move, 8, al, d)
  4839. {
  4840. uint res = MASK_OUT_ABOVE_8(DY);
  4841. uint ea = EA_AL_8();
  4842. m68ki_write_8(ea, res);
  4843. FLAG_N = NFLAG_8(res);
  4844. FLAG_Z = res;
  4845. FLAG_V = VFLAG_CLEAR;
  4846. FLAG_C = CFLAG_CLEAR;
  4847. }
  4848. M68KMAKE_OP(move, 8, al, .)
  4849. {
  4850. uint res = M68KMAKE_GET_OPER_AY_8;
  4851. uint ea = EA_AL_8();
  4852. m68ki_write_8(ea, res);
  4853. FLAG_N = NFLAG_8(res);
  4854. FLAG_Z = res;
  4855. FLAG_V = VFLAG_CLEAR;
  4856. FLAG_C = CFLAG_CLEAR;
  4857. }
  4858. M68KMAKE_OP(move, 16, d, d)
  4859. {
  4860. uint res = MASK_OUT_ABOVE_16(DY);
  4861. uint* r_dst = &DX;
  4862. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  4863. FLAG_N = NFLAG_16(res);
  4864. FLAG_Z = res;
  4865. FLAG_V = VFLAG_CLEAR;
  4866. FLAG_C = CFLAG_CLEAR;
  4867. }
  4868. M68KMAKE_OP(move, 16, d, a)
  4869. {
  4870. uint res = MASK_OUT_ABOVE_16(AY);
  4871. uint* r_dst = &DX;
  4872. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  4873. FLAG_N = NFLAG_16(res);
  4874. FLAG_Z = res;
  4875. FLAG_V = VFLAG_CLEAR;
  4876. FLAG_C = CFLAG_CLEAR;
  4877. }
  4878. M68KMAKE_OP(move, 16, d, .)
  4879. {
  4880. uint res = M68KMAKE_GET_OPER_AY_16;
  4881. uint* r_dst = &DX;
  4882. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  4883. FLAG_N = NFLAG_16(res);
  4884. FLAG_Z = res;
  4885. FLAG_V = VFLAG_CLEAR;
  4886. FLAG_C = CFLAG_CLEAR;
  4887. }
  4888. M68KMAKE_OP(move, 16, ai, d)
  4889. {
  4890. uint res = MASK_OUT_ABOVE_16(DY);
  4891. uint ea = EA_AX_AI_16();
  4892. m68ki_write_16(ea, res);
  4893. FLAG_N = NFLAG_16(res);
  4894. FLAG_Z = res;
  4895. FLAG_V = VFLAG_CLEAR;
  4896. FLAG_C = CFLAG_CLEAR;
  4897. }
  4898. M68KMAKE_OP(move, 16, ai, a)
  4899. {
  4900. uint res = MASK_OUT_ABOVE_16(AY);
  4901. uint ea = EA_AX_AI_16();
  4902. m68ki_write_16(ea, res);
  4903. FLAG_N = NFLAG_16(res);
  4904. FLAG_Z = res;
  4905. FLAG_V = VFLAG_CLEAR;
  4906. FLAG_C = CFLAG_CLEAR;
  4907. }
  4908. M68KMAKE_OP(move, 16, ai, .)
  4909. {
  4910. uint res = M68KMAKE_GET_OPER_AY_16;
  4911. uint ea = EA_AX_AI_16();
  4912. m68ki_write_16(ea, res);
  4913. FLAG_N = NFLAG_16(res);
  4914. FLAG_Z = res;
  4915. FLAG_V = VFLAG_CLEAR;
  4916. FLAG_C = CFLAG_CLEAR;
  4917. }
  4918. M68KMAKE_OP(move, 16, pi, d)
  4919. {
  4920. uint res = MASK_OUT_ABOVE_16(DY);
  4921. uint ea = EA_AX_PI_16();
  4922. m68ki_write_16(ea, res);
  4923. FLAG_N = NFLAG_16(res);
  4924. FLAG_Z = res;
  4925. FLAG_V = VFLAG_CLEAR;
  4926. FLAG_C = CFLAG_CLEAR;
  4927. }
  4928. M68KMAKE_OP(move, 16, pi, a)
  4929. {
  4930. uint res = MASK_OUT_ABOVE_16(AY);
  4931. uint ea = EA_AX_PI_16();
  4932. m68ki_write_16(ea, res);
  4933. FLAG_N = NFLAG_16(res);
  4934. FLAG_Z = res;
  4935. FLAG_V = VFLAG_CLEAR;
  4936. FLAG_C = CFLAG_CLEAR;
  4937. }
  4938. M68KMAKE_OP(move, 16, pi, .)
  4939. {
  4940. uint res = M68KMAKE_GET_OPER_AY_16;
  4941. uint ea = EA_AX_PI_16();
  4942. m68ki_write_16(ea, res);
  4943. FLAG_N = NFLAG_16(res);
  4944. FLAG_Z = res;
  4945. FLAG_V = VFLAG_CLEAR;
  4946. FLAG_C = CFLAG_CLEAR;
  4947. }
  4948. M68KMAKE_OP(move, 16, pd, d)
  4949. {
  4950. uint res = MASK_OUT_ABOVE_16(DY);
  4951. uint ea = EA_AX_PD_16();
  4952. m68ki_write_16(ea, res);
  4953. FLAG_N = NFLAG_16(res);
  4954. FLAG_Z = res;
  4955. FLAG_V = VFLAG_CLEAR;
  4956. FLAG_C = CFLAG_CLEAR;
  4957. }
  4958. M68KMAKE_OP(move, 16, pd, a)
  4959. {
  4960. uint res = MASK_OUT_ABOVE_16(AY);
  4961. uint ea = EA_AX_PD_16();
  4962. m68ki_write_16(ea, res);
  4963. FLAG_N = NFLAG_16(res);
  4964. FLAG_Z = res;
  4965. FLAG_V = VFLAG_CLEAR;
  4966. FLAG_C = CFLAG_CLEAR;
  4967. }
  4968. M68KMAKE_OP(move, 16, pd, .)
  4969. {
  4970. uint res = M68KMAKE_GET_OPER_AY_16;
  4971. uint ea = EA_AX_PD_16();
  4972. m68ki_write_16(ea, res);
  4973. FLAG_N = NFLAG_16(res);
  4974. FLAG_Z = res;
  4975. FLAG_V = VFLAG_CLEAR;
  4976. FLAG_C = CFLAG_CLEAR;
  4977. }
  4978. M68KMAKE_OP(move, 16, di, d)
  4979. {
  4980. uint res = MASK_OUT_ABOVE_16(DY);
  4981. uint ea = EA_AX_DI_16();
  4982. m68ki_write_16(ea, res);
  4983. FLAG_N = NFLAG_16(res);
  4984. FLAG_Z = res;
  4985. FLAG_V = VFLAG_CLEAR;
  4986. FLAG_C = CFLAG_CLEAR;
  4987. }
  4988. M68KMAKE_OP(move, 16, di, a)
  4989. {
  4990. uint res = MASK_OUT_ABOVE_16(AY);
  4991. uint ea = EA_AX_DI_16();
  4992. m68ki_write_16(ea, res);
  4993. FLAG_N = NFLAG_16(res);
  4994. FLAG_Z = res;
  4995. FLAG_V = VFLAG_CLEAR;
  4996. FLAG_C = CFLAG_CLEAR;
  4997. }
  4998. M68KMAKE_OP(move, 16, di, .)
  4999. {
  5000. uint res = M68KMAKE_GET_OPER_AY_16;
  5001. uint ea = EA_AX_DI_16();
  5002. m68ki_write_16(ea, res);
  5003. FLAG_N = NFLAG_16(res);
  5004. FLAG_Z = res;
  5005. FLAG_V = VFLAG_CLEAR;
  5006. FLAG_C = CFLAG_CLEAR;
  5007. }
  5008. M68KMAKE_OP(move, 16, ix, d)
  5009. {
  5010. uint res = MASK_OUT_ABOVE_16(DY);
  5011. uint ea = EA_AX_IX_16();
  5012. m68ki_write_16(ea, res);
  5013. FLAG_N = NFLAG_16(res);
  5014. FLAG_Z = res;
  5015. FLAG_V = VFLAG_CLEAR;
  5016. FLAG_C = CFLAG_CLEAR;
  5017. }
  5018. M68KMAKE_OP(move, 16, ix, a)
  5019. {
  5020. uint res = MASK_OUT_ABOVE_16(AY);
  5021. uint ea = EA_AX_IX_16();
  5022. m68ki_write_16(ea, res);
  5023. FLAG_N = NFLAG_16(res);
  5024. FLAG_Z = res;
  5025. FLAG_V = VFLAG_CLEAR;
  5026. FLAG_C = CFLAG_CLEAR;
  5027. }
  5028. M68KMAKE_OP(move, 16, ix, .)
  5029. {
  5030. uint res = M68KMAKE_GET_OPER_AY_16;
  5031. uint ea = EA_AX_IX_16();
  5032. m68ki_write_16(ea, res);
  5033. FLAG_N = NFLAG_16(res);
  5034. FLAG_Z = res;
  5035. FLAG_V = VFLAG_CLEAR;
  5036. FLAG_C = CFLAG_CLEAR;
  5037. }
  5038. M68KMAKE_OP(move, 16, aw, d)
  5039. {
  5040. uint res = MASK_OUT_ABOVE_16(DY);
  5041. uint ea = EA_AW_16();
  5042. m68ki_write_16(ea, res);
  5043. FLAG_N = NFLAG_16(res);
  5044. FLAG_Z = res;
  5045. FLAG_V = VFLAG_CLEAR;
  5046. FLAG_C = CFLAG_CLEAR;
  5047. }
  5048. M68KMAKE_OP(move, 16, aw, a)
  5049. {
  5050. uint res = MASK_OUT_ABOVE_16(AY);
  5051. uint ea = EA_AW_16();
  5052. m68ki_write_16(ea, res);
  5053. FLAG_N = NFLAG_16(res);
  5054. FLAG_Z = res;
  5055. FLAG_V = VFLAG_CLEAR;
  5056. FLAG_C = CFLAG_CLEAR;
  5057. }
  5058. M68KMAKE_OP(move, 16, aw, .)
  5059. {
  5060. uint res = M68KMAKE_GET_OPER_AY_16;
  5061. uint ea = EA_AW_16();
  5062. m68ki_write_16(ea, res);
  5063. FLAG_N = NFLAG_16(res);
  5064. FLAG_Z = res;
  5065. FLAG_V = VFLAG_CLEAR;
  5066. FLAG_C = CFLAG_CLEAR;
  5067. }
  5068. M68KMAKE_OP(move, 16, al, d)
  5069. {
  5070. uint res = MASK_OUT_ABOVE_16(DY);
  5071. uint ea = EA_AL_16();
  5072. m68ki_write_16(ea, res);
  5073. FLAG_N = NFLAG_16(res);
  5074. FLAG_Z = res;
  5075. FLAG_V = VFLAG_CLEAR;
  5076. FLAG_C = CFLAG_CLEAR;
  5077. }
  5078. M68KMAKE_OP(move, 16, al, a)
  5079. {
  5080. uint res = MASK_OUT_ABOVE_16(AY);
  5081. uint ea = EA_AL_16();
  5082. m68ki_write_16(ea, res);
  5083. FLAG_N = NFLAG_16(res);
  5084. FLAG_Z = res;
  5085. FLAG_V = VFLAG_CLEAR;
  5086. FLAG_C = CFLAG_CLEAR;
  5087. }
  5088. M68KMAKE_OP(move, 16, al, .)
  5089. {
  5090. uint res = M68KMAKE_GET_OPER_AY_16;
  5091. uint ea = EA_AL_16();
  5092. m68ki_write_16(ea, res);
  5093. FLAG_N = NFLAG_16(res);
  5094. FLAG_Z = res;
  5095. FLAG_V = VFLAG_CLEAR;
  5096. FLAG_C = CFLAG_CLEAR;
  5097. }
  5098. M68KMAKE_OP(move, 32, d, d)
  5099. {
  5100. uint res = DY;
  5101. uint* r_dst = &DX;
  5102. *r_dst = res;
  5103. FLAG_N = NFLAG_32(res);
  5104. FLAG_Z = res;
  5105. FLAG_V = VFLAG_CLEAR;
  5106. FLAG_C = CFLAG_CLEAR;
  5107. }
  5108. M68KMAKE_OP(move, 32, d, a)
  5109. {
  5110. uint res = AY;
  5111. uint* r_dst = &DX;
  5112. *r_dst = res;
  5113. FLAG_N = NFLAG_32(res);
  5114. FLAG_Z = res;
  5115. FLAG_V = VFLAG_CLEAR;
  5116. FLAG_C = CFLAG_CLEAR;
  5117. }
  5118. M68KMAKE_OP(move, 32, d, .)
  5119. {
  5120. uint res = M68KMAKE_GET_OPER_AY_32;
  5121. uint* r_dst = &DX;
  5122. *r_dst = res;
  5123. FLAG_N = NFLAG_32(res);
  5124. FLAG_Z = res;
  5125. FLAG_V = VFLAG_CLEAR;
  5126. FLAG_C = CFLAG_CLEAR;
  5127. }
  5128. M68KMAKE_OP(move, 32, ai, d)
  5129. {
  5130. uint res = DY;
  5131. uint ea = EA_AX_AI_32();
  5132. m68ki_write_32(ea, res);
  5133. FLAG_N = NFLAG_32(res);
  5134. FLAG_Z = res;
  5135. FLAG_V = VFLAG_CLEAR;
  5136. FLAG_C = CFLAG_CLEAR;
  5137. }
  5138. M68KMAKE_OP(move, 32, ai, a)
  5139. {
  5140. uint res = AY;
  5141. uint ea = EA_AX_AI_32();
  5142. m68ki_write_32(ea, res);
  5143. FLAG_N = NFLAG_32(res);
  5144. FLAG_Z = res;
  5145. FLAG_V = VFLAG_CLEAR;
  5146. FLAG_C = CFLAG_CLEAR;
  5147. }
  5148. M68KMAKE_OP(move, 32, ai, .)
  5149. {
  5150. uint res = M68KMAKE_GET_OPER_AY_32;
  5151. uint ea = EA_AX_AI_32();
  5152. m68ki_write_32(ea, res);
  5153. FLAG_N = NFLAG_32(res);
  5154. FLAG_Z = res;
  5155. FLAG_V = VFLAG_CLEAR;
  5156. FLAG_C = CFLAG_CLEAR;
  5157. }
  5158. M68KMAKE_OP(move, 32, pi, d)
  5159. {
  5160. uint res = DY;
  5161. uint ea = EA_AX_PI_32();
  5162. m68ki_write_32(ea, res);
  5163. FLAG_N = NFLAG_32(res);
  5164. FLAG_Z = res;
  5165. FLAG_V = VFLAG_CLEAR;
  5166. FLAG_C = CFLAG_CLEAR;
  5167. }
  5168. M68KMAKE_OP(move, 32, pi, a)
  5169. {
  5170. uint res = AY;
  5171. uint ea = EA_AX_PI_32();
  5172. m68ki_write_32(ea, res);
  5173. FLAG_N = NFLAG_32(res);
  5174. FLAG_Z = res;
  5175. FLAG_V = VFLAG_CLEAR;
  5176. FLAG_C = CFLAG_CLEAR;
  5177. }
  5178. M68KMAKE_OP(move, 32, pi, .)
  5179. {
  5180. uint res = M68KMAKE_GET_OPER_AY_32;
  5181. uint ea = EA_AX_PI_32();
  5182. m68ki_write_32(ea, res);
  5183. FLAG_N = NFLAG_32(res);
  5184. FLAG_Z = res;
  5185. FLAG_V = VFLAG_CLEAR;
  5186. FLAG_C = CFLAG_CLEAR;
  5187. }
  5188. M68KMAKE_OP(move, 32, pd, d)
  5189. {
  5190. uint res = DY;
  5191. uint ea = EA_AX_PD_32();
  5192. m68ki_write_16(ea+2, res & 0xFFFF );
  5193. m68ki_write_16(ea, (res >> 16) & 0xFFFF );
  5194. FLAG_N = NFLAG_32(res);
  5195. FLAG_Z = res;
  5196. FLAG_V = VFLAG_CLEAR;
  5197. FLAG_C = CFLAG_CLEAR;
  5198. }
  5199. M68KMAKE_OP(move, 32, pd, a)
  5200. {
  5201. uint res = AY;
  5202. uint ea = EA_AX_PD_32();
  5203. m68ki_write_16(ea+2, res & 0xFFFF );
  5204. m68ki_write_16(ea, (res >> 16) & 0xFFFF );
  5205. FLAG_N = NFLAG_32(res);
  5206. FLAG_Z = res;
  5207. FLAG_V = VFLAG_CLEAR;
  5208. FLAG_C = CFLAG_CLEAR;
  5209. }
  5210. M68KMAKE_OP(move, 32, pd, .)
  5211. {
  5212. uint res = M68KMAKE_GET_OPER_AY_32;
  5213. uint ea = EA_AX_PD_32();
  5214. m68ki_write_16(ea+2, res & 0xFFFF );
  5215. m68ki_write_16(ea, (res >> 16) & 0xFFFF );
  5216. FLAG_N = NFLAG_32(res);
  5217. FLAG_Z = res;
  5218. FLAG_V = VFLAG_CLEAR;
  5219. FLAG_C = CFLAG_CLEAR;
  5220. }
  5221. M68KMAKE_OP(move, 32, di, d)
  5222. {
  5223. uint res = DY;
  5224. uint ea = EA_AX_DI_32();
  5225. m68ki_write_32(ea, res);
  5226. FLAG_N = NFLAG_32(res);
  5227. FLAG_Z = res;
  5228. FLAG_V = VFLAG_CLEAR;
  5229. FLAG_C = CFLAG_CLEAR;
  5230. }
  5231. M68KMAKE_OP(move, 32, di, a)
  5232. {
  5233. uint res = AY;
  5234. uint ea = EA_AX_DI_32();
  5235. m68ki_write_32(ea, res);
  5236. FLAG_N = NFLAG_32(res);
  5237. FLAG_Z = res;
  5238. FLAG_V = VFLAG_CLEAR;
  5239. FLAG_C = CFLAG_CLEAR;
  5240. }
  5241. M68KMAKE_OP(move, 32, di, .)
  5242. {
  5243. uint res = M68KMAKE_GET_OPER_AY_32;
  5244. uint ea = EA_AX_DI_32();
  5245. m68ki_write_32(ea, res);
  5246. FLAG_N = NFLAG_32(res);
  5247. FLAG_Z = res;
  5248. FLAG_V = VFLAG_CLEAR;
  5249. FLAG_C = CFLAG_CLEAR;
  5250. }
  5251. M68KMAKE_OP(move, 32, ix, d)
  5252. {
  5253. uint res = DY;
  5254. uint ea = EA_AX_IX_32();
  5255. m68ki_write_32(ea, res);
  5256. FLAG_N = NFLAG_32(res);
  5257. FLAG_Z = res;
  5258. FLAG_V = VFLAG_CLEAR;
  5259. FLAG_C = CFLAG_CLEAR;
  5260. }
  5261. M68KMAKE_OP(move, 32, ix, a)
  5262. {
  5263. uint res = AY;
  5264. uint ea = EA_AX_IX_32();
  5265. m68ki_write_32(ea, res);
  5266. FLAG_N = NFLAG_32(res);
  5267. FLAG_Z = res;
  5268. FLAG_V = VFLAG_CLEAR;
  5269. FLAG_C = CFLAG_CLEAR;
  5270. }
  5271. M68KMAKE_OP(move, 32, ix, .)
  5272. {
  5273. uint res = M68KMAKE_GET_OPER_AY_32;
  5274. uint ea = EA_AX_IX_32();
  5275. m68ki_write_32(ea, res);
  5276. FLAG_N = NFLAG_32(res);
  5277. FLAG_Z = res;
  5278. FLAG_V = VFLAG_CLEAR;
  5279. FLAG_C = CFLAG_CLEAR;
  5280. }
  5281. M68KMAKE_OP(move, 32, aw, d)
  5282. {
  5283. uint res = DY;
  5284. uint ea = EA_AW_32();
  5285. m68ki_write_32(ea, res);
  5286. FLAG_N = NFLAG_32(res);
  5287. FLAG_Z = res;
  5288. FLAG_V = VFLAG_CLEAR;
  5289. FLAG_C = CFLAG_CLEAR;
  5290. }
  5291. M68KMAKE_OP(move, 32, aw, a)
  5292. {
  5293. uint res = AY;
  5294. uint ea = EA_AW_32();
  5295. m68ki_write_32(ea, res);
  5296. FLAG_N = NFLAG_32(res);
  5297. FLAG_Z = res;
  5298. FLAG_V = VFLAG_CLEAR;
  5299. FLAG_C = CFLAG_CLEAR;
  5300. }
  5301. M68KMAKE_OP(move, 32, aw, .)
  5302. {
  5303. uint res = M68KMAKE_GET_OPER_AY_32;
  5304. uint ea = EA_AW_32();
  5305. m68ki_write_32(ea, res);
  5306. FLAG_N = NFLAG_32(res);
  5307. FLAG_Z = res;
  5308. FLAG_V = VFLAG_CLEAR;
  5309. FLAG_C = CFLAG_CLEAR;
  5310. }
  5311. M68KMAKE_OP(move, 32, al, d)
  5312. {
  5313. uint res = DY;
  5314. uint ea = EA_AL_32();
  5315. m68ki_write_32(ea, res);
  5316. FLAG_N = NFLAG_32(res);
  5317. FLAG_Z = res;
  5318. FLAG_V = VFLAG_CLEAR;
  5319. FLAG_C = CFLAG_CLEAR;
  5320. }
  5321. M68KMAKE_OP(move, 32, al, a)
  5322. {
  5323. uint res = AY;
  5324. uint ea = EA_AL_32();
  5325. m68ki_write_32(ea, res);
  5326. FLAG_N = NFLAG_32(res);
  5327. FLAG_Z = res;
  5328. FLAG_V = VFLAG_CLEAR;
  5329. FLAG_C = CFLAG_CLEAR;
  5330. }
  5331. M68KMAKE_OP(move, 32, al, .)
  5332. {
  5333. uint res = M68KMAKE_GET_OPER_AY_32;
  5334. uint ea = EA_AL_32();
  5335. m68ki_write_32(ea, res);
  5336. FLAG_N = NFLAG_32(res);
  5337. FLAG_Z = res;
  5338. FLAG_V = VFLAG_CLEAR;
  5339. FLAG_C = CFLAG_CLEAR;
  5340. }
  5341. M68KMAKE_OP(movea, 16, ., d)
  5342. {
  5343. AX = MAKE_INT_16(DY);
  5344. }
  5345. M68KMAKE_OP(movea, 16, ., a)
  5346. {
  5347. AX = MAKE_INT_16(AY);
  5348. }
  5349. M68KMAKE_OP(movea, 16, ., .)
  5350. {
  5351. AX = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
  5352. }
  5353. M68KMAKE_OP(movea, 32, ., d)
  5354. {
  5355. AX = DY;
  5356. }
  5357. M68KMAKE_OP(movea, 32, ., a)
  5358. {
  5359. AX = AY;
  5360. }
  5361. M68KMAKE_OP(movea, 32, ., .)
  5362. {
  5363. AX = M68KMAKE_GET_OPER_AY_32;
  5364. }
  5365. M68KMAKE_OP(move, 16, frc, d)
  5366. {
  5367. if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
  5368. {
  5369. DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr();
  5370. return;
  5371. }
  5372. m68ki_exception_illegal();
  5373. }
  5374. M68KMAKE_OP(move, 16, frc, .)
  5375. {
  5376. if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
  5377. {
  5378. m68ki_write_16(M68KMAKE_GET_EA_AY_16, m68ki_get_ccr());
  5379. return;
  5380. }
  5381. m68ki_exception_illegal();
  5382. }
  5383. M68KMAKE_OP(move, 16, toc, d)
  5384. {
  5385. m68ki_set_ccr(DY);
  5386. }
  5387. M68KMAKE_OP(move, 16, toc, .)
  5388. {
  5389. m68ki_set_ccr(M68KMAKE_GET_OPER_AY_16);
  5390. }
  5391. M68KMAKE_OP(move, 16, frs, d)
  5392. {
  5393. if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
  5394. {
  5395. DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr();
  5396. return;
  5397. }
  5398. m68ki_exception_privilege_violation();
  5399. }
  5400. M68KMAKE_OP(move, 16, frs, .)
  5401. {
  5402. if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
  5403. {
  5404. uint ea = M68KMAKE_GET_EA_AY_16;
  5405. m68ki_write_16(ea, m68ki_get_sr());
  5406. return;
  5407. }
  5408. m68ki_exception_privilege_violation();
  5409. }
  5410. M68KMAKE_OP(move, 16, tos, d)
  5411. {
  5412. if(FLAG_S)
  5413. {
  5414. m68ki_set_sr(DY);
  5415. return;
  5416. }
  5417. m68ki_exception_privilege_violation();
  5418. }
  5419. M68KMAKE_OP(move, 16, tos, .)
  5420. {
  5421. if(FLAG_S)
  5422. {
  5423. uint new_sr = M68KMAKE_GET_OPER_AY_16;
  5424. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  5425. m68ki_set_sr(new_sr);
  5426. return;
  5427. }
  5428. m68ki_exception_privilege_violation();
  5429. }
  5430. M68KMAKE_OP(move, 32, fru, .)
  5431. {
  5432. if(FLAG_S)
  5433. {
  5434. AY = REG_USP;
  5435. return;
  5436. }
  5437. m68ki_exception_privilege_violation();
  5438. }
  5439. M68KMAKE_OP(move, 32, tou, .)
  5440. {
  5441. if(FLAG_S)
  5442. {
  5443. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  5444. REG_USP = AY;
  5445. return;
  5446. }
  5447. m68ki_exception_privilege_violation();
  5448. }
  5449. M68KMAKE_OP(movec, 32, cr, .)
  5450. {
  5451. if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
  5452. {
  5453. if(FLAG_S)
  5454. {
  5455. uint word2 = OPER_I_16();
  5456. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  5457. switch (word2 & 0xfff)
  5458. {
  5459. case 0x000: /* SFC */
  5460. REG_DA[(word2 >> 12) & 15] = REG_SFC;
  5461. return;
  5462. case 0x001: /* DFC */
  5463. REG_DA[(word2 >> 12) & 15] = REG_DFC;
  5464. return;
  5465. case 0x002: /* CACR */
  5466. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  5467. {
  5468. REG_DA[(word2 >> 12) & 15] = REG_CACR;
  5469. return;
  5470. }
  5471. return;
  5472. case 0x800: /* USP */
  5473. REG_DA[(word2 >> 12) & 15] = REG_USP;
  5474. return;
  5475. case 0x801: /* VBR */
  5476. REG_DA[(word2 >> 12) & 15] = REG_VBR;
  5477. return;
  5478. case 0x802: /* CAAR */
  5479. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  5480. {
  5481. REG_DA[(word2 >> 12) & 15] = REG_CAAR;
  5482. return;
  5483. }
  5484. m68ki_exception_illegal();
  5485. break;
  5486. case 0x803: /* MSP */
  5487. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  5488. {
  5489. REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_SP : REG_MSP;
  5490. return;
  5491. }
  5492. m68ki_exception_illegal();
  5493. return;
  5494. case 0x804: /* ISP */
  5495. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  5496. {
  5497. REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_ISP : REG_SP;
  5498. return;
  5499. }
  5500. m68ki_exception_illegal();
  5501. return;
  5502. case 0x003: /* TC */
  5503. if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5504. {
  5505. /* TODO */
  5506. return;
  5507. }
  5508. m68ki_exception_illegal();
  5509. return;
  5510. case 0x004: /* ITT0 */
  5511. if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5512. {
  5513. /* TODO */
  5514. return;
  5515. }
  5516. m68ki_exception_illegal();
  5517. return;
  5518. case 0x005: /* ITT1 */
  5519. if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5520. {
  5521. /* TODO */
  5522. return;
  5523. }
  5524. m68ki_exception_illegal();
  5525. return;
  5526. case 0x006: /* DTT0 */
  5527. if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5528. {
  5529. /* TODO */
  5530. return;
  5531. }
  5532. m68ki_exception_illegal();
  5533. return;
  5534. case 0x007: /* DTT1 */
  5535. if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5536. {
  5537. /* TODO */
  5538. return;
  5539. }
  5540. m68ki_exception_illegal();
  5541. return;
  5542. case 0x805: /* MMUSR */
  5543. if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5544. {
  5545. /* TODO */
  5546. return;
  5547. }
  5548. m68ki_exception_illegal();
  5549. return;
  5550. case 0x806: /* URP */
  5551. if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5552. {
  5553. /* TODO */
  5554. return;
  5555. }
  5556. m68ki_exception_illegal();
  5557. return;
  5558. case 0x807: /* SRP */
  5559. if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5560. {
  5561. /* TODO */
  5562. return;
  5563. }
  5564. m68ki_exception_illegal();
  5565. return;
  5566. default:
  5567. m68ki_exception_illegal();
  5568. return;
  5569. }
  5570. }
  5571. m68ki_exception_privilege_violation();
  5572. return;
  5573. }
  5574. m68ki_exception_illegal();
  5575. }
  5576. M68KMAKE_OP(movec, 32, rc, .)
  5577. {
  5578. if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
  5579. {
  5580. if(FLAG_S)
  5581. {
  5582. uint word2 = OPER_I_16();
  5583. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  5584. switch (word2 & 0xfff)
  5585. {
  5586. case 0x000: /* SFC */
  5587. REG_SFC = REG_DA[(word2 >> 12) & 15] & 7;
  5588. return;
  5589. case 0x001: /* DFC */
  5590. REG_DFC = REG_DA[(word2 >> 12) & 15] & 7;
  5591. return;
  5592. case 0x002: /* CACR */
  5593. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  5594. {
  5595. if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5596. {
  5597. REG_CACR = REG_DA[(word2 >> 12) & 15];
  5598. }
  5599. else
  5600. {
  5601. /* non 68040 can only set the lower 4 bits (C,CE,F,E) */
  5602. REG_CACR = REG_DA[(word2 >> 12) & 15] & 0x0f;
  5603. }
  5604. return;
  5605. }
  5606. m68ki_exception_illegal();
  5607. return;
  5608. case 0x800: /* USP */
  5609. REG_USP = REG_DA[(word2 >> 12) & 15];
  5610. return;
  5611. case 0x801: /* VBR */
  5612. REG_VBR = REG_DA[(word2 >> 12) & 15];
  5613. return;
  5614. case 0x802: /* CAAR */
  5615. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  5616. {
  5617. REG_CAAR = REG_DA[(word2 >> 12) & 15];
  5618. return;
  5619. }
  5620. m68ki_exception_illegal();
  5621. return;
  5622. case 0x803: /* MSP */
  5623. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  5624. {
  5625. /* we are in supervisor mode so just check for M flag */
  5626. if(!FLAG_M)
  5627. {
  5628. REG_MSP = REG_DA[(word2 >> 12) & 15];
  5629. return;
  5630. }
  5631. REG_SP = REG_DA[(word2 >> 12) & 15];
  5632. return;
  5633. }
  5634. m68ki_exception_illegal();
  5635. return;
  5636. case 0x804: /* ISP */
  5637. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  5638. {
  5639. if(!FLAG_M)
  5640. {
  5641. REG_SP = REG_DA[(word2 >> 12) & 15];
  5642. return;
  5643. }
  5644. REG_ISP = REG_DA[(word2 >> 12) & 15];
  5645. return;
  5646. }
  5647. m68ki_exception_illegal();
  5648. return;
  5649. case 0x003: /* TC */
  5650. if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5651. {
  5652. /* TODO */
  5653. return;
  5654. }
  5655. m68ki_exception_illegal();
  5656. return;
  5657. case 0x004: /* ITT0 */
  5658. if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5659. {
  5660. /* TODO */
  5661. return;
  5662. }
  5663. m68ki_exception_illegal();
  5664. return;
  5665. case 0x005: /* ITT1 */
  5666. if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5667. {
  5668. /* TODO */
  5669. return;
  5670. }
  5671. m68ki_exception_illegal();
  5672. return;
  5673. case 0x006: /* DTT0 */
  5674. if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5675. {
  5676. /* TODO */
  5677. return;
  5678. }
  5679. m68ki_exception_illegal();
  5680. return;
  5681. case 0x007: /* DTT1 */
  5682. if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5683. {
  5684. /* TODO */
  5685. return;
  5686. }
  5687. m68ki_exception_illegal();
  5688. return;
  5689. case 0x805: /* MMUSR */
  5690. if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5691. {
  5692. /* TODO */
  5693. return;
  5694. }
  5695. m68ki_exception_illegal();
  5696. return;
  5697. case 0x806: /* URP */
  5698. if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5699. {
  5700. /* TODO */
  5701. return;
  5702. }
  5703. m68ki_exception_illegal();
  5704. return;
  5705. case 0x807: /* SRP */
  5706. if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5707. {
  5708. /* TODO */
  5709. return;
  5710. }
  5711. m68ki_exception_illegal();
  5712. return;
  5713. default:
  5714. m68ki_exception_illegal();
  5715. return;
  5716. }
  5717. }
  5718. m68ki_exception_privilege_violation();
  5719. return;
  5720. }
  5721. m68ki_exception_illegal();
  5722. }
  5723. M68KMAKE_OP(movem, 16, re, pd)
  5724. {
  5725. uint i = 0;
  5726. uint register_list = OPER_I_16();
  5727. uint ea = AY;
  5728. uint count = 0;
  5729. for(; i < 16; i++)
  5730. if(register_list & (1 << i))
  5731. {
  5732. ea -= 2;
  5733. m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i]));
  5734. count++;
  5735. }
  5736. AY = ea;
  5737. USE_CYCLES(count<<CYC_MOVEM_W);
  5738. }
  5739. M68KMAKE_OP(movem, 16, re, .)
  5740. {
  5741. uint i = 0;
  5742. uint register_list = OPER_I_16();
  5743. uint ea = M68KMAKE_GET_EA_AY_16;
  5744. uint count = 0;
  5745. for(; i < 16; i++)
  5746. if(register_list & (1 << i))
  5747. {
  5748. m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
  5749. ea += 2;
  5750. count++;
  5751. }
  5752. USE_CYCLES(count<<CYC_MOVEM_W);
  5753. }
  5754. M68KMAKE_OP(movem, 32, re, pd)
  5755. {
  5756. uint i = 0;
  5757. uint register_list = OPER_I_16();
  5758. uint ea = AY;
  5759. uint count = 0;
  5760. for(; i < 16; i++)
  5761. if(register_list & (1 << i))
  5762. {
  5763. ea -= 4;
  5764. #if 0
  5765. m68ki_write_32(ea, REG_DA[15-i] ); // notaz Cyclone hack
  5766. #else
  5767. m68ki_write_16(ea+2, REG_DA[15-i] & 0xFFFF );
  5768. m68ki_write_16(ea, (REG_DA[15-i] >> 16) & 0xFFFF );
  5769. #endif
  5770. count++;
  5771. }
  5772. AY = ea;
  5773. USE_CYCLES(count<<CYC_MOVEM_L);
  5774. }
  5775. M68KMAKE_OP(movem, 32, re, .)
  5776. {
  5777. uint i = 0;
  5778. uint register_list = OPER_I_16();
  5779. uint ea = M68KMAKE_GET_EA_AY_32;
  5780. uint count = 0;
  5781. for(; i < 16; i++)
  5782. if(register_list & (1 << i))
  5783. {
  5784. m68ki_write_32(ea, REG_DA[i]);
  5785. ea += 4;
  5786. count++;
  5787. }
  5788. USE_CYCLES(count<<CYC_MOVEM_L);
  5789. }
  5790. M68KMAKE_OP(movem, 16, er, pi)
  5791. {
  5792. uint i = 0;
  5793. uint register_list = OPER_I_16();
  5794. uint ea = AY;
  5795. uint count = 0;
  5796. for(; i < 16; i++)
  5797. if(register_list & (1 << i))
  5798. {
  5799. REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
  5800. ea += 2;
  5801. count++;
  5802. }
  5803. AY = ea;
  5804. USE_CYCLES(count<<CYC_MOVEM_W);
  5805. }
  5806. M68KMAKE_OP(movem, 16, er, pcdi)
  5807. {
  5808. uint i = 0;
  5809. uint register_list = OPER_I_16();
  5810. uint ea = EA_PCDI_16();
  5811. uint count = 0;
  5812. for(; i < 16; i++)
  5813. if(register_list & (1 << i))
  5814. {
  5815. REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
  5816. ea += 2;
  5817. count++;
  5818. }
  5819. USE_CYCLES(count<<CYC_MOVEM_W);
  5820. }
  5821. M68KMAKE_OP(movem, 16, er, pcix)
  5822. {
  5823. uint i = 0;
  5824. uint register_list = OPER_I_16();
  5825. uint ea = EA_PCIX_16();
  5826. uint count = 0;
  5827. for(; i < 16; i++)
  5828. if(register_list & (1 << i))
  5829. {
  5830. REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
  5831. ea += 2;
  5832. count++;
  5833. }
  5834. USE_CYCLES(count<<CYC_MOVEM_W);
  5835. }
  5836. M68KMAKE_OP(movem, 16, er, .)
  5837. {
  5838. uint i = 0;
  5839. uint register_list = OPER_I_16();
  5840. uint ea = M68KMAKE_GET_EA_AY_16;
  5841. uint count = 0;
  5842. for(; i < 16; i++)
  5843. if(register_list & (1 << i))
  5844. {
  5845. REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
  5846. ea += 2;
  5847. count++;
  5848. }
  5849. USE_CYCLES(count<<CYC_MOVEM_W);
  5850. }
  5851. M68KMAKE_OP(movem, 32, er, pi)
  5852. {
  5853. uint i = 0;
  5854. uint register_list = OPER_I_16();
  5855. uint ea = AY;
  5856. uint count = 0;
  5857. for(; i < 16; i++)
  5858. if(register_list & (1 << i))
  5859. {
  5860. REG_DA[i] = m68ki_read_32(ea);
  5861. ea += 4;
  5862. count++;
  5863. }
  5864. AY = ea;
  5865. USE_CYCLES(count<<CYC_MOVEM_L);
  5866. }
  5867. M68KMAKE_OP(movem, 32, er, pcdi)
  5868. {
  5869. uint i = 0;
  5870. uint register_list = OPER_I_16();
  5871. uint ea = EA_PCDI_32();
  5872. uint count = 0;
  5873. for(; i < 16; i++)
  5874. if(register_list & (1 << i))
  5875. {
  5876. REG_DA[i] = m68ki_read_pcrel_32(ea);
  5877. ea += 4;
  5878. count++;
  5879. }
  5880. USE_CYCLES(count<<CYC_MOVEM_L);
  5881. }
  5882. M68KMAKE_OP(movem, 32, er, pcix)
  5883. {
  5884. uint i = 0;
  5885. uint register_list = OPER_I_16();
  5886. uint ea = EA_PCIX_32();
  5887. uint count = 0;
  5888. for(; i < 16; i++)
  5889. if(register_list & (1 << i))
  5890. {
  5891. REG_DA[i] = m68ki_read_pcrel_32(ea);
  5892. ea += 4;
  5893. count++;
  5894. }
  5895. USE_CYCLES(count<<CYC_MOVEM_L);
  5896. }
  5897. M68KMAKE_OP(movem, 32, er, .)
  5898. {
  5899. uint i = 0;
  5900. uint register_list = OPER_I_16();
  5901. uint ea = M68KMAKE_GET_EA_AY_32;
  5902. uint count = 0;
  5903. for(; i < 16; i++)
  5904. if(register_list & (1 << i))
  5905. {
  5906. REG_DA[i] = m68ki_read_32(ea);
  5907. ea += 4;
  5908. count++;
  5909. }
  5910. USE_CYCLES(count<<CYC_MOVEM_L);
  5911. }
  5912. M68KMAKE_OP(movep, 16, re, .)
  5913. {
  5914. uint ea = EA_AY_DI_16();
  5915. uint src = DX;
  5916. m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 8));
  5917. m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
  5918. }
  5919. M68KMAKE_OP(movep, 32, re, .)
  5920. {
  5921. uint ea = EA_AY_DI_32();
  5922. uint src = DX;
  5923. m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24));
  5924. m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16));
  5925. m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8));
  5926. m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
  5927. }
  5928. M68KMAKE_OP(movep, 16, er, .)
  5929. {
  5930. uint ea = EA_AY_DI_16();
  5931. uint* r_dst = &DX;
  5932. *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2));
  5933. }
  5934. M68KMAKE_OP(movep, 32, er, .)
  5935. {
  5936. uint ea = EA_AY_DI_32();
  5937. DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16)
  5938. + (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6);
  5939. }
  5940. M68KMAKE_OP(moves, 8, ., .)
  5941. {
  5942. if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
  5943. {
  5944. if(FLAG_S)
  5945. {
  5946. uint word2 = OPER_I_16();
  5947. uint ea = M68KMAKE_GET_EA_AY_8;
  5948. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  5949. if(BIT_B(word2)) /* Register to memory */
  5950. {
  5951. m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
  5952. return;
  5953. }
  5954. if(BIT_F(word2)) /* Memory to address register */
  5955. {
  5956. REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
  5957. if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
  5958. USE_CYCLES(2);
  5959. return;
  5960. }
  5961. /* Memory to data register */
  5962. REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
  5963. if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
  5964. USE_CYCLES(2);
  5965. return;
  5966. }
  5967. m68ki_exception_privilege_violation();
  5968. return;
  5969. }
  5970. m68ki_exception_illegal();
  5971. }
  5972. M68KMAKE_OP(moves, 16, ., .)
  5973. {
  5974. if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
  5975. {
  5976. if(FLAG_S)
  5977. {
  5978. uint word2 = OPER_I_16();
  5979. uint ea = M68KMAKE_GET_EA_AY_16;
  5980. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  5981. if(BIT_B(word2)) /* Register to memory */
  5982. {
  5983. m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
  5984. return;
  5985. }
  5986. if(BIT_F(word2)) /* Memory to address register */
  5987. {
  5988. REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
  5989. if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
  5990. USE_CYCLES(2);
  5991. return;
  5992. }
  5993. /* Memory to data register */
  5994. REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
  5995. if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
  5996. USE_CYCLES(2);
  5997. return;
  5998. }
  5999. m68ki_exception_privilege_violation();
  6000. return;
  6001. }
  6002. m68ki_exception_illegal();
  6003. }
  6004. M68KMAKE_OP(moves, 32, ., .)
  6005. {
  6006. if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
  6007. {
  6008. if(FLAG_S)
  6009. {
  6010. uint word2 = OPER_I_16();
  6011. uint ea = M68KMAKE_GET_EA_AY_32;
  6012. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  6013. if(BIT_B(word2)) /* Register to memory */
  6014. {
  6015. m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
  6016. if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
  6017. USE_CYCLES(2);
  6018. return;
  6019. }
  6020. /* Memory to register */
  6021. REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
  6022. if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
  6023. USE_CYCLES(2);
  6024. return;
  6025. }
  6026. m68ki_exception_privilege_violation();
  6027. return;
  6028. }
  6029. m68ki_exception_illegal();
  6030. }
  6031. M68KMAKE_OP(moveq, 32, ., .)
  6032. {
  6033. uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR));
  6034. FLAG_N = NFLAG_32(res);
  6035. FLAG_Z = res;
  6036. FLAG_V = VFLAG_CLEAR;
  6037. FLAG_C = CFLAG_CLEAR;
  6038. }
  6039. M68KMAKE_OP(move16, 32, ., .)
  6040. {
  6041. UINT16 w2 = OPER_I_16();
  6042. int ax = REG_IR & 7;
  6043. int ay = (w2 >> 12) & 7;
  6044. m68ki_write_32(REG_A[ay], m68ki_read_32(REG_A[ax]));
  6045. m68ki_write_32(REG_A[ay]+4, m68ki_read_32(REG_A[ax]+4));
  6046. m68ki_write_32(REG_A[ay]+8, m68ki_read_32(REG_A[ax]+8));
  6047. m68ki_write_32(REG_A[ay]+12, m68ki_read_32(REG_A[ax]+12));
  6048. REG_A[ax] += 16;
  6049. REG_A[ay] += 16;
  6050. }
  6051. M68KMAKE_OP(muls, 16, ., d)
  6052. {
  6053. uint* r_dst = &DX;
  6054. uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(DY) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
  6055. *r_dst = res;
  6056. FLAG_Z = res;
  6057. FLAG_N = NFLAG_32(res);
  6058. FLAG_V = VFLAG_CLEAR;
  6059. FLAG_C = CFLAG_CLEAR;
  6060. }
  6061. M68KMAKE_OP(muls, 16, ., .)
  6062. {
  6063. uint* r_dst = &DX;
  6064. uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(M68KMAKE_GET_OPER_AY_16) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
  6065. *r_dst = res;
  6066. FLAG_Z = res;
  6067. FLAG_N = NFLAG_32(res);
  6068. FLAG_V = VFLAG_CLEAR;
  6069. FLAG_C = CFLAG_CLEAR;
  6070. }
  6071. M68KMAKE_OP(mulu, 16, ., d)
  6072. {
  6073. uint* r_dst = &DX;
  6074. uint res = MASK_OUT_ABOVE_16(DY) * MASK_OUT_ABOVE_16(*r_dst);
  6075. *r_dst = res;
  6076. FLAG_Z = res;
  6077. FLAG_N = NFLAG_32(res);
  6078. FLAG_V = VFLAG_CLEAR;
  6079. FLAG_C = CFLAG_CLEAR;
  6080. }
  6081. M68KMAKE_OP(mulu, 16, ., .)
  6082. {
  6083. uint* r_dst = &DX;
  6084. uint res = M68KMAKE_GET_OPER_AY_16 * MASK_OUT_ABOVE_16(*r_dst);
  6085. *r_dst = res;
  6086. FLAG_Z = res;
  6087. FLAG_N = NFLAG_32(res);
  6088. FLAG_V = VFLAG_CLEAR;
  6089. FLAG_C = CFLAG_CLEAR;
  6090. }
  6091. M68KMAKE_OP(mull, 32, ., d)
  6092. {
  6093. #if M68K_USE_64_BIT
  6094. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  6095. {
  6096. uint word2 = OPER_I_16();
  6097. uint64 src = DY;
  6098. uint64 dst = REG_D[(word2 >> 12) & 7];
  6099. uint64 res;
  6100. FLAG_C = CFLAG_CLEAR;
  6101. if(BIT_B(word2)) /* signed */
  6102. {
  6103. res = (sint64)((sint32)src) * (sint64)((sint32)dst);
  6104. if(!BIT_A(word2))
  6105. {
  6106. FLAG_Z = MASK_OUT_ABOVE_32(res);
  6107. FLAG_N = NFLAG_32(res);
  6108. FLAG_V = ((sint64)res != (sint32)res)<<7;
  6109. REG_D[(word2 >> 12) & 7] = FLAG_Z;
  6110. return;
  6111. }
  6112. FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
  6113. FLAG_N = NFLAG_64(res);
  6114. FLAG_V = VFLAG_CLEAR;
  6115. REG_D[word2 & 7] = (res >> 32);
  6116. REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
  6117. return;
  6118. }
  6119. res = src * dst;
  6120. if(!BIT_A(word2))
  6121. {
  6122. FLAG_Z = MASK_OUT_ABOVE_32(res);
  6123. FLAG_N = NFLAG_32(res);
  6124. FLAG_V = (res > 0xffffffff)<<7;
  6125. REG_D[(word2 >> 12) & 7] = FLAG_Z;
  6126. return;
  6127. }
  6128. FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
  6129. FLAG_N = NFLAG_64(res);
  6130. FLAG_V = VFLAG_CLEAR;
  6131. REG_D[word2 & 7] = (res >> 32);
  6132. REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
  6133. return;
  6134. }
  6135. m68ki_exception_illegal();
  6136. #else
  6137. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  6138. {
  6139. uint word2 = OPER_I_16();
  6140. uint src = DY;
  6141. uint dst = REG_D[(word2 >> 12) & 7];
  6142. uint neg = GET_MSB_32(src ^ dst);
  6143. uint src1;
  6144. uint src2;
  6145. uint dst1;
  6146. uint dst2;
  6147. uint r1;
  6148. uint r2;
  6149. uint r3;
  6150. uint r4;
  6151. uint lo;
  6152. uint hi;
  6153. FLAG_C = CFLAG_CLEAR;
  6154. if(BIT_B(word2)) /* signed */
  6155. {
  6156. if(GET_MSB_32(src))
  6157. src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
  6158. if(GET_MSB_32(dst))
  6159. dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
  6160. }
  6161. src1 = MASK_OUT_ABOVE_16(src);
  6162. src2 = src>>16;
  6163. dst1 = MASK_OUT_ABOVE_16(dst);
  6164. dst2 = dst>>16;
  6165. r1 = src1 * dst1;
  6166. r2 = src1 * dst2;
  6167. r3 = src2 * dst1;
  6168. r4 = src2 * dst2;
  6169. lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
  6170. hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
  6171. if(BIT_B(word2) && neg)
  6172. {
  6173. hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
  6174. lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
  6175. }
  6176. if(BIT_A(word2))
  6177. {
  6178. REG_D[word2 & 7] = hi;
  6179. REG_D[(word2 >> 12) & 7] = lo;
  6180. FLAG_N = NFLAG_32(hi);
  6181. FLAG_Z = hi | lo;
  6182. FLAG_V = VFLAG_CLEAR;
  6183. return;
  6184. }
  6185. REG_D[(word2 >> 12) & 7] = lo;
  6186. FLAG_N = NFLAG_32(lo);
  6187. FLAG_Z = lo;
  6188. if(BIT_B(word2))
  6189. FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
  6190. else
  6191. FLAG_V = (hi != 0) << 7;
  6192. return;
  6193. }
  6194. m68ki_exception_illegal();
  6195. #endif
  6196. }
  6197. M68KMAKE_OP(mull, 32, ., .)
  6198. {
  6199. #if M68K_USE_64_BIT
  6200. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  6201. {
  6202. uint word2 = OPER_I_16();
  6203. uint64 src = M68KMAKE_GET_OPER_AY_32;
  6204. uint64 dst = REG_D[(word2 >> 12) & 7];
  6205. uint64 res;
  6206. FLAG_C = CFLAG_CLEAR;
  6207. if(BIT_B(word2)) /* signed */
  6208. {
  6209. res = (sint64)((sint32)src) * (sint64)((sint32)dst);
  6210. if(!BIT_A(word2))
  6211. {
  6212. FLAG_Z = MASK_OUT_ABOVE_32(res);
  6213. FLAG_N = NFLAG_32(res);
  6214. FLAG_V = ((sint64)res != (sint32)res)<<7;
  6215. REG_D[(word2 >> 12) & 7] = FLAG_Z;
  6216. return;
  6217. }
  6218. FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
  6219. FLAG_N = NFLAG_64(res);
  6220. FLAG_V = VFLAG_CLEAR;
  6221. REG_D[word2 & 7] = (res >> 32);
  6222. REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
  6223. return;
  6224. }
  6225. res = src * dst;
  6226. if(!BIT_A(word2))
  6227. {
  6228. FLAG_Z = MASK_OUT_ABOVE_32(res);
  6229. FLAG_N = NFLAG_32(res);
  6230. FLAG_V = (res > 0xffffffff)<<7;
  6231. REG_D[(word2 >> 12) & 7] = FLAG_Z;
  6232. return;
  6233. }
  6234. FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
  6235. FLAG_N = NFLAG_64(res);
  6236. FLAG_V = VFLAG_CLEAR;
  6237. REG_D[word2 & 7] = (res >> 32);
  6238. REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
  6239. return;
  6240. }
  6241. m68ki_exception_illegal();
  6242. #else
  6243. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  6244. {
  6245. uint word2 = OPER_I_16();
  6246. uint src = M68KMAKE_GET_OPER_AY_32;
  6247. uint dst = REG_D[(word2 >> 12) & 7];
  6248. uint neg = GET_MSB_32(src ^ dst);
  6249. uint src1;
  6250. uint src2;
  6251. uint dst1;
  6252. uint dst2;
  6253. uint r1;
  6254. uint r2;
  6255. uint r3;
  6256. uint r4;
  6257. uint lo;
  6258. uint hi;
  6259. FLAG_C = CFLAG_CLEAR;
  6260. if(BIT_B(word2)) /* signed */
  6261. {
  6262. if(GET_MSB_32(src))
  6263. src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
  6264. if(GET_MSB_32(dst))
  6265. dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
  6266. }
  6267. src1 = MASK_OUT_ABOVE_16(src);
  6268. src2 = src>>16;
  6269. dst1 = MASK_OUT_ABOVE_16(dst);
  6270. dst2 = dst>>16;
  6271. r1 = src1 * dst1;
  6272. r2 = src1 * dst2;
  6273. r3 = src2 * dst1;
  6274. r4 = src2 * dst2;
  6275. lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
  6276. hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
  6277. if(BIT_B(word2) && neg)
  6278. {
  6279. hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
  6280. lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
  6281. }
  6282. if(BIT_A(word2))
  6283. {
  6284. REG_D[word2 & 7] = hi;
  6285. REG_D[(word2 >> 12) & 7] = lo;
  6286. FLAG_N = NFLAG_32(hi);
  6287. FLAG_Z = hi | lo;
  6288. FLAG_V = VFLAG_CLEAR;
  6289. return;
  6290. }
  6291. REG_D[(word2 >> 12) & 7] = lo;
  6292. FLAG_N = NFLAG_32(lo);
  6293. FLAG_Z = lo;
  6294. if(BIT_B(word2))
  6295. FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
  6296. else
  6297. FLAG_V = (hi != 0) << 7;
  6298. return;
  6299. }
  6300. m68ki_exception_illegal();
  6301. #endif
  6302. }
  6303. M68KMAKE_OP(nbcd, 8, ., d)
  6304. {
  6305. uint* r_dst = &DY;
  6306. uint dst = MASK_OUT_ABOVE_8(*r_dst);
  6307. uint res = -dst - XFLAG_AS_1();
  6308. if(res != 0)
  6309. {
  6310. FLAG_V = res; /* Undefined V behavior */
  6311. if(((res|dst) & 0x0f) == 0)
  6312. res = (res & 0xf0) + 6;
  6313. res = MASK_OUT_ABOVE_8(res + 0x9a);
  6314. FLAG_V &= ~res; /* Undefined V behavior part II */
  6315. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  6316. FLAG_Z |= res;
  6317. FLAG_C = CFLAG_SET;
  6318. FLAG_X = XFLAG_SET;
  6319. }
  6320. else
  6321. {
  6322. FLAG_V = VFLAG_CLEAR;
  6323. FLAG_C = CFLAG_CLEAR;
  6324. FLAG_X = XFLAG_CLEAR;
  6325. }
  6326. FLAG_N = NFLAG_8(res); /* Undefined N behavior */
  6327. }
  6328. M68KMAKE_OP(nbcd, 8, ., .)
  6329. {
  6330. uint ea = M68KMAKE_GET_EA_AY_8;
  6331. uint dst = m68ki_read_8(ea);
  6332. uint res = -dst - XFLAG_AS_1();
  6333. if(res != 0)
  6334. {
  6335. FLAG_V = res; /* Undefined V behavior */
  6336. if(((res|dst) & 0x0f) == 0)
  6337. res = (res & 0xf0) + 6;
  6338. res = MASK_OUT_ABOVE_8(res + 0x9a);
  6339. FLAG_V &= ~res; /* Undefined V behavior part II */
  6340. m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
  6341. FLAG_Z |= res;
  6342. FLAG_C = CFLAG_SET;
  6343. FLAG_X = XFLAG_SET;
  6344. }
  6345. else
  6346. {
  6347. FLAG_V = VFLAG_CLEAR;
  6348. FLAG_C = CFLAG_CLEAR;
  6349. FLAG_X = XFLAG_CLEAR;
  6350. }
  6351. FLAG_N = NFLAG_8(res); /* Undefined N behavior */
  6352. }
  6353. M68KMAKE_OP(neg, 8, ., d)
  6354. {
  6355. uint* r_dst = &DY;
  6356. uint res = 0 - MASK_OUT_ABOVE_8(*r_dst);
  6357. FLAG_N = NFLAG_8(res);
  6358. FLAG_C = FLAG_X = CFLAG_8(res);
  6359. FLAG_V = *r_dst & res;
  6360. FLAG_Z = MASK_OUT_ABOVE_8(res);
  6361. *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
  6362. }
  6363. M68KMAKE_OP(neg, 8, ., .)
  6364. {
  6365. uint ea = M68KMAKE_GET_EA_AY_8;
  6366. uint src = m68ki_read_8(ea);
  6367. uint res = 0 - src;
  6368. FLAG_N = NFLAG_8(res);
  6369. FLAG_C = FLAG_X = CFLAG_8(res);
  6370. FLAG_V = src & res;
  6371. FLAG_Z = MASK_OUT_ABOVE_8(res);
  6372. m68ki_write_8(ea, FLAG_Z);
  6373. }
  6374. M68KMAKE_OP(neg, 16, ., d)
  6375. {
  6376. uint* r_dst = &DY;
  6377. uint res = 0 - MASK_OUT_ABOVE_16(*r_dst);
  6378. FLAG_N = NFLAG_16(res);
  6379. FLAG_C = FLAG_X = CFLAG_16(res);
  6380. FLAG_V = (*r_dst & res)>>8;
  6381. FLAG_Z = MASK_OUT_ABOVE_16(res);
  6382. *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
  6383. }
  6384. M68KMAKE_OP(neg, 16, ., .)
  6385. {
  6386. uint ea = M68KMAKE_GET_EA_AY_16;
  6387. uint src = m68ki_read_16(ea);
  6388. uint res = 0 - src;
  6389. FLAG_N = NFLAG_16(res);
  6390. FLAG_C = FLAG_X = CFLAG_16(res);
  6391. FLAG_V = (src & res)>>8;
  6392. FLAG_Z = MASK_OUT_ABOVE_16(res);
  6393. m68ki_write_16(ea, FLAG_Z);
  6394. }
  6395. M68KMAKE_OP(neg, 32, ., d)
  6396. {
  6397. uint* r_dst = &DY;
  6398. uint res = 0 - *r_dst;
  6399. FLAG_N = NFLAG_32(res);
  6400. FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res);
  6401. FLAG_V = (*r_dst & res)>>24;
  6402. FLAG_Z = MASK_OUT_ABOVE_32(res);
  6403. *r_dst = FLAG_Z;
  6404. }
  6405. M68KMAKE_OP(neg, 32, ., .)
  6406. {
  6407. uint ea = M68KMAKE_GET_EA_AY_32;
  6408. uint src = m68ki_read_32(ea);
  6409. uint res = 0 - src;
  6410. FLAG_N = NFLAG_32(res);
  6411. FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
  6412. FLAG_V = (src & res)>>24;
  6413. FLAG_Z = MASK_OUT_ABOVE_32(res);
  6414. m68ki_write_32(ea, FLAG_Z);
  6415. }
  6416. M68KMAKE_OP(negx, 8, ., d)
  6417. {
  6418. uint* r_dst = &DY;
  6419. uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1();
  6420. FLAG_N = NFLAG_8(res);
  6421. FLAG_X = FLAG_C = CFLAG_8(res);
  6422. FLAG_V = *r_dst & res;
  6423. res = MASK_OUT_ABOVE_8(res);
  6424. FLAG_Z |= res;
  6425. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  6426. }
  6427. M68KMAKE_OP(negx, 8, ., .)
  6428. {
  6429. uint ea = M68KMAKE_GET_EA_AY_8;
  6430. uint src = m68ki_read_8(ea);
  6431. uint res = 0 - src - XFLAG_AS_1();
  6432. FLAG_N = NFLAG_8(res);
  6433. FLAG_X = FLAG_C = CFLAG_8(res);
  6434. FLAG_V = src & res;
  6435. res = MASK_OUT_ABOVE_8(res);
  6436. FLAG_Z |= res;
  6437. m68ki_write_8(ea, res);
  6438. }
  6439. M68KMAKE_OP(negx, 16, ., d)
  6440. {
  6441. uint* r_dst = &DY;
  6442. uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1();
  6443. FLAG_N = NFLAG_16(res);
  6444. FLAG_X = FLAG_C = CFLAG_16(res);
  6445. FLAG_V = (*r_dst & res)>>8;
  6446. res = MASK_OUT_ABOVE_16(res);
  6447. FLAG_Z |= res;
  6448. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  6449. }
  6450. M68KMAKE_OP(negx, 16, ., .)
  6451. {
  6452. uint ea = M68KMAKE_GET_EA_AY_16;
  6453. uint src = m68ki_read_16(ea);
  6454. uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
  6455. FLAG_N = NFLAG_16(res);
  6456. FLAG_X = FLAG_C = CFLAG_16(res);
  6457. FLAG_V = (src & res)>>8;
  6458. res = MASK_OUT_ABOVE_16(res);
  6459. FLAG_Z |= res;
  6460. m68ki_write_16(ea, res);
  6461. }
  6462. M68KMAKE_OP(negx, 32, ., d)
  6463. {
  6464. uint* r_dst = &DY;
  6465. uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1();
  6466. FLAG_N = NFLAG_32(res);
  6467. FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res);
  6468. FLAG_V = (*r_dst & res)>>24;
  6469. res = MASK_OUT_ABOVE_32(res);
  6470. FLAG_Z |= res;
  6471. *r_dst = res;
  6472. }
  6473. M68KMAKE_OP(negx, 32, ., .)
  6474. {
  6475. uint ea = M68KMAKE_GET_EA_AY_32;
  6476. uint src = m68ki_read_32(ea);
  6477. uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
  6478. FLAG_N = NFLAG_32(res);
  6479. FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
  6480. FLAG_V = (src & res)>>24;
  6481. res = MASK_OUT_ABOVE_32(res);
  6482. FLAG_Z |= res;
  6483. m68ki_write_32(ea, res);
  6484. }
  6485. M68KMAKE_OP(nop, 0, ., .)
  6486. {
  6487. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  6488. }
  6489. M68KMAKE_OP(not, 8, ., d)
  6490. {
  6491. uint* r_dst = &DY;
  6492. uint res = MASK_OUT_ABOVE_8(~*r_dst);
  6493. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  6494. FLAG_N = NFLAG_8(res);
  6495. FLAG_Z = res;
  6496. FLAG_C = CFLAG_CLEAR;
  6497. FLAG_V = VFLAG_CLEAR;
  6498. }
  6499. M68KMAKE_OP(not, 8, ., .)
  6500. {
  6501. uint ea = M68KMAKE_GET_EA_AY_8;
  6502. uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
  6503. m68ki_write_8(ea, res);
  6504. FLAG_N = NFLAG_8(res);
  6505. FLAG_Z = res;
  6506. FLAG_C = CFLAG_CLEAR;
  6507. FLAG_V = VFLAG_CLEAR;
  6508. }
  6509. M68KMAKE_OP(not, 16, ., d)
  6510. {
  6511. uint* r_dst = &DY;
  6512. uint res = MASK_OUT_ABOVE_16(~*r_dst);
  6513. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  6514. FLAG_N = NFLAG_16(res);
  6515. FLAG_Z = res;
  6516. FLAG_C = CFLAG_CLEAR;
  6517. FLAG_V = VFLAG_CLEAR;
  6518. }
  6519. M68KMAKE_OP(not, 16, ., .)
  6520. {
  6521. uint ea = M68KMAKE_GET_EA_AY_16;
  6522. uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
  6523. m68ki_write_16(ea, res);
  6524. FLAG_N = NFLAG_16(res);
  6525. FLAG_Z = res;
  6526. FLAG_C = CFLAG_CLEAR;
  6527. FLAG_V = VFLAG_CLEAR;
  6528. }
  6529. M68KMAKE_OP(not, 32, ., d)
  6530. {
  6531. uint* r_dst = &DY;
  6532. uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst);
  6533. FLAG_N = NFLAG_32(res);
  6534. FLAG_Z = res;
  6535. FLAG_C = CFLAG_CLEAR;
  6536. FLAG_V = VFLAG_CLEAR;
  6537. }
  6538. M68KMAKE_OP(not, 32, ., .)
  6539. {
  6540. uint ea = M68KMAKE_GET_EA_AY_32;
  6541. uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
  6542. m68ki_write_32(ea, res);
  6543. FLAG_N = NFLAG_32(res);
  6544. FLAG_Z = res;
  6545. FLAG_C = CFLAG_CLEAR;
  6546. FLAG_V = VFLAG_CLEAR;
  6547. }
  6548. M68KMAKE_OP(or, 8, er, d)
  6549. {
  6550. uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY)));
  6551. FLAG_N = NFLAG_8(res);
  6552. FLAG_Z = res;
  6553. FLAG_C = CFLAG_CLEAR;
  6554. FLAG_V = VFLAG_CLEAR;
  6555. }
  6556. M68KMAKE_OP(or, 8, er, .)
  6557. {
  6558. uint res = MASK_OUT_ABOVE_8((DX |= M68KMAKE_GET_OPER_AY_8));
  6559. FLAG_N = NFLAG_8(res);
  6560. FLAG_Z = res;
  6561. FLAG_C = CFLAG_CLEAR;
  6562. FLAG_V = VFLAG_CLEAR;
  6563. }
  6564. M68KMAKE_OP(or, 16, er, d)
  6565. {
  6566. uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY)));
  6567. FLAG_N = NFLAG_16(res);
  6568. FLAG_Z = res;
  6569. FLAG_C = CFLAG_CLEAR;
  6570. FLAG_V = VFLAG_CLEAR;
  6571. }
  6572. M68KMAKE_OP(or, 16, er, .)
  6573. {
  6574. uint res = MASK_OUT_ABOVE_16((DX |= M68KMAKE_GET_OPER_AY_16));
  6575. FLAG_N = NFLAG_16(res);
  6576. FLAG_Z = res;
  6577. FLAG_C = CFLAG_CLEAR;
  6578. FLAG_V = VFLAG_CLEAR;
  6579. }
  6580. M68KMAKE_OP(or, 32, er, d)
  6581. {
  6582. uint res = DX |= DY;
  6583. FLAG_N = NFLAG_32(res);
  6584. FLAG_Z = res;
  6585. FLAG_C = CFLAG_CLEAR;
  6586. FLAG_V = VFLAG_CLEAR;
  6587. }
  6588. M68KMAKE_OP(or, 32, er, .)
  6589. {
  6590. uint res = DX |= M68KMAKE_GET_OPER_AY_32;
  6591. FLAG_N = NFLAG_32(res);
  6592. FLAG_Z = res;
  6593. FLAG_C = CFLAG_CLEAR;
  6594. FLAG_V = VFLAG_CLEAR;
  6595. }
  6596. M68KMAKE_OP(or, 8, re, .)
  6597. {
  6598. uint ea = M68KMAKE_GET_EA_AY_8;
  6599. uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
  6600. m68ki_write_8(ea, res);
  6601. FLAG_N = NFLAG_8(res);
  6602. FLAG_Z = res;
  6603. FLAG_C = CFLAG_CLEAR;
  6604. FLAG_V = VFLAG_CLEAR;
  6605. }
  6606. M68KMAKE_OP(or, 16, re, .)
  6607. {
  6608. uint ea = M68KMAKE_GET_EA_AY_16;
  6609. uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
  6610. m68ki_write_16(ea, res);
  6611. FLAG_N = NFLAG_16(res);
  6612. FLAG_Z = res;
  6613. FLAG_C = CFLAG_CLEAR;
  6614. FLAG_V = VFLAG_CLEAR;
  6615. }
  6616. M68KMAKE_OP(or, 32, re, .)
  6617. {
  6618. uint ea = M68KMAKE_GET_EA_AY_32;
  6619. uint res = DX | m68ki_read_32(ea);
  6620. m68ki_write_32(ea, res);
  6621. FLAG_N = NFLAG_32(res);
  6622. FLAG_Z = res;
  6623. FLAG_C = CFLAG_CLEAR;
  6624. FLAG_V = VFLAG_CLEAR;
  6625. }
  6626. M68KMAKE_OP(ori, 8, ., d)
  6627. {
  6628. uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8()));
  6629. FLAG_N = NFLAG_8(res);
  6630. FLAG_Z = res;
  6631. FLAG_C = CFLAG_CLEAR;
  6632. FLAG_V = VFLAG_CLEAR;
  6633. }
  6634. M68KMAKE_OP(ori, 8, ., .)
  6635. {
  6636. uint src = OPER_I_8();
  6637. uint ea = M68KMAKE_GET_EA_AY_8;
  6638. uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
  6639. m68ki_write_8(ea, res);
  6640. FLAG_N = NFLAG_8(res);
  6641. FLAG_Z = res;
  6642. FLAG_C = CFLAG_CLEAR;
  6643. FLAG_V = VFLAG_CLEAR;
  6644. }
  6645. M68KMAKE_OP(ori, 16, ., d)
  6646. {
  6647. uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16());
  6648. FLAG_N = NFLAG_16(res);
  6649. FLAG_Z = res;
  6650. FLAG_C = CFLAG_CLEAR;
  6651. FLAG_V = VFLAG_CLEAR;
  6652. }
  6653. M68KMAKE_OP(ori, 16, ., .)
  6654. {
  6655. uint src = OPER_I_16();
  6656. uint ea = M68KMAKE_GET_EA_AY_16;
  6657. uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
  6658. m68ki_write_16(ea, res);
  6659. FLAG_N = NFLAG_16(res);
  6660. FLAG_Z = res;
  6661. FLAG_C = CFLAG_CLEAR;
  6662. FLAG_V = VFLAG_CLEAR;
  6663. }
  6664. M68KMAKE_OP(ori, 32, ., d)
  6665. {
  6666. uint res = DY |= OPER_I_32();
  6667. FLAG_N = NFLAG_32(res);
  6668. FLAG_Z = res;
  6669. FLAG_C = CFLAG_CLEAR;
  6670. FLAG_V = VFLAG_CLEAR;
  6671. }
  6672. M68KMAKE_OP(ori, 32, ., .)
  6673. {
  6674. uint src = OPER_I_32();
  6675. uint ea = M68KMAKE_GET_EA_AY_32;
  6676. uint res = src | m68ki_read_32(ea);
  6677. m68ki_write_32(ea, res);
  6678. FLAG_N = NFLAG_32(res);
  6679. FLAG_Z = res;
  6680. FLAG_C = CFLAG_CLEAR;
  6681. FLAG_V = VFLAG_CLEAR;
  6682. }
  6683. M68KMAKE_OP(ori, 16, toc, .)
  6684. {
  6685. m68ki_set_ccr(m68ki_get_ccr() | OPER_I_16());
  6686. }
  6687. M68KMAKE_OP(ori, 16, tos, .)
  6688. {
  6689. if(FLAG_S)
  6690. {
  6691. uint src = OPER_I_16();
  6692. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  6693. m68ki_set_sr(m68ki_get_sr() | src);
  6694. return;
  6695. }
  6696. m68ki_exception_privilege_violation();
  6697. }
  6698. M68KMAKE_OP(pack, 16, rr, .)
  6699. {
  6700. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  6701. {
  6702. /* Note: DX and DY are reversed in Motorola's docs */
  6703. uint src = DY + OPER_I_16();
  6704. uint* r_dst = &DX;
  6705. *r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f);
  6706. return;
  6707. }
  6708. m68ki_exception_illegal();
  6709. }
  6710. M68KMAKE_OP(pack, 16, mm, ax7)
  6711. {
  6712. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  6713. {
  6714. /* Note: AX and AY are reversed in Motorola's docs */
  6715. uint ea_src = EA_AY_PD_8();
  6716. uint src = m68ki_read_8(ea_src);
  6717. ea_src = EA_AY_PD_8();
  6718. src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
  6719. m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
  6720. return;
  6721. }
  6722. m68ki_exception_illegal();
  6723. }
  6724. M68KMAKE_OP(pack, 16, mm, ay7)
  6725. {
  6726. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  6727. {
  6728. /* Note: AX and AY are reversed in Motorola's docs */
  6729. uint ea_src = EA_A7_PD_8();
  6730. uint src = m68ki_read_8(ea_src);
  6731. ea_src = EA_A7_PD_8();
  6732. src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
  6733. m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
  6734. return;
  6735. }
  6736. m68ki_exception_illegal();
  6737. }
  6738. M68KMAKE_OP(pack, 16, mm, axy7)
  6739. {
  6740. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  6741. {
  6742. uint ea_src = EA_A7_PD_8();
  6743. uint src = m68ki_read_8(ea_src);
  6744. ea_src = EA_A7_PD_8();
  6745. src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
  6746. m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
  6747. return;
  6748. }
  6749. m68ki_exception_illegal();
  6750. }
  6751. M68KMAKE_OP(pack, 16, mm, .)
  6752. {
  6753. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  6754. {
  6755. /* Note: AX and AY are reversed in Motorola's docs */
  6756. uint ea_src = EA_AY_PD_8();
  6757. uint src = m68ki_read_8(ea_src);
  6758. ea_src = EA_AY_PD_8();
  6759. src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
  6760. m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
  6761. return;
  6762. }
  6763. m68ki_exception_illegal();
  6764. }
  6765. M68KMAKE_OP(pea, 32, ., .)
  6766. {
  6767. uint ea = M68KMAKE_GET_EA_AY_32;
  6768. m68ki_push_32(ea);
  6769. }
  6770. M68KMAKE_OP(pflush, 32, ., .)
  6771. {
  6772. if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  6773. {
  6774. // Nothing to do, unless address translation cache is emulated
  6775. return;
  6776. }
  6777. m68ki_exception_illegal();
  6778. }
  6779. M68KMAKE_OP(reset, 0, ., .)
  6780. {
  6781. if(FLAG_S)
  6782. {
  6783. m68ki_output_reset(); /* auto-disable (see m68kcpu.h) */
  6784. USE_CYCLES(CYC_RESET);
  6785. return;
  6786. }
  6787. m68ki_exception_privilege_violation();
  6788. }
  6789. M68KMAKE_OP(ror, 8, s, .)
  6790. {
  6791. uint* r_dst = &DY;
  6792. uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
  6793. uint shift = orig_shift & 7;
  6794. uint src = MASK_OUT_ABOVE_8(*r_dst);
  6795. uint res = ROR_8(src, shift);
  6796. if(orig_shift != 0)
  6797. USE_CYCLES(orig_shift<<CYC_SHIFT);
  6798. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  6799. FLAG_N = NFLAG_8(res);
  6800. FLAG_Z = res;
  6801. FLAG_C = src << (9-orig_shift);
  6802. FLAG_V = VFLAG_CLEAR;
  6803. }
  6804. M68KMAKE_OP(ror, 16, s, .)
  6805. {
  6806. uint* r_dst = &DY;
  6807. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  6808. uint src = MASK_OUT_ABOVE_16(*r_dst);
  6809. uint res = ROR_16(src, shift);
  6810. if(shift != 0)
  6811. USE_CYCLES(shift<<CYC_SHIFT);
  6812. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  6813. FLAG_N = NFLAG_16(res);
  6814. FLAG_Z = res;
  6815. FLAG_C = src << (9-shift);
  6816. FLAG_V = VFLAG_CLEAR;
  6817. }
  6818. M68KMAKE_OP(ror, 32, s, .)
  6819. {
  6820. uint* r_dst = &DY;
  6821. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  6822. uint64 src = *r_dst;
  6823. uint res = ROR_32(src, shift);
  6824. if(shift != 0)
  6825. USE_CYCLES(shift<<CYC_SHIFT);
  6826. *r_dst = res;
  6827. FLAG_N = NFLAG_32(res);
  6828. FLAG_Z = res;
  6829. FLAG_C = src << (9-shift);
  6830. FLAG_V = VFLAG_CLEAR;
  6831. }
  6832. M68KMAKE_OP(ror, 8, r, .)
  6833. {
  6834. uint* r_dst = &DY;
  6835. uint orig_shift = DX & 0x3f;
  6836. uint shift = orig_shift & 7;
  6837. uint src = MASK_OUT_ABOVE_8(*r_dst);
  6838. uint res = ROR_8(src, shift);
  6839. if(orig_shift != 0)
  6840. {
  6841. USE_CYCLES(orig_shift<<CYC_SHIFT);
  6842. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  6843. FLAG_C = src << (8-((shift-1)&7));
  6844. FLAG_N = NFLAG_8(res);
  6845. FLAG_Z = res;
  6846. FLAG_V = VFLAG_CLEAR;
  6847. return;
  6848. }
  6849. FLAG_C = CFLAG_CLEAR;
  6850. FLAG_N = NFLAG_8(src);
  6851. FLAG_Z = src;
  6852. FLAG_V = VFLAG_CLEAR;
  6853. }
  6854. M68KMAKE_OP(ror, 16, r, .)
  6855. {
  6856. uint* r_dst = &DY;
  6857. uint orig_shift = DX & 0x3f;
  6858. uint shift = orig_shift & 15;
  6859. uint src = MASK_OUT_ABOVE_16(*r_dst);
  6860. uint res = ROR_16(src, shift);
  6861. if(orig_shift != 0)
  6862. {
  6863. USE_CYCLES(orig_shift<<CYC_SHIFT);
  6864. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  6865. FLAG_C = (src >> ((shift - 1) & 15)) << 8;
  6866. FLAG_N = NFLAG_16(res);
  6867. FLAG_Z = res;
  6868. FLAG_V = VFLAG_CLEAR;
  6869. return;
  6870. }
  6871. FLAG_C = CFLAG_CLEAR;
  6872. FLAG_N = NFLAG_16(src);
  6873. FLAG_Z = src;
  6874. FLAG_V = VFLAG_CLEAR;
  6875. }
  6876. M68KMAKE_OP(ror, 32, r, .)
  6877. {
  6878. uint* r_dst = &DY;
  6879. uint orig_shift = DX & 0x3f;
  6880. uint shift = orig_shift & 31;
  6881. uint64 src = *r_dst;
  6882. uint res = ROR_32(src, shift);
  6883. if(orig_shift != 0)
  6884. {
  6885. USE_CYCLES(orig_shift<<CYC_SHIFT);
  6886. *r_dst = res;
  6887. FLAG_C = (src >> ((shift - 1) & 31)) << 8;
  6888. FLAG_N = NFLAG_32(res);
  6889. FLAG_Z = res;
  6890. FLAG_V = VFLAG_CLEAR;
  6891. return;
  6892. }
  6893. FLAG_C = CFLAG_CLEAR;
  6894. FLAG_N = NFLAG_32(src);
  6895. FLAG_Z = src;
  6896. FLAG_V = VFLAG_CLEAR;
  6897. }
  6898. M68KMAKE_OP(ror, 16, ., .)
  6899. {
  6900. uint ea = M68KMAKE_GET_EA_AY_16;
  6901. uint src = m68ki_read_16(ea);
  6902. uint res = ROR_16(src, 1);
  6903. m68ki_write_16(ea, res);
  6904. FLAG_N = NFLAG_16(res);
  6905. FLAG_Z = res;
  6906. FLAG_C = src << 8;
  6907. FLAG_V = VFLAG_CLEAR;
  6908. }
  6909. M68KMAKE_OP(rol, 8, s, .)
  6910. {
  6911. uint* r_dst = &DY;
  6912. uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
  6913. uint shift = orig_shift & 7;
  6914. uint src = MASK_OUT_ABOVE_8(*r_dst);
  6915. uint res = ROL_8(src, shift);
  6916. if(orig_shift != 0)
  6917. USE_CYCLES(orig_shift<<CYC_SHIFT);
  6918. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  6919. FLAG_N = NFLAG_8(res);
  6920. FLAG_Z = res;
  6921. FLAG_C = src << orig_shift;
  6922. FLAG_V = VFLAG_CLEAR;
  6923. }
  6924. M68KMAKE_OP(rol, 16, s, .)
  6925. {
  6926. uint* r_dst = &DY;
  6927. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  6928. uint src = MASK_OUT_ABOVE_16(*r_dst);
  6929. uint res = ROL_16(src, shift);
  6930. if(shift != 0)
  6931. USE_CYCLES(shift<<CYC_SHIFT);
  6932. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  6933. FLAG_N = NFLAG_16(res);
  6934. FLAG_Z = res;
  6935. FLAG_C = src >> (8-shift);
  6936. FLAG_V = VFLAG_CLEAR;
  6937. }
  6938. M68KMAKE_OP(rol, 32, s, .)
  6939. {
  6940. uint* r_dst = &DY;
  6941. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  6942. uint64 src = *r_dst;
  6943. uint res = ROL_32(src, shift);
  6944. if(shift != 0)
  6945. USE_CYCLES(shift<<CYC_SHIFT);
  6946. *r_dst = res;
  6947. FLAG_N = NFLAG_32(res);
  6948. FLAG_Z = res;
  6949. FLAG_C = src >> (24-shift);
  6950. FLAG_V = VFLAG_CLEAR;
  6951. }
  6952. M68KMAKE_OP(rol, 8, r, .)
  6953. {
  6954. uint* r_dst = &DY;
  6955. uint orig_shift = DX & 0x3f;
  6956. uint shift = orig_shift & 7;
  6957. uint src = MASK_OUT_ABOVE_8(*r_dst);
  6958. uint res = ROL_8(src, shift);
  6959. if(orig_shift != 0)
  6960. {
  6961. USE_CYCLES(orig_shift<<CYC_SHIFT);
  6962. if(shift != 0)
  6963. {
  6964. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  6965. FLAG_C = src << shift;
  6966. FLAG_N = NFLAG_8(res);
  6967. FLAG_Z = res;
  6968. FLAG_V = VFLAG_CLEAR;
  6969. return;
  6970. }
  6971. FLAG_C = (src & 1)<<8;
  6972. FLAG_N = NFLAG_8(src);
  6973. FLAG_Z = src;
  6974. FLAG_V = VFLAG_CLEAR;
  6975. return;
  6976. }
  6977. FLAG_C = CFLAG_CLEAR;
  6978. FLAG_N = NFLAG_8(src);
  6979. FLAG_Z = src;
  6980. FLAG_V = VFLAG_CLEAR;
  6981. }
  6982. M68KMAKE_OP(rol, 16, r, .)
  6983. {
  6984. uint* r_dst = &DY;
  6985. uint orig_shift = DX & 0x3f;
  6986. uint shift = orig_shift & 15;
  6987. uint src = MASK_OUT_ABOVE_16(*r_dst);
  6988. uint res = MASK_OUT_ABOVE_16(ROL_16(src, shift));
  6989. if(orig_shift != 0)
  6990. {
  6991. USE_CYCLES(orig_shift<<CYC_SHIFT);
  6992. if(shift != 0)
  6993. {
  6994. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  6995. FLAG_C = (src << shift) >> 8;
  6996. FLAG_N = NFLAG_16(res);
  6997. FLAG_Z = res;
  6998. FLAG_V = VFLAG_CLEAR;
  6999. return;
  7000. }
  7001. FLAG_C = (src & 1)<<8;
  7002. FLAG_N = NFLAG_16(src);
  7003. FLAG_Z = src;
  7004. FLAG_V = VFLAG_CLEAR;
  7005. return;
  7006. }
  7007. FLAG_C = CFLAG_CLEAR;
  7008. FLAG_N = NFLAG_16(src);
  7009. FLAG_Z = src;
  7010. FLAG_V = VFLAG_CLEAR;
  7011. }
  7012. M68KMAKE_OP(rol, 32, r, .)
  7013. {
  7014. uint* r_dst = &DY;
  7015. uint orig_shift = DX & 0x3f;
  7016. uint shift = orig_shift & 31;
  7017. uint64 src = *r_dst;
  7018. uint res = ROL_32(src, shift);
  7019. if(orig_shift != 0)
  7020. {
  7021. USE_CYCLES(orig_shift<<CYC_SHIFT);
  7022. *r_dst = res;
  7023. FLAG_C = (src >> ((32 - shift) & 0x1f)) << 8;
  7024. FLAG_N = NFLAG_32(res);
  7025. FLAG_Z = res;
  7026. FLAG_V = VFLAG_CLEAR;
  7027. return;
  7028. }
  7029. FLAG_C = CFLAG_CLEAR;
  7030. FLAG_N = NFLAG_32(src);
  7031. FLAG_Z = src;
  7032. FLAG_V = VFLAG_CLEAR;
  7033. }
  7034. M68KMAKE_OP(rol, 16, ., .)
  7035. {
  7036. uint ea = M68KMAKE_GET_EA_AY_16;
  7037. uint src = m68ki_read_16(ea);
  7038. uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
  7039. m68ki_write_16(ea, res);
  7040. FLAG_N = NFLAG_16(res);
  7041. FLAG_Z = res;
  7042. FLAG_C = src >> 7;
  7043. FLAG_V = VFLAG_CLEAR;
  7044. }
  7045. M68KMAKE_OP(roxr, 8, s, .)
  7046. {
  7047. uint* r_dst = &DY;
  7048. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  7049. uint src = MASK_OUT_ABOVE_8(*r_dst);
  7050. uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
  7051. if(shift != 0)
  7052. USE_CYCLES(shift<<CYC_SHIFT);
  7053. FLAG_C = FLAG_X = res;
  7054. res = MASK_OUT_ABOVE_8(res);
  7055. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  7056. FLAG_N = NFLAG_8(res);
  7057. FLAG_Z = res;
  7058. FLAG_V = VFLAG_CLEAR;
  7059. }
  7060. M68KMAKE_OP(roxr, 16, s, .)
  7061. {
  7062. uint* r_dst = &DY;
  7063. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  7064. uint src = MASK_OUT_ABOVE_16(*r_dst);
  7065. uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
  7066. if(shift != 0)
  7067. USE_CYCLES(shift<<CYC_SHIFT);
  7068. FLAG_C = FLAG_X = res >> 8;
  7069. res = MASK_OUT_ABOVE_16(res);
  7070. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  7071. FLAG_N = NFLAG_16(res);
  7072. FLAG_Z = res;
  7073. FLAG_V = VFLAG_CLEAR;
  7074. }
  7075. M68KMAKE_OP(roxr, 32, s, .)
  7076. {
  7077. #if M68K_USE_64_BIT
  7078. uint* r_dst = &DY;
  7079. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  7080. uint64 src = *r_dst;
  7081. uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
  7082. if(shift != 0)
  7083. USE_CYCLES(shift<<CYC_SHIFT);
  7084. res = ROR_33_64(res, shift);
  7085. FLAG_C = FLAG_X = res >> 24;
  7086. res = MASK_OUT_ABOVE_32(res);
  7087. *r_dst = res;
  7088. FLAG_N = NFLAG_32(res);
  7089. FLAG_Z = res;
  7090. FLAG_V = VFLAG_CLEAR;
  7091. #else
  7092. uint* r_dst = &DY;
  7093. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  7094. uint src = *r_dst;
  7095. uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
  7096. uint new_x_flag = src & (1 << (shift - 1));
  7097. if(shift != 0)
  7098. USE_CYCLES(shift<<CYC_SHIFT);
  7099. *r_dst = res;
  7100. FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
  7101. FLAG_N = NFLAG_32(res);
  7102. FLAG_Z = res;
  7103. FLAG_V = VFLAG_CLEAR;
  7104. #endif
  7105. }
  7106. M68KMAKE_OP(roxr, 8, r, .)
  7107. {
  7108. uint* r_dst = &DY;
  7109. uint orig_shift = DX & 0x3f;
  7110. if(orig_shift != 0)
  7111. {
  7112. uint shift = orig_shift % 9;
  7113. uint src = MASK_OUT_ABOVE_8(*r_dst);
  7114. uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
  7115. USE_CYCLES(orig_shift<<CYC_SHIFT);
  7116. FLAG_C = FLAG_X = res;
  7117. res = MASK_OUT_ABOVE_8(res);
  7118. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  7119. FLAG_N = NFLAG_8(res);
  7120. FLAG_Z = res;
  7121. FLAG_V = VFLAG_CLEAR;
  7122. return;
  7123. }
  7124. FLAG_C = FLAG_X;
  7125. FLAG_N = NFLAG_8(*r_dst);
  7126. FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
  7127. FLAG_V = VFLAG_CLEAR;
  7128. }
  7129. M68KMAKE_OP(roxr, 16, r, .)
  7130. {
  7131. uint* r_dst = &DY;
  7132. uint orig_shift = DX & 0x3f;
  7133. if(orig_shift != 0)
  7134. {
  7135. uint shift = orig_shift % 17;
  7136. uint src = MASK_OUT_ABOVE_16(*r_dst);
  7137. uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
  7138. USE_CYCLES(orig_shift<<CYC_SHIFT);
  7139. FLAG_C = FLAG_X = res >> 8;
  7140. res = MASK_OUT_ABOVE_16(res);
  7141. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  7142. FLAG_N = NFLAG_16(res);
  7143. FLAG_Z = res;
  7144. FLAG_V = VFLAG_CLEAR;
  7145. return;
  7146. }
  7147. FLAG_C = FLAG_X;
  7148. FLAG_N = NFLAG_16(*r_dst);
  7149. FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
  7150. FLAG_V = VFLAG_CLEAR;
  7151. }
  7152. M68KMAKE_OP(roxr, 32, r, .)
  7153. {
  7154. #if M68K_USE_64_BIT
  7155. uint* r_dst = &DY;
  7156. uint orig_shift = DX & 0x3f;
  7157. if(orig_shift != 0)
  7158. {
  7159. uint shift = orig_shift % 33;
  7160. uint64 src = *r_dst;
  7161. uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
  7162. res = ROR_33_64(res, shift);
  7163. USE_CYCLES(orig_shift<<CYC_SHIFT);
  7164. FLAG_C = FLAG_X = res >> 24;
  7165. res = MASK_OUT_ABOVE_32(res);
  7166. *r_dst = res;
  7167. FLAG_N = NFLAG_32(res);
  7168. FLAG_Z = res;
  7169. FLAG_V = VFLAG_CLEAR;
  7170. return;
  7171. }
  7172. FLAG_C = FLAG_X;
  7173. FLAG_N = NFLAG_32(*r_dst);
  7174. FLAG_Z = *r_dst;
  7175. FLAG_V = VFLAG_CLEAR;
  7176. #else
  7177. uint* r_dst = &DY;
  7178. uint orig_shift = DX & 0x3f;
  7179. uint shift = orig_shift % 33;
  7180. uint src = *r_dst;
  7181. uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
  7182. uint new_x_flag = src & (1 << (shift - 1));
  7183. if(orig_shift != 0)
  7184. USE_CYCLES(orig_shift<<CYC_SHIFT);
  7185. if(shift != 0)
  7186. {
  7187. *r_dst = res;
  7188. FLAG_X = (new_x_flag != 0)<<8;
  7189. }
  7190. else
  7191. res = src;
  7192. FLAG_C = FLAG_X;
  7193. FLAG_N = NFLAG_32(res);
  7194. FLAG_Z = res;
  7195. FLAG_V = VFLAG_CLEAR;
  7196. #endif
  7197. }
  7198. M68KMAKE_OP(roxr, 16, ., .)
  7199. {
  7200. uint ea = M68KMAKE_GET_EA_AY_16;
  7201. uint src = m68ki_read_16(ea);
  7202. uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
  7203. FLAG_C = FLAG_X = res >> 8;
  7204. res = MASK_OUT_ABOVE_16(res);
  7205. m68ki_write_16(ea, res);
  7206. FLAG_N = NFLAG_16(res);
  7207. FLAG_Z = res;
  7208. FLAG_V = VFLAG_CLEAR;
  7209. }
  7210. M68KMAKE_OP(roxl, 8, s, .)
  7211. {
  7212. uint* r_dst = &DY;
  7213. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  7214. uint src = MASK_OUT_ABOVE_8(*r_dst);
  7215. uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
  7216. if(shift != 0)
  7217. USE_CYCLES(shift<<CYC_SHIFT);
  7218. FLAG_C = FLAG_X = res;
  7219. res = MASK_OUT_ABOVE_8(res);
  7220. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  7221. FLAG_N = NFLAG_8(res);
  7222. FLAG_Z = res;
  7223. FLAG_V = VFLAG_CLEAR;
  7224. }
  7225. M68KMAKE_OP(roxl, 16, s, .)
  7226. {
  7227. uint* r_dst = &DY;
  7228. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  7229. uint src = MASK_OUT_ABOVE_16(*r_dst);
  7230. uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
  7231. if(shift != 0)
  7232. USE_CYCLES(shift<<CYC_SHIFT);
  7233. FLAG_C = FLAG_X = res >> 8;
  7234. res = MASK_OUT_ABOVE_16(res);
  7235. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  7236. FLAG_N = NFLAG_16(res);
  7237. FLAG_Z = res;
  7238. FLAG_V = VFLAG_CLEAR;
  7239. }
  7240. M68KMAKE_OP(roxl, 32, s, .)
  7241. {
  7242. #if M68K_USE_64_BIT
  7243. uint* r_dst = &DY;
  7244. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  7245. uint64 src = *r_dst;
  7246. uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
  7247. if(shift != 0)
  7248. USE_CYCLES(shift<<CYC_SHIFT);
  7249. res = ROL_33_64(res, shift);
  7250. FLAG_C = FLAG_X = res >> 24;
  7251. res = MASK_OUT_ABOVE_32(res);
  7252. *r_dst = res;
  7253. FLAG_N = NFLAG_32(res);
  7254. FLAG_Z = res;
  7255. FLAG_V = VFLAG_CLEAR;
  7256. #else
  7257. uint* r_dst = &DY;
  7258. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  7259. uint src = *r_dst;
  7260. uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
  7261. uint new_x_flag = src & (1 << (32 - shift));
  7262. if(shift != 0)
  7263. USE_CYCLES(shift<<CYC_SHIFT);
  7264. *r_dst = res;
  7265. FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
  7266. FLAG_N = NFLAG_32(res);
  7267. FLAG_Z = res;
  7268. FLAG_V = VFLAG_CLEAR;
  7269. #endif
  7270. }
  7271. M68KMAKE_OP(roxl, 8, r, .)
  7272. {
  7273. uint* r_dst = &DY;
  7274. uint orig_shift = DX & 0x3f;
  7275. if(orig_shift != 0)
  7276. {
  7277. uint shift = orig_shift % 9;
  7278. uint src = MASK_OUT_ABOVE_8(*r_dst);
  7279. uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
  7280. USE_CYCLES(orig_shift<<CYC_SHIFT);
  7281. FLAG_C = FLAG_X = res;
  7282. res = MASK_OUT_ABOVE_8(res);
  7283. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  7284. FLAG_N = NFLAG_8(res);
  7285. FLAG_Z = res;
  7286. FLAG_V = VFLAG_CLEAR;
  7287. return;
  7288. }
  7289. FLAG_C = FLAG_X;
  7290. FLAG_N = NFLAG_8(*r_dst);
  7291. FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
  7292. FLAG_V = VFLAG_CLEAR;
  7293. }
  7294. M68KMAKE_OP(roxl, 16, r, .)
  7295. {
  7296. uint* r_dst = &DY;
  7297. uint orig_shift = DX & 0x3f;
  7298. if(orig_shift != 0)
  7299. {
  7300. uint shift = orig_shift % 17;
  7301. uint src = MASK_OUT_ABOVE_16(*r_dst);
  7302. uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
  7303. USE_CYCLES(orig_shift<<CYC_SHIFT);
  7304. FLAG_C = FLAG_X = res >> 8;
  7305. res = MASK_OUT_ABOVE_16(res);
  7306. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  7307. FLAG_N = NFLAG_16(res);
  7308. FLAG_Z = res;
  7309. FLAG_V = VFLAG_CLEAR;
  7310. return;
  7311. }
  7312. FLAG_C = FLAG_X;
  7313. FLAG_N = NFLAG_16(*r_dst);
  7314. FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
  7315. FLAG_V = VFLAG_CLEAR;
  7316. }
  7317. M68KMAKE_OP(roxl, 32, r, .)
  7318. {
  7319. #if M68K_USE_64_BIT
  7320. uint* r_dst = &DY;
  7321. uint orig_shift = DX & 0x3f;
  7322. if(orig_shift != 0)
  7323. {
  7324. uint shift = orig_shift % 33;
  7325. uint64 src = *r_dst;
  7326. uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
  7327. res = ROL_33_64(res, shift);
  7328. USE_CYCLES(orig_shift<<CYC_SHIFT);
  7329. FLAG_C = FLAG_X = res >> 24;
  7330. res = MASK_OUT_ABOVE_32(res);
  7331. *r_dst = res;
  7332. FLAG_N = NFLAG_32(res);
  7333. FLAG_Z = res;
  7334. FLAG_V = VFLAG_CLEAR;
  7335. return;
  7336. }
  7337. FLAG_C = FLAG_X;
  7338. FLAG_N = NFLAG_32(*r_dst);
  7339. FLAG_Z = *r_dst;
  7340. FLAG_V = VFLAG_CLEAR;
  7341. #else
  7342. uint* r_dst = &DY;
  7343. uint orig_shift = DX & 0x3f;
  7344. uint shift = orig_shift % 33;
  7345. uint src = *r_dst;
  7346. uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
  7347. uint new_x_flag = src & (1 << (32 - shift));
  7348. if(orig_shift != 0)
  7349. USE_CYCLES(orig_shift<<CYC_SHIFT);
  7350. if(shift != 0)
  7351. {
  7352. *r_dst = res;
  7353. FLAG_X = (new_x_flag != 0)<<8;
  7354. }
  7355. else
  7356. res = src;
  7357. FLAG_C = FLAG_X;
  7358. FLAG_N = NFLAG_32(res);
  7359. FLAG_Z = res;
  7360. FLAG_V = VFLAG_CLEAR;
  7361. #endif
  7362. }
  7363. M68KMAKE_OP(roxl, 16, ., .)
  7364. {
  7365. uint ea = M68KMAKE_GET_EA_AY_16;
  7366. uint src = m68ki_read_16(ea);
  7367. uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
  7368. FLAG_C = FLAG_X = res >> 8;
  7369. res = MASK_OUT_ABOVE_16(res);
  7370. m68ki_write_16(ea, res);
  7371. FLAG_N = NFLAG_16(res);
  7372. FLAG_Z = res;
  7373. FLAG_V = VFLAG_CLEAR;
  7374. }
  7375. M68KMAKE_OP(rtd, 32, ., .)
  7376. {
  7377. if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
  7378. {
  7379. uint new_pc = m68ki_pull_32();
  7380. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  7381. REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
  7382. m68ki_jump(new_pc);
  7383. return;
  7384. }
  7385. m68ki_exception_illegal();
  7386. }
  7387. M68KMAKE_OP(rte, 32, ., .)
  7388. {
  7389. if(FLAG_S)
  7390. {
  7391. uint new_sr;
  7392. uint new_pc;
  7393. uint format_word;
  7394. m68ki_rte_callback(); /* auto-disable (see m68kcpu.h) */
  7395. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  7396. if(CPU_TYPE_IS_000(CPU_TYPE))
  7397. {
  7398. new_sr = m68ki_pull_16();
  7399. new_pc = m68ki_pull_32();
  7400. m68ki_jump(new_pc);
  7401. m68ki_set_sr(new_sr);
  7402. CPU_INSTR_MODE = INSTRUCTION_YES;
  7403. CPU_RUN_MODE = RUN_MODE_NORMAL;
  7404. return;
  7405. }
  7406. if(CPU_TYPE_IS_010(CPU_TYPE))
  7407. {
  7408. format_word = m68ki_read_16(REG_A[7]+6) >> 12;
  7409. if(format_word == 0)
  7410. {
  7411. new_sr = m68ki_pull_16();
  7412. new_pc = m68ki_pull_32();
  7413. m68ki_fake_pull_16(); /* format word */
  7414. m68ki_jump(new_pc);
  7415. m68ki_set_sr(new_sr);
  7416. CPU_INSTR_MODE = INSTRUCTION_YES;
  7417. CPU_RUN_MODE = RUN_MODE_NORMAL;
  7418. return;
  7419. }
  7420. CPU_INSTR_MODE = INSTRUCTION_YES;
  7421. CPU_RUN_MODE = RUN_MODE_NORMAL;
  7422. /* Not handling bus fault (9) */
  7423. m68ki_exception_format_error();
  7424. return;
  7425. }
  7426. /* Otherwise it's 020 */
  7427. rte_loop:
  7428. format_word = m68ki_read_16(REG_A[7]+6) >> 12;
  7429. switch(format_word)
  7430. {
  7431. case 0: /* Normal */
  7432. new_sr = m68ki_pull_16();
  7433. new_pc = m68ki_pull_32();
  7434. m68ki_fake_pull_16(); /* format word */
  7435. m68ki_jump(new_pc);
  7436. m68ki_set_sr(new_sr);
  7437. CPU_INSTR_MODE = INSTRUCTION_YES;
  7438. CPU_RUN_MODE = RUN_MODE_NORMAL;
  7439. return;
  7440. case 1: /* Throwaway */
  7441. new_sr = m68ki_pull_16();
  7442. m68ki_fake_pull_32(); /* program counter */
  7443. m68ki_fake_pull_16(); /* format word */
  7444. m68ki_set_sr_noint(new_sr);
  7445. goto rte_loop;
  7446. case 2: /* Trap */
  7447. new_sr = m68ki_pull_16();
  7448. new_pc = m68ki_pull_32();
  7449. m68ki_fake_pull_16(); /* format word */
  7450. m68ki_fake_pull_32(); /* address */
  7451. m68ki_jump(new_pc);
  7452. m68ki_set_sr(new_sr);
  7453. CPU_INSTR_MODE = INSTRUCTION_YES;
  7454. CPU_RUN_MODE = RUN_MODE_NORMAL;
  7455. return;
  7456. }
  7457. /* Not handling long or short bus fault */
  7458. CPU_INSTR_MODE = INSTRUCTION_YES;
  7459. CPU_RUN_MODE = RUN_MODE_NORMAL;
  7460. m68ki_exception_format_error();
  7461. return;
  7462. }
  7463. m68ki_exception_privilege_violation();
  7464. }
  7465. M68KMAKE_OP(rtm, 32, ., .)
  7466. {
  7467. if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
  7468. {
  7469. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  7470. M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
  7471. m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
  7472. m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
  7473. return;
  7474. }
  7475. m68ki_exception_illegal();
  7476. }
  7477. M68KMAKE_OP(rtr, 32, ., .)
  7478. {
  7479. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  7480. m68ki_set_ccr(m68ki_pull_16());
  7481. m68ki_jump(m68ki_pull_32());
  7482. }
  7483. M68KMAKE_OP(rts, 32, ., .)
  7484. {
  7485. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  7486. m68ki_jump(m68ki_pull_32());
  7487. }
  7488. M68KMAKE_OP(sbcd, 8, rr, .)
  7489. {
  7490. uint* r_dst = &DX;
  7491. uint src = DY;
  7492. uint dst = *r_dst;
  7493. uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
  7494. uint corf = 0;
  7495. if(res > 0xf)
  7496. corf = 6;
  7497. res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
  7498. FLAG_V = res; /* Undefined V behavior */
  7499. if(res > 0xff)
  7500. {
  7501. res += 0xa0;
  7502. FLAG_X = FLAG_C = CFLAG_SET;
  7503. }
  7504. else if(res < corf)
  7505. FLAG_X = FLAG_C = CFLAG_SET;
  7506. else
  7507. FLAG_X = FLAG_C = 0;
  7508. res = MASK_OUT_ABOVE_8(res - corf);
  7509. FLAG_V &= ~res; /* Undefined V behavior part II */
  7510. FLAG_N = NFLAG_8(res); /* Undefined N behavior */
  7511. FLAG_Z |= res;
  7512. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  7513. }
  7514. M68KMAKE_OP(sbcd, 8, mm, ax7)
  7515. {
  7516. uint src = OPER_AY_PD_8();
  7517. uint ea = EA_A7_PD_8();
  7518. uint dst = m68ki_read_8(ea);
  7519. uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
  7520. uint corf = 0;
  7521. if(res > 0xf)
  7522. corf = 6;
  7523. res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
  7524. FLAG_V = res; /* Undefined V behavior */
  7525. if(res > 0xff)
  7526. {
  7527. res += 0xa0;
  7528. FLAG_X = FLAG_C = CFLAG_SET;
  7529. }
  7530. else if(res < corf)
  7531. FLAG_X = FLAG_C = CFLAG_SET;
  7532. else
  7533. FLAG_X = FLAG_C = 0;
  7534. res = MASK_OUT_ABOVE_8(res - corf);
  7535. FLAG_V &= ~res; /* Undefined V behavior part II */
  7536. FLAG_N = NFLAG_8(res); /* Undefined N behavior */
  7537. FLAG_Z |= res;
  7538. m68ki_write_8(ea, res);
  7539. }
  7540. M68KMAKE_OP(sbcd, 8, mm, ay7)
  7541. {
  7542. uint src = OPER_A7_PD_8();
  7543. uint ea = EA_AX_PD_8();
  7544. uint dst = m68ki_read_8(ea);
  7545. uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
  7546. uint corf = 0;
  7547. if(res > 0xf)
  7548. corf = 6;
  7549. res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
  7550. FLAG_V = res; /* Undefined V behavior */
  7551. if(res > 0xff)
  7552. {
  7553. res += 0xa0;
  7554. FLAG_X = FLAG_C = CFLAG_SET;
  7555. }
  7556. else if(res < corf)
  7557. FLAG_X = FLAG_C = CFLAG_SET;
  7558. else
  7559. FLAG_X = FLAG_C = 0;
  7560. res = MASK_OUT_ABOVE_8(res - corf);
  7561. FLAG_V &= ~res; /* Undefined V behavior part II */
  7562. FLAG_N = NFLAG_8(res); /* Undefined N behavior */
  7563. FLAG_Z |= res;
  7564. m68ki_write_8(ea, res);
  7565. }
  7566. M68KMAKE_OP(sbcd, 8, mm, axy7)
  7567. {
  7568. uint src = OPER_A7_PD_8();
  7569. uint ea = EA_A7_PD_8();
  7570. uint dst = m68ki_read_8(ea);
  7571. uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
  7572. uint corf = 0;
  7573. if(res > 0xf)
  7574. corf = 6;
  7575. res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
  7576. FLAG_V = res; /* Undefined V behavior */
  7577. if(res > 0xff)
  7578. {
  7579. res += 0xa0;
  7580. FLAG_X = FLAG_C = CFLAG_SET;
  7581. }
  7582. else if(res < corf)
  7583. FLAG_X = FLAG_C = CFLAG_SET;
  7584. else
  7585. FLAG_X = FLAG_C = 0;
  7586. res = MASK_OUT_ABOVE_8(res - corf);
  7587. FLAG_V &= ~res; /* Undefined V behavior part II */
  7588. FLAG_N = NFLAG_8(res); /* Undefined N behavior */
  7589. FLAG_Z |= res;
  7590. m68ki_write_8(ea, res);
  7591. }
  7592. M68KMAKE_OP(sbcd, 8, mm, .)
  7593. {
  7594. uint src = OPER_AY_PD_8();
  7595. uint ea = EA_AX_PD_8();
  7596. uint dst = m68ki_read_8(ea);
  7597. uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
  7598. uint corf = 0;
  7599. if(res > 0xf)
  7600. corf = 6;
  7601. res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
  7602. FLAG_V = res; /* Undefined V behavior */
  7603. if(res > 0xff)
  7604. {
  7605. res += 0xa0;
  7606. FLAG_X = FLAG_C = CFLAG_SET;
  7607. }
  7608. else if(res < corf)
  7609. FLAG_X = FLAG_C = CFLAG_SET;
  7610. else
  7611. FLAG_X = FLAG_C = 0;
  7612. res = MASK_OUT_ABOVE_8(res - corf);
  7613. FLAG_V &= ~res; /* Undefined V behavior part II */
  7614. FLAG_N = NFLAG_8(res); /* Undefined N behavior */
  7615. FLAG_Z |= res;
  7616. m68ki_write_8(ea, res);
  7617. }
  7618. M68KMAKE_OP(st, 8, ., d)
  7619. {
  7620. DY |= 0xff;
  7621. }
  7622. M68KMAKE_OP(st, 8, ., .)
  7623. {
  7624. m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0xff);
  7625. }
  7626. M68KMAKE_OP(sf, 8, ., d)
  7627. {
  7628. DY &= 0xffffff00;
  7629. }
  7630. M68KMAKE_OP(sf, 8, ., .)
  7631. {
  7632. m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
  7633. }
  7634. M68KMAKE_OP(scc, 8, ., d)
  7635. {
  7636. if(M68KMAKE_CC)
  7637. {
  7638. DY |= 0xff;
  7639. USE_CYCLES(CYC_SCC_R_TRUE);
  7640. return;
  7641. }
  7642. DY &= 0xffffff00;
  7643. }
  7644. M68KMAKE_OP(scc, 8, ., .)
  7645. {
  7646. m68ki_write_8(M68KMAKE_GET_EA_AY_8, M68KMAKE_CC ? 0xff : 0);
  7647. }
  7648. M68KMAKE_OP(stop, 0, ., .)
  7649. {
  7650. if(FLAG_S)
  7651. {
  7652. uint new_sr = OPER_I_16();
  7653. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  7654. CPU_STOPPED |= STOP_LEVEL_STOP;
  7655. m68ki_set_sr(new_sr);
  7656. m68ki_remaining_cycles = 0;
  7657. return;
  7658. }
  7659. m68ki_exception_privilege_violation();
  7660. }
  7661. M68KMAKE_OP(sub, 8, er, d)
  7662. {
  7663. uint* r_dst = &DX;
  7664. uint src = MASK_OUT_ABOVE_8(DY);
  7665. uint dst = MASK_OUT_ABOVE_8(*r_dst);
  7666. uint res = dst - src;
  7667. FLAG_N = NFLAG_8(res);
  7668. FLAG_X = FLAG_C = CFLAG_8(res);
  7669. FLAG_V = VFLAG_SUB_8(src, dst, res);
  7670. FLAG_Z = MASK_OUT_ABOVE_8(res);
  7671. *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
  7672. }
  7673. M68KMAKE_OP(sub, 8, er, .)
  7674. {
  7675. uint* r_dst = &DX;
  7676. uint src = M68KMAKE_GET_OPER_AY_8;
  7677. uint dst = MASK_OUT_ABOVE_8(*r_dst);
  7678. uint res = dst - src;
  7679. FLAG_N = NFLAG_8(res);
  7680. FLAG_X = FLAG_C = CFLAG_8(res);
  7681. FLAG_V = VFLAG_SUB_8(src, dst, res);
  7682. FLAG_Z = MASK_OUT_ABOVE_8(res);
  7683. *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
  7684. }
  7685. M68KMAKE_OP(sub, 16, er, d)
  7686. {
  7687. uint* r_dst = &DX;
  7688. uint src = MASK_OUT_ABOVE_16(DY);
  7689. uint dst = MASK_OUT_ABOVE_16(*r_dst);
  7690. uint res = dst - src;
  7691. FLAG_N = NFLAG_16(res);
  7692. FLAG_X = FLAG_C = CFLAG_16(res);
  7693. FLAG_V = VFLAG_SUB_16(src, dst, res);
  7694. FLAG_Z = MASK_OUT_ABOVE_16(res);
  7695. *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
  7696. }
  7697. M68KMAKE_OP(sub, 16, er, a)
  7698. {
  7699. uint* r_dst = &DX;
  7700. uint src = MASK_OUT_ABOVE_16(AY);
  7701. uint dst = MASK_OUT_ABOVE_16(*r_dst);
  7702. uint res = dst - src;
  7703. FLAG_N = NFLAG_16(res);
  7704. FLAG_X = FLAG_C = CFLAG_16(res);
  7705. FLAG_V = VFLAG_SUB_16(src, dst, res);
  7706. FLAG_Z = MASK_OUT_ABOVE_16(res);
  7707. *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
  7708. }
  7709. M68KMAKE_OP(sub, 16, er, .)
  7710. {
  7711. uint* r_dst = &DX;
  7712. uint src = M68KMAKE_GET_OPER_AY_16;
  7713. uint dst = MASK_OUT_ABOVE_16(*r_dst);
  7714. uint res = dst - src;
  7715. FLAG_N = NFLAG_16(res);
  7716. FLAG_X = FLAG_C = CFLAG_16(res);
  7717. FLAG_V = VFLAG_SUB_16(src, dst, res);
  7718. FLAG_Z = MASK_OUT_ABOVE_16(res);
  7719. *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
  7720. }
  7721. M68KMAKE_OP(sub, 32, er, d)
  7722. {
  7723. uint* r_dst = &DX;
  7724. uint src = DY;
  7725. uint dst = *r_dst;
  7726. uint res = dst - src;
  7727. FLAG_N = NFLAG_32(res);
  7728. FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
  7729. FLAG_V = VFLAG_SUB_32(src, dst, res);
  7730. FLAG_Z = MASK_OUT_ABOVE_32(res);
  7731. *r_dst = FLAG_Z;
  7732. }
  7733. M68KMAKE_OP(sub, 32, er, a)
  7734. {
  7735. uint* r_dst = &DX;
  7736. uint src = AY;
  7737. uint dst = *r_dst;
  7738. uint res = dst - src;
  7739. FLAG_N = NFLAG_32(res);
  7740. FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
  7741. FLAG_V = VFLAG_SUB_32(src, dst, res);
  7742. FLAG_Z = MASK_OUT_ABOVE_32(res);
  7743. *r_dst = FLAG_Z;
  7744. }
  7745. M68KMAKE_OP(sub, 32, er, .)
  7746. {
  7747. uint* r_dst = &DX;
  7748. uint src = M68KMAKE_GET_OPER_AY_32;
  7749. uint dst = *r_dst;
  7750. uint res = dst - src;
  7751. FLAG_N = NFLAG_32(res);
  7752. FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
  7753. FLAG_V = VFLAG_SUB_32(src, dst, res);
  7754. FLAG_Z = MASK_OUT_ABOVE_32(res);
  7755. *r_dst = FLAG_Z;
  7756. }
  7757. M68KMAKE_OP(sub, 8, re, .)
  7758. {
  7759. uint ea = M68KMAKE_GET_EA_AY_8;
  7760. uint src = MASK_OUT_ABOVE_8(DX);
  7761. uint dst = m68ki_read_8(ea);
  7762. uint res = dst - src;
  7763. FLAG_N = NFLAG_8(res);
  7764. FLAG_Z = MASK_OUT_ABOVE_8(res);
  7765. FLAG_X = FLAG_C = CFLAG_8(res);
  7766. FLAG_V = VFLAG_SUB_8(src, dst, res);
  7767. m68ki_write_8(ea, FLAG_Z);
  7768. }
  7769. M68KMAKE_OP(sub, 16, re, .)
  7770. {
  7771. uint ea = M68KMAKE_GET_EA_AY_16;
  7772. uint src = MASK_OUT_ABOVE_16(DX);
  7773. uint dst = m68ki_read_16(ea);
  7774. uint res = dst - src;
  7775. FLAG_N = NFLAG_16(res);
  7776. FLAG_Z = MASK_OUT_ABOVE_16(res);
  7777. FLAG_X = FLAG_C = CFLAG_16(res);
  7778. FLAG_V = VFLAG_SUB_16(src, dst, res);
  7779. m68ki_write_16(ea, FLAG_Z);
  7780. }
  7781. M68KMAKE_OP(sub, 32, re, .)
  7782. {
  7783. uint ea = M68KMAKE_GET_EA_AY_32;
  7784. uint src = DX;
  7785. uint dst = m68ki_read_32(ea);
  7786. uint res = dst - src;
  7787. FLAG_N = NFLAG_32(res);
  7788. FLAG_Z = MASK_OUT_ABOVE_32(res);
  7789. FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
  7790. FLAG_V = VFLAG_SUB_32(src, dst, res);
  7791. m68ki_write_32(ea, FLAG_Z);
  7792. }
  7793. M68KMAKE_OP(suba, 16, ., d)
  7794. {
  7795. uint* r_dst = &AX;
  7796. *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY));
  7797. }
  7798. M68KMAKE_OP(suba, 16, ., a)
  7799. {
  7800. uint* r_dst = &AX;
  7801. *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY));
  7802. }
  7803. M68KMAKE_OP(suba, 16, ., .)
  7804. {
  7805. uint* r_dst = &AX;
  7806. uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
  7807. *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
  7808. }
  7809. M68KMAKE_OP(suba, 32, ., d)
  7810. {
  7811. uint* r_dst = &AX;
  7812. *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY);
  7813. }
  7814. M68KMAKE_OP(suba, 32, ., a)
  7815. {
  7816. uint* r_dst = &AX;
  7817. *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY);
  7818. }
  7819. M68KMAKE_OP(suba, 32, ., .)
  7820. {
  7821. uint* r_dst = &AX;
  7822. uint src = M68KMAKE_GET_OPER_AY_32; // notaz
  7823. *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
  7824. }
  7825. M68KMAKE_OP(subi, 8, ., d)
  7826. {
  7827. uint* r_dst = &DY;
  7828. uint src = OPER_I_8();
  7829. uint dst = MASK_OUT_ABOVE_8(*r_dst);
  7830. uint res = dst - src;
  7831. FLAG_N = NFLAG_8(res);
  7832. FLAG_Z = MASK_OUT_ABOVE_8(res);
  7833. FLAG_X = FLAG_C = CFLAG_8(res);
  7834. FLAG_V = VFLAG_SUB_8(src, dst, res);
  7835. *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
  7836. }
  7837. M68KMAKE_OP(subi, 8, ., .)
  7838. {
  7839. uint src = OPER_I_8();
  7840. uint ea = M68KMAKE_GET_EA_AY_8;
  7841. uint dst = m68ki_read_8(ea);
  7842. uint res = dst - src;
  7843. FLAG_N = NFLAG_8(res);
  7844. FLAG_Z = MASK_OUT_ABOVE_8(res);
  7845. FLAG_X = FLAG_C = CFLAG_8(res);
  7846. FLAG_V = VFLAG_SUB_8(src, dst, res);
  7847. m68ki_write_8(ea, FLAG_Z);
  7848. }
  7849. M68KMAKE_OP(subi, 16, ., d)
  7850. {
  7851. uint* r_dst = &DY;
  7852. uint src = OPER_I_16();
  7853. uint dst = MASK_OUT_ABOVE_16(*r_dst);
  7854. uint res = dst - src;
  7855. FLAG_N = NFLAG_16(res);
  7856. FLAG_Z = MASK_OUT_ABOVE_16(res);
  7857. FLAG_X = FLAG_C = CFLAG_16(res);
  7858. FLAG_V = VFLAG_SUB_16(src, dst, res);
  7859. *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
  7860. }
  7861. M68KMAKE_OP(subi, 16, ., .)
  7862. {
  7863. uint src = OPER_I_16();
  7864. uint ea = M68KMAKE_GET_EA_AY_16;
  7865. uint dst = m68ki_read_16(ea);
  7866. uint res = dst - src;
  7867. FLAG_N = NFLAG_16(res);
  7868. FLAG_Z = MASK_OUT_ABOVE_16(res);
  7869. FLAG_X = FLAG_C = CFLAG_16(res);
  7870. FLAG_V = VFLAG_SUB_16(src, dst, res);
  7871. m68ki_write_16(ea, FLAG_Z);
  7872. }
  7873. M68KMAKE_OP(subi, 32, ., d)
  7874. {
  7875. uint* r_dst = &DY;
  7876. uint src = OPER_I_32();
  7877. uint dst = *r_dst;
  7878. uint res = dst - src;
  7879. FLAG_N = NFLAG_32(res);
  7880. FLAG_Z = MASK_OUT_ABOVE_32(res);
  7881. FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
  7882. FLAG_V = VFLAG_SUB_32(src, dst, res);
  7883. *r_dst = FLAG_Z;
  7884. }
  7885. M68KMAKE_OP(subi, 32, ., .)
  7886. {
  7887. uint src = OPER_I_32();
  7888. uint ea = M68KMAKE_GET_EA_AY_32;
  7889. uint dst = m68ki_read_32(ea);
  7890. uint res = dst - src;
  7891. FLAG_N = NFLAG_32(res);
  7892. FLAG_Z = MASK_OUT_ABOVE_32(res);
  7893. FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
  7894. FLAG_V = VFLAG_SUB_32(src, dst, res);
  7895. m68ki_write_32(ea, FLAG_Z);
  7896. }
  7897. M68KMAKE_OP(subq, 8, ., d)
  7898. {
  7899. uint* r_dst = &DY;
  7900. uint src = (((REG_IR >> 9) - 1) & 7) + 1;
  7901. uint dst = MASK_OUT_ABOVE_8(*r_dst);
  7902. uint res = dst - src;
  7903. FLAG_N = NFLAG_8(res);
  7904. FLAG_Z = MASK_OUT_ABOVE_8(res);
  7905. FLAG_X = FLAG_C = CFLAG_8(res);
  7906. FLAG_V = VFLAG_SUB_8(src, dst, res);
  7907. *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
  7908. }
  7909. M68KMAKE_OP(subq, 8, ., .)
  7910. {
  7911. uint src = (((REG_IR >> 9) - 1) & 7) + 1;
  7912. uint ea = M68KMAKE_GET_EA_AY_8;
  7913. uint dst = m68ki_read_8(ea);
  7914. uint res = dst - src;
  7915. FLAG_N = NFLAG_8(res);
  7916. FLAG_Z = MASK_OUT_ABOVE_8(res);
  7917. FLAG_X = FLAG_C = CFLAG_8(res);
  7918. FLAG_V = VFLAG_SUB_8(src, dst, res);
  7919. m68ki_write_8(ea, FLAG_Z);
  7920. }
  7921. M68KMAKE_OP(subq, 16, ., d)
  7922. {
  7923. uint* r_dst = &DY;
  7924. uint src = (((REG_IR >> 9) - 1) & 7) + 1;
  7925. uint dst = MASK_OUT_ABOVE_16(*r_dst);
  7926. uint res = dst - src;
  7927. FLAG_N = NFLAG_16(res);
  7928. FLAG_Z = MASK_OUT_ABOVE_16(res);
  7929. FLAG_X = FLAG_C = CFLAG_16(res);
  7930. FLAG_V = VFLAG_SUB_16(src, dst, res);
  7931. *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
  7932. }
  7933. M68KMAKE_OP(subq, 16, ., a)
  7934. {
  7935. uint* r_dst = &AY;
  7936. *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
  7937. }
  7938. M68KMAKE_OP(subq, 16, ., .)
  7939. {
  7940. uint src = (((REG_IR >> 9) - 1) & 7) + 1;
  7941. uint ea = M68KMAKE_GET_EA_AY_16;
  7942. uint dst = m68ki_read_16(ea);
  7943. uint res = dst - src;
  7944. FLAG_N = NFLAG_16(res);
  7945. FLAG_Z = MASK_OUT_ABOVE_16(res);
  7946. FLAG_X = FLAG_C = CFLAG_16(res);
  7947. FLAG_V = VFLAG_SUB_16(src, dst, res);
  7948. m68ki_write_16(ea, FLAG_Z);
  7949. }
  7950. M68KMAKE_OP(subq, 32, ., d)
  7951. {
  7952. uint* r_dst = &DY;
  7953. uint src = (((REG_IR >> 9) - 1) & 7) + 1;
  7954. uint dst = *r_dst;
  7955. uint res = dst - src;
  7956. FLAG_N = NFLAG_32(res);
  7957. FLAG_Z = MASK_OUT_ABOVE_32(res);
  7958. FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
  7959. FLAG_V = VFLAG_SUB_32(src, dst, res);
  7960. *r_dst = FLAG_Z;
  7961. }
  7962. M68KMAKE_OP(subq, 32, ., a)
  7963. {
  7964. uint* r_dst = &AY;
  7965. *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
  7966. }
  7967. M68KMAKE_OP(subq, 32, ., .)
  7968. {
  7969. uint src = (((REG_IR >> 9) - 1) & 7) + 1;
  7970. uint ea = M68KMAKE_GET_EA_AY_32;
  7971. uint dst = m68ki_read_32(ea);
  7972. uint res = dst - src;
  7973. FLAG_N = NFLAG_32(res);
  7974. FLAG_Z = MASK_OUT_ABOVE_32(res);
  7975. FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
  7976. FLAG_V = VFLAG_SUB_32(src, dst, res);
  7977. m68ki_write_32(ea, FLAG_Z);
  7978. }
  7979. M68KMAKE_OP(subx, 8, rr, .)
  7980. {
  7981. uint* r_dst = &DX;
  7982. uint src = MASK_OUT_ABOVE_8(DY);
  7983. uint dst = MASK_OUT_ABOVE_8(*r_dst);
  7984. uint res = dst - src - XFLAG_AS_1();
  7985. FLAG_N = NFLAG_8(res);
  7986. FLAG_X = FLAG_C = CFLAG_8(res);
  7987. FLAG_V = VFLAG_SUB_8(src, dst, res);
  7988. res = MASK_OUT_ABOVE_8(res);
  7989. FLAG_Z |= res;
  7990. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  7991. }
  7992. M68KMAKE_OP(subx, 16, rr, .)
  7993. {
  7994. uint* r_dst = &DX;
  7995. uint src = MASK_OUT_ABOVE_16(DY);
  7996. uint dst = MASK_OUT_ABOVE_16(*r_dst);
  7997. uint res = dst - src - XFLAG_AS_1();
  7998. FLAG_N = NFLAG_16(res);
  7999. FLAG_X = FLAG_C = CFLAG_16(res);
  8000. FLAG_V = VFLAG_SUB_16(src, dst, res);
  8001. res = MASK_OUT_ABOVE_16(res);
  8002. FLAG_Z |= res;
  8003. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  8004. }
  8005. M68KMAKE_OP(subx, 32, rr, .)
  8006. {
  8007. uint* r_dst = &DX;
  8008. uint src = DY;
  8009. uint dst = *r_dst;
  8010. uint res = dst - src - XFLAG_AS_1();
  8011. FLAG_N = NFLAG_32(res);
  8012. FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
  8013. FLAG_V = VFLAG_SUB_32(src, dst, res);
  8014. res = MASK_OUT_ABOVE_32(res);
  8015. FLAG_Z |= res;
  8016. *r_dst = res;
  8017. }
  8018. M68KMAKE_OP(subx, 8, mm, ax7)
  8019. {
  8020. uint src = OPER_AY_PD_8();
  8021. uint ea = EA_A7_PD_8();
  8022. uint dst = m68ki_read_8(ea);
  8023. uint res = dst - src - XFLAG_AS_1();
  8024. FLAG_N = NFLAG_8(res);
  8025. FLAG_X = FLAG_C = CFLAG_8(res);
  8026. FLAG_V = VFLAG_SUB_8(src, dst, res);
  8027. res = MASK_OUT_ABOVE_8(res);
  8028. FLAG_Z |= res;
  8029. m68ki_write_8(ea, res);
  8030. }
  8031. M68KMAKE_OP(subx, 8, mm, ay7)
  8032. {
  8033. uint src = OPER_A7_PD_8();
  8034. uint ea = EA_AX_PD_8();
  8035. uint dst = m68ki_read_8(ea);
  8036. uint res = dst - src - XFLAG_AS_1();
  8037. FLAG_N = NFLAG_8(res);
  8038. FLAG_X = FLAG_C = CFLAG_8(res);
  8039. FLAG_V = VFLAG_SUB_8(src, dst, res);
  8040. res = MASK_OUT_ABOVE_8(res);
  8041. FLAG_Z |= res;
  8042. m68ki_write_8(ea, res);
  8043. }
  8044. M68KMAKE_OP(subx, 8, mm, axy7)
  8045. {
  8046. uint src = OPER_A7_PD_8();
  8047. uint ea = EA_A7_PD_8();
  8048. uint dst = m68ki_read_8(ea);
  8049. uint res = dst - src - XFLAG_AS_1();
  8050. FLAG_N = NFLAG_8(res);
  8051. FLAG_X = FLAG_C = CFLAG_8(res);
  8052. FLAG_V = VFLAG_SUB_8(src, dst, res);
  8053. res = MASK_OUT_ABOVE_8(res);
  8054. FLAG_Z |= res;
  8055. m68ki_write_8(ea, res);
  8056. }
  8057. M68KMAKE_OP(subx, 8, mm, .)
  8058. {
  8059. uint src = OPER_AY_PD_8();
  8060. uint ea = EA_AX_PD_8();
  8061. uint dst = m68ki_read_8(ea);
  8062. uint res = dst - src - XFLAG_AS_1();
  8063. FLAG_N = NFLAG_8(res);
  8064. FLAG_X = FLAG_C = CFLAG_8(res);
  8065. FLAG_V = VFLAG_SUB_8(src, dst, res);
  8066. res = MASK_OUT_ABOVE_8(res);
  8067. FLAG_Z |= res;
  8068. m68ki_write_8(ea, res);
  8069. }
  8070. M68KMAKE_OP(subx, 16, mm, .)
  8071. {
  8072. uint src = OPER_AY_PD_16();
  8073. uint ea = EA_AX_PD_16();
  8074. uint dst = m68ki_read_16(ea);
  8075. uint res = dst - src - XFLAG_AS_1();
  8076. FLAG_N = NFLAG_16(res);
  8077. FLAG_X = FLAG_C = CFLAG_16(res);
  8078. FLAG_V = VFLAG_SUB_16(src, dst, res);
  8079. res = MASK_OUT_ABOVE_16(res);
  8080. FLAG_Z |= res;
  8081. m68ki_write_16(ea, res);
  8082. }
  8083. M68KMAKE_OP(subx, 32, mm, .)
  8084. {
  8085. uint src = OPER_AY_PD_32();
  8086. uint ea = EA_AX_PD_32();
  8087. uint dst = m68ki_read_32(ea);
  8088. uint res = dst - src - XFLAG_AS_1();
  8089. FLAG_N = NFLAG_32(res);
  8090. FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
  8091. FLAG_V = VFLAG_SUB_32(src, dst, res);
  8092. res = MASK_OUT_ABOVE_32(res);
  8093. FLAG_Z |= res;
  8094. m68ki_write_32(ea, res);
  8095. }
  8096. M68KMAKE_OP(swap, 32, ., .)
  8097. {
  8098. uint* r_dst = &DY;
  8099. FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16);
  8100. *r_dst = (*r_dst>>16) | FLAG_Z;
  8101. FLAG_Z = *r_dst;
  8102. FLAG_N = NFLAG_32(*r_dst);
  8103. FLAG_C = CFLAG_CLEAR;
  8104. FLAG_V = VFLAG_CLEAR;
  8105. }
  8106. M68KMAKE_OP(tas, 8, ., d)
  8107. {
  8108. uint* r_dst = &DY;
  8109. FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
  8110. FLAG_N = NFLAG_8(*r_dst);
  8111. FLAG_V = VFLAG_CLEAR;
  8112. FLAG_C = CFLAG_CLEAR;
  8113. *r_dst |= 0x80;
  8114. }
  8115. M68KMAKE_OP(tas, 8, ., .)
  8116. {
  8117. uint ea = M68KMAKE_GET_EA_AY_8;
  8118. uint dst = m68ki_read_8(ea);
  8119. uint allow_writeback;
  8120. FLAG_Z = dst;
  8121. FLAG_N = NFLAG_8(dst);
  8122. FLAG_V = VFLAG_CLEAR;
  8123. FLAG_C = CFLAG_CLEAR;
  8124. /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
  8125. disabled in order to function properly. Some Amiga software may also rely
  8126. on this, but only when accessing specific addresses so additional functionality
  8127. will be needed. */
  8128. allow_writeback = m68ki_tas_callback();
  8129. if (allow_writeback==1) m68ki_write_8(ea, dst | 0x80);
  8130. }
  8131. M68KMAKE_OP(trap, 0, ., .)
  8132. {
  8133. /* Trap#n stacks exception frame type 0 */
  8134. m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf)); /* HJB 990403 */
  8135. }
  8136. M68KMAKE_OP(trapt, 0, ., .)
  8137. {
  8138. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8139. {
  8140. m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
  8141. return;
  8142. }
  8143. m68ki_exception_illegal();
  8144. }
  8145. M68KMAKE_OP(trapt, 16, ., .)
  8146. {
  8147. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8148. {
  8149. m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
  8150. return;
  8151. }
  8152. m68ki_exception_illegal();
  8153. }
  8154. M68KMAKE_OP(trapt, 32, ., .)
  8155. {
  8156. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8157. {
  8158. m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
  8159. return;
  8160. }
  8161. m68ki_exception_illegal();
  8162. }
  8163. M68KMAKE_OP(trapf, 0, ., .)
  8164. {
  8165. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8166. {
  8167. return;
  8168. }
  8169. m68ki_exception_illegal();
  8170. }
  8171. M68KMAKE_OP(trapf, 16, ., .)
  8172. {
  8173. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8174. {
  8175. REG_PC += 2;
  8176. return;
  8177. }
  8178. m68ki_exception_illegal();
  8179. }
  8180. M68KMAKE_OP(trapf, 32, ., .)
  8181. {
  8182. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8183. {
  8184. REG_PC += 4;
  8185. return;
  8186. }
  8187. m68ki_exception_illegal();
  8188. }
  8189. M68KMAKE_OP(trapcc, 0, ., .)
  8190. {
  8191. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8192. {
  8193. if(M68KMAKE_CC)
  8194. m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
  8195. return;
  8196. }
  8197. m68ki_exception_illegal();
  8198. }
  8199. M68KMAKE_OP(trapcc, 16, ., .)
  8200. {
  8201. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8202. {
  8203. if(M68KMAKE_CC)
  8204. {
  8205. m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
  8206. return;
  8207. }
  8208. REG_PC += 2;
  8209. return;
  8210. }
  8211. m68ki_exception_illegal();
  8212. }
  8213. M68KMAKE_OP(trapcc, 32, ., .)
  8214. {
  8215. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8216. {
  8217. if(M68KMAKE_CC)
  8218. {
  8219. m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
  8220. return;
  8221. }
  8222. REG_PC += 4;
  8223. return;
  8224. }
  8225. m68ki_exception_illegal();
  8226. }
  8227. M68KMAKE_OP(trapv, 0, ., .)
  8228. {
  8229. if(COND_VC())
  8230. {
  8231. return;
  8232. }
  8233. m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
  8234. }
  8235. M68KMAKE_OP(tst, 8, ., d)
  8236. {
  8237. uint res = MASK_OUT_ABOVE_8(DY);
  8238. FLAG_N = NFLAG_8(res);
  8239. FLAG_Z = res;
  8240. FLAG_V = VFLAG_CLEAR;
  8241. FLAG_C = CFLAG_CLEAR;
  8242. }
  8243. M68KMAKE_OP(tst, 8, ., .)
  8244. {
  8245. uint res = M68KMAKE_GET_OPER_AY_8;
  8246. FLAG_N = NFLAG_8(res);
  8247. FLAG_Z = res;
  8248. FLAG_V = VFLAG_CLEAR;
  8249. FLAG_C = CFLAG_CLEAR;
  8250. }
  8251. M68KMAKE_OP(tst, 8, ., pcdi)
  8252. {
  8253. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8254. {
  8255. uint res = OPER_PCDI_8();
  8256. FLAG_N = NFLAG_8(res);
  8257. FLAG_Z = res;
  8258. FLAG_V = VFLAG_CLEAR;
  8259. FLAG_C = CFLAG_CLEAR;
  8260. return;
  8261. }
  8262. m68ki_exception_illegal();
  8263. }
  8264. M68KMAKE_OP(tst, 8, ., pcix)
  8265. {
  8266. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8267. {
  8268. uint res = OPER_PCIX_8();
  8269. FLAG_N = NFLAG_8(res);
  8270. FLAG_Z = res;
  8271. FLAG_V = VFLAG_CLEAR;
  8272. FLAG_C = CFLAG_CLEAR;
  8273. return;
  8274. }
  8275. m68ki_exception_illegal();
  8276. }
  8277. M68KMAKE_OP(tst, 8, ., i)
  8278. {
  8279. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8280. {
  8281. uint res = OPER_I_8();
  8282. FLAG_N = NFLAG_8(res);
  8283. FLAG_Z = res;
  8284. FLAG_V = VFLAG_CLEAR;
  8285. FLAG_C = CFLAG_CLEAR;
  8286. return;
  8287. }
  8288. m68ki_exception_illegal();
  8289. }
  8290. M68KMAKE_OP(tst, 16, ., d)
  8291. {
  8292. uint res = MASK_OUT_ABOVE_16(DY);
  8293. FLAG_N = NFLAG_16(res);
  8294. FLAG_Z = res;
  8295. FLAG_V = VFLAG_CLEAR;
  8296. FLAG_C = CFLAG_CLEAR;
  8297. }
  8298. M68KMAKE_OP(tst, 16, ., a)
  8299. {
  8300. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8301. {
  8302. uint res = MAKE_INT_16(AY);
  8303. FLAG_N = NFLAG_16(res);
  8304. FLAG_Z = res;
  8305. FLAG_V = VFLAG_CLEAR;
  8306. FLAG_C = CFLAG_CLEAR;
  8307. return;
  8308. }
  8309. m68ki_exception_illegal();
  8310. }
  8311. M68KMAKE_OP(tst, 16, ., .)
  8312. {
  8313. uint res = M68KMAKE_GET_OPER_AY_16;
  8314. FLAG_N = NFLAG_16(res);
  8315. FLAG_Z = res;
  8316. FLAG_V = VFLAG_CLEAR;
  8317. FLAG_C = CFLAG_CLEAR;
  8318. }
  8319. M68KMAKE_OP(tst, 16, ., pcdi)
  8320. {
  8321. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8322. {
  8323. uint res = OPER_PCDI_16();
  8324. FLAG_N = NFLAG_16(res);
  8325. FLAG_Z = res;
  8326. FLAG_V = VFLAG_CLEAR;
  8327. FLAG_C = CFLAG_CLEAR;
  8328. return;
  8329. }
  8330. m68ki_exception_illegal();
  8331. }
  8332. M68KMAKE_OP(tst, 16, ., pcix)
  8333. {
  8334. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8335. {
  8336. uint res = OPER_PCIX_16();
  8337. FLAG_N = NFLAG_16(res);
  8338. FLAG_Z = res;
  8339. FLAG_V = VFLAG_CLEAR;
  8340. FLAG_C = CFLAG_CLEAR;
  8341. return;
  8342. }
  8343. m68ki_exception_illegal();
  8344. }
  8345. M68KMAKE_OP(tst, 16, ., i)
  8346. {
  8347. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8348. {
  8349. uint res = OPER_I_16();
  8350. FLAG_N = NFLAG_16(res);
  8351. FLAG_Z = res;
  8352. FLAG_V = VFLAG_CLEAR;
  8353. FLAG_C = CFLAG_CLEAR;
  8354. return;
  8355. }
  8356. m68ki_exception_illegal();
  8357. }
  8358. M68KMAKE_OP(tst, 32, ., d)
  8359. {
  8360. uint res = DY;
  8361. FLAG_N = NFLAG_32(res);
  8362. FLAG_Z = res;
  8363. FLAG_V = VFLAG_CLEAR;
  8364. FLAG_C = CFLAG_CLEAR;
  8365. }
  8366. M68KMAKE_OP(tst, 32, ., a)
  8367. {
  8368. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8369. {
  8370. uint res = AY;
  8371. FLAG_N = NFLAG_32(res);
  8372. FLAG_Z = res;
  8373. FLAG_V = VFLAG_CLEAR;
  8374. FLAG_C = CFLAG_CLEAR;
  8375. return;
  8376. }
  8377. m68ki_exception_illegal();
  8378. }
  8379. M68KMAKE_OP(tst, 32, ., .)
  8380. {
  8381. uint res = M68KMAKE_GET_OPER_AY_32;
  8382. FLAG_N = NFLAG_32(res);
  8383. FLAG_Z = res;
  8384. FLAG_V = VFLAG_CLEAR;
  8385. FLAG_C = CFLAG_CLEAR;
  8386. }
  8387. M68KMAKE_OP(tst, 32, ., pcdi)
  8388. {
  8389. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8390. {
  8391. uint res = OPER_PCDI_32();
  8392. FLAG_N = NFLAG_32(res);
  8393. FLAG_Z = res;
  8394. FLAG_V = VFLAG_CLEAR;
  8395. FLAG_C = CFLAG_CLEAR;
  8396. return;
  8397. }
  8398. m68ki_exception_illegal();
  8399. }
  8400. M68KMAKE_OP(tst, 32, ., pcix)
  8401. {
  8402. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8403. {
  8404. uint res = OPER_PCIX_32();
  8405. FLAG_N = NFLAG_32(res);
  8406. FLAG_Z = res;
  8407. FLAG_V = VFLAG_CLEAR;
  8408. FLAG_C = CFLAG_CLEAR;
  8409. return;
  8410. }
  8411. m68ki_exception_illegal();
  8412. }
  8413. M68KMAKE_OP(tst, 32, ., i)
  8414. {
  8415. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8416. {
  8417. uint res = OPER_I_32();
  8418. FLAG_N = NFLAG_32(res);
  8419. FLAG_Z = res;
  8420. FLAG_V = VFLAG_CLEAR;
  8421. FLAG_C = CFLAG_CLEAR;
  8422. return;
  8423. }
  8424. m68ki_exception_illegal();
  8425. }
  8426. M68KMAKE_OP(unlk, 32, ., a7)
  8427. {
  8428. REG_A[7] = m68ki_read_32(REG_A[7]);
  8429. }
  8430. M68KMAKE_OP(unlk, 32, ., .)
  8431. {
  8432. uint* r_dst = &AY;
  8433. REG_A[7] = *r_dst;
  8434. *r_dst = m68ki_pull_32();
  8435. }
  8436. M68KMAKE_OP(unpk, 16, rr, .)
  8437. {
  8438. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8439. {
  8440. /* Note: DX and DY are reversed in Motorola's docs */
  8441. uint src = DY;
  8442. uint* r_dst = &DX;
  8443. *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff);
  8444. return;
  8445. }
  8446. m68ki_exception_illegal();
  8447. }
  8448. M68KMAKE_OP(unpk, 16, mm, ax7)
  8449. {
  8450. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8451. {
  8452. /* Note: AX and AY are reversed in Motorola's docs */
  8453. uint src = OPER_AY_PD_8();
  8454. uint ea_dst;
  8455. src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
  8456. ea_dst = EA_A7_PD_8();
  8457. m68ki_write_8(ea_dst, (src >> 8) & 0xff);
  8458. ea_dst = EA_A7_PD_8();
  8459. m68ki_write_8(ea_dst, src & 0xff);
  8460. return;
  8461. }
  8462. m68ki_exception_illegal();
  8463. }
  8464. M68KMAKE_OP(unpk, 16, mm, ay7)
  8465. {
  8466. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8467. {
  8468. /* Note: AX and AY are reversed in Motorola's docs */
  8469. uint src = OPER_A7_PD_8();
  8470. uint ea_dst;
  8471. src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
  8472. ea_dst = EA_AX_PD_8();
  8473. m68ki_write_8(ea_dst, (src >> 8) & 0xff);
  8474. ea_dst = EA_AX_PD_8();
  8475. m68ki_write_8(ea_dst, src & 0xff);
  8476. return;
  8477. }
  8478. m68ki_exception_illegal();
  8479. }
  8480. M68KMAKE_OP(unpk, 16, mm, axy7)
  8481. {
  8482. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8483. {
  8484. uint src = OPER_A7_PD_8();
  8485. uint ea_dst;
  8486. src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
  8487. ea_dst = EA_A7_PD_8();
  8488. m68ki_write_8(ea_dst, (src >> 8) & 0xff);
  8489. ea_dst = EA_A7_PD_8();
  8490. m68ki_write_8(ea_dst, src & 0xff);
  8491. return;
  8492. }
  8493. m68ki_exception_illegal();
  8494. }
  8495. M68KMAKE_OP(unpk, 16, mm, .)
  8496. {
  8497. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8498. {
  8499. /* Note: AX and AY are reversed in Motorola's docs */
  8500. uint src = OPER_AY_PD_8();
  8501. uint ea_dst;
  8502. src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
  8503. ea_dst = EA_AX_PD_8();
  8504. m68ki_write_8(ea_dst, (src >> 8) & 0xff);
  8505. ea_dst = EA_AX_PD_8();
  8506. m68ki_write_8(ea_dst, src & 0xff);
  8507. return;
  8508. }
  8509. m68ki_exception_illegal();
  8510. }
  8511. XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  8512. M68KMAKE_END