sh2.c 50 KB

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  1. /*****************************************************************************
  2. *
  3. * sh2.c
  4. * Portable Hitachi SH-2 (SH7600 family) emulator
  5. *
  6. * Copyright Juergen Buchmueller <pullmoll@t-online.de>,
  7. * all rights reserved.
  8. *
  9. * - This source code is released as freeware for non-commercial purposes.
  10. * - You are free to use and redistribute this code in modified or
  11. * unmodified form, provided you list me in the credits.
  12. * - If you modify this source code, you must add a notice to each modified
  13. * source file that it has been changed. If you're a nice person, you
  14. * will clearly mark each change too. :)
  15. * - If you wish to use this for commercial purposes, please contact me at
  16. * pullmoll@t-online.de
  17. * - The author of this copywritten work reserves the right to change the
  18. * terms of its usage and license at any time, including retroactively
  19. * - This entire notice must remain in the source code.
  20. *
  21. * This work is based on <tiraniddo@hotmail.com> C/C++ implementation of
  22. * the SH-2 CPU core and was adapted to the MAME CPU core requirements.
  23. * Thanks also go to Chuck Mason <chukjr@sundail.net> and Olivier Galibert
  24. * <galibert@pobox.com> for letting me peek into their SEMU code :-)
  25. *
  26. *****************************************************************************/
  27. /*****************************************************************************
  28. Changes
  29. 20130129 Angelo Salese
  30. - added illegal opcode exception handling, side effect of some Saturn games
  31. on loading like Feda or Falcom Classics Vol. 1
  32. (i.e. Master CPU Incautiously transfers memory from CD to work RAM H, and
  33. wipes out Slave CPU program code too while at it).
  34. 20051129 Mariusz Wojcieszek
  35. - introduced memory_decrypted_read_word() for opcode fetching
  36. 20050813 Mariusz Wojcieszek
  37. - fixed 64 bit / 32 bit division in division unit
  38. 20031015 O. Galibert
  39. - dma fixes, thanks to sthief
  40. 20031013 O. Galibert, A. Giles
  41. - timer fixes
  42. - multi-cpu simplifications
  43. 20030915 O. Galibert
  44. - fix DMA1 irq vector
  45. - ignore writes to DRCRx
  46. - fix cpu number issues
  47. - fix slave/master recognition
  48. - fix wrong-cpu-in-context problem with the timers
  49. 20021020 O. Galibert
  50. - DMA implementation, lightly tested
  51. - delay slot in debugger fixed
  52. - add divide box mirrors
  53. - Nicola-ify the indentation
  54. - Uncrapify sh2_internal_*
  55. - Put back nmi support that had been lost somehow
  56. 20020914 R. Belmont
  57. - Initial SH2 internal timers implementation, based on code by O. Galibert.
  58. Makes music work in galspanic4/s/s2, panic street, cyvern, other SKNS games.
  59. - Fix to external division, thanks to "spice" on the E2J board.
  60. Corrects behavior of s1945ii turret boss.
  61. 20020302 Olivier Galibert (galibert@mame.net)
  62. - Fixed interrupt in delay slot
  63. - Fixed rotcr
  64. - Fixed div1
  65. - Fixed mulu
  66. - Fixed negc
  67. 20020301 R. Belmont
  68. - Fixed external division
  69. 20020225 Olivier Galibert (galibert@mame.net)
  70. - Fixed interrupt handling
  71. 20010207 Sylvain Glaize (mokona@puupuu.org)
  72. - Bug fix in INLINE void MOVBM(UINT32 m, UINT32 n) (see comment)
  73. - Support of full 32 bit addressing (RB, RW, RL and WB, WW, WL functions)
  74. reason : when the two high bits of the address are set, access is
  75. done directly in the cache data array. The SUPER KANEKO NOVA SYSTEM
  76. sets the stack pointer here, using these addresses as usual RAM access.
  77. No real cache support has been added.
  78. - Read/Write memory format correction (_bew to _bedw) (see also SH2
  79. definition in cpuintrf.c and DasmSH2(..) in sh2dasm.c )
  80. 20010623 James Forshaw (TyRaNiD@totalise.net)
  81. - Modified operation of sh2_exception. Done cause mame irq system is stupid, and
  82. doesnt really seem designed for any more than 8 interrupt lines.
  83. 20010701 James Forshaw (TyRaNiD@totalise.net)
  84. - Fixed DIV1 operation. Q bit now correctly generated
  85. 20020218 Added save states (mokona@puupuu.org)
  86. *****************************************************************************/
  87. //#include "debugger.h"
  88. //#include "sh2.h"
  89. //#include "sh2comn.h"
  90. #undef INLINE
  91. #define INLINE static
  92. //CPU_DISASSEMBLE( sh2 );
  93. #ifndef USE_SH2DRC
  94. /* speed up delay loops, bail out of tight loops */
  95. //#define BUSY_LOOP_HACKS 1
  96. #define VERBOSE 0
  97. #define LOG(x) do { if (VERBOSE) logerror x; } while (0)
  98. #if 0
  99. INLINE UINT8 RB(sh2_state *sh2, offs_t A)
  100. {
  101. if (A >= 0xe0000000)
  102. return sh2_internal_r(*sh2->internal, (A & 0x1fc)>>2, 0xff << (((~A) & 3)*8)) >> (((~A) & 3)*8);
  103. if (A >= 0xc0000000)
  104. return sh2->program->read_byte(A);
  105. if (A >= 0x40000000)
  106. return 0xa5;
  107. return sh2->program->read_byte(A & AM);
  108. }
  109. INLINE UINT16 RW(sh2_state *sh2, offs_t A)
  110. {
  111. if (A >= 0xe0000000)
  112. return sh2_internal_r(*sh2->internal, (A & 0x1fc)>>2, 0xffff << (((~A) & 2)*8)) >> (((~A) & 2)*8);
  113. if (A >= 0xc0000000)
  114. return sh2->program->read_word(A);
  115. if (A >= 0x40000000)
  116. return 0xa5a5;
  117. return sh2->program->read_word(A & AM);
  118. }
  119. INLINE UINT32 RL(sh2_state *sh2, offs_t A)
  120. {
  121. if (A >= 0xe0000000)
  122. return sh2_internal_r(*sh2->internal, (A & 0x1fc)>>2, 0xffffffff);
  123. if (A >= 0xc0000000)
  124. return sh2->program->read_dword(A);
  125. if (A >= 0x40000000)
  126. return 0xa5a5a5a5;
  127. return sh2->program->read_dword(A & AM);
  128. }
  129. INLINE void WB(sh2_state *sh2, offs_t A, UINT8 V)
  130. {
  131. if (A >= 0xe0000000)
  132. {
  133. sh2_internal_w(*sh2->internal, (A & 0x1fc)>>2, V << (((~A) & 3)*8), 0xff << (((~A) & 3)*8));
  134. return;
  135. }
  136. if (A >= 0xc0000000)
  137. {
  138. sh2->program->write_byte(A,V);
  139. return;
  140. }
  141. if (A >= 0x40000000)
  142. return;
  143. sh2->program->write_byte(A & AM,V);
  144. }
  145. INLINE void WW(sh2_state *sh2, offs_t A, UINT16 V)
  146. {
  147. if (A >= 0xe0000000)
  148. {
  149. sh2_internal_w(*sh2->internal, (A & 0x1fc)>>2, V << (((~A) & 2)*8), 0xffff << (((~A) & 2)*8));
  150. return;
  151. }
  152. if (A >= 0xc0000000)
  153. {
  154. sh2->program->write_word(A,V);
  155. return;
  156. }
  157. if (A >= 0x40000000)
  158. return;
  159. sh2->program->write_word(A & AM,V);
  160. }
  161. INLINE void WL(sh2_state *sh2, offs_t A, UINT32 V)
  162. {
  163. if (A >= 0xe0000000)
  164. {
  165. sh2_internal_w(*sh2->internal, (A & 0x1fc)>>2, V, 0xffffffff);
  166. return;
  167. }
  168. if (A >= 0xc0000000)
  169. {
  170. sh2->program->write_dword(A,V);
  171. return;
  172. }
  173. if (A >= 0x40000000)
  174. return;
  175. sh2->program->write_dword(A & AM,V);
  176. }
  177. #endif
  178. /* code cycles t-bit
  179. * 0011 nnnn mmmm 1100 1 -
  180. * ADD Rm,Rn
  181. */
  182. INLINE void ADD(sh2_state *sh2, UINT32 m, UINT32 n)
  183. {
  184. sh2->r[n] += sh2->r[m];
  185. }
  186. /* code cycles t-bit
  187. * 0111 nnnn iiii iiii 1 -
  188. * ADD #imm,Rn
  189. */
  190. INLINE void ADDI(sh2_state *sh2, UINT32 i, UINT32 n)
  191. {
  192. sh2->r[n] += (INT32)(INT16)(INT8)i;
  193. }
  194. /* code cycles t-bit
  195. * 0011 nnnn mmmm 1110 1 carry
  196. * ADDC Rm,Rn
  197. */
  198. INLINE void ADDC(sh2_state *sh2, UINT32 m, UINT32 n)
  199. {
  200. UINT32 tmp0, tmp1;
  201. tmp1 = sh2->r[n] + sh2->r[m];
  202. tmp0 = sh2->r[n];
  203. sh2->r[n] = tmp1 + (sh2->sr & T);
  204. if (tmp0 > tmp1)
  205. sh2->sr |= T;
  206. else
  207. sh2->sr &= ~T;
  208. if (tmp1 > sh2->r[n])
  209. sh2->sr |= T;
  210. }
  211. /* code cycles t-bit
  212. * 0011 nnnn mmmm 1111 1 overflow
  213. * ADDV Rm,Rn
  214. */
  215. INLINE void ADDV(sh2_state *sh2, UINT32 m, UINT32 n)
  216. {
  217. INT32 dest, src, ans;
  218. if ((INT32) sh2->r[n] >= 0)
  219. dest = 0;
  220. else
  221. dest = 1;
  222. if ((INT32) sh2->r[m] >= 0)
  223. src = 0;
  224. else
  225. src = 1;
  226. src += dest;
  227. sh2->r[n] += sh2->r[m];
  228. if ((INT32) sh2->r[n] >= 0)
  229. ans = 0;
  230. else
  231. ans = 1;
  232. ans += dest;
  233. if (src == 0 || src == 2)
  234. {
  235. if (ans == 1)
  236. sh2->sr |= T;
  237. else
  238. sh2->sr &= ~T;
  239. }
  240. else
  241. sh2->sr &= ~T;
  242. }
  243. /* code cycles t-bit
  244. * 0010 nnnn mmmm 1001 1 -
  245. * AND Rm,Rn
  246. */
  247. INLINE void AND(sh2_state *sh2, UINT32 m, UINT32 n)
  248. {
  249. sh2->r[n] &= sh2->r[m];
  250. }
  251. /* code cycles t-bit
  252. * 1100 1001 iiii iiii 1 -
  253. * AND #imm,R0
  254. */
  255. INLINE void ANDI(sh2_state *sh2, UINT32 i)
  256. {
  257. sh2->r[0] &= i;
  258. }
  259. /* code cycles t-bit
  260. * 1100 1101 iiii iiii 1 -
  261. * AND.B #imm,@(R0,GBR)
  262. */
  263. INLINE void ANDM(sh2_state *sh2, UINT32 i)
  264. {
  265. UINT32 temp;
  266. sh2->ea = sh2->gbr + sh2->r[0];
  267. temp = i & RB( sh2, sh2->ea );
  268. WB( sh2, sh2->ea, temp );
  269. sh2->icount -= 2;
  270. }
  271. /* code cycles t-bit
  272. * 1000 1011 dddd dddd 3/1 -
  273. * BF disp8
  274. */
  275. INLINE void BF(sh2_state *sh2, UINT32 d)
  276. {
  277. if ((sh2->sr & T) == 0)
  278. {
  279. INT32 disp = ((INT32)d << 24) >> 24;
  280. sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;
  281. sh2->icount -= 2;
  282. }
  283. }
  284. /* code cycles t-bit
  285. * 1000 1111 dddd dddd 3/1 -
  286. * BFS disp8
  287. */
  288. INLINE void BFS(sh2_state *sh2, UINT32 d)
  289. {
  290. sh2->delay = sh2->pc;
  291. sh2->pc += 2;
  292. if ((sh2->sr & T) == 0)
  293. {
  294. INT32 disp = ((INT32)d << 24) >> 24;
  295. sh2->pc = sh2->ea = sh2->pc + disp * 2;
  296. sh2->icount--;
  297. }
  298. }
  299. /* code cycles t-bit
  300. * 1010 dddd dddd dddd 2 -
  301. * BRA disp12
  302. */
  303. INLINE void BRA(sh2_state *sh2, UINT32 d)
  304. {
  305. INT32 disp = ((INT32)d << 20) >> 20;
  306. #if BUSY_LOOP_HACKS
  307. if (disp == -2)
  308. {
  309. UINT32 next_opcode = RW( sh2, sh2->ppc & AM );
  310. /* BRA $
  311. * NOP
  312. */
  313. if (next_opcode == 0x0009)
  314. sh2->icount %= 3; /* cycles for BRA $ and NOP taken (3) */
  315. }
  316. #endif
  317. sh2->delay = sh2->pc;
  318. sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;
  319. sh2->icount--;
  320. }
  321. /* code cycles t-bit
  322. * 0000 mmmm 0010 0011 2 -
  323. * BRAF Rm
  324. */
  325. INLINE void BRAF(sh2_state *sh2, UINT32 m)
  326. {
  327. sh2->delay = sh2->pc;
  328. sh2->pc += sh2->r[m] + 2;
  329. sh2->icount--;
  330. }
  331. /* code cycles t-bit
  332. * 1011 dddd dddd dddd 2 -
  333. * BSR disp12
  334. */
  335. INLINE void BSR(sh2_state *sh2, UINT32 d)
  336. {
  337. INT32 disp = ((INT32)d << 20) >> 20;
  338. sh2->pr = sh2->pc + 2;
  339. sh2->delay = sh2->pc;
  340. sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;
  341. sh2->icount--;
  342. }
  343. /* code cycles t-bit
  344. * 0000 mmmm 0000 0011 2 -
  345. * BSRF Rm
  346. */
  347. INLINE void BSRF(sh2_state *sh2, UINT32 m)
  348. {
  349. sh2->pr = sh2->pc + 2;
  350. sh2->delay = sh2->pc;
  351. sh2->pc += sh2->r[m] + 2;
  352. sh2->icount--;
  353. }
  354. /* code cycles t-bit
  355. * 1000 1001 dddd dddd 3/1 -
  356. * BT disp8
  357. */
  358. INLINE void BT(sh2_state *sh2, UINT32 d)
  359. {
  360. if ((sh2->sr & T) != 0)
  361. {
  362. INT32 disp = ((INT32)d << 24) >> 24;
  363. sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;
  364. sh2->icount -= 2;
  365. }
  366. }
  367. /* code cycles t-bit
  368. * 1000 1101 dddd dddd 2/1 -
  369. * BTS disp8
  370. */
  371. INLINE void BTS(sh2_state *sh2, UINT32 d)
  372. {
  373. sh2->delay = sh2->pc;
  374. sh2->pc += 2;
  375. if ((sh2->sr & T) != 0)
  376. {
  377. INT32 disp = ((INT32)d << 24) >> 24;
  378. sh2->pc = sh2->ea = sh2->pc + disp * 2;
  379. sh2->icount--;
  380. }
  381. }
  382. /* code cycles t-bit
  383. * 0000 0000 0010 1000 1 -
  384. * CLRMAC
  385. */
  386. INLINE void CLRMAC(sh2_state *sh2)
  387. {
  388. sh2->mach = 0;
  389. sh2->macl = 0;
  390. }
  391. /* code cycles t-bit
  392. * 0000 0000 0000 1000 1 -
  393. * CLRT
  394. */
  395. INLINE void CLRT(sh2_state *sh2)
  396. {
  397. sh2->sr &= ~T;
  398. }
  399. /* code cycles t-bit
  400. * 0011 nnnn mmmm 0000 1 comparison result
  401. * CMP_EQ Rm,Rn
  402. */
  403. INLINE void CMPEQ(sh2_state *sh2, UINT32 m, UINT32 n)
  404. {
  405. if (sh2->r[n] == sh2->r[m])
  406. sh2->sr |= T;
  407. else
  408. sh2->sr &= ~T;
  409. }
  410. /* code cycles t-bit
  411. * 0011 nnnn mmmm 0011 1 comparison result
  412. * CMP_GE Rm,Rn
  413. */
  414. INLINE void CMPGE(sh2_state *sh2, UINT32 m, UINT32 n)
  415. {
  416. if ((INT32) sh2->r[n] >= (INT32) sh2->r[m])
  417. sh2->sr |= T;
  418. else
  419. sh2->sr &= ~T;
  420. }
  421. /* code cycles t-bit
  422. * 0011 nnnn mmmm 0111 1 comparison result
  423. * CMP_GT Rm,Rn
  424. */
  425. INLINE void CMPGT(sh2_state *sh2, UINT32 m, UINT32 n)
  426. {
  427. if ((INT32) sh2->r[n] > (INT32) sh2->r[m])
  428. sh2->sr |= T;
  429. else
  430. sh2->sr &= ~T;
  431. }
  432. /* code cycles t-bit
  433. * 0011 nnnn mmmm 0110 1 comparison result
  434. * CMP_HI Rm,Rn
  435. */
  436. INLINE void CMPHI(sh2_state *sh2, UINT32 m, UINT32 n)
  437. {
  438. if ((UINT32) sh2->r[n] > (UINT32) sh2->r[m])
  439. sh2->sr |= T;
  440. else
  441. sh2->sr &= ~T;
  442. }
  443. /* code cycles t-bit
  444. * 0011 nnnn mmmm 0010 1 comparison result
  445. * CMP_HS Rm,Rn
  446. */
  447. INLINE void CMPHS(sh2_state *sh2, UINT32 m, UINT32 n)
  448. {
  449. if ((UINT32) sh2->r[n] >= (UINT32) sh2->r[m])
  450. sh2->sr |= T;
  451. else
  452. sh2->sr &= ~T;
  453. }
  454. /* code cycles t-bit
  455. * 0100 nnnn 0001 0101 1 comparison result
  456. * CMP_PL Rn
  457. */
  458. INLINE void CMPPL(sh2_state *sh2, UINT32 n)
  459. {
  460. if ((INT32) sh2->r[n] > 0)
  461. sh2->sr |= T;
  462. else
  463. sh2->sr &= ~T;
  464. }
  465. /* code cycles t-bit
  466. * 0100 nnnn 0001 0001 1 comparison result
  467. * CMP_PZ Rn
  468. */
  469. INLINE void CMPPZ(sh2_state *sh2, UINT32 n)
  470. {
  471. if ((INT32) sh2->r[n] >= 0)
  472. sh2->sr |= T;
  473. else
  474. sh2->sr &= ~T;
  475. }
  476. /* code cycles t-bit
  477. * 0010 nnnn mmmm 1100 1 comparison result
  478. * CMP_STR Rm,Rn
  479. */
  480. INLINE void CMPSTR(sh2_state *sh2, UINT32 m, UINT32 n)
  481. {
  482. UINT32 temp;
  483. INT32 HH, HL, LH, LL;
  484. temp = sh2->r[n] ^ sh2->r[m];
  485. HH = (temp >> 24) & 0xff;
  486. HL = (temp >> 16) & 0xff;
  487. LH = (temp >> 8) & 0xff;
  488. LL = temp & 0xff;
  489. if (HH && HL && LH && LL)
  490. sh2->sr &= ~T;
  491. else
  492. sh2->sr |= T;
  493. }
  494. /* code cycles t-bit
  495. * 1000 1000 iiii iiii 1 comparison result
  496. * CMP/EQ #imm,R0
  497. */
  498. INLINE void CMPIM(sh2_state *sh2, UINT32 i)
  499. {
  500. UINT32 imm = (UINT32)(INT32)(INT16)(INT8)i;
  501. if (sh2->r[0] == imm)
  502. sh2->sr |= T;
  503. else
  504. sh2->sr &= ~T;
  505. }
  506. /* code cycles t-bit
  507. * 0010 nnnn mmmm 0111 1 calculation result
  508. * DIV0S Rm,Rn
  509. */
  510. INLINE void DIV0S(sh2_state *sh2, UINT32 m, UINT32 n)
  511. {
  512. if ((sh2->r[n] & 0x80000000) == 0)
  513. sh2->sr &= ~Q;
  514. else
  515. sh2->sr |= Q;
  516. if ((sh2->r[m] & 0x80000000) == 0)
  517. sh2->sr &= ~M;
  518. else
  519. sh2->sr |= M;
  520. if ((sh2->r[m] ^ sh2->r[n]) & 0x80000000)
  521. sh2->sr |= T;
  522. else
  523. sh2->sr &= ~T;
  524. }
  525. /* code cycles t-bit
  526. * 0000 0000 0001 1001 1 0
  527. * DIV0U
  528. */
  529. INLINE void DIV0U(sh2_state *sh2)
  530. {
  531. sh2->sr &= ~(M | Q | T);
  532. }
  533. /* code cycles t-bit
  534. * 0011 nnnn mmmm 0100 1 calculation result
  535. * DIV1 Rm,Rn
  536. */
  537. INLINE void DIV1(sh2_state *sh2, UINT32 m, UINT32 n)
  538. {
  539. UINT32 tmp0;
  540. UINT32 old_q;
  541. old_q = sh2->sr & Q;
  542. if (0x80000000 & sh2->r[n])
  543. sh2->sr |= Q;
  544. else
  545. sh2->sr &= ~Q;
  546. sh2->r[n] = (sh2->r[n] << 1) | (sh2->sr & T);
  547. if (!old_q)
  548. {
  549. if (!(sh2->sr & M))
  550. {
  551. tmp0 = sh2->r[n];
  552. sh2->r[n] -= sh2->r[m];
  553. if(!(sh2->sr & Q))
  554. if(sh2->r[n] > tmp0)
  555. sh2->sr |= Q;
  556. else
  557. sh2->sr &= ~Q;
  558. else
  559. if(sh2->r[n] > tmp0)
  560. sh2->sr &= ~Q;
  561. else
  562. sh2->sr |= Q;
  563. }
  564. else
  565. {
  566. tmp0 = sh2->r[n];
  567. sh2->r[n] += sh2->r[m];
  568. if(!(sh2->sr & Q))
  569. {
  570. if(sh2->r[n] < tmp0)
  571. sh2->sr &= ~Q;
  572. else
  573. sh2->sr |= Q;
  574. }
  575. else
  576. {
  577. if(sh2->r[n] < tmp0)
  578. sh2->sr |= Q;
  579. else
  580. sh2->sr &= ~Q;
  581. }
  582. }
  583. }
  584. else
  585. {
  586. if (!(sh2->sr & M))
  587. {
  588. tmp0 = sh2->r[n];
  589. sh2->r[n] += sh2->r[m];
  590. if(!(sh2->sr & Q))
  591. if(sh2->r[n] < tmp0)
  592. sh2->sr |= Q;
  593. else
  594. sh2->sr &= ~Q;
  595. else
  596. if(sh2->r[n] < tmp0)
  597. sh2->sr &= ~Q;
  598. else
  599. sh2->sr |= Q;
  600. }
  601. else
  602. {
  603. tmp0 = sh2->r[n];
  604. sh2->r[n] -= sh2->r[m];
  605. if(!(sh2->sr & Q))
  606. if(sh2->r[n] > tmp0)
  607. sh2->sr &= ~Q;
  608. else
  609. sh2->sr |= Q;
  610. else
  611. if(sh2->r[n] > tmp0)
  612. sh2->sr |= Q;
  613. else
  614. sh2->sr &= ~Q;
  615. }
  616. }
  617. tmp0 = (sh2->sr & (Q | M));
  618. if((!tmp0) || (tmp0 == 0x300)) /* if Q == M set T else clear T */
  619. sh2->sr |= T;
  620. else
  621. sh2->sr &= ~T;
  622. }
  623. /* DMULS.L Rm,Rn */
  624. INLINE void DMULS(sh2_state *sh2, UINT32 m, UINT32 n)
  625. {
  626. UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2;
  627. UINT32 temp0, temp1, temp2, temp3;
  628. INT32 tempm, tempn, fnLmL;
  629. tempn = (INT32) sh2->r[n];
  630. tempm = (INT32) sh2->r[m];
  631. if (tempn < 0)
  632. tempn = 0 - tempn;
  633. if (tempm < 0)
  634. tempm = 0 - tempm;
  635. if ((INT32) (sh2->r[n] ^ sh2->r[m]) < 0)
  636. fnLmL = -1;
  637. else
  638. fnLmL = 0;
  639. temp1 = (UINT32) tempn;
  640. temp2 = (UINT32) tempm;
  641. RnL = temp1 & 0x0000ffff;
  642. RnH = (temp1 >> 16) & 0x0000ffff;
  643. RmL = temp2 & 0x0000ffff;
  644. RmH = (temp2 >> 16) & 0x0000ffff;
  645. temp0 = RmL * RnL;
  646. temp1 = RmH * RnL;
  647. temp2 = RmL * RnH;
  648. temp3 = RmH * RnH;
  649. Res2 = 0;
  650. Res1 = temp1 + temp2;
  651. if (Res1 < temp1)
  652. Res2 += 0x00010000;
  653. temp1 = (Res1 << 16) & 0xffff0000;
  654. Res0 = temp0 + temp1;
  655. if (Res0 < temp0)
  656. Res2++;
  657. Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3;
  658. if (fnLmL < 0)
  659. {
  660. Res2 = ~Res2;
  661. if (Res0 == 0)
  662. Res2++;
  663. else
  664. Res0 = (~Res0) + 1;
  665. }
  666. sh2->mach = Res2;
  667. sh2->macl = Res0;
  668. sh2->icount--;
  669. }
  670. /* DMULU.L Rm,Rn */
  671. INLINE void DMULU(sh2_state *sh2, UINT32 m, UINT32 n)
  672. {
  673. UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2;
  674. UINT32 temp0, temp1, temp2, temp3;
  675. RnL = sh2->r[n] & 0x0000ffff;
  676. RnH = (sh2->r[n] >> 16) & 0x0000ffff;
  677. RmL = sh2->r[m] & 0x0000ffff;
  678. RmH = (sh2->r[m] >> 16) & 0x0000ffff;
  679. temp0 = RmL * RnL;
  680. temp1 = RmH * RnL;
  681. temp2 = RmL * RnH;
  682. temp3 = RmH * RnH;
  683. Res2 = 0;
  684. Res1 = temp1 + temp2;
  685. if (Res1 < temp1)
  686. Res2 += 0x00010000;
  687. temp1 = (Res1 << 16) & 0xffff0000;
  688. Res0 = temp0 + temp1;
  689. if (Res0 < temp0)
  690. Res2++;
  691. Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3;
  692. sh2->mach = Res2;
  693. sh2->macl = Res0;
  694. sh2->icount--;
  695. }
  696. /* DT Rn */
  697. INLINE void DT(sh2_state *sh2, UINT32 n)
  698. {
  699. sh2->r[n]--;
  700. if (sh2->r[n] == 0)
  701. sh2->sr |= T;
  702. else
  703. sh2->sr &= ~T;
  704. #if BUSY_LOOP_HACKS
  705. {
  706. UINT32 next_opcode = RW( sh2, sh2->ppc & AM );
  707. /* DT Rn
  708. * BF $-2
  709. */
  710. if (next_opcode == 0x8bfd)
  711. {
  712. while (sh2->r[n] > 1 && sh2->icount > 4)
  713. {
  714. sh2->r[n]--;
  715. sh2->icount -= 4; /* cycles for DT (1) and BF taken (3) */
  716. }
  717. }
  718. }
  719. #endif
  720. }
  721. /* EXTS.B Rm,Rn */
  722. INLINE void EXTSB(sh2_state *sh2, UINT32 m, UINT32 n)
  723. {
  724. sh2->r[n] = ((INT32)sh2->r[m] << 24) >> 24;
  725. }
  726. /* EXTS.W Rm,Rn */
  727. INLINE void EXTSW(sh2_state *sh2, UINT32 m, UINT32 n)
  728. {
  729. sh2->r[n] = ((INT32)sh2->r[m] << 16) >> 16;
  730. }
  731. /* EXTU.B Rm,Rn */
  732. INLINE void EXTUB(sh2_state *sh2, UINT32 m, UINT32 n)
  733. {
  734. sh2->r[n] = sh2->r[m] & 0x000000ff;
  735. }
  736. /* EXTU.W Rm,Rn */
  737. INLINE void EXTUW(sh2_state *sh2, UINT32 m, UINT32 n)
  738. {
  739. sh2->r[n] = sh2->r[m] & 0x0000ffff;
  740. }
  741. /* ILLEGAL */
  742. INLINE void ILLEGAL(sh2_state *sh2)
  743. {
  744. logerror("SH2: Illegal opcode at %08x\n", sh2->pc - 2);
  745. sh2->r[15] -= 4;
  746. WL( sh2, sh2->r[15], sh2->sr ); /* push SR onto stack */
  747. sh2->r[15] -= 4;
  748. WL( sh2, sh2->r[15], sh2->pc - 2 ); /* push PC onto stack */
  749. /* fetch PC */
  750. sh2->pc = RL( sh2, sh2->vbr + 4 * 4 );
  751. /* TODO: timing is a guess */
  752. sh2->icount -= 5;
  753. }
  754. /* JMP @Rm */
  755. INLINE void JMP(sh2_state *sh2, UINT32 m)
  756. {
  757. sh2->delay = sh2->pc;
  758. sh2->pc = sh2->ea = sh2->r[m];
  759. sh2->icount--;
  760. }
  761. /* JSR @Rm */
  762. INLINE void JSR(sh2_state *sh2, UINT32 m)
  763. {
  764. sh2->delay = sh2->pc;
  765. sh2->pr = sh2->pc + 2;
  766. sh2->pc = sh2->ea = sh2->r[m];
  767. sh2->icount--;
  768. }
  769. /* LDC Rm,SR */
  770. INLINE void LDCSR(sh2_state *sh2, UINT32 m)
  771. {
  772. sh2->sr = sh2->r[m] & FLAGS;
  773. sh2->test_irq = 1;
  774. }
  775. /* LDC Rm,GBR */
  776. INLINE void LDCGBR(sh2_state *sh2, UINT32 m)
  777. {
  778. sh2->gbr = sh2->r[m];
  779. }
  780. /* LDC Rm,VBR */
  781. INLINE void LDCVBR(sh2_state *sh2, UINT32 m)
  782. {
  783. sh2->vbr = sh2->r[m];
  784. }
  785. /* LDC.L @Rm+,SR */
  786. INLINE void LDCMSR(sh2_state *sh2, UINT32 m)
  787. {
  788. sh2->ea = sh2->r[m];
  789. sh2->sr = RL( sh2, sh2->ea ) & FLAGS;
  790. sh2->r[m] += 4;
  791. sh2->icount -= 2;
  792. sh2->test_irq = 1;
  793. }
  794. /* LDC.L @Rm+,GBR */
  795. INLINE void LDCMGBR(sh2_state *sh2, UINT32 m)
  796. {
  797. sh2->ea = sh2->r[m];
  798. sh2->gbr = RL( sh2, sh2->ea );
  799. sh2->r[m] += 4;
  800. sh2->icount -= 2;
  801. }
  802. /* LDC.L @Rm+,VBR */
  803. INLINE void LDCMVBR(sh2_state *sh2, UINT32 m)
  804. {
  805. sh2->ea = sh2->r[m];
  806. sh2->vbr = RL( sh2, sh2->ea );
  807. sh2->r[m] += 4;
  808. sh2->icount -= 2;
  809. }
  810. /* LDS Rm,MACH */
  811. INLINE void LDSMACH(sh2_state *sh2, UINT32 m)
  812. {
  813. sh2->mach = sh2->r[m];
  814. }
  815. /* LDS Rm,MACL */
  816. INLINE void LDSMACL(sh2_state *sh2, UINT32 m)
  817. {
  818. sh2->macl = sh2->r[m];
  819. }
  820. /* LDS Rm,PR */
  821. INLINE void LDSPR(sh2_state *sh2, UINT32 m)
  822. {
  823. sh2->pr = sh2->r[m];
  824. }
  825. /* LDS.L @Rm+,MACH */
  826. INLINE void LDSMMACH(sh2_state *sh2, UINT32 m)
  827. {
  828. sh2->ea = sh2->r[m];
  829. sh2->mach = RL( sh2, sh2->ea );
  830. sh2->r[m] += 4;
  831. }
  832. /* LDS.L @Rm+,MACL */
  833. INLINE void LDSMMACL(sh2_state *sh2, UINT32 m)
  834. {
  835. sh2->ea = sh2->r[m];
  836. sh2->macl = RL( sh2, sh2->ea );
  837. sh2->r[m] += 4;
  838. }
  839. /* LDS.L @Rm+,PR */
  840. INLINE void LDSMPR(sh2_state *sh2, UINT32 m)
  841. {
  842. sh2->ea = sh2->r[m];
  843. sh2->pr = RL( sh2, sh2->ea );
  844. sh2->r[m] += 4;
  845. }
  846. /* MAC.L @Rm+,@Rn+ */
  847. INLINE void MAC_L(sh2_state *sh2, UINT32 m, UINT32 n)
  848. {
  849. UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2;
  850. UINT32 temp0, temp1, temp2, temp3;
  851. INT32 tempm, tempn, fnLmL;
  852. tempn = (INT32) RL( sh2, sh2->r[n] );
  853. sh2->r[n] += 4;
  854. tempm = (INT32) RL( sh2, sh2->r[m] );
  855. sh2->r[m] += 4;
  856. if ((INT32) (tempn ^ tempm) < 0)
  857. fnLmL = -1;
  858. else
  859. fnLmL = 0;
  860. if (tempn < 0)
  861. tempn = 0 - tempn;
  862. if (tempm < 0)
  863. tempm = 0 - tempm;
  864. temp1 = (UINT32) tempn;
  865. temp2 = (UINT32) tempm;
  866. RnL = temp1 & 0x0000ffff;
  867. RnH = (temp1 >> 16) & 0x0000ffff;
  868. RmL = temp2 & 0x0000ffff;
  869. RmH = (temp2 >> 16) & 0x0000ffff;
  870. temp0 = RmL * RnL;
  871. temp1 = RmH * RnL;
  872. temp2 = RmL * RnH;
  873. temp3 = RmH * RnH;
  874. Res2 = 0;
  875. Res1 = temp1 + temp2;
  876. if (Res1 < temp1)
  877. Res2 += 0x00010000;
  878. temp1 = (Res1 << 16) & 0xffff0000;
  879. Res0 = temp0 + temp1;
  880. if (Res0 < temp0)
  881. Res2++;
  882. Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3;
  883. if (fnLmL < 0)
  884. {
  885. Res2 = ~Res2;
  886. if (Res0 == 0)
  887. Res2++;
  888. else
  889. Res0 = (~Res0) + 1;
  890. }
  891. if (sh2->sr & S)
  892. {
  893. Res0 = sh2->macl + Res0;
  894. if (sh2->macl > Res0)
  895. Res2++;
  896. Res2 += (sh2->mach & 0x0000ffff);
  897. if (((INT32) Res2 < 0) && (Res2 < 0xffff8000))
  898. {
  899. Res2 = 0x00008000;
  900. Res0 = 0x00000000;
  901. }
  902. else if (((INT32) Res2 > 0) && (Res2 > 0x00007fff))
  903. {
  904. Res2 = 0x00007fff;
  905. Res0 = 0xffffffff;
  906. }
  907. sh2->mach = Res2;
  908. sh2->macl = Res0;
  909. }
  910. else
  911. {
  912. Res0 = sh2->macl + Res0;
  913. if (sh2->macl > Res0)
  914. Res2++;
  915. Res2 += sh2->mach;
  916. sh2->mach = Res2;
  917. sh2->macl = Res0;
  918. }
  919. sh2->icount -= 2;
  920. }
  921. /* MAC.W @Rm+,@Rn+ */
  922. INLINE void MAC_W(sh2_state *sh2, UINT32 m, UINT32 n)
  923. {
  924. INT32 tempm, tempn, dest, src, ans;
  925. UINT32 templ;
  926. tempn = (INT32) RW( sh2, sh2->r[n] );
  927. sh2->r[n] += 2;
  928. tempm = (INT32) RW( sh2, sh2->r[m] );
  929. sh2->r[m] += 2;
  930. templ = sh2->macl;
  931. tempm = ((INT32) (short) tempn * (INT32) (short) tempm);
  932. if ((INT32) sh2->macl >= 0)
  933. dest = 0;
  934. else
  935. dest = 1;
  936. if ((INT32) tempm >= 0)
  937. {
  938. src = 0;
  939. tempn = 0;
  940. }
  941. else
  942. {
  943. src = 1;
  944. tempn = 0xffffffff;
  945. }
  946. src += dest;
  947. sh2->macl += tempm;
  948. if ((INT32) sh2->macl >= 0)
  949. ans = 0;
  950. else
  951. ans = 1;
  952. ans += dest;
  953. if (sh2->sr & S)
  954. {
  955. if (ans == 1)
  956. {
  957. if (src == 0)
  958. sh2->macl = 0x7fffffff;
  959. if (src == 2)
  960. sh2->macl = 0x80000000;
  961. }
  962. }
  963. else
  964. {
  965. sh2->mach += tempn;
  966. if (templ > sh2->macl)
  967. sh2->mach += 1;
  968. }
  969. sh2->icount -= 2;
  970. }
  971. /* MOV Rm,Rn */
  972. INLINE void MOV(sh2_state *sh2, UINT32 m, UINT32 n)
  973. {
  974. sh2->r[n] = sh2->r[m];
  975. }
  976. /* MOV.B Rm,@Rn */
  977. INLINE void MOVBS(sh2_state *sh2, UINT32 m, UINT32 n)
  978. {
  979. sh2->ea = sh2->r[n];
  980. WB( sh2, sh2->ea, sh2->r[m] & 0x000000ff);
  981. }
  982. /* MOV.W Rm,@Rn */
  983. INLINE void MOVWS(sh2_state *sh2, UINT32 m, UINT32 n)
  984. {
  985. sh2->ea = sh2->r[n];
  986. WW( sh2, sh2->ea, sh2->r[m] & 0x0000ffff);
  987. }
  988. /* MOV.L Rm,@Rn */
  989. INLINE void MOVLS(sh2_state *sh2, UINT32 m, UINT32 n)
  990. {
  991. sh2->ea = sh2->r[n];
  992. WL( sh2, sh2->ea, sh2->r[m] );
  993. }
  994. /* MOV.B @Rm,Rn */
  995. INLINE void MOVBL(sh2_state *sh2, UINT32 m, UINT32 n)
  996. {
  997. sh2->ea = sh2->r[m];
  998. sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->ea );
  999. }
  1000. /* MOV.W @Rm,Rn */
  1001. INLINE void MOVWL(sh2_state *sh2, UINT32 m, UINT32 n)
  1002. {
  1003. sh2->ea = sh2->r[m];
  1004. sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2, sh2->ea );
  1005. }
  1006. /* MOV.L @Rm,Rn */
  1007. INLINE void MOVLL(sh2_state *sh2, UINT32 m, UINT32 n)
  1008. {
  1009. sh2->ea = sh2->r[m];
  1010. sh2->r[n] = RL( sh2, sh2->ea );
  1011. }
  1012. /* MOV.B Rm,@-Rn */
  1013. INLINE void MOVBM(sh2_state *sh2, UINT32 m, UINT32 n)
  1014. {
  1015. /* SMG : bug fix, was reading sh2->r[n] */
  1016. UINT32 data = sh2->r[m] & 0x000000ff;
  1017. sh2->r[n] -= 1;
  1018. WB( sh2, sh2->r[n], data );
  1019. }
  1020. /* MOV.W Rm,@-Rn */
  1021. INLINE void MOVWM(sh2_state *sh2, UINT32 m, UINT32 n)
  1022. {
  1023. UINT32 data = sh2->r[m] & 0x0000ffff;
  1024. sh2->r[n] -= 2;
  1025. WW( sh2, sh2->r[n], data );
  1026. }
  1027. /* MOV.L Rm,@-Rn */
  1028. INLINE void MOVLM(sh2_state *sh2, UINT32 m, UINT32 n)
  1029. {
  1030. UINT32 data = sh2->r[m];
  1031. sh2->r[n] -= 4;
  1032. WL( sh2, sh2->r[n], data );
  1033. }
  1034. /* MOV.B @Rm+,Rn */
  1035. INLINE void MOVBP(sh2_state *sh2, UINT32 m, UINT32 n)
  1036. {
  1037. sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->r[m] );
  1038. if (n != m)
  1039. sh2->r[m] += 1;
  1040. }
  1041. /* MOV.W @Rm+,Rn */
  1042. INLINE void MOVWP(sh2_state *sh2, UINT32 m, UINT32 n)
  1043. {
  1044. sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2, sh2->r[m] );
  1045. if (n != m)
  1046. sh2->r[m] += 2;
  1047. }
  1048. /* MOV.L @Rm+,Rn */
  1049. INLINE void MOVLP(sh2_state *sh2, UINT32 m, UINT32 n)
  1050. {
  1051. sh2->r[n] = RL( sh2, sh2->r[m] );
  1052. if (n != m)
  1053. sh2->r[m] += 4;
  1054. }
  1055. /* MOV.B Rm,@(R0,Rn) */
  1056. INLINE void MOVBS0(sh2_state *sh2, UINT32 m, UINT32 n)
  1057. {
  1058. sh2->ea = sh2->r[n] + sh2->r[0];
  1059. WB( sh2, sh2->ea, sh2->r[m] & 0x000000ff );
  1060. }
  1061. /* MOV.W Rm,@(R0,Rn) */
  1062. INLINE void MOVWS0(sh2_state *sh2, UINT32 m, UINT32 n)
  1063. {
  1064. sh2->ea = sh2->r[n] + sh2->r[0];
  1065. WW( sh2, sh2->ea, sh2->r[m] & 0x0000ffff );
  1066. }
  1067. /* MOV.L Rm,@(R0,Rn) */
  1068. INLINE void MOVLS0(sh2_state *sh2, UINT32 m, UINT32 n)
  1069. {
  1070. sh2->ea = sh2->r[n] + sh2->r[0];
  1071. WL( sh2, sh2->ea, sh2->r[m] );
  1072. }
  1073. /* MOV.B @(R0,Rm),Rn */
  1074. INLINE void MOVBL0(sh2_state *sh2, UINT32 m, UINT32 n)
  1075. {
  1076. sh2->ea = sh2->r[m] + sh2->r[0];
  1077. sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->ea );
  1078. }
  1079. /* MOV.W @(R0,Rm),Rn */
  1080. INLINE void MOVWL0(sh2_state *sh2, UINT32 m, UINT32 n)
  1081. {
  1082. sh2->ea = sh2->r[m] + sh2->r[0];
  1083. sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2, sh2->ea );
  1084. }
  1085. /* MOV.L @(R0,Rm),Rn */
  1086. INLINE void MOVLL0(sh2_state *sh2, UINT32 m, UINT32 n)
  1087. {
  1088. sh2->ea = sh2->r[m] + sh2->r[0];
  1089. sh2->r[n] = RL( sh2, sh2->ea );
  1090. }
  1091. /* MOV #imm,Rn */
  1092. INLINE void MOVI(sh2_state *sh2, UINT32 i, UINT32 n)
  1093. {
  1094. sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) i;
  1095. }
  1096. /* MOV.W @(disp8,PC),Rn */
  1097. INLINE void MOVWI(sh2_state *sh2, UINT32 d, UINT32 n)
  1098. {
  1099. UINT32 disp = d & 0xff;
  1100. sh2->ea = sh2->pc + disp * 2 + 2;
  1101. sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2, sh2->ea );
  1102. }
  1103. /* MOV.L @(disp8,PC),Rn */
  1104. INLINE void MOVLI(sh2_state *sh2, UINT32 d, UINT32 n)
  1105. {
  1106. UINT32 disp = d & 0xff;
  1107. sh2->ea = ((sh2->pc + 2) & ~3) + disp * 4;
  1108. sh2->r[n] = RL( sh2, sh2->ea );
  1109. }
  1110. /* MOV.B @(disp8,GBR),R0 */
  1111. INLINE void MOVBLG(sh2_state *sh2, UINT32 d)
  1112. {
  1113. UINT32 disp = d & 0xff;
  1114. sh2->ea = sh2->gbr + disp;
  1115. sh2->r[0] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->ea );
  1116. }
  1117. /* MOV.W @(disp8,GBR),R0 */
  1118. INLINE void MOVWLG(sh2_state *sh2, UINT32 d)
  1119. {
  1120. UINT32 disp = d & 0xff;
  1121. sh2->ea = sh2->gbr + disp * 2;
  1122. sh2->r[0] = (INT32)(INT16) RW( sh2, sh2->ea );
  1123. }
  1124. /* MOV.L @(disp8,GBR),R0 */
  1125. INLINE void MOVLLG(sh2_state *sh2, UINT32 d)
  1126. {
  1127. UINT32 disp = d & 0xff;
  1128. sh2->ea = sh2->gbr + disp * 4;
  1129. sh2->r[0] = RL( sh2, sh2->ea );
  1130. }
  1131. /* MOV.B R0,@(disp8,GBR) */
  1132. INLINE void MOVBSG(sh2_state *sh2, UINT32 d)
  1133. {
  1134. UINT32 disp = d & 0xff;
  1135. sh2->ea = sh2->gbr + disp;
  1136. WB( sh2, sh2->ea, sh2->r[0] & 0x000000ff );
  1137. }
  1138. /* MOV.W R0,@(disp8,GBR) */
  1139. INLINE void MOVWSG(sh2_state *sh2, UINT32 d)
  1140. {
  1141. UINT32 disp = d & 0xff;
  1142. sh2->ea = sh2->gbr + disp * 2;
  1143. WW( sh2, sh2->ea, sh2->r[0] & 0x0000ffff );
  1144. }
  1145. /* MOV.L R0,@(disp8,GBR) */
  1146. INLINE void MOVLSG(sh2_state *sh2, UINT32 d)
  1147. {
  1148. UINT32 disp = d & 0xff;
  1149. sh2->ea = sh2->gbr + disp * 4;
  1150. WL( sh2, sh2->ea, sh2->r[0] );
  1151. }
  1152. /* MOV.B R0,@(disp4,Rn) */
  1153. INLINE void MOVBS4(sh2_state *sh2, UINT32 d, UINT32 n)
  1154. {
  1155. UINT32 disp = d & 0x0f;
  1156. sh2->ea = sh2->r[n] + disp;
  1157. WB( sh2, sh2->ea, sh2->r[0] & 0x000000ff );
  1158. }
  1159. /* MOV.W R0,@(disp4,Rn) */
  1160. INLINE void MOVWS4(sh2_state *sh2, UINT32 d, UINT32 n)
  1161. {
  1162. UINT32 disp = d & 0x0f;
  1163. sh2->ea = sh2->r[n] + disp * 2;
  1164. WW( sh2, sh2->ea, sh2->r[0] & 0x0000ffff );
  1165. }
  1166. /* MOV.L Rm,@(disp4,Rn) */
  1167. INLINE void MOVLS4(sh2_state *sh2, UINT32 m, UINT32 d, UINT32 n)
  1168. {
  1169. UINT32 disp = d & 0x0f;
  1170. sh2->ea = sh2->r[n] + disp * 4;
  1171. WL( sh2, sh2->ea, sh2->r[m] );
  1172. }
  1173. /* MOV.B @(disp4,Rm),R0 */
  1174. INLINE void MOVBL4(sh2_state *sh2, UINT32 m, UINT32 d)
  1175. {
  1176. UINT32 disp = d & 0x0f;
  1177. sh2->ea = sh2->r[m] + disp;
  1178. sh2->r[0] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->ea );
  1179. }
  1180. /* MOV.W @(disp4,Rm),R0 */
  1181. INLINE void MOVWL4(sh2_state *sh2, UINT32 m, UINT32 d)
  1182. {
  1183. UINT32 disp = d & 0x0f;
  1184. sh2->ea = sh2->r[m] + disp * 2;
  1185. sh2->r[0] = (UINT32)(INT32)(INT16) RW( sh2, sh2->ea );
  1186. }
  1187. /* MOV.L @(disp4,Rm),Rn */
  1188. INLINE void MOVLL4(sh2_state *sh2, UINT32 m, UINT32 d, UINT32 n)
  1189. {
  1190. UINT32 disp = d & 0x0f;
  1191. sh2->ea = sh2->r[m] + disp * 4;
  1192. sh2->r[n] = RL( sh2, sh2->ea );
  1193. }
  1194. /* MOVA @(disp8,PC),R0 */
  1195. INLINE void MOVA(sh2_state *sh2, UINT32 d)
  1196. {
  1197. UINT32 disp = d & 0xff;
  1198. sh2->ea = ((sh2->pc + 2) & ~3) + disp * 4;
  1199. sh2->r[0] = sh2->ea;
  1200. }
  1201. /* MOVT Rn */
  1202. INLINE void MOVT(sh2_state *sh2, UINT32 n)
  1203. {
  1204. sh2->r[n] = sh2->sr & T;
  1205. }
  1206. /* MUL.L Rm,Rn */
  1207. INLINE void MULL(sh2_state *sh2, UINT32 m, UINT32 n)
  1208. {
  1209. sh2->macl = sh2->r[n] * sh2->r[m];
  1210. sh2->icount--;
  1211. }
  1212. /* MULS Rm,Rn */
  1213. INLINE void MULS(sh2_state *sh2, UINT32 m, UINT32 n)
  1214. {
  1215. sh2->macl = (INT16) sh2->r[n] * (INT16) sh2->r[m];
  1216. }
  1217. /* MULU Rm,Rn */
  1218. INLINE void MULU(sh2_state *sh2, UINT32 m, UINT32 n)
  1219. {
  1220. sh2->macl = (UINT16) sh2->r[n] * (UINT16) sh2->r[m];
  1221. }
  1222. /* NEG Rm,Rn */
  1223. INLINE void NEG(sh2_state *sh2, UINT32 m, UINT32 n)
  1224. {
  1225. sh2->r[n] = 0 - sh2->r[m];
  1226. }
  1227. /* NEGC Rm,Rn */
  1228. INLINE void NEGC(sh2_state *sh2, UINT32 m, UINT32 n)
  1229. {
  1230. UINT32 temp;
  1231. temp = sh2->r[m];
  1232. sh2->r[n] = -temp - (sh2->sr & T);
  1233. if (temp || (sh2->sr & T))
  1234. sh2->sr |= T;
  1235. else
  1236. sh2->sr &= ~T;
  1237. }
  1238. /* NOP */
  1239. INLINE void NOP(void)
  1240. {
  1241. }
  1242. /* NOT Rm,Rn */
  1243. INLINE void NOT(sh2_state *sh2, UINT32 m, UINT32 n)
  1244. {
  1245. sh2->r[n] = ~sh2->r[m];
  1246. }
  1247. /* OR Rm,Rn */
  1248. INLINE void OR(sh2_state *sh2, UINT32 m, UINT32 n)
  1249. {
  1250. sh2->r[n] |= sh2->r[m];
  1251. }
  1252. /* OR #imm,R0 */
  1253. INLINE void ORI(sh2_state *sh2, UINT32 i)
  1254. {
  1255. sh2->r[0] |= i;
  1256. }
  1257. /* OR.B #imm,@(R0,GBR) */
  1258. INLINE void ORM(sh2_state *sh2, UINT32 i)
  1259. {
  1260. UINT32 temp;
  1261. sh2->ea = sh2->gbr + sh2->r[0];
  1262. temp = RB( sh2, sh2->ea );
  1263. temp |= i;
  1264. WB( sh2, sh2->ea, temp );
  1265. sh2->icount -= 2;
  1266. }
  1267. /* ROTCL Rn */
  1268. INLINE void ROTCL(sh2_state *sh2, UINT32 n)
  1269. {
  1270. UINT32 temp;
  1271. temp = (sh2->r[n] >> 31) & T;
  1272. sh2->r[n] = (sh2->r[n] << 1) | (sh2->sr & T);
  1273. sh2->sr = (sh2->sr & ~T) | temp;
  1274. }
  1275. /* ROTCR Rn */
  1276. INLINE void ROTCR(sh2_state *sh2, UINT32 n)
  1277. {
  1278. UINT32 temp;
  1279. temp = (sh2->sr & T) << 31;
  1280. if (sh2->r[n] & T)
  1281. sh2->sr |= T;
  1282. else
  1283. sh2->sr &= ~T;
  1284. sh2->r[n] = (sh2->r[n] >> 1) | temp;
  1285. }
  1286. /* ROTL Rn */
  1287. INLINE void ROTL(sh2_state *sh2, UINT32 n)
  1288. {
  1289. sh2->sr = (sh2->sr & ~T) | ((sh2->r[n] >> 31) & T);
  1290. sh2->r[n] = (sh2->r[n] << 1) | (sh2->r[n] >> 31);
  1291. }
  1292. /* ROTR Rn */
  1293. INLINE void ROTR(sh2_state *sh2, UINT32 n)
  1294. {
  1295. sh2->sr = (sh2->sr & ~T) | (sh2->r[n] & T);
  1296. sh2->r[n] = (sh2->r[n] >> 1) | (sh2->r[n] << 31);
  1297. }
  1298. /* RTE */
  1299. INLINE void RTE(sh2_state *sh2)
  1300. {
  1301. sh2->ea = sh2->r[15];
  1302. sh2->delay = sh2->pc;
  1303. sh2->pc = RL( sh2, sh2->ea );
  1304. sh2->r[15] += 4;
  1305. sh2->ea = sh2->r[15];
  1306. sh2->sr = RL( sh2, sh2->ea ) & FLAGS;
  1307. sh2->r[15] += 4;
  1308. sh2->icount -= 3;
  1309. sh2->test_irq = 1;
  1310. }
  1311. /* RTS */
  1312. INLINE void RTS(sh2_state *sh2)
  1313. {
  1314. sh2->delay = sh2->pc;
  1315. sh2->pc = sh2->ea = sh2->pr;
  1316. sh2->icount--;
  1317. }
  1318. /* SETT */
  1319. INLINE void SETT(sh2_state *sh2)
  1320. {
  1321. sh2->sr |= T;
  1322. }
  1323. /* SHAL Rn (same as SHLL) */
  1324. INLINE void SHAL(sh2_state *sh2, UINT32 n)
  1325. {
  1326. sh2->sr = (sh2->sr & ~T) | ((sh2->r[n] >> 31) & T);
  1327. sh2->r[n] <<= 1;
  1328. }
  1329. /* SHAR Rn */
  1330. INLINE void SHAR(sh2_state *sh2, UINT32 n)
  1331. {
  1332. sh2->sr = (sh2->sr & ~T) | (sh2->r[n] & T);
  1333. sh2->r[n] = (UINT32)((INT32)sh2->r[n] >> 1);
  1334. }
  1335. /* SHLL Rn (same as SHAL) */
  1336. INLINE void SHLL(sh2_state *sh2, UINT32 n)
  1337. {
  1338. sh2->sr = (sh2->sr & ~T) | ((sh2->r[n] >> 31) & T);
  1339. sh2->r[n] <<= 1;
  1340. }
  1341. /* SHLL2 Rn */
  1342. INLINE void SHLL2(sh2_state *sh2, UINT32 n)
  1343. {
  1344. sh2->r[n] <<= 2;
  1345. }
  1346. /* SHLL8 Rn */
  1347. INLINE void SHLL8(sh2_state *sh2, UINT32 n)
  1348. {
  1349. sh2->r[n] <<= 8;
  1350. }
  1351. /* SHLL16 Rn */
  1352. INLINE void SHLL16(sh2_state *sh2, UINT32 n)
  1353. {
  1354. sh2->r[n] <<= 16;
  1355. }
  1356. /* SHLR Rn */
  1357. INLINE void SHLR(sh2_state *sh2, UINT32 n)
  1358. {
  1359. sh2->sr = (sh2->sr & ~T) | (sh2->r[n] & T);
  1360. sh2->r[n] >>= 1;
  1361. }
  1362. /* SHLR2 Rn */
  1363. INLINE void SHLR2(sh2_state *sh2, UINT32 n)
  1364. {
  1365. sh2->r[n] >>= 2;
  1366. }
  1367. /* SHLR8 Rn */
  1368. INLINE void SHLR8(sh2_state *sh2, UINT32 n)
  1369. {
  1370. sh2->r[n] >>= 8;
  1371. }
  1372. /* SHLR16 Rn */
  1373. INLINE void SHLR16(sh2_state *sh2, UINT32 n)
  1374. {
  1375. sh2->r[n] >>= 16;
  1376. }
  1377. /* SLEEP */
  1378. INLINE void SLEEP(sh2_state *sh2)
  1379. {
  1380. //if(sh2->sleep_mode != 2)
  1381. sh2->pc -= 2;
  1382. sh2->icount -= 2;
  1383. /* Wait_for_exception; */
  1384. /*if(sh2->sleep_mode == 0)
  1385. sh2->sleep_mode = 1;
  1386. else if(sh2->sleep_mode == 2)
  1387. sh2->sleep_mode = 0;*/
  1388. }
  1389. /* STC SR,Rn */
  1390. INLINE void STCSR(sh2_state *sh2, UINT32 n)
  1391. {
  1392. sh2->r[n] = sh2->sr;
  1393. }
  1394. /* STC GBR,Rn */
  1395. INLINE void STCGBR(sh2_state *sh2, UINT32 n)
  1396. {
  1397. sh2->r[n] = sh2->gbr;
  1398. }
  1399. /* STC VBR,Rn */
  1400. INLINE void STCVBR(sh2_state *sh2, UINT32 n)
  1401. {
  1402. sh2->r[n] = sh2->vbr;
  1403. }
  1404. /* STC.L SR,@-Rn */
  1405. INLINE void STCMSR(sh2_state *sh2, UINT32 n)
  1406. {
  1407. sh2->r[n] -= 4;
  1408. sh2->ea = sh2->r[n];
  1409. WL( sh2, sh2->ea, sh2->sr );
  1410. sh2->icount--;
  1411. }
  1412. /* STC.L GBR,@-Rn */
  1413. INLINE void STCMGBR(sh2_state *sh2, UINT32 n)
  1414. {
  1415. sh2->r[n] -= 4;
  1416. sh2->ea = sh2->r[n];
  1417. WL( sh2, sh2->ea, sh2->gbr );
  1418. sh2->icount--;
  1419. }
  1420. /* STC.L VBR,@-Rn */
  1421. INLINE void STCMVBR(sh2_state *sh2, UINT32 n)
  1422. {
  1423. sh2->r[n] -= 4;
  1424. sh2->ea = sh2->r[n];
  1425. WL( sh2, sh2->ea, sh2->vbr );
  1426. sh2->icount--;
  1427. }
  1428. /* STS MACH,Rn */
  1429. INLINE void STSMACH(sh2_state *sh2, UINT32 n)
  1430. {
  1431. sh2->r[n] = sh2->mach;
  1432. }
  1433. /* STS MACL,Rn */
  1434. INLINE void STSMACL(sh2_state *sh2, UINT32 n)
  1435. {
  1436. sh2->r[n] = sh2->macl;
  1437. }
  1438. /* STS PR,Rn */
  1439. INLINE void STSPR(sh2_state *sh2, UINT32 n)
  1440. {
  1441. sh2->r[n] = sh2->pr;
  1442. }
  1443. /* STS.L MACH,@-Rn */
  1444. INLINE void STSMMACH(sh2_state *sh2, UINT32 n)
  1445. {
  1446. sh2->r[n] -= 4;
  1447. sh2->ea = sh2->r[n];
  1448. WL( sh2, sh2->ea, sh2->mach );
  1449. }
  1450. /* STS.L MACL,@-Rn */
  1451. INLINE void STSMMACL(sh2_state *sh2, UINT32 n)
  1452. {
  1453. sh2->r[n] -= 4;
  1454. sh2->ea = sh2->r[n];
  1455. WL( sh2, sh2->ea, sh2->macl );
  1456. }
  1457. /* STS.L PR,@-Rn */
  1458. INLINE void STSMPR(sh2_state *sh2, UINT32 n)
  1459. {
  1460. sh2->r[n] -= 4;
  1461. sh2->ea = sh2->r[n];
  1462. WL( sh2, sh2->ea, sh2->pr );
  1463. }
  1464. /* SUB Rm,Rn */
  1465. INLINE void SUB(sh2_state *sh2, UINT32 m, UINT32 n)
  1466. {
  1467. sh2->r[n] -= sh2->r[m];
  1468. }
  1469. /* SUBC Rm,Rn */
  1470. INLINE void SUBC(sh2_state *sh2, UINT32 m, UINT32 n)
  1471. {
  1472. UINT32 tmp0, tmp1;
  1473. tmp1 = sh2->r[n] - sh2->r[m];
  1474. tmp0 = sh2->r[n];
  1475. sh2->r[n] = tmp1 - (sh2->sr & T);
  1476. if (tmp0 < tmp1)
  1477. sh2->sr |= T;
  1478. else
  1479. sh2->sr &= ~T;
  1480. if (tmp1 < sh2->r[n])
  1481. sh2->sr |= T;
  1482. }
  1483. /* SUBV Rm,Rn */
  1484. INLINE void SUBV(sh2_state *sh2, UINT32 m, UINT32 n)
  1485. {
  1486. INT32 dest, src, ans;
  1487. if ((INT32) sh2->r[n] >= 0)
  1488. dest = 0;
  1489. else
  1490. dest = 1;
  1491. if ((INT32) sh2->r[m] >= 0)
  1492. src = 0;
  1493. else
  1494. src = 1;
  1495. src += dest;
  1496. sh2->r[n] -= sh2->r[m];
  1497. if ((INT32) sh2->r[n] >= 0)
  1498. ans = 0;
  1499. else
  1500. ans = 1;
  1501. ans += dest;
  1502. if (src == 1)
  1503. {
  1504. if (ans == 1)
  1505. sh2->sr |= T;
  1506. else
  1507. sh2->sr &= ~T;
  1508. }
  1509. else
  1510. sh2->sr &= ~T;
  1511. }
  1512. /* SWAP.B Rm,Rn */
  1513. INLINE void SWAPB(sh2_state *sh2, UINT32 m, UINT32 n)
  1514. {
  1515. UINT32 temp0, temp1;
  1516. temp0 = sh2->r[m] & 0xffff0000;
  1517. temp1 = (sh2->r[m] & 0x000000ff) << 8;
  1518. sh2->r[n] = (sh2->r[m] >> 8) & 0x000000ff;
  1519. sh2->r[n] = sh2->r[n] | temp1 | temp0;
  1520. }
  1521. /* SWAP.W Rm,Rn */
  1522. INLINE void SWAPW(sh2_state *sh2, UINT32 m, UINT32 n)
  1523. {
  1524. UINT32 temp;
  1525. temp = (sh2->r[m] >> 16) & 0x0000ffff;
  1526. sh2->r[n] = (sh2->r[m] << 16) | temp;
  1527. }
  1528. /* TAS.B @Rn */
  1529. INLINE void TAS(sh2_state *sh2, UINT32 n)
  1530. {
  1531. UINT32 temp;
  1532. sh2->ea = sh2->r[n];
  1533. /* Bus Lock enable */
  1534. temp = RB( sh2, sh2->ea );
  1535. if (temp == 0)
  1536. sh2->sr |= T;
  1537. else
  1538. sh2->sr &= ~T;
  1539. temp |= 0x80;
  1540. /* Bus Lock disable */
  1541. WB( sh2, sh2->ea, temp );
  1542. sh2->icount -= 3;
  1543. }
  1544. /* TRAPA #imm */
  1545. INLINE void TRAPA(sh2_state *sh2, UINT32 i)
  1546. {
  1547. UINT32 imm = i & 0xff;
  1548. sh2->ea = sh2->vbr + imm * 4;
  1549. sh2->r[15] -= 4;
  1550. WL( sh2, sh2->r[15], sh2->sr );
  1551. sh2->r[15] -= 4;
  1552. WL( sh2, sh2->r[15], sh2->pc );
  1553. sh2->pc = RL( sh2, sh2->ea );
  1554. sh2->icount -= 7;
  1555. }
  1556. /* TST Rm,Rn */
  1557. INLINE void TST(sh2_state *sh2, UINT32 m, UINT32 n)
  1558. {
  1559. if ((sh2->r[n] & sh2->r[m]) == 0)
  1560. sh2->sr |= T;
  1561. else
  1562. sh2->sr &= ~T;
  1563. }
  1564. /* TST #imm,R0 */
  1565. INLINE void TSTI(sh2_state *sh2, UINT32 i)
  1566. {
  1567. UINT32 imm = i & 0xff;
  1568. if ((imm & sh2->r[0]) == 0)
  1569. sh2->sr |= T;
  1570. else
  1571. sh2->sr &= ~T;
  1572. }
  1573. /* TST.B #imm,@(R0,GBR) */
  1574. INLINE void TSTM(sh2_state *sh2, UINT32 i)
  1575. {
  1576. UINT32 imm = i & 0xff;
  1577. sh2->ea = sh2->gbr + sh2->r[0];
  1578. if ((imm & RB( sh2, sh2->ea )) == 0)
  1579. sh2->sr |= T;
  1580. else
  1581. sh2->sr &= ~T;
  1582. sh2->icount -= 2;
  1583. }
  1584. /* XOR Rm,Rn */
  1585. INLINE void XOR(sh2_state *sh2, UINT32 m, UINT32 n)
  1586. {
  1587. sh2->r[n] ^= sh2->r[m];
  1588. }
  1589. /* XOR #imm,R0 */
  1590. INLINE void XORI(sh2_state *sh2, UINT32 i)
  1591. {
  1592. UINT32 imm = i & 0xff;
  1593. sh2->r[0] ^= imm;
  1594. }
  1595. /* XOR.B #imm,@(R0,GBR) */
  1596. INLINE void XORM(sh2_state *sh2, UINT32 i)
  1597. {
  1598. UINT32 imm = i & 0xff;
  1599. UINT32 temp;
  1600. sh2->ea = sh2->gbr + sh2->r[0];
  1601. temp = RB( sh2, sh2->ea );
  1602. temp ^= imm;
  1603. WB( sh2, sh2->ea, temp );
  1604. sh2->icount -= 2;
  1605. }
  1606. /* XTRCT Rm,Rn */
  1607. INLINE void XTRCT(sh2_state *sh2, UINT32 m, UINT32 n)
  1608. {
  1609. UINT32 temp;
  1610. temp = (sh2->r[m] << 16) & 0xffff0000;
  1611. sh2->r[n] = (sh2->r[n] >> 16) & 0x0000ffff;
  1612. sh2->r[n] |= temp;
  1613. }
  1614. /*****************************************************************************
  1615. * OPCODE DISPATCHERS
  1616. *****************************************************************************/
  1617. INLINE void op0000(sh2_state *sh2, UINT16 opcode)
  1618. {
  1619. switch (opcode & 0x3F)
  1620. {
  1621. case 0x00: ILLEGAL(sh2); rlog(0); break;
  1622. case 0x01: ILLEGAL(sh2); rlog(0); break;
  1623. case 0x02: STCSR(sh2, Rn); rlog(LRN); break;
  1624. case 0x03: BSRF(sh2, Rn); rlog(LRN); break;
  1625. case 0x04: MOVBS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
  1626. case 0x05: MOVWS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
  1627. case 0x06: MOVLS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
  1628. case 0x07: MULL(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;
  1629. case 0x08: CLRT(sh2); rlog(0); break;
  1630. case 0x09: NOP(); rlog(0); break;
  1631. case 0x0a: STSMACH(sh2, Rn); rlog(LRN); rlog1(SHR_MACH); break;
  1632. case 0x0b: RTS(sh2); rlog(0); rlog1(SHR_PR); break;
  1633. case 0x0c: MOVBL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
  1634. case 0x0d: MOVWL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
  1635. case 0x0e: MOVLL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
  1636. case 0x0f: MAC_L(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
  1637. case 0x10: ILLEGAL(sh2); rlog(0); break;
  1638. case 0x11: ILLEGAL(sh2); rlog(0); break;
  1639. case 0x12: STCGBR(sh2, Rn); rlog(LRN); rlog1(SHR_GBR); break;
  1640. case 0x13: ILLEGAL(sh2); rlog(0); break;
  1641. case 0x14: MOVBS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
  1642. case 0x15: MOVWS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
  1643. case 0x16: MOVLS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
  1644. case 0x17: MULL(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;
  1645. case 0x18: SETT(sh2); rlog(0); break;
  1646. case 0x19: DIV0U(sh2); rlog(0); break;
  1647. case 0x1a: STSMACL(sh2, Rn); rlog(LRN); rlog1(SHR_MACL); break;
  1648. case 0x1b: SLEEP(sh2); rlog(0); break;
  1649. case 0x1c: MOVBL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
  1650. case 0x1d: MOVWL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
  1651. case 0x1e: MOVLL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
  1652. case 0x1f: MAC_L(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
  1653. case 0x20: ILLEGAL(sh2); rlog(0); break;
  1654. case 0x21: ILLEGAL(sh2); rlog(0); break;
  1655. case 0x22: STCVBR(sh2, Rn); rlog(LRN); rlog1(SHR_VBR); break;
  1656. case 0x23: BRAF(sh2, Rn); rlog(LRN); break;
  1657. case 0x24: MOVBS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
  1658. case 0x25: MOVWS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
  1659. case 0x26: MOVLS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
  1660. case 0x27: MULL(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;
  1661. case 0x28: CLRMAC(sh2); rlog(0); rlog2(SHR_MACL,SHR_MACH); break;
  1662. case 0x29: MOVT(sh2, Rn); rlog(LRN); break;
  1663. case 0x2a: STSPR(sh2, Rn); rlog(LRN); rlog1(SHR_PR); break;
  1664. case 0x2b: RTE(sh2); rlog(0); break;
  1665. case 0x2c: MOVBL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
  1666. case 0x2d: MOVWL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
  1667. case 0x2e: MOVLL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
  1668. case 0x2f: MAC_L(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
  1669. case 0x30: ILLEGAL(sh2); rlog(0); break;
  1670. case 0x31: ILLEGAL(sh2); rlog(0); break;
  1671. case 0x32: ILLEGAL(sh2); rlog(0); break;
  1672. case 0x33: ILLEGAL(sh2); rlog(0); break;
  1673. case 0x34: MOVBS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
  1674. case 0x35: MOVWS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
  1675. case 0x36: MOVLS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
  1676. case 0x37: MULL(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;
  1677. case 0x38: ILLEGAL(sh2); rlog(0); break;
  1678. case 0x39: ILLEGAL(sh2); rlog(0); break;
  1679. case 0x3c: MOVBL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
  1680. case 0x3d: MOVWL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
  1681. case 0x3e: MOVLL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
  1682. case 0x3f: MAC_L(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
  1683. case 0x3a: ILLEGAL(sh2); rlog(0); break;
  1684. case 0x3b: ILLEGAL(sh2); rlog(0); break;
  1685. }
  1686. }
  1687. INLINE void op0001(sh2_state *sh2, UINT16 opcode)
  1688. {
  1689. MOVLS4(sh2, Rm, opcode & 0x0f, Rn);
  1690. rlog(LRNM);
  1691. }
  1692. INLINE void op0010(sh2_state *sh2, UINT16 opcode)
  1693. {
  1694. switch (opcode & 15)
  1695. {
  1696. case 0: MOVBS(sh2, Rm, Rn); rlog(LRNM); break;
  1697. case 1: MOVWS(sh2, Rm, Rn); rlog(LRNM); break;
  1698. case 2: MOVLS(sh2, Rm, Rn); rlog(LRNM); break;
  1699. case 3: ILLEGAL(sh2); rlog(0); break;
  1700. case 4: MOVBM(sh2, Rm, Rn); rlog(LRNM); break;
  1701. case 5: MOVWM(sh2, Rm, Rn); rlog(LRNM); break;
  1702. case 6: MOVLM(sh2, Rm, Rn); rlog(LRNM); break;
  1703. case 7: DIV0S(sh2, Rm, Rn); rlog(LRNM); break;
  1704. case 8: TST(sh2, Rm, Rn); rlog(LRNM); break;
  1705. case 9: AND(sh2, Rm, Rn); rlog(LRNM); break;
  1706. case 10: XOR(sh2, Rm, Rn); rlog(LRNM); break;
  1707. case 11: OR(sh2, Rm, Rn); rlog(LRNM); break;
  1708. case 12: CMPSTR(sh2, Rm, Rn); rlog(LRNM); break;
  1709. case 13: XTRCT(sh2, Rm, Rn); rlog(LRNM); break;
  1710. case 14: MULU(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;
  1711. case 15: MULS(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;
  1712. }
  1713. }
  1714. INLINE void op0011(sh2_state *sh2, UINT16 opcode)
  1715. {
  1716. switch (opcode & 15)
  1717. {
  1718. case 0: CMPEQ(sh2, Rm, Rn); rlog(LRNM); break;
  1719. case 1: ILLEGAL(sh2); rlog(0); break;
  1720. case 2: CMPHS(sh2, Rm, Rn); rlog(LRNM); break;
  1721. case 3: CMPGE(sh2, Rm, Rn); rlog(LRNM); break;
  1722. case 4: DIV1(sh2, Rm, Rn); rlog(LRNM); break;
  1723. case 5: DMULU(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
  1724. case 6: CMPHI(sh2, Rm, Rn); rlog(LRNM); break;
  1725. case 7: CMPGT(sh2, Rm, Rn); rlog(LRNM); break;
  1726. case 8: SUB(sh2, Rm, Rn); rlog(LRNM); break;
  1727. case 9: ILLEGAL(sh2); rlog(0); break;
  1728. case 10: SUBC(sh2, Rm, Rn); rlog(LRNM); break;
  1729. case 11: SUBV(sh2, Rm, Rn); rlog(LRNM); break;
  1730. case 12: ADD(sh2, Rm, Rn); rlog(LRNM); break;
  1731. case 13: DMULS(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
  1732. case 14: ADDC(sh2, Rm, Rn); rlog(LRNM); break;
  1733. case 15: ADDV(sh2, Rm, Rn); rlog(LRNM); break;
  1734. }
  1735. }
  1736. INLINE void op0100(sh2_state *sh2, UINT16 opcode)
  1737. {
  1738. switch (opcode & 0x3F)
  1739. {
  1740. case 0x00: SHLL(sh2, Rn); rlog(LRN); break;
  1741. case 0x01: SHLR(sh2, Rn); rlog(LRN); break;
  1742. case 0x02: STSMMACH(sh2, Rn); rlog(LRN); rlog1(SHR_MACH); break;
  1743. case 0x03: STCMSR(sh2, Rn); rlog(LRN); break;
  1744. case 0x04: ROTL(sh2, Rn); rlog(LRN); break;
  1745. case 0x05: ROTR(sh2, Rn); rlog(LRN); break;
  1746. case 0x06: LDSMMACH(sh2, Rn); rlog(LRN); rlog1(SHR_MACH); break;
  1747. case 0x07: LDCMSR(sh2, Rn); rlog(LRN); break;
  1748. case 0x08: SHLL2(sh2, Rn); rlog(LRN); break;
  1749. case 0x09: SHLR2(sh2, Rn); rlog(LRN); break;
  1750. case 0x0a: LDSMACH(sh2, Rn); rlog(LRN); rlog1(SHR_MACH); break;
  1751. case 0x0b: JSR(sh2, Rn); rlog(LRN); rlog1(SHR_PR); break;
  1752. case 0x0c: ILLEGAL(sh2); rlog(0); break;
  1753. case 0x0d: ILLEGAL(sh2); rlog(0); break;
  1754. case 0x0e: LDCSR(sh2, Rn); rlog(LRN); break;
  1755. case 0x0f: MAC_W(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
  1756. case 0x10: DT(sh2, Rn); rlog(LRN); break;
  1757. case 0x11: CMPPZ(sh2, Rn); rlog(LRN); break;
  1758. case 0x12: STSMMACL(sh2, Rn); rlog(LRN); rlog1(SHR_MACL); break;
  1759. case 0x13: STCMGBR(sh2, Rn); rlog(LRN); rlog1(SHR_GBR); break;
  1760. case 0x14: ILLEGAL(sh2); rlog(0); break;
  1761. case 0x15: CMPPL(sh2, Rn); rlog(LRN); break;
  1762. case 0x16: LDSMMACL(sh2, Rn); rlog(LRN); rlog1(SHR_MACL); break;
  1763. case 0x17: LDCMGBR(sh2, Rn); rlog(LRN); rlog1(SHR_GBR); break;
  1764. case 0x18: SHLL8(sh2, Rn); rlog(LRN); break;
  1765. case 0x19: SHLR8(sh2, Rn); rlog(LRN); break;
  1766. case 0x1a: LDSMACL(sh2, Rn); rlog(LRN); rlog1(SHR_MACL); break;
  1767. case 0x1b: TAS(sh2, Rn); rlog(LRN); break;
  1768. case 0x1c: ILLEGAL(sh2); rlog(0); break;
  1769. case 0x1d: ILLEGAL(sh2); rlog(0); break;
  1770. case 0x1e: LDCGBR(sh2, Rn); rlog(LRN); rlog1(SHR_GBR); break;
  1771. case 0x1f: MAC_W(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
  1772. case 0x20: SHAL(sh2, Rn); rlog(LRN); break;
  1773. case 0x21: SHAR(sh2, Rn); rlog(LRN); break;
  1774. case 0x22: STSMPR(sh2, Rn); rlog(LRN); rlog1(SHR_PR); break;
  1775. case 0x23: STCMVBR(sh2, Rn); rlog(LRN); rlog1(SHR_VBR); break;
  1776. case 0x24: ROTCL(sh2, Rn); rlog(LRN); break;
  1777. case 0x25: ROTCR(sh2, Rn); rlog(LRN); break;
  1778. case 0x26: LDSMPR(sh2, Rn); rlog(LRN); rlog1(SHR_PR); break;
  1779. case 0x27: LDCMVBR(sh2, Rn); rlog(LRN); rlog1(SHR_VBR); break;
  1780. case 0x28: SHLL16(sh2, Rn); rlog(LRN); break;
  1781. case 0x29: SHLR16(sh2, Rn); rlog(LRN); break;
  1782. case 0x2a: LDSPR(sh2, Rn); rlog(LRN); rlog1(SHR_PR); break;
  1783. case 0x2b: JMP(sh2, Rn); rlog(LRN); break;
  1784. case 0x2c: ILLEGAL(sh2); rlog(0); break;
  1785. case 0x2d: ILLEGAL(sh2); rlog(0); break;
  1786. case 0x2e: LDCVBR(sh2, Rn); rlog(LRN); rlog1(SHR_VBR); break;
  1787. case 0x2f: MAC_W(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
  1788. case 0x30:
  1789. case 0x31:
  1790. case 0x32:
  1791. case 0x33:
  1792. case 0x34:
  1793. case 0x35:
  1794. case 0x36:
  1795. case 0x37:
  1796. case 0x38:
  1797. case 0x39:
  1798. case 0x3a:
  1799. case 0x3b:
  1800. case 0x3c:
  1801. case 0x3d:
  1802. case 0x3e: ILLEGAL(sh2); rlog(0); break;
  1803. case 0x3f: MAC_W(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
  1804. }
  1805. }
  1806. INLINE void op0101(sh2_state *sh2, UINT16 opcode)
  1807. {
  1808. MOVLL4(sh2, Rm, opcode & 0x0f, Rn);
  1809. rlog(LRNM);
  1810. }
  1811. INLINE void op0110(sh2_state *sh2, UINT16 opcode)
  1812. {
  1813. switch (opcode & 15)
  1814. {
  1815. case 0: MOVBL(sh2, Rm, Rn); break;
  1816. case 1: MOVWL(sh2, Rm, Rn); break;
  1817. case 2: MOVLL(sh2, Rm, Rn); break;
  1818. case 3: MOV(sh2, Rm, Rn); break;
  1819. case 4: MOVBP(sh2, Rm, Rn); break;
  1820. case 5: MOVWP(sh2, Rm, Rn); break;
  1821. case 6: MOVLP(sh2, Rm, Rn); break;
  1822. case 7: NOT(sh2, Rm, Rn); break;
  1823. case 8: SWAPB(sh2, Rm, Rn); break;
  1824. case 9: SWAPW(sh2, Rm, Rn); break;
  1825. case 10: NEGC(sh2, Rm, Rn); break;
  1826. case 11: NEG(sh2, Rm, Rn); break;
  1827. case 12: EXTUB(sh2, Rm, Rn); break;
  1828. case 13: EXTUW(sh2, Rm, Rn); break;
  1829. case 14: EXTSB(sh2, Rm, Rn); break;
  1830. case 15: EXTSW(sh2, Rm, Rn); break;
  1831. }
  1832. rlog(LRNM);
  1833. }
  1834. INLINE void op0111(sh2_state *sh2, UINT16 opcode)
  1835. {
  1836. ADDI(sh2, opcode & 0xff, Rn);
  1837. rlog(LRN);
  1838. }
  1839. INLINE void op1000(sh2_state *sh2, UINT16 opcode)
  1840. {
  1841. switch ( opcode & (15<<8) )
  1842. {
  1843. case 0<< 8: MOVBS4(sh2, opcode & 0x0f, Rm); rlog(LRM); rlog1(0); break;
  1844. case 1<< 8: MOVWS4(sh2, opcode & 0x0f, Rm); rlog(LRM); rlog1(0); break;
  1845. case 2<< 8: ILLEGAL(sh2); rlog(0); break;
  1846. case 3<< 8: ILLEGAL(sh2); rlog(0); break;
  1847. case 4<< 8: MOVBL4(sh2, Rm, opcode & 0x0f); rlog(LRM); rlog1(0); break;
  1848. case 5<< 8: MOVWL4(sh2, Rm, opcode & 0x0f); rlog(LRM); rlog1(0); break;
  1849. case 6<< 8: ILLEGAL(sh2); rlog(0); break;
  1850. case 7<< 8: ILLEGAL(sh2); rlog(0); break;
  1851. case 8<< 8: CMPIM(sh2, opcode & 0xff); rlog(0); rlog1(0); break;
  1852. case 9<< 8: BT(sh2, opcode & 0xff); rlog(0); break;
  1853. case 10<< 8: ILLEGAL(sh2); rlog(0); break;
  1854. case 11<< 8: BF(sh2, opcode & 0xff); rlog(0); break;
  1855. case 12<< 8: ILLEGAL(sh2); rlog(0); break;
  1856. case 13<< 8: BTS(sh2, opcode & 0xff); rlog(0); break;
  1857. case 14<< 8: ILLEGAL(sh2); rlog(0); break;
  1858. case 15<< 8: BFS(sh2, opcode & 0xff); rlog(0); break;
  1859. }
  1860. }
  1861. INLINE void op1001(sh2_state *sh2, UINT16 opcode)
  1862. {
  1863. MOVWI(sh2, opcode & 0xff, Rn);
  1864. rlog(LRN);
  1865. }
  1866. INLINE void op1010(sh2_state *sh2, UINT16 opcode)
  1867. {
  1868. BRA(sh2, opcode & 0xfff);
  1869. rlog(0);
  1870. }
  1871. INLINE void op1011(sh2_state *sh2, UINT16 opcode)
  1872. {
  1873. BSR(sh2, opcode & 0xfff);
  1874. rlog(0);
  1875. rlog1(SHR_PR);
  1876. }
  1877. INLINE void op1100(sh2_state *sh2, UINT16 opcode)
  1878. {
  1879. switch (opcode & (15<<8))
  1880. {
  1881. case 0<<8: MOVBSG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;
  1882. case 1<<8: MOVWSG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;
  1883. case 2<<8: MOVLSG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;
  1884. case 3<<8: TRAPA(sh2, opcode & 0xff); rlog1(SHR_VBR); break;
  1885. case 4<<8: MOVBLG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;
  1886. case 5<<8: MOVWLG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;
  1887. case 6<<8: MOVLLG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;
  1888. case 7<<8: MOVA(sh2, opcode & 0xff); rlog1(0); break;
  1889. case 8<<8: TSTI(sh2, opcode & 0xff); rlog1(0); break;
  1890. case 9<<8: ANDI(sh2, opcode & 0xff); rlog1(0); break;
  1891. case 10<<8: XORI(sh2, opcode & 0xff); rlog1(0); break;
  1892. case 11<<8: ORI(sh2, opcode & 0xff); rlog1(0); break;
  1893. case 12<<8: TSTM(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;
  1894. case 13<<8: ANDM(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;
  1895. case 14<<8: XORM(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;
  1896. case 15<<8: ORM(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;
  1897. }
  1898. rlog(0);
  1899. }
  1900. INLINE void op1101(sh2_state *sh2, UINT16 opcode)
  1901. {
  1902. MOVLI(sh2, opcode & 0xff, Rn);
  1903. rlog(LRN);
  1904. }
  1905. INLINE void op1110(sh2_state *sh2, UINT16 opcode)
  1906. {
  1907. MOVI(sh2, opcode & 0xff, Rn);
  1908. rlog(LRN);
  1909. }
  1910. INLINE void op1111(sh2_state *sh2, UINT16 opcode)
  1911. {
  1912. ILLEGAL(sh2);
  1913. rlog(0);
  1914. }
  1915. #endif