compiler.h 2.0 KB

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  1. int sh2_drc_init(SH2 *sh2);
  2. void sh2_drc_finish(SH2 *sh2);
  3. void sh2_drc_wcheck_ram(unsigned int a, unsigned len, SH2 *sh2);
  4. void sh2_drc_wcheck_da(unsigned int a, unsigned len, SH2 *sh2);
  5. #ifdef DRC_SH2
  6. void sh2_drc_mem_setup(SH2 *sh2);
  7. void sh2_drc_flush_all(void);
  8. void sh2_drc_frame(void);
  9. #else
  10. #define sh2_drc_mem_setup(x)
  11. #define sh2_drc_flush_all()
  12. #define sh2_drc_frame()
  13. #endif
  14. #define BLOCK_INSN_LIMIT 1024
  15. /* op_flags */
  16. #define OF_DELAY_OP (1 << 0)
  17. #define OF_BTARGET (1 << 1)
  18. #define OF_LOOP (3 << 2) // NONE, IDLE, DELAY, POLL loop
  19. #define OF_B_IN_DS (1 << 4)
  20. #define OF_DELAY_INSN (1 << 5) // DT, (TODO ADD+CMP?)
  21. #define OF_POLL_INSN (1 << 6) // MOV @(...),Rn (no post increment), TST @(...)
  22. #define OF_BASIC_LOOP (1 << 7) // pinnable loop without any branches in it
  23. #define OF_IDLE_LOOP (1 << 2)
  24. #define OF_DELAY_LOOP (2 << 2)
  25. #define OF_POLL_LOOP (3 << 2)
  26. unsigned short scan_block(unsigned int base_pc, int is_slave,
  27. unsigned char *op_flags, unsigned int *end_pc,
  28. unsigned int *base_literals, unsigned int *end_literals);
  29. #if defined(DRC_SH2)
  30. // direct access to some host CPU registers used by the DRC
  31. // XXX MUST match definitions for SHR_SR in cpu/sh2/compiler.c
  32. #if defined(__arm__)
  33. #define DRC_SR_REG "r10"
  34. #elif defined(__aarch64__)
  35. #define DRC_SR_REG "r28"
  36. #elif defined(__mips__)
  37. #define DRC_SR_REG "s6"
  38. #elif defined(__riscv__) || defined(__riscv)
  39. #define DRC_SR_REG "s11"
  40. #elif defined(__i386__)
  41. #define DRC_SR_REG "edi"
  42. #elif defined(__x86_64__)
  43. #define DRC_SR_REG "ebx"
  44. #else
  45. #warning "direct DRC register access not available for this host"
  46. #endif
  47. #endif
  48. #ifdef DRC_SR_REG
  49. #define DRC_DECLARE_SR register int sh2_sr asm(DRC_SR_REG)
  50. #define DRC_SAVE_SR(sh2) \
  51. if ((sh2->state & (SH2_STATE_RUN|SH2_STATE_SLEEP)) == SH2_STATE_RUN) \
  52. sh2->sr = sh2_sr;
  53. #define DRC_RESTORE_SR(sh2) \
  54. if ((sh2->state & (SH2_STATE_RUN|SH2_STATE_SLEEP)) == SH2_STATE_RUN) \
  55. sh2_sr = sh2->sr;
  56. #else
  57. #define DRC_DECLARE_SR
  58. #define DRC_SAVE_SR(sh2)
  59. #define DRC_RESTORE_SR(sh2)
  60. #endif