emit_arm64.c 40 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388
  1. /*
  2. * Basic macros to emit ARM A64 instructions and some utils
  3. * Copyright (C) 2019 kub
  4. *
  5. * This work is licensed under the terms of MAME license.
  6. * See COPYING file in the top-level directory.
  7. */
  8. #define HOST_REGS 32
  9. // AAPCS64: params: r0-r7, return: r0-r1, temp: r8-r17, saved: r19-r29
  10. // reserved: r18 (for platform use)
  11. #define RET_REG 0
  12. #define PARAM_REGS { 0, 1, 2, 3, 4, 5, 6, 7 }
  13. #define PRESERVED_REGS { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29 }
  14. #define TEMPORARY_REGS { 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 }
  15. #define CONTEXT_REG 29
  16. #define STATIC_SH2_REGS { SHR_SR,28 , SHR_R0,27 , SHR_R0+1,26 }
  17. // R31 doesn't exist, it aliases either with zero or SP
  18. #define SP 31 // stack pointer
  19. #define Z0 31 // zero register
  20. #define LR 30 // link register
  21. #define FP 29 // frame pointer
  22. #define PR 18 // platform register
  23. // All operations but ptr ops are using the lower 32 bits of the A64 registers.
  24. // The upper 32 bits are only used in ptr ops.
  25. #define A64_COND_EQ 0x0
  26. #define A64_COND_NE 0x1
  27. #define A64_COND_HS 0x2
  28. #define A64_COND_LO 0x3
  29. #define A64_COND_MI 0x4
  30. #define A64_COND_PL 0x5
  31. #define A64_COND_VS 0x6
  32. #define A64_COND_VC 0x7
  33. #define A64_COND_HI 0x8
  34. #define A64_COND_LS 0x9
  35. #define A64_COND_GE 0xa
  36. #define A64_COND_LT 0xb
  37. #define A64_COND_GT 0xc
  38. #define A64_COND_LE 0xd
  39. #define A64_COND_CS A64_COND_HS
  40. #define A64_COND_CC A64_COND_LO
  41. #define A64_COND_AL 0xe
  42. #define A64_COND_NV 0xf
  43. /* unified conditions */
  44. #define DCOND_EQ A64_COND_EQ
  45. #define DCOND_NE A64_COND_NE
  46. #define DCOND_MI A64_COND_MI
  47. #define DCOND_PL A64_COND_PL
  48. #define DCOND_HI A64_COND_HI
  49. #define DCOND_HS A64_COND_HS
  50. #define DCOND_LO A64_COND_LO
  51. #define DCOND_GE A64_COND_GE
  52. #define DCOND_GT A64_COND_GT
  53. #define DCOND_LT A64_COND_LT
  54. #define DCOND_LS A64_COND_LS
  55. #define DCOND_LE A64_COND_LE
  56. #define DCOND_VS A64_COND_VS
  57. #define DCOND_VC A64_COND_VC
  58. #define DCOND_CS A64_COND_HS
  59. #define DCOND_CC A64_COND_LO
  60. // unified insn
  61. #define A64_INSN(op, b29, b22, b21, b16, b12, b10, b5, b0) \
  62. (((op)<<25)|((b29)<<29)|((b22)<<22)|((b21)<<21)|((b16)<<16)|((b12)<<12)|((b10)<<10)|((b5)<<5)|((b0)<<0))
  63. #define _ 0 // marker for "field unused"
  64. #define A64_NOP \
  65. A64_INSN(0xa,0x6,0x4,_,0x3,0x2,_,0,0x1f) // 0xd503201f
  66. // arithmetic/logical
  67. enum { OP_AND, OP_OR, OP_EOR, OP_ANDS, OP_ADD, OP_ADDS, OP_SUB, OP_SUBS };
  68. enum { ST_LSL, ST_LSR, ST_ASR, ST_ROR };
  69. enum { XT_UXTW=0x4, XT_UXTX=0x6, XT_LSL=0x7, XT_SXTW=0xc, XT_SXTX=0xe };
  70. #define OP_SZ64 (1 << 31) // bit for 64 bit op selection
  71. #define OP_N64 (1 << 22) // N-bit for 64 bit logical immediate ops
  72. #define A64_OP_REG(op, n, rd, rn, rm, stype, simm) /* arith+logical, ST_ */ \
  73. A64_INSN(0x5,(op)&3,((op)&4)|stype,n,rm,_,simm,rn,rd)
  74. #define A64_OP_XREG(op, rd, rn, rm, xtopt, simm) /* arith, XT_ */ \
  75. A64_INSN(0x5,(op)&3,0x4,1,rm,xtopt,simm,rn,rd)
  76. #define A64_OP_IMM12(op, rd, rn, imm, lsl12) /* arith */ \
  77. A64_INSN(0x8,(op)&3,((op)&4)|lsl12,_,_,_,(imm)&0xfff,rn,rd)
  78. #define A64_OP_IMMBM(op, rd, rn, immr, imms) /* logical */ \
  79. A64_INSN(0x9,(op)&3,0x0,_,immr,_,(imms)&0x3f,rn,rd)
  80. // rd = rn OP (rm SHIFT simm)
  81. #define A64_ADD_REG(rd, rn, rm, stype, simm) \
  82. A64_OP_REG(OP_ADD,0,rd,rn,rm,stype,simm)
  83. #define A64_ADDS_REG(rd, rn, rm, stype, simm) \
  84. A64_OP_REG(OP_ADDS,0,rd,rn,rm,stype,simm)
  85. #define A64_SUB_REG(rd, rn, rm, stype, simm) \
  86. A64_OP_REG(OP_SUB,0,rd,rn,rm,stype,simm)
  87. #define A64_SUBS_REG(rd, rn, rm, stype, simm) \
  88. A64_OP_REG(OP_SUBS,0,rd,rn,rm,stype,simm)
  89. #define A64_NEG_REG(rd, rm, stype, simm) \
  90. A64_SUB_REG(rd,Z0,rm,stype,simm)
  91. #define A64_NEGS_REG(rd, rm, stype, simm) \
  92. A64_SUBS_REG(rd,Z0,rm,stype,simm)
  93. #define A64_NEGC_REG(rd, rm) \
  94. A64_SBC_REG(rd,Z0,rm)
  95. #define A64_NEGCS_REG(rd, rm) \
  96. A64_SBCS_REG(rd,Z0,rm)
  97. #define A64_CMP_REG(rn, rm, stype, simm) \
  98. A64_SUBS_REG(Z0, rn, rm, stype, simm)
  99. #define A64_CMN_REG(rn, rm, stype, simm) \
  100. A64_ADDS_REG(Z0, rn, rm, stype, simm)
  101. #define A64_EOR_REG(rd, rn, rm, stype, simm) \
  102. A64_OP_REG(OP_EOR,0,rd,rn,rm,stype,simm)
  103. #define A64_OR_REG(rd, rn, rm, stype, simm) \
  104. A64_OP_REG(OP_OR,0,rd,rn,rm,stype,simm)
  105. #define A64_ORN_REG(rd, rn, rm, stype, simm) \
  106. A64_OP_REG(OP_OR,1,rd,rn,rm,stype,simm)
  107. #define A64_AND_REG(rd, rn, rm, stype, simm) \
  108. A64_OP_REG(OP_AND,0,rd,rn,rm,stype,simm)
  109. #define A64_ANDS_REG(rd, rn, rm, stype, simm) \
  110. A64_OP_REG(OP_ANDS,0,rd,rn,rm,stype,simm)
  111. #define A64_BIC_REG(rd, rn, rm, stype, simm) \
  112. A64_OP_REG(OP_AND,1,rd,rn,rm,stype,simm)
  113. #define A64_BICS_REG(rd, rn, rm, stype, simm) \
  114. A64_OP_REG(OP_ANDS,1,rd,rn,rm,stype,simm)
  115. #define A64_TST_REG(rn, rm, stype, simm) \
  116. A64_ANDS_REG(Z0, rn, rm, stype, simm)
  117. #define A64_MOV_REG(rd, rm, stype, simm) \
  118. A64_OR_REG(rd, Z0, rm, stype, simm)
  119. #define A64_MVN_REG(rd, rm, stype, simm) \
  120. A64_ORN_REG(rd, Z0, rm, stype, simm)
  121. // rd = rn OP (rm EXTEND simm)
  122. #define A64_ADD_XREG(rd, rn, rm, xtopt, simm) \
  123. A64_OP_XREG(OP_ADD,rd,rn,rm,xtopt,simm)
  124. #define A64_ADDS_XREG(rd, rn, rm, xtopt, simm) \
  125. A64_OP_XREG(OP_ADDS,rd,rn,rm,xtopt,simm)
  126. #define A64_SUB_XREG(rd, rn, rm, stype, simm) \
  127. A64_OP_XREG(OP_SUB,rd,rn,rm,xtopt,simm)
  128. #define A64_SUBS_XREG(rd, rn, rm, stype, simm) \
  129. A64_OP_XREG(OP_SUBS,rd,rn,rm,xtopt,simm)
  130. // rd = rn OP rm OP carry
  131. #define A64_ADC_REG(rd, rn, rm) \
  132. A64_INSN(0xd,OP_ADD &3,0x0,_,rm,_,_,rn,rd)
  133. #define A64_ADCS_REG(rd, rn, rm) \
  134. A64_INSN(0xd,OP_ADDS&3,0x0,_,rm,_,_,rn,rd)
  135. #define A64_SBC_REG(rd, rn, rm) \
  136. A64_INSN(0xd,OP_SUB &3,0x0,_,rm,_,_,rn,rd)
  137. #define A64_SBCS_REG(rd, rn, rm) \
  138. A64_INSN(0xd,OP_SUBS&3,0x0,_,rm,_,_,rn,rd)
  139. // rd = rn SHIFT rm
  140. #define A64_LSL_REG(rd, rn, rm) \
  141. A64_INSN(0xd,0x0,0x3,_,rm,_,0x8,rn,rd)
  142. #define A64_LSR_REG(rd, rn, rm) \
  143. A64_INSN(0xd,0x0,0x3,_,rm,_,0xa,rn,rd)
  144. #define A64_ASR_REG(rd, rn, rm) \
  145. A64_INSN(0xd,0x0,0x3,_,rm,_,0x9,rn,rd)
  146. #define A64_ROR_REG(rd, rn, rm) \
  147. A64_INSN(0xd,0x0,0x3,_,rm,_,0xb,rn,rd)
  148. // rd = REVERSE(rn)
  149. #define A64_RBIT_REG(rd, rn) \
  150. A64_INSN(0xd,0x2,0x3,_,_,_,_,rn,rd)
  151. // rd = rn OP (imm12 << (0|12))
  152. #define A64_ADD_IMM(rd, rn, imm12, lsl12) \
  153. A64_OP_IMM12(OP_ADD, rd, rn, imm12, lsl12)
  154. #define A64_ADDS_IMM(rd, rn, imm12, lsl12) \
  155. A64_OP_IMM12(OP_ADDS, rd, rn, imm12, lsl12)
  156. #define A64_SUB_IMM(rd, rn, imm12, lsl12) \
  157. A64_OP_IMM12(OP_SUB, rd, rn, imm12, lsl12)
  158. #define A64_SUBS_IMM(rd, rn, imm12, lsl12) \
  159. A64_OP_IMM12(OP_SUBS, rd, rn, imm12, lsl12)
  160. #define A64_CMP_IMM(rn, imm12, lsl12) \
  161. A64_SUBS_IMM(Z0,rn,imm12,lsl12)
  162. #define A64_CMN_IMM(rn, imm12, lsl12) \
  163. A64_ADDS_IMM(Z0,rn,imm12,lsl12)
  164. // rd = rn OP immbm; immbm is a repeated special pattern of 2^n bits length
  165. #define A64_EOR_IMM(rd, rn, immr, imms) \
  166. A64_OP_IMMBM(OP_EOR,rd,rn,immr,imms)
  167. #define A64_OR_IMM(rd, rn, immr, imms) \
  168. A64_OP_IMMBM(OP_OR,rd,rn,immr,imms)
  169. #define A64_AND_IMM(rd, rn, immr, imms) \
  170. A64_OP_IMMBM(OP_AND,rd,rn,immr,imms)
  171. #define A64_ANDS_IMM(rd, rn, immr, imms) \
  172. A64_OP_IMMBM(OP_ANDS,rd,rn,immr,imms)
  173. #define A64_TST_IMM(rn, immr, imms) \
  174. A64_OP_IMMBM(OP_ANDS,Z0,rn,immr,imms)
  175. #define A64_MOV_IMM(rd, rn, immr, imms) \
  176. A64_OP_IMMBM(OP_OR,rd,Z0,immr,imms)
  177. // rd = (imm16 << (0|16|32|48))
  178. #define A64_MOVN_IMM(rd, imm16, lsl16) \
  179. A64_INSN(0x9,0x0,0x2,lsl16,_,_,_,(imm16)&0xffff,rd)
  180. #define A64_MOVZ_IMM(rd, imm16, lsl16) \
  181. A64_INSN(0x9,0x2,0x2,lsl16,_,_,_,(imm16)&0xffff,rd)
  182. #define A64_MOVK_IMM(rd, imm16, lsl16) \
  183. A64_INSN(0x9,0x3,0x2,lsl16,_,_,_,(imm16)&0xffff,rd)
  184. #define A64_MOVT_IMM(rd, imm16, lsl16) \
  185. A64_INSN(0x9,0x3,0x2,lsl16,_,_,_,(imm16)&0xffff,rd)
  186. // rd = rn SHIFT imm6
  187. #define A64_LSL_IMM(rd, rn, bits) /* UBFM */ \
  188. A64_INSN(0x9,0x2,0x4,_,32-(bits),_,31-(bits),rn,rd)
  189. #define A64_LSR_IMM(rd, rn, bits) /* UBFM */ \
  190. A64_INSN(0x9,0x2,0x4,_,bits,_,31,rn,rd)
  191. #define A64_ASR_IMM(rd, rn, bits) /* SBFM */ \
  192. A64_INSN(0x9,0x0,0x4,_,bits,_,31,rn,rd)
  193. #define A64_ROR_IMM(rd, rn, bits) /* EXTR */ \
  194. A64_INSN(0x9,0x0,0x6,_,rn,_,bits,rn,rd)
  195. #define A64_SXT_IMM(rd, rn, bits) \
  196. A64_INSN(0x9,0x0,0x4,0,0,_,bits-1,rn,rd)
  197. #define A64_UXT_IMM(rd, rn, bits) \
  198. A64_INSN(0x9,0x2,0x4,0,0,_,bits-1,rn,rd)
  199. // multiplication
  200. #define A64_SMULL(rd, rn, rm) /* Xd = Wn*Wm (+ Xa) */ \
  201. A64_INSN(0xd,0x4,0x4,1,rm,_,Z0,rn,rd)
  202. #define A64_SMADDL(rd, rn, rm, ra) \
  203. A64_INSN(0xd,0x4,0x4,1,rm,_,ra,rn,rd)
  204. #define A64_UMULL(rd, rn, rm) \
  205. A64_INSN(0xd,0x4,0x6,1,rm,_,Z0,rn,rd)
  206. #define A64_UMADDL(rd, rn, rm, ra) \
  207. A64_INSN(0xd,0x4,0x6,1,rm,_,ra,rn,rd)
  208. #define A64_MUL(rd, rn, rm) /* Wd = Wn*Wm (+ Wa) */ \
  209. A64_INSN(0xd,0x0,0x4,0,rm,_,Z0,rn,rd)
  210. #define A64_MADD(rd, rn, rm, ra) \
  211. A64_INSN(0xd,0x0,0x4,0,rm,_,ra,rn,rd)
  212. // branching
  213. #define A64_B(offs26) \
  214. A64_INSN(0xa,0x0,_,_,_,_,_,_,(offs26) >> 2)
  215. #define A64_BL(offs26) \
  216. A64_INSN(0xa,0x4,_,_,_,_,_,_,(offs26) >> 2)
  217. #define A64_BR(rn) \
  218. A64_INSN(0xb,0x6,_,_,0x1f,_,_,rn,_)
  219. #define A64_BLR(rn) \
  220. A64_INSN(0xb,0x6,_,_,0x3f,_,_,rn,_)
  221. #define A64_RET(rn) /* same as BR, but hint for cpu */ \
  222. A64_INSN(0xb,0x6,_,_,0x5f,_,_,rn,_)
  223. #define A64_BCOND(cond, offs19) \
  224. A64_INSN(0xa,0x2,_,_,_,_,_,(offs19) >> 2,(cond))
  225. // load pc-relative
  226. #define A64_LDRLIT_IMM(rd, offs19) \
  227. A64_INSN(0xc,0x0,0x0,_,_,_,_,(offs19) >> 2,rd)
  228. #define A64_LDRXLIT_IMM(rd, offs19) \
  229. A64_INSN(0xc,0x2,0x0,_,_,_,_,(offs19) >> 2,rd)
  230. #define A64_ADRXLIT_IMM(rd, offs21) \
  231. A64_INSN(0x8,(offs21)&3,0x0,_,_,_,_,(offs21) >> 2,rd)
  232. // load/store indexed base. Only the signed unscaled variant is used here.
  233. enum { LT_ST, LT_LD, LT_LDSX, LT_LDS };
  234. enum { AM_B=0x1, AM_H=0x3, AM_W=0x5, AM_X=0x7 };
  235. enum { AM_IDX, AM_IDXPOST, AM_IDXREG, AM_IDXPRE };
  236. #define A64_LDST_AM(ir,rm,optimm) (((ir)<<9)|((rm)<<4)|((optimm)&0x1ff))
  237. #define A64_OP_LDST(sz, op, am, mode, rm, rd) \
  238. A64_INSN(0xc,sz,op,_,_,am,mode,rm,rd)
  239. #define A64_LDSTX_IMM(rd, rn, offs9, ld, mode) \
  240. A64_OP_LDST(AM_X,ld,A64_LDST_AM(0,_,offs9),mode,rn,rd)
  241. #define A64_LDST_IMM(rd, rn, offs9, ld, mode) \
  242. A64_OP_LDST(AM_W,ld,A64_LDST_AM(0,_,offs9),mode,rn,rd)
  243. #define A64_LDSTH_IMM(rd, rn, offs9, ld, mode) \
  244. A64_OP_LDST(AM_H,ld,A64_LDST_AM(0,_,offs9),mode,rn,rd)
  245. #define A64_LDSTB_IMM(rd, rn, offs9, ld, mode) \
  246. A64_OP_LDST(AM_B,ld,A64_LDST_AM(0,_,offs9),mode,rn,rd)
  247. // NB: pre/postindex isn't available with register offset
  248. #define A64_LDSTX_REG(rd, rn, rm, ld, opt) \
  249. A64_OP_LDST(AM_X,ld,A64_LDST_AM(1,rm,opt),AM_IDXREG,rn,rd)
  250. #define A64_LDST_REG(rd, rn, rm, ld, opt) \
  251. A64_OP_LDST(AM_W,ld,A64_LDST_AM(1,rm,opt),AM_IDXREG,rn,rd)
  252. #define A64_LDSTH_REG(rd, rn, rm, ld, opt) \
  253. A64_OP_LDST(AM_H,ld,A64_LDST_AM(1,rm,opt),AM_IDXREG,rn,rd)
  254. #define A64_LDSTB_REG(rd, rn, rm, ld, opt) \
  255. A64_OP_LDST(AM_B,ld,A64_LDST_AM(1,rm,opt),AM_IDXREG,rn,rd)
  256. #define A64_LDSTPX_IMM(rn, r1, r2, offs7, ld, mode) \
  257. A64_INSN(0x4,0x5,(mode<<1)|ld,_,_,(offs7)&0x3f8,r2,rn,r1)
  258. // 64 bit stuff for pointer handling
  259. #define A64_ADDX_XREG(rd, rn, rm, xtopt, simm) \
  260. OP_SZ64|A64_OP_XREG(OP_ADD,rd,rn,rm,xtopt,simm)
  261. #define A64_ADDX_REG(rd, rn, rm, stype, simm) \
  262. OP_SZ64|A64_ADD_REG(rd, rn, rm, stype, simm)
  263. #define A64_ADDXS_REG(rd, rn, rm, stype, simm) \
  264. OP_SZ64|A64_ADDS_REG(rd, rn, rm, stype, simm)
  265. #define A64_ORX_REG(rd, rn, rm, stype, simm) \
  266. OP_SZ64|A64_OR_REG(rd, rn, rm, stype, simm)
  267. #define A64_TSTX_REG(rn, rm, stype, simm) \
  268. OP_SZ64|A64_TST_REG(rn, rm, stype, simm)
  269. #define A64_MOVX_REG(rd, rm, stype, simm) \
  270. OP_SZ64|A64_MOV_REG(rd, rm, stype, simm)
  271. #define A64_ADDX_IMM(rd, rn, imm12) \
  272. OP_SZ64|A64_ADD_IMM(rd, rn, imm12, 0)
  273. #define A64_EORX_IMM(rd, rn, immr, imms) \
  274. OP_SZ64|OP_N64|A64_EOR_IMM(rd, rn, immr, imms)
  275. #define A64_UXTX_IMM(rd, rn, bits) \
  276. OP_SZ64|OP_N64|A64_UXT_IMM(rd, rn, bits)
  277. #define A64_LSRX_IMM(rd, rn, bits) \
  278. OP_SZ64|OP_N64|A64_LSR_IMM(rd, rn, bits)|(63<<10)
  279. // XXX: tcache_ptr type for SVP and SH2 compilers differs..
  280. #define EMIT_PTR(ptr, x) \
  281. do { \
  282. *(u32 *)(ptr) = x; \
  283. ptr = (void *)((u8 *)(ptr) + sizeof(u32)); \
  284. } while (0)
  285. #define EMIT(op) \
  286. do { \
  287. EMIT_PTR(tcache_ptr, op); \
  288. COUNT_OP; \
  289. } while (0)
  290. // if-then-else conditional execution helpers
  291. #define JMP_POS(ptr) { \
  292. ptr = tcache_ptr; \
  293. EMIT(A64_B(0)); \
  294. }
  295. #define JMP_EMIT(cond, ptr) { \
  296. u32 val_ = (u8 *)tcache_ptr - (u8 *)(ptr); \
  297. EMIT_PTR(ptr, A64_BCOND(cond, val_ & 0x001fffff)); \
  298. }
  299. #define JMP_EMIT_NC(ptr) { \
  300. u32 val_ = (u8 *)tcache_ptr - (u8 *)(ptr); \
  301. EMIT_PTR(ptr, A64_B(val_ & 0x0fffffff)); \
  302. }
  303. #define EMITH_JMP_START(cond) { \
  304. u8 *cond_ptr; \
  305. JMP_POS(cond_ptr)
  306. #define EMITH_JMP_END(cond) \
  307. JMP_EMIT(cond, cond_ptr); \
  308. }
  309. #define EMITH_JMP3_START(cond) { \
  310. u8 *cond_ptr, *else_ptr; \
  311. JMP_POS(cond_ptr)
  312. #define EMITH_JMP3_MID(cond) \
  313. JMP_POS(else_ptr); \
  314. JMP_EMIT(cond, cond_ptr);
  315. #define EMITH_JMP3_END() \
  316. JMP_EMIT_NC(else_ptr); \
  317. }
  318. #define EMITH_HINT_COND(cond) /**/
  319. // "simple" jump (no more then a few insns)
  320. // ARM32 will use conditional instructions here
  321. #define EMITH_SJMP_START EMITH_JMP_START
  322. #define EMITH_SJMP_END EMITH_JMP_END
  323. #define EMITH_SJMP3_START EMITH_JMP3_START
  324. #define EMITH_SJMP3_MID EMITH_JMP3_MID
  325. #define EMITH_SJMP3_END EMITH_JMP3_END
  326. #define EMITH_SJMP2_START(cond) \
  327. EMITH_SJMP3_START(cond)
  328. #define EMITH_SJMP2_MID(cond) \
  329. EMITH_SJMP3_MID(cond)
  330. #define EMITH_SJMP2_END(cond) \
  331. EMITH_SJMP3_END()
  332. // data processing, register
  333. #define emith_move_r_r_ptr(d, s) \
  334. EMIT(A64_MOVX_REG(d, s, ST_LSL, 0))
  335. #define emith_move_r_r_ptr_c(cond, d, s) \
  336. emith_move_r_r_ptr(d, s)
  337. #define emith_move_r_r(d, s) \
  338. EMIT(A64_MOV_REG(d, s, ST_LSL, 0))
  339. #define emith_move_r_r_c(cond, d, s) \
  340. emith_move_r_r(d, s)
  341. #define emith_mvn_r_r(d, s) \
  342. EMIT(A64_MVN_REG(d, s, ST_LSL, 0))
  343. #define emith_add_r_r_r_lsl_ptr(d, s1, s2, simm) do { \
  344. if (simm < 4) EMIT(A64_ADDX_XREG(d, s1, s2, XT_SXTW, simm)); \
  345. else EMIT(A64_ADDX_REG(d, s1, s2, ST_LSL, simm)); \
  346. } while (0)
  347. #define emith_add_r_r_r_lsl(d, s1, s2, simm) \
  348. EMIT(A64_ADD_REG(d, s1, s2, ST_LSL, simm))
  349. #define emith_addf_r_r_r_lsl(d, s1, s2, simm) \
  350. EMIT(A64_ADDS_REG(d, s1, s2, ST_LSL, simm))
  351. #define emith_addf_r_r_r_lsr(d, s1, s2, simm) \
  352. EMIT(A64_ADDS_REG(d, s1, s2, ST_LSR, simm))
  353. #define emith_adc_r_r_r_lsl(d, s1, s2, simm) \
  354. if (simm) { int _t = rcache_get_tmp(); \
  355. emith_lsl(_t, s2, simm); \
  356. emith_adc_r_r_r(d, s1, _t); \
  357. rcache_free_tmp(_t); \
  358. } else \
  359. emith_adc_r_r_r(d, s1, s2); \
  360. } while (0)
  361. #define emith_sbc_r_r_r_lsl(d, s1, s2, simm) \
  362. if (simm) { int _t = rcache_get_tmp(); \
  363. emith_lsl(_t, s2, simm); \
  364. emith_sbc_r_r_r(d, s1, _t); \
  365. rcache_free_tmp(_t); \
  366. } else \
  367. emith_sbc_r_r_r(d, s1, s2); \
  368. } while (0)
  369. #define emith_sub_r_r_r_lsl(d, s1, s2, simm) \
  370. EMIT(A64_SUB_REG(d, s1, s2, ST_LSL, simm))
  371. #define emith_subf_r_r_r_lsl(d, s1, s2, simm) \
  372. EMIT(A64_SUBS_REG(d, s1, s2, ST_LSL, simm))
  373. #define emith_or_r_r_r_lsl(d, s1, s2, simm) \
  374. EMIT(A64_OR_REG(d, s1, s2, ST_LSL, simm))
  375. #define emith_or_r_r_r_lsr(d, s1, s2, simm) \
  376. EMIT(A64_OR_REG(d, s1, s2, ST_LSR, simm))
  377. #define emith_eor_r_r_r_lsl(d, s1, s2, simm) \
  378. EMIT(A64_EOR_REG(d, s1, s2, ST_LSL, simm))
  379. #define emith_eor_r_r_r_lsr(d, s1, s2, simm) \
  380. EMIT(A64_EOR_REG(d, s1, s2, ST_LSR, simm))
  381. #define emith_and_r_r_r_lsl(d, s1, s2, simm) \
  382. EMIT(A64_AND_REG(d, s1, s2, ST_LSL, simm))
  383. #define emith_or_r_r_lsl(d, s, lslimm) \
  384. emith_or_r_r_r_lsl(d, d, s, lslimm)
  385. #define emith_or_r_r_lsr(d, s, lsrimm) \
  386. emith_or_r_r_r_lsr(d, d, s, lsrimm)
  387. #define emith_eor_r_r_lsl(d, s, lslimm) \
  388. emith_eor_r_r_r_lsl(d, d, s, lslimm)
  389. #define emith_eor_r_r_lsr(d, s, lsrimm) \
  390. emith_eor_r_r_r_lsr(d, d, s, lsrimm)
  391. #define emith_add_r_r_r(d, s1, s2) \
  392. emith_add_r_r_r_lsl(d, s1, s2, 0)
  393. #define emith_addf_r_r_r(d, s1, s2) \
  394. emith_addf_r_r_r_lsl(d, s1, s2, 0)
  395. #define emith_sub_r_r_r(d, s1, s2) \
  396. emith_sub_r_r_r_lsl(d, s1, s2, 0)
  397. #define emith_subf_r_r_r(d, s1, s2) \
  398. emith_subf_r_r_r_lsl(d, s1, s2, 0)
  399. #define emith_or_r_r_r(d, s1, s2) \
  400. emith_or_r_r_r_lsl(d, s1, s2, 0)
  401. #define emith_eor_r_r_r(d, s1, s2) \
  402. emith_eor_r_r_r_lsl(d, s1, s2, 0)
  403. #define emith_add_r_r_r_ptr(d, s1, s2) \
  404. emith_add_r_r_r_lsl_ptr(d, s1, s2, 0)
  405. #define emith_and_r_r_r(d, s1, s2) \
  406. emith_and_r_r_r_lsl(d, s1, s2, 0)
  407. #define emith_add_r_r_ptr(d, s) \
  408. emith_add_r_r_r_lsl_ptr(d, d, s, 0)
  409. #define emith_add_r_r(d, s) \
  410. emith_add_r_r_r(d, d, s)
  411. #define emith_sub_r_r(d, s) \
  412. emith_sub_r_r_r(d, d, s)
  413. #define emith_neg_r_r(d, s) \
  414. EMIT(A64_NEG_REG(d, s, ST_LSL, 0))
  415. #define emith_negc_r_r(d, s) \
  416. EMIT(A64_NEGC_REG(d, s))
  417. #define emith_adc_r_r_r(d, s1, s2) \
  418. EMIT(A64_ADC_REG(d, s1, s2))
  419. #define emith_adc_r_r(d, s) \
  420. EMIT(A64_ADC_REG(d, d, s))
  421. #define emith_adcf_r_r_r(d, s1, s2) \
  422. EMIT(A64_ADCS_REG(d, s1, s2))
  423. #define emith_sbc_r_r_r(d, s1, s2) \
  424. EMIT(A64_SBC_REG(d, s1, s2))
  425. #define emith_sbcf_r_r_r(d, s1, s2) \
  426. EMIT(A64_SBCS_REG(d, s1, s2))
  427. #define emith_and_r_r(d, s) \
  428. emith_and_r_r_r(d, d, s)
  429. #define emith_and_r_r_c(cond, d, s) \
  430. emith_and_r_r(d, s)
  431. #define emith_or_r_r(d, s) \
  432. emith_or_r_r_r(d, d, s)
  433. #define emith_eor_r_r(d, s) \
  434. emith_eor_r_r_r(d, d, s)
  435. #define emith_tst_r_r_ptr(d, s) \
  436. EMIT(A64_TSTX_REG(d, s, ST_LSL, 0))
  437. #define emith_tst_r_r(d, s) \
  438. EMIT(A64_TST_REG(d, s, ST_LSL, 0))
  439. #define emith_teq_r_r(d, s) do { \
  440. int _t = rcache_get_tmp(); \
  441. emith_eor_r_r_r(_t, d, s); \
  442. emith_cmp_r_imm(_t, 0); \
  443. rcache_free_tmp(_t); \
  444. } while (0)
  445. #define emith_cmp_r_r(d, s) \
  446. EMIT(A64_CMP_REG(d, s, ST_LSL, 0))
  447. #define emith_addf_r_r(d, s) \
  448. emith_addf_r_r_r(d, d, s)
  449. #define emith_subf_r_r(d, s) \
  450. emith_subf_r_r_r(d, d, s)
  451. #define emith_adcf_r_r(d, s) \
  452. emith_adcf_r_r_r(d, d, s)
  453. #define emith_sbcf_r_r(d, s) \
  454. emith_sbcf_r_r_r(d, d, s)
  455. #define emith_negcf_r_r(d, s) \
  456. emith_sbcf_r_r_r(d, Z0, s)
  457. // move immediate
  458. static void emith_move_imm64(int r, int wx, int64_t imm)
  459. {
  460. int sz64 = wx ? OP_SZ64:0;
  461. int c, s;
  462. if (!imm) {
  463. EMIT(sz64|A64_MOVZ_IMM(r, imm, 0));
  464. return;
  465. }
  466. if (imm && -imm == (u16)-imm) {
  467. EMIT(sz64|A64_MOVN_IMM(r, ~imm, 0));
  468. return;
  469. }
  470. for (c = s = 0; s < (wx ? 4:2) && imm; s++, imm >>= 16)
  471. if ((u16)(imm)) {
  472. if (c++) EMIT(sz64|A64_MOVK_IMM(r, imm, s));
  473. else EMIT(sz64|A64_MOVZ_IMM(r, imm, s));
  474. }
  475. }
  476. #define emith_move_r_ptr_imm(r, imm) \
  477. emith_move_imm64(r, 1, (intptr_t)(imm))
  478. #define emith_move_r_imm(r, imm) \
  479. emith_move_imm64(r, 0, (s32)(imm))
  480. #define emith_move_r_imm_c(cond, r, imm) \
  481. emith_move_r_imm(r, imm)
  482. #define emith_move_r_imm_s8_patchable(r, imm) do { \
  483. if ((s8)(imm) < 0) \
  484. EMIT(A64_MOVN_IMM(r, ~(s8)(imm), 0)); \
  485. else \
  486. EMIT(A64_MOVZ_IMM(r, (s8)(imm), 0)); \
  487. } while (0)
  488. #define emith_move_r_imm_s8_patch(ptr, imm) do { \
  489. u32 *ptr_ = (u32 *)ptr; \
  490. int r_ = *ptr_ & 0x1f; \
  491. if ((s8)(imm) < 0) \
  492. EMIT_PTR(ptr_, A64_MOVN_IMM(r_, ~(s8)(imm), 0)); \
  493. else \
  494. EMIT_PTR(ptr_, A64_MOVZ_IMM(r_, (s8)(imm), 0)); \
  495. } while (0)
  496. // arithmetic, immediate
  497. static void emith_arith_imm(int op, int wx, int rd, int rn, s32 imm)
  498. {
  499. u32 sz64 = wx ? OP_SZ64:0;
  500. if (imm < 0) {
  501. op ^= (OP_ADD ^ OP_SUB);
  502. imm = -imm;
  503. }
  504. if (imm == 0) {
  505. // value 0, must emit if op is *S or source isn't dest
  506. if ((op & 1) || rd != rn)
  507. EMIT(sz64|A64_OP_IMM12(op, rd, rn, 0, 0));
  508. } else if (imm >> 24) {
  509. // value too large
  510. int _t = rcache_get_tmp();
  511. emith_move_r_imm(_t, imm);
  512. EMIT(sz64|A64_OP_REG(op, 0, rd, rn, _t, ST_LSL, 0));
  513. rcache_free_tmp(_t);
  514. } else {
  515. int rs = rn;
  516. if ((imm) & 0x000fff) {
  517. EMIT(sz64|A64_OP_IMM12(op, rd, rs, imm, 0)); rs = rd;
  518. }
  519. if ((imm) & 0xfff000) {
  520. EMIT(sz64|A64_OP_IMM12(op, rd, rs, imm >>12, 1));
  521. }
  522. }
  523. }
  524. #define emith_add_r_imm(r, imm) \
  525. emith_arith_imm(OP_ADD, 0, r, r, imm)
  526. #define emith_add_r_imm_c(cond, r, imm) \
  527. emith_add_r_imm(r, imm)
  528. #define emith_addf_r_imm(r, imm) \
  529. emith_arith_imm(OP_ADDS, 0, r, r, imm)
  530. #define emith_sub_r_imm(r, imm) \
  531. emith_arith_imm(OP_SUB, 0, r, r, imm)
  532. #define emith_sub_r_imm_c(cond, r, imm) \
  533. emith_sub_r_imm(r, imm)
  534. #define emith_subf_r_imm(r, imm) \
  535. emith_arith_imm(OP_SUBS, 0, r, r, imm)
  536. #define emith_adc_r_imm(r, imm) do { \
  537. int _t = rcache_get_tmp(); \
  538. emith_move_r_imm(_t, imm); \
  539. emith_adc_r_r(r, _t); \
  540. rcache_free_tmp(_t); \
  541. } while (0)
  542. #define emith_adcf_r_imm(r, imm) do { \
  543. int _t = rcache_get_tmp(); \
  544. emith_move_r_imm(_t, imm); \
  545. emith_adcf_r_r(r, _t); \
  546. rcache_free_tmp(_t); \
  547. } while (0)
  548. #define emith_cmp_r_imm(r, imm) do { \
  549. u32 op_ = OP_SUBS, imm_ = (u8)imm; \
  550. if ((s8)imm_ < 0) { \
  551. imm_ = (u8)-imm_; \
  552. op_ = OP_ADDS; \
  553. } \
  554. EMIT(A64_OP_IMM12(op_, Z0, r, imm_, 0)); \
  555. } while (0)
  556. #define emith_add_r_r_ptr_imm(d, s, imm) \
  557. emith_arith_imm(OP_ADD, 1, d, s, imm)
  558. #define emith_add_r_r_imm(d, s, imm) \
  559. emith_arith_imm(OP_ADD, 0, d, s, imm)
  560. #define emith_sub_r_r_imm(d, s, imm) \
  561. emith_arith_imm(OP_SUB, 0, d, s, imm)
  562. #define emith_sub_r_r_imm_c(cond, d, s, imm) \
  563. emith_sub_r_r_imm(d, s, imm)
  564. #define emith_subf_r_r_imm(d, s, imm) \
  565. emith_arith_imm(OP_SUBS, 0, d, s, imm)
  566. // logical, immediate; the value describes a bitmask, see ARMv8 ArchRefMan
  567. // NB: deal only with simple masks 0{n}1{m}0{o} or 1{n}0{m}1{o}, 0<m<32 n+m+o=32
  568. static int emith_log_isbm(u32 imm, int *n, int *m, int *invert)
  569. {
  570. *invert = (s32)imm < 0; // topmost bit set?
  571. if (*invert)
  572. imm = ~imm;
  573. if (imm) {
  574. *n = __builtin_clz(imm); imm = ~(imm << *n); // insert 1's
  575. *m = __builtin_clz(imm); imm = ~ imm << *m; // insert 0's
  576. return !imm;
  577. } else {
  578. *n = *m = 0;
  579. return 0;
  580. }
  581. }
  582. static void emith_log_imm(int op, int wx, int rd, int rn, u32 imm)
  583. {
  584. int n, m, invert;
  585. u32 sz64 = wx ? OP_SZ64:0;
  586. if (emith_log_isbm(imm, &n, &m, &invert) && (!wx || !invert)) {
  587. n += (wx ? 32:0); // extend pattern if 64 bit regs are used
  588. if (invert) EMIT(sz64|A64_OP_IMMBM(op, rd, rn, n, 32-m-1));
  589. else EMIT(sz64|A64_OP_IMMBM(op, rd, rn, n+m, m-1));
  590. } else {
  591. // imm too complex
  592. int _t = rcache_get_tmp();
  593. if (count_bits(imm) > 16) {
  594. emith_move_r_imm(_t, ~imm);
  595. EMIT(sz64|A64_OP_REG(op, 1, rd, rn, _t, ST_LSL, 0));
  596. } else {
  597. emith_move_r_imm(_t, imm);
  598. EMIT(sz64|A64_OP_REG(op, 0, rd, rn, _t, ST_LSL, 0));
  599. }
  600. rcache_free_tmp(_t);
  601. }
  602. }
  603. #define emith_and_r_imm(r, imm) \
  604. emith_log_imm(OP_AND, 0, r, r, imm)
  605. #define emith_or_r_imm(r, imm) \
  606. emith_log_imm(OP_OR, 0, r, r, imm)
  607. #define emith_or_r_imm_c(cond, r, imm) \
  608. emith_or_r_imm(r, imm)
  609. #define emith_eor_r_imm_ptr(r, imm) \
  610. emith_log_imm(OP_EOR, 1, r, r, imm)
  611. #define emith_eor_r_imm_ptr_c(cond, r, imm) \
  612. emith_eor_r_imm_ptr(r, imm)
  613. #define emith_eor_r_imm(r, imm) \
  614. emith_log_imm(OP_EOR, 0, r, r, imm)
  615. #define emith_eor_r_imm_c(cond, r, imm) \
  616. emith_eor_r_imm(r, imm)
  617. /* NB: BIC #imm not available in A64; use AND #~imm instead */
  618. #define emith_bic_r_imm(r, imm) \
  619. emith_log_imm(OP_AND, 0, r, r, ~(imm))
  620. #define emith_bic_r_imm_c(cond, r, imm) \
  621. emith_bic_r_imm(r, imm)
  622. #define emith_tst_r_imm(r, imm) \
  623. emith_log_imm(OP_ANDS, 0, Z0, r, imm)
  624. #define emith_tst_r_imm_c(cond, r, imm) \
  625. emith_tst_r_imm(r, imm)
  626. #define emith_and_r_r_imm(d, s, imm) \
  627. emith_log_imm(OP_AND, 0, d, s, imm)
  628. #define emith_or_r_r_imm(d, s, imm) \
  629. emith_log_imm(OP_OR, 0, d, s, imm)
  630. #define emith_eor_r_r_imm(d, s, imm) \
  631. emith_log_imm(OP_EOR, 0, d, s, imm)
  632. // shift
  633. #define emith_lsl(d, s, cnt) \
  634. EMIT(A64_LSL_IMM(d, s, cnt))
  635. #define emith_lsr(d, s, cnt) \
  636. EMIT(A64_LSR_IMM(d, s, cnt))
  637. #define emith_asr(d, s, cnt) \
  638. EMIT(A64_ASR_IMM(d, s, cnt))
  639. #define emith_ror(d, s, cnt) \
  640. EMIT(A64_ROR_IMM(d, s, cnt))
  641. #define emith_ror_c(cond, d, s, cnt) \
  642. emith_ror(d, s, cnt)
  643. #define emith_rol(d, s, cnt) \
  644. EMIT(A64_ROR_IMM(d, s, 32-(cnt)))
  645. // NB: shift with carry not directly supported in A64 :-|.
  646. #define emith_lslf(d, s, cnt) do { \
  647. if ((cnt) > 1) { \
  648. emith_lsl(d, s, cnt-1); \
  649. emith_addf_r_r_r(d, d, d); \
  650. } else if ((cnt) > 0) \
  651. emith_addf_r_r_r(d, s, s); \
  652. } while (0)
  653. #define emith_lsrf(d, s, cnt) do { \
  654. EMIT(A64_RBIT_REG(d, s)); \
  655. emith_lslf(d, d, cnt); \
  656. EMIT(A64_RBIT_REG(d, d)); \
  657. } while (0)
  658. #define emith_asrf(d, s, cnt) do { \
  659. int _s = s; \
  660. if ((cnt) > 1) { \
  661. emith_asr(d, s, cnt-1); \
  662. _s = d; \
  663. } \
  664. if ((cnt) > 0) { \
  665. emith_addf_r_r_r(Z0, _s, _s); \
  666. EMIT(A64_RBIT_REG(d, _s)); \
  667. emith_adcf_r_r_r(d, d, d); \
  668. EMIT(A64_RBIT_REG(d, d)); \
  669. } \
  670. } while (0)
  671. #define emith_rolf(d, s, cnt) do { \
  672. int _s = s; \
  673. if ((cnt) > 1) { \
  674. emith_rol(d, s, cnt-1); \
  675. _s = d; \
  676. } \
  677. if ((cnt) > 0) { \
  678. emith_addf_r_r_r(d, _s, _s); \
  679. emith_adc_r_r_r(d, d, Z0); \
  680. } \
  681. } while (0)
  682. #define emith_rorf(d, s, cnt) do { \
  683. if ((cnt) > 0) { \
  684. emith_ror(d, s, cnt); \
  685. emith_addf_r_r_r(Z0, d, d); \
  686. } \
  687. } while (0)
  688. #define emith_rolcf(d) \
  689. emith_adcf_r_r(d, d)
  690. #define emith_rolc(d) \
  691. emith_adc_r_r(d, d)
  692. #define emith_rorcf(d) do { \
  693. EMIT(A64_RBIT_REG(d, d)); \
  694. emith_adcf_r_r(d, d); \
  695. EMIT(A64_RBIT_REG(d, d)); \
  696. } while (0)
  697. #define emith_rorc(d) do { \
  698. EMIT(A64_RBIT_REG(d, d)); \
  699. emith_adc_r_r(d, d); \
  700. EMIT(A64_RBIT_REG(d, d)); \
  701. } while (0)
  702. // signed/unsigned extend
  703. #define emith_clear_msb(d, s, count) /* bits to clear */ \
  704. EMIT(A64_UXT_IMM(d, s, 32-(count)))
  705. #define emith_clear_msb_c(cond, d, s, count) \
  706. emith_clear_msb(d, s, count)
  707. #define emith_sext(d, s, count) /* bits to keep */ \
  708. EMIT(A64_SXT_IMM(d, s, count))
  709. // multiply Rd = Rn*Rm (+ Ra)
  710. #define emith_mul(d, s1, s2) \
  711. EMIT(A64_MUL(d, s1, s2))
  712. // NB: must combine/split Xd from/into 2 Wd's; play safe and clear upper bits
  713. #define emith_combine64(dlo, dhi) \
  714. EMIT(A64_UXTX_IMM(dlo, dlo, 32)); \
  715. EMIT(A64_ORX_REG(dlo, dlo, dhi, ST_LSL, 32));
  716. #define emith_split64(dlo, dhi) \
  717. EMIT(A64_LSRX_IMM(dhi, dlo, 32)); \
  718. EMIT(A64_UXTX_IMM(dlo, dlo, 32));
  719. #define emith_mul_u64(dlo, dhi, s1, s2) do { \
  720. EMIT(A64_UMULL(dlo, s1, s2)); \
  721. emith_split64(dlo, dhi); \
  722. } while (0)
  723. #define emith_mul_s64(dlo, dhi, s1, s2) do { \
  724. EMIT(A64_SMULL(dlo, s1, s2)); \
  725. emith_split64(dlo, dhi); \
  726. } while (0)
  727. #define emith_mula_s64(dlo, dhi, s1, s2) do { \
  728. emith_combine64(dlo, dhi); \
  729. EMIT(A64_SMADDL(dlo, s1, s2, dlo)); \
  730. emith_split64(dlo, dhi); \
  731. } while (0)
  732. #define emith_mula_s64_c(cond, dlo, dhi, s1, s2) \
  733. emith_mula_s64(dlo, dhi, s1, s2)
  734. // load/store. offs has 9 bits signed, hence larger offs may use a temp
  735. static void emith_ldst_offs(int sz, int rd, int rn, int o9, int ld, int mode)
  736. {
  737. if (o9 >= -256 && o9 < 256) {
  738. EMIT(A64_OP_LDST(sz, ld, A64_LDST_AM(0,_,o9), mode, rn, rd));
  739. } else if (mode == AM_IDXPRE) {
  740. emith_add_r_r_ptr_imm(rn, rn, o9);
  741. EMIT(A64_OP_LDST(sz, ld, A64_LDST_AM(0,_,0), AM_IDX, rn, rd));
  742. } else if (mode == AM_IDXPOST) {
  743. EMIT(A64_OP_LDST(sz, ld, A64_LDST_AM(0,_,0), AM_IDX, rn, rd));
  744. emith_add_r_r_ptr_imm(rn, rn, o9);
  745. } else {
  746. int _t = rcache_get_tmp();
  747. emith_add_r_r_ptr_imm(_t, rn, o9);
  748. EMIT(A64_OP_LDST(sz, ld, A64_LDST_AM(0,_,0), AM_IDX, _t, rd));
  749. rcache_free_tmp(_t);
  750. }
  751. }
  752. #define emith_read_r_r_offs_ptr(r, rs, offs) \
  753. emith_ldst_offs(AM_X, r, rs, offs, LT_LD, AM_IDX)
  754. #define emith_read_r_r_offs_ptr_c(cond, r, rs, offs) \
  755. emith_read_r_r_offs_ptr(r, rs, offs)
  756. #define emith_read_r_r_offs(r, rs, offs) \
  757. emith_ldst_offs(AM_W, r, rs, offs, LT_LD, AM_IDX)
  758. #define emith_read_r_r_offs_c(cond, r, rs, offs) \
  759. emith_read_r_r_offs(r, rs, offs)
  760. #define emith_read_r_r_r_ptr(r, rs, rm) \
  761. EMIT(A64_LDSTX_REG(r, rs, rm, LT_LD, XT_SXTW))
  762. #define emith_read_r_r_r(r, rs, rm) \
  763. EMIT(A64_LDST_REG(r, rs, rm, LT_LD, XT_SXTW))
  764. #define emith_read_r_r_r_c(cond, r, rs, rm) \
  765. emith_read_r_r_r(r, rs, rm)
  766. #define emith_read8_r_r_offs(r, rs, offs) \
  767. emith_ldst_offs(AM_B, r, rs, offs, LT_LD, AM_IDX)
  768. #define emith_read8_r_r_offs_c(cond, r, rs, offs) \
  769. emith_read8_r_r_offs(r, rs, offs)
  770. #define emith_read8_r_r_r(r, rs, rm) \
  771. EMIT(A64_LDSTB_REG(r, rs, rm, LT_LD, XT_SXTW))
  772. #define emith_read8_r_r_r_c(cond, r, rs, rm) \
  773. emith_read8_r_r_r(r, rs, rm)
  774. #define emith_read16_r_r_offs(r, rs, offs) \
  775. emith_ldst_offs(AM_H, r, rs, offs, LT_LD, AM_IDX)
  776. #define emith_read16_r_r_offs_c(cond, r, rs, offs) \
  777. emith_read16_r_r_offs(r, rs, offs)
  778. #define emith_read16_r_r_r(r, rs, rm) \
  779. EMIT(A64_LDSTH_REG(r, rs, rm, LT_LD, XT_SXTW))
  780. #define emith_read16_r_r_r_c(cond, r, rs, rm) \
  781. emith_read16_r_r_r(r, rs, rm)
  782. #define emith_read8s_r_r_offs(r, rs, offs) \
  783. emith_ldst_offs(AM_B, r, rs, offs, LT_LDS, AM_IDX)
  784. #define emith_read8s_r_r_offs_c(cond, r, rs, offs) \
  785. emith_read8s_r_r_offs(r, rs, offs)
  786. #define emith_read8s_r_r_r(r, rs, rm) \
  787. EMIT(A64_LDSTB_REG(r, rs, rm, LT_LDS, XT_SXTW))
  788. #define emith_read8s_r_r_r_c(cond, r, rs, rm) \
  789. emith_read8s_r_r_r(r, rs, rm)
  790. #define emith_read16s_r_r_offs(r, rs, offs) \
  791. emith_ldst_offs(AM_H, r, rs, offs, LT_LDS, AM_IDX)
  792. #define emith_read16s_r_r_offs_c(cond, r, rs, offs) \
  793. emith_read16s_r_r_offs(r, rs, offs)
  794. #define emith_read16s_r_r_r(r, rs, rm) \
  795. EMIT(A64_LDSTH_REG(r, rs, rm, LT_LDS, XT_SXTW))
  796. #define emith_read16s_r_r_r_c(cond, r, rs, rm) \
  797. emith_read16s_r_r_r(r, rs, rm)
  798. #define emith_write_r_r_offs_ptr(r, rs, offs) \
  799. emith_ldst_offs(AM_X, r, rs, offs, LT_ST, AM_IDX)
  800. #define emith_write_r_r_offs_ptr_c(cond, r, rs, offs) \
  801. emith_write_r_r_offs_ptr(r, rs, offs)
  802. #define emith_write_r_r_r_ptr(r, rs, rm) \
  803. EMIT(A64_LDSTX_REG(r, rs, rm, LT_ST, XT_SXTW))
  804. #define emith_write_r_r_r_ptr_c(cond, r, rs, rm) \
  805. emith_write_r_r_r_ptr(r, rs, rm)
  806. #define emith_write_r_r_offs(r, rs, offs) \
  807. emith_ldst_offs(AM_W, r, rs, offs, LT_ST, AM_IDX)
  808. #define emith_write_r_r_offs_c(cond, r, rs, offs) \
  809. emith_write_r_r_offs(r, rs, offs)
  810. #define emith_write_r_r_r(r, rs, rm) \
  811. EMIT(A64_LDST_REG(r, rs, rm, LT_ST, XT_SXTW))
  812. #define emith_write_r_r_r_c(cond, r, rs, rm) \
  813. emith_write_r_r_r(r, rs, rm)
  814. #define emith_ctx_read_ptr(r, offs) \
  815. emith_read_r_r_offs_ptr(r, CONTEXT_REG, offs)
  816. #define emith_ctx_read(r, offs) \
  817. emith_read_r_r_offs(r, CONTEXT_REG, offs)
  818. #define emith_ctx_read_c(cond, r, offs) \
  819. emith_ctx_read(r, offs)
  820. #define emith_ctx_write_ptr(r, offs) \
  821. emith_write_r_r_offs_ptr(r, CONTEXT_REG, offs)
  822. #define emith_ctx_write(r, offs) \
  823. emith_write_r_r_offs(r, CONTEXT_REG, offs)
  824. #define emith_ctx_read_multiple(r, offs, cnt, tmpr) do { \
  825. int r_ = r, offs_ = offs, cnt_ = cnt; \
  826. for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
  827. emith_ctx_read(r_, offs_); \
  828. } while (0)
  829. #define emith_ctx_write_multiple(r, offs, cnt, tmpr) do { \
  830. int r_ = r, offs_ = offs, cnt_ = cnt; \
  831. for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
  832. emith_ctx_write(r_, offs_); \
  833. } while (0)
  834. // push pairs; NB: SP must be 16 byte aligned (HW requirement!)
  835. #define emith_push2(r1, r2) \
  836. EMIT(A64_LDSTPX_IMM(SP, r1, r2, -2*8, LT_ST, AM_IDXPRE))
  837. #define emith_pop2(r1, r2) \
  838. EMIT(A64_LDSTPX_IMM(SP, r1, r2, 2*8, LT_LD, AM_IDXPOST))
  839. // function call handling
  840. #define emith_save_caller_regs(mask) do { \
  841. int _c, _r1, _r2; u32 _m = mask & 0x3ffff; \
  842. if (__builtin_parity(_m) == 1) _m |= 0x40000; /* hardware align */ \
  843. for (_c = HOST_REGS-1, _r1 = -1; _m && _c >= 0; _m &= ~(1 << _c), _c--)\
  844. if (_m & (1 << _c)) { \
  845. _r2 = _r1, _r1 = _c; \
  846. if (_r2 != -1) { \
  847. emith_push2(_r1, _r2); \
  848. _r1 = -1; \
  849. } \
  850. } \
  851. } while (0)
  852. #define emith_restore_caller_regs(mask) do { \
  853. int _c, _r1, _r2; u32 _m = mask & 0x3ffff; \
  854. if (__builtin_parity(_m) == 1) _m |= 0x40000; /* hardware align */ \
  855. for (_c = 0, _r1 = -1; _m && _c < HOST_REGS; _m &= ~(1 << _c), _c++) \
  856. if (_m & (1 << _c)) { \
  857. _r2 = _r1, _r1 = _c; \
  858. if (_r2 != -1) { \
  859. emith_pop2(_r2, _r1); \
  860. _r1 = -1; \
  861. } \
  862. } \
  863. } while (0)
  864. #define host_arg2reg(rd, arg) \
  865. rd = arg
  866. #define emith_pass_arg_r(arg, reg) \
  867. emith_move_r_r(arg, reg)
  868. #define emith_pass_arg_imm(arg, imm) \
  869. emith_move_r_imm(arg, imm)
  870. // branching; NB: A64 B.cond has only +/- 1MB range
  871. #define emith_jump(target) do {\
  872. u32 disp_ = (u8 *)target - (u8 *)tcache_ptr; \
  873. EMIT(A64_B(disp_ & 0x0fffffff)); \
  874. } while (0)
  875. #define emith_jump_patchable(target) \
  876. emith_jump(target)
  877. #define emith_jump_cond(cond, target) do { \
  878. u32 disp_ = (u8 *)target - (u8 *)tcache_ptr; \
  879. EMIT(A64_BCOND(cond, disp_ & 0x001fffff)); \
  880. } while (0)
  881. #define emith_jump_cond_patchable(cond, target) \
  882. emith_jump_cond(cond, target)
  883. #define emith_jump_cond_inrange(target) \
  884. !(((u8 *)target - (u8 *)tcache_ptr + 0x100000) >> 21)
  885. #define emith_jump_patch(ptr, target, pos) do { \
  886. u32 *ptr_ = (u32 *)ptr; \
  887. u32 disp_ = (u8 *)target - (u8 *)ptr, mask_; \
  888. if ((*ptr_ & 0xff000000) == 0x54000000) \
  889. mask_ = 0xff00001f, disp_ <<= 5; /* B.cond, range 21 bit */ \
  890. else mask_ = 0xfc000000; /* B[L], range 28 bit */ \
  891. EMIT_PTR(ptr_, (*ptr_ & mask_) | ((disp_ >> 2) & ~mask_)); \
  892. if ((void *)(pos) != NULL) *(u8 **)(pos) = (u8 *)(ptr_-1); \
  893. } while (0)
  894. #define emith_jump_patch_inrange(ptr, target) \
  895. !(((u8 *)target - (u8 *)ptr + 0x100000) >> 21)
  896. #define emith_jump_patch_size() 4
  897. #define emith_jump_at(ptr, target) do { \
  898. u32 disp_ = (u8 *)target - (u8 *)ptr; \
  899. EMIT_PTR(ptr, A64_B(disp_ & 0x0fffffff)); \
  900. } while (0)
  901. #define emith_jump_at_size() 4
  902. #define emith_jump_reg(r) \
  903. EMIT(A64_BR(r))
  904. #define emith_jump_reg_c(cond, r) \
  905. emith_jump_reg(r)
  906. #define emith_jump_ctx(offs) do { \
  907. int _t = rcache_get_tmp(); \
  908. emith_ctx_read_ptr(_t, offs); \
  909. emith_jump_reg(_t); \
  910. rcache_free_tmp(_t); \
  911. } while (0)
  912. #define emith_jump_ctx_c(cond, offs) \
  913. emith_jump_ctx(offs)
  914. #define emith_call(target) do { \
  915. u32 disp_ = (u8 *)target - (u8 *)tcache_ptr; \
  916. EMIT(A64_BL(disp_ & 0x0fffffff)); \
  917. } while (0)
  918. #define emith_call_cond(cond, target) \
  919. emith_call(target)
  920. #define emith_call_reg(r) \
  921. EMIT(A64_BLR(r))
  922. #define emith_call_ctx(offs) do { \
  923. int _t = rcache_get_tmp(); \
  924. emith_ctx_read_ptr(_t, offs); \
  925. emith_call_reg(_t); \
  926. rcache_free_tmp(_t); \
  927. } while (0)
  928. #define emith_call_cleanup() /**/
  929. #define emith_ret() \
  930. EMIT(A64_RET(LR))
  931. #define emith_ret_c(cond) \
  932. emith_ret()
  933. #define emith_ret_to_ctx(offs) \
  934. emith_ctx_write_ptr(LR, offs)
  935. #define emith_add_r_ret(r) \
  936. emith_add_r_r_r_ptr(r, LR, r)
  937. // NB: pushes r or r18 for SP hardware alignment
  938. #define emith_push_ret(r) do { \
  939. int r_ = (r >= 0 ? r : 18); \
  940. emith_push2(r_, LR); \
  941. } while (0)
  942. #define emith_pop_and_ret(r) do { \
  943. int r_ = (r >= 0 ? r : 18); \
  944. emith_pop2(r_, LR); \
  945. emith_ret(); \
  946. } while (0)
  947. // emitter ABI stuff
  948. #define emith_pool_check() /**/
  949. #define emith_pool_commit(j) /**/
  950. #define emith_insn_ptr() ((u8 *)tcache_ptr)
  951. #define emith_flush() /**/
  952. #define host_instructions_updated(base, end) __builtin___clear_cache(base, end)
  953. #define emith_update_cache() /**/
  954. #define emith_rw_offs_max() 0xff
  955. // SH2 drc specific
  956. #define emith_sh2_drc_entry() do { \
  957. emith_push2(LR, FP); \
  958. emith_push2(28, 27); \
  959. emith_push2(26, 25); \
  960. emith_push2(24, 23); \
  961. emith_push2(22, 21); \
  962. emith_push2(20, 19); \
  963. } while (0)
  964. #define emith_sh2_drc_exit() do { \
  965. emith_pop2(20, 19); \
  966. emith_pop2(22, 21); \
  967. emith_pop2(24, 23); \
  968. emith_pop2(26, 25); \
  969. emith_pop2(28, 27); \
  970. emith_pop2(LR, FP); \
  971. emith_ret(); \
  972. } while (0)
  973. // NB: assumes a is in arg0, tab, func and mask are temp
  974. #define emith_sh2_rcall(a, tab, func, mask) do { \
  975. emith_lsr(mask, a, SH2_READ_SHIFT); \
  976. EMIT(A64_ADDX_REG(tab, tab, mask, ST_LSL, 4)); \
  977. emith_read_r_r_offs_ptr(func, tab, 0); \
  978. emith_read_r_r_offs(mask, tab, 8); \
  979. EMIT(A64_ADDXS_REG(func, func, func, ST_LSL, 0)); \
  980. } while (0)
  981. // NB: assumes a, val are in arg0 and arg1, tab and func are temp
  982. #define emith_sh2_wcall(a, val, tab, func) do { \
  983. emith_lsr(func, a, SH2_WRITE_SHIFT); \
  984. emith_lsl(func, func, 3); \
  985. emith_read_r_r_r_ptr(func, tab, func); \
  986. emith_move_r_r_ptr(2, CONTEXT_REG); /* arg2 */ \
  987. emith_jump_reg(func); \
  988. } while (0)
  989. #define emith_sh2_delay_loop(cycles, reg) do { \
  990. int sr = rcache_get_reg(SHR_SR, RC_GR_RMW, NULL); \
  991. int t1 = rcache_get_tmp(); \
  992. int t2 = rcache_get_tmp(); \
  993. int t3 = rcache_get_tmp(); \
  994. /* if (sr < 0) return */ \
  995. emith_cmp_r_imm(sr, 0); \
  996. EMITH_JMP_START(DCOND_LE); \
  997. /* turns = sr.cycles / cycles */ \
  998. emith_asr(t2, sr, 12); \
  999. emith_move_r_imm(t3, (u32)((1ULL<<32) / (cycles)) + 1); \
  1000. emith_mul_u64(t1, t2, t2, t3); /* multiply by 1/x */ \
  1001. rcache_free_tmp(t3); \
  1002. if (reg >= 0) { \
  1003. /* if (reg <= turns) turns = reg-1 */ \
  1004. t3 = rcache_get_reg(reg, RC_GR_RMW, NULL); \
  1005. emith_cmp_r_r(t3, t2); \
  1006. EMITH_SJMP_START(DCOND_HI); \
  1007. emith_sub_r_r_imm_c(DCOND_LS, t2, t3, 1); \
  1008. EMITH_SJMP_END(DCOND_HI); \
  1009. /* if (reg <= 1) turns = 0 */ \
  1010. emith_cmp_r_imm(t3, 1); \
  1011. EMITH_SJMP_START(DCOND_HI); \
  1012. emith_move_r_imm_c(DCOND_LS, t2, 0); \
  1013. EMITH_SJMP_END(DCOND_HI); \
  1014. /* reg -= turns */ \
  1015. emith_sub_r_r(t3, t2); \
  1016. } \
  1017. /* sr.cycles -= turns * cycles; */ \
  1018. emith_move_r_imm(t1, cycles); \
  1019. emith_mul(t1, t2, t1); \
  1020. emith_sub_r_r_r_lsl(sr, sr, t1, 12); \
  1021. EMITH_JMP_END(DCOND_LE); \
  1022. rcache_free_tmp(t1); \
  1023. rcache_free_tmp(t2); \
  1024. } while (0)
  1025. /*
  1026. * if Q
  1027. * t = carry(Rn += Rm)
  1028. * else
  1029. * t = carry(Rn -= Rm)
  1030. * T ^= t
  1031. */
  1032. #define emith_sh2_div1_step(rn, rm, sr) do { \
  1033. int tmp_ = rcache_get_tmp(); \
  1034. emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
  1035. EMITH_SJMP3_START(DCOND_EQ); \
  1036. emith_addf_r_r(rn, rm); \
  1037. emith_adc_r_r_r(tmp_, Z0, Z0); \
  1038. EMITH_SJMP3_MID(DCOND_EQ); \
  1039. emith_subf_r_r(rn, rm); \
  1040. emith_adc_r_r_r(tmp_, Z0, Z0); \
  1041. emith_eor_r_imm(tmp_, 1); \
  1042. EMITH_SJMP3_END(); \
  1043. emith_eor_r_r(sr, tmp_); \
  1044. rcache_free_tmp(tmp_); \
  1045. } while (0)
  1046. /* mh:ml += rn*rm, does saturation if required by S bit. rn, rm must be TEMP */
  1047. #define emith_sh2_macl(ml, mh, rn, rm, sr) do { \
  1048. emith_tst_r_imm(sr, S); \
  1049. EMITH_SJMP_START(DCOND_EQ); \
  1050. /* MACH top 16 bits unused if saturated. sign ext for overfl detect */ \
  1051. emith_sext(mh, mh, 16); \
  1052. EMITH_SJMP_END(DCOND_EQ); \
  1053. emith_mula_s64(ml, mh, rn, rm); \
  1054. emith_tst_r_imm(sr, S); \
  1055. EMITH_SJMP_START(DCOND_EQ); \
  1056. /* overflow if top 17 bits of MACH aren't all 1 or 0 */ \
  1057. /* to check: add MACH >> 31 to MACH >> 15. this is 0 if no overflow */ \
  1058. emith_asr(rn, mh, 15); \
  1059. emith_addf_r_r_r_lsr(rn, rn, mh, 31); \
  1060. EMITH_SJMP_START(DCOND_EQ); /* sum != 0 -> ov */ \
  1061. emith_move_r_imm_c(DCOND_NE, ml, 0x0000); /* -overflow */ \
  1062. emith_move_r_imm_c(DCOND_NE, mh, 0x8000); \
  1063. EMITH_SJMP_START(DCOND_LE); /* sum > 0 -> +ovl */ \
  1064. emith_sub_r_imm_c(DCOND_GT, ml, 1); /* 0xffffffff */ \
  1065. emith_sub_r_imm_c(DCOND_GT, mh, 1); /* 0x00007fff */ \
  1066. EMITH_SJMP_END(DCOND_LE); \
  1067. EMITH_SJMP_END(DCOND_EQ); \
  1068. EMITH_SJMP_END(DCOND_EQ); \
  1069. } while (0)
  1070. /* mh:ml += rn*rm, does saturation if required by S bit. rn, rm must be TEMP */
  1071. #define emith_sh2_macw(ml, mh, rn, rm, sr) do { \
  1072. emith_tst_r_imm(sr, S); \
  1073. EMITH_SJMP_START(DCOND_EQ); \
  1074. /* XXX: MACH should be untouched when S is set? */ \
  1075. emith_asr(mh, ml, 31); /* sign ext MACL to MACH for ovrfl check */ \
  1076. EMITH_SJMP_END(DCOND_EQ); \
  1077. emith_mula_s64(ml, mh, rn, rm); \
  1078. emith_tst_r_imm(sr, S); \
  1079. EMITH_SJMP_START(DCOND_EQ); \
  1080. /* overflow if top 33 bits of MACH:MACL aren't all 1 or 0 */ \
  1081. /* to check: add MACL[31] to MACH. this is 0 if no overflow */ \
  1082. emith_lsr(rn, ml, 31); \
  1083. emith_addf_r_r(rn, mh); /* sum = MACH + ((MACL>>31)&1) */ \
  1084. EMITH_SJMP_START(DCOND_EQ); /* sum != 0 -> overflow */ \
  1085. /* XXX: LSB signalling only in SH1, or in SH2 too? */ \
  1086. emith_move_r_imm_c(DCOND_NE, mh, 0x00000001); /* LSB of MACH */ \
  1087. emith_move_r_imm_c(DCOND_NE, ml, 0x80000000); /* negative ovrfl */ \
  1088. EMITH_SJMP_START(DCOND_LE); /* sum > 0 -> positive ovrfl */ \
  1089. emith_sub_r_imm_c(DCOND_GT, ml, 1); /* 0x7fffffff */ \
  1090. EMITH_SJMP_END(DCOND_LE); \
  1091. EMITH_SJMP_END(DCOND_EQ); \
  1092. EMITH_SJMP_END(DCOND_EQ); \
  1093. } while (0)
  1094. #define emith_write_sr(sr, srcr) do { \
  1095. emith_lsr(sr, sr, 10); \
  1096. emith_or_r_r_r_lsl(sr, sr, srcr, 22); \
  1097. emith_ror(sr, sr, 22); \
  1098. } while (0)
  1099. #define emith_carry_to_t(srr, is_sub) do { \
  1100. emith_lsr(sr, sr, 1); \
  1101. emith_adc_r_r(sr, sr); \
  1102. if (is_sub) /* SUB has inverted C on ARM */ \
  1103. emith_eor_r_imm(sr, 1); \
  1104. } while (0)
  1105. #define emith_t_to_carry(srr, is_sub) do { \
  1106. if (is_sub) { \
  1107. int t_ = rcache_get_tmp(); \
  1108. emith_eor_r_r_imm(t_, srr, 1); \
  1109. emith_rorf(t_, t_, 1); \
  1110. rcache_free_tmp(t_); \
  1111. } else { \
  1112. emith_rorf(srr, srr, 1); \
  1113. emith_rol(srr, srr, 1); \
  1114. } \
  1115. } while (0)
  1116. #define emith_tpop_carry(sr, is_sub) do { \
  1117. if (is_sub) \
  1118. emith_eor_r_imm(sr, 1); \
  1119. emith_ror(sr, sr, 1); \
  1120. emith_addf_r_r(sr, sr); \
  1121. } while (0)
  1122. #define emith_tpush_carry(sr, is_sub) do { \
  1123. emith_adc_r_r(sr, Z0); \
  1124. if (is_sub) \
  1125. emith_eor_r_imm(sr, 1); \
  1126. } while (0)
  1127. #ifdef T
  1128. // T bit handling
  1129. #define emith_invert_cond(cond) \
  1130. ((cond) ^ 1)
  1131. static void emith_clr_t_cond(int sr)
  1132. {
  1133. emith_bic_r_imm(sr, T);
  1134. }
  1135. static void emith_set_t_cond(int sr, int cond)
  1136. {
  1137. EMITH_SJMP_START(emith_invert_cond(cond));
  1138. emith_or_r_imm_c(cond, sr, T);
  1139. EMITH_SJMP_END(emith_invert_cond(cond));
  1140. }
  1141. #define emith_get_t_cond() -1
  1142. #define emith_sync_t(sr) ((void)sr)
  1143. #define emith_invalidate_t()
  1144. static void emith_set_t(int sr, int val)
  1145. {
  1146. if (val)
  1147. emith_or_r_imm(sr, T);
  1148. else
  1149. emith_bic_r_imm(sr, T);
  1150. }
  1151. static int emith_tst_t(int sr, int tf)
  1152. {
  1153. emith_tst_r_imm(sr, T);
  1154. return tf ? DCOND_NE: DCOND_EQ;
  1155. }
  1156. #endif