config.h 7.1 KB

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  1. /**
  2. * Cyclone 68000 configuration file
  3. **/
  4. /*
  5. * If this option is enabled, Microsoft ARMASM compatible output is generated
  6. * (output file - Cyclone.asm). Otherwise GNU as syntax is used (Cyclone.s).
  7. */
  8. #define USE_MS_SYNTAX 0
  9. /*
  10. * Enable this option if you are going to use Cyclone to emulate Genesis /
  11. * Mega Drive system. As VDP chip in these systems had control of the bus,
  12. * several instructions were acting differently, for example TAS did'n have
  13. * the write-back phase. That will be emulated, if this option is enabled.
  14. */
  15. #define CYCLONE_FOR_GENESIS 0
  16. /*
  17. * This option compresses Cyclone's jumptable. Because of this the executable
  18. * will be smaller and load slightly faster and less relocations will be needed.
  19. * This also fixes the crash problem with 0xfffe and 0xffff opcodes.
  20. * Warning: if you enable this, you MUST call CycloneInit() before calling
  21. * CycloneRun(), or else it will crash.
  22. */
  23. #define COMPRESS_JUMPTABLE 1
  24. /*
  25. * Address mask for memory hadlers. The bits set will be masked out of address
  26. * parameter, which is passed to r/w memory handlers.
  27. * Using 0xff000000 means that only 24 least significant bits should be used.
  28. * Set to 0 if you want to mask unused address bits in the memory handlers yourself.
  29. */
  30. #define MEMHANDLERS_ADDR_MASK 0
  31. /*
  32. * Cyclone keeps the 4 least significant bits of SR, PC+membase and it's cycle
  33. * counter in ARM registers instead of the context for performance reasons. If you for
  34. * any reason need to access them in your memory handlers, enable the options below,
  35. * otherwise disable them to improve performance.
  36. *
  37. * MEMHANDLERS_NEED_PC updates .pc context field with PC value effective at the time
  38. * when memhandler was called (opcode address + 2-10 bytes).
  39. * MEMHANDLERS_NEED_PREV_PC updates .prev_pc context field to currently executed
  40. * opcode address + 2.
  41. * Note that .pc and .prev_pc values are always real pointers to memory, so you must
  42. * subtract .membase to get M68k PC value.
  43. *
  44. * Warning: updating PC in memhandlers is dangerous, as Cyclone may internally
  45. * increment the PC before fetching the next instruction and continue executing
  46. * at wrong location. It's better to wait until Cyclone CycloneRun() finishes.
  47. *
  48. * Warning: if you enable MEMHANDLERS_CHANGE_CYCLES, you must also enable
  49. * MEMHANDLERS_NEED_CYCLES, or else Cyclone will keep reloading the same cycle
  50. * count and this will screw timing (if not cause a deadlock).
  51. */
  52. #define MEMHANDLERS_NEED_PC 0
  53. #define MEMHANDLERS_NEED_PREV_PC 0
  54. #define MEMHANDLERS_NEED_FLAGS 0
  55. #define MEMHANDLERS_NEED_CYCLES 0
  56. #define MEMHANDLERS_CHANGE_PC 0
  57. #define MEMHANDLERS_CHANGE_FLAGS 0
  58. #define MEMHANDLERS_CHANGE_CYCLES 0
  59. /*
  60. * If the following macro is defined, Cyclone no longer calls read*, write*,
  61. * fetch* and checkpc from it's context, it calls these functions directly
  62. * instead, prefixed with prefix selected below. For example, if
  63. * MEMHANDLERS_DIRECT_PREFIX is set to cyclone_, it will call cyclone_read8
  64. * on byte reads.
  65. * This is to avoid indirect jumps, which are slower. It also saves one ARM
  66. * instruction.
  67. */
  68. /* MEMHANDLERS_DIRECT_PREFIX "cyclone_" */
  69. /*
  70. * If enabled, Cyclone will call .IrqCallback routine from it's context whenever it
  71. * acknowledges an IRQ. IRQ level (.irq) is not cleared automatically, do this in your
  72. * handler if needed.
  73. * This function must either return vector number to use for interrupt exception,
  74. * CYCLONE_INT_ACK_AUTOVECTOR to use autovector (this is the most common case), or
  75. * CYCLONE_INT_ACK_SPURIOUS (least common case).
  76. * If disabled, it simply uses appropriate autovector, clears the IRQ level and
  77. * continues execution.
  78. */
  79. #define USE_INT_ACK_CALLBACK 0
  80. /*
  81. * Enable this if you need old PC, flags or cycles;
  82. * or you change cycles in your IrqCallback function.
  83. */
  84. #define INT_ACK_NEEDS_STUFF 0
  85. #define INT_ACK_CHANGES_CYCLES 0
  86. /*
  87. * If enabled, .ResetCallback is called from the context, whenever RESET opcode is
  88. * encountered. All context members are valid and can be changed.
  89. * If disabled, RESET opcode acts as an NOP.
  90. */
  91. #define USE_RESET_CALLBACK 0
  92. /*
  93. * If enabled, UnrecognizedCallback is called if an invalid opcode is
  94. * encountered. All context members are valid and can be changed. The handler
  95. * should return zero if you want Cyclone to gererate "Illegal Instruction"
  96. * exception after this, or nonzero if not. In the later case you should change
  97. * the PC by yourself, or else Cyclone will keep executing that opcode all over
  98. * again.
  99. * If disabled, "Illegal Instruction" exception is generated and execution is
  100. * continued.
  101. */
  102. #define USE_UNRECOGNIZED_CALLBACK 0
  103. /*
  104. * This option will also call UnrecognizedCallback for a-line and f-line
  105. * (0xa*** and 0xf***) opcodes the same way as described above, only appropriate
  106. * exceptions will be generated.
  107. */
  108. #define USE_AFLINE_CALLBACK 0
  109. /*
  110. * This makes Cyclone to call checkpc from it's context whenever it changes the PC
  111. * by a large value. It takes and should return the PC value in PC+membase form.
  112. * The flags and cycle counter are not valid in this function.
  113. */
  114. #define USE_CHECKPC_CALLBACK 1
  115. /*
  116. * This determines if checkpc() should be called after jumps when 8 and 16 bit
  117. * displacement values were used.
  118. */
  119. #define USE_CHECKPC_OFFSETBITS_16 1
  120. #define USE_CHECKPC_OFFSETBITS_8 0
  121. /*
  122. * Call checkpc() after DBcc jumps (which use 16bit displacement). Cyclone prior to
  123. * 0.0087 never did that.
  124. */
  125. #define USE_CHECKPC_DBRA 0
  126. /*
  127. * When this option is enabled Cyclone will do two word writes instead of one
  128. * long write when handling MOVE.L or MOVEM.L with pre-decrementing destination,
  129. * as described in Bart Trzynadlowski's doc (http://www.trzy.org/files/68knotes.txt).
  130. * Enable this if you are emulating a 16 bit system.
  131. */
  132. #define SPLIT_MOVEL_PD 1
  133. /*
  134. * Enable emulation of trace mode. Shouldn't cause any performance decrease, so it
  135. * should be safe to keep this ON.
  136. */
  137. #define EMULATE_TRACE 1
  138. /*
  139. * If enabled, address error exception will be generated if 68k code jumps to an
  140. * odd address. Causes very small performance hit (2 ARM instructions for every
  141. * emulated jump/return/exception in normal case).
  142. * Note: checkpc() must not clear least significant bit of rebased address
  143. * for this to work, as checks are performed after calling checkpc().
  144. */
  145. #define EMULATE_ADDRESS_ERRORS_JUMP 1
  146. /*
  147. * If enabled, address error exception will be generated if 68k code tries to
  148. * access a word or longword at an odd address. The performance cost is also 2 ARM
  149. * instructions per access (for address error checks).
  150. */
  151. #define EMULATE_ADDRESS_ERRORS_IO 0
  152. /*
  153. * If an address error happens during another address error processing,
  154. * the processor halts until it is reset (catastrophic system failure, as the manual
  155. * states). This option enables halt emulation.
  156. * Note that this might be not desired if it is known that emulated system should
  157. * never reach this state.
  158. */
  159. #define EMULATE_HALT 0