Cyclone.txt 26 KB

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  1. _____ __
  2. / ___/__ __ ____ / /___ ___ ___ ___________________
  3. / /__ / // // __// // _ \ / _ \/ -_) ___________________
  4. \___/ \_, / \__//_/ \___//_//_/\__/ ___________________
  5. /___/
  6. ___________________ ____ ___ ___ ___ ___
  7. ___________________ / __// _ \ / _ \ / _ \ / _ \
  8. ___________________ / _ \/ _ // // // // // // /
  9. \___/\___/ \___/ \___/ \___/
  10. ___________________________________________________________________________
  11. Cyclone 68000 (c) Copyright 2004 Dave. Free for non-commercial use
  12. Homepage: http://www.finalburn.com/
  13. Dave's e-mail: emudave(atsymbol)googlemail.com
  14. Replace (atsymbol) with @
  15. Additional coding and bugfixes done by notaz, 2005-2007
  16. Homepage: http://notaz.gp2x.de
  17. e-mail: notasas(atsymbol)gmail.com
  18. ___________________________________________________________________________
  19. About
  20. -----
  21. Cyclone 68000 is an emulator for the 68000 microprocessor, written in ARM 32-bit assembly.
  22. It is aimed at chips such as ARM7 and ARM9 cores, StrongARM and XScale, to interpret 68000
  23. code as fast as possible. It can emulate all 68000 instructions quite accurately, instruction
  24. timing was synchronized with MAME's Musashi. Most 68k features are emulated (trace mode,
  25. address errors), but prefetch is not emulated.
  26. How to Compile
  27. --------------
  28. Like Starscream and A68K, Cyclone uses a 'Core Creator' program which calculates and outputs
  29. all possible 68000 Opcodes and a jump table into file called Cyclone.s or Cyclone.asm.
  30. Only Cyclone.h and the mentioned .s or .asm file will be needed for your project, other files
  31. are here to produce or test it.
  32. First unzip "Cyclone.zip" into a "Cyclone" directory. The next thing to do is to edit config.h
  33. file to tune Cyclone for your project. There are lots of options in config.h, but all of them
  34. are documented and have defaults. You should set a define value to 1 to enable option, and
  35. to 0 to disable.
  36. After you are done with config.h, save it and compile Cyclone. If you are using Linux, Cygwin,
  37. mingw or similar, you can simply cd to Cyclone/proj and type "make". If you are under Windows
  38. and have Visual Studio installed, you can import cyclone.dsp in the proj/ directory and compile
  39. it from there (this will produce cyclone.exe which you will have to run to get .s or .asm).
  40. You can also use Microsoft command line compile tools by entering Cyclone/proj directory and
  41. typing "nmake -f Makefile.win". Note that this step is done only to produce .s or .asm, and it
  42. is done using native tools on your PC (not using cross-compiler or similar).
  43. The .s file is meant to be compiled with GNU assembler, and .asm with ARMASM.EXE
  44. (the Microsoft ARM assembler). Once you have the file, you can add it to your
  45. Makefile/project/whatever.
  46. Adding to your project
  47. ----------------------
  48. Compiling the .s or .asm (from previous step) for your target platform may require custom
  49. build rules in your Makefile/project.
  50. If you use some gcc-based toolchain, you will need to add Cyclone.o to an object list in
  51. the Makefile. GNU make will use "as" to build Cyclone.o from Cyclone.s by default, so
  52. you may need to define correct cross-assembler by setting AS variable like this:
  53. AS = arm-linux-as
  54. This might be different in your case, basically it should be same prefix as for gcc.
  55. You may also need to specify floating point type in your assembler flags for Cyclone.o
  56. to link properly. This is done like this:
  57. ASFLAGS = -mfloat-abi=soft
  58. Note that Cyclone does not use floating points, this is just to make the linker happy.
  59. If you are using Visual Studio, you may need to add "custom build step", which creates
  60. Cyclone.obj from Cyclone.asm (asmasm.exe Cyclone.asm). Alternatively you can create
  61. Cyclone.obj by using armasm once and then just add it to you project.
  62. Don't worry if this seem very minimal - its all you need to run as many 68000s as you want.
  63. It works with both C and C++.
  64. Byteswapped Memory
  65. ------------------
  66. If you have used Starscream, A68K or Turbo68K or similar emulators you'll be familiar with this!
  67. Any memory which the 68000 can access directly must be have every two bytes swapped around.
  68. This is to speed up 16-bit memory accesses, because the 68000 has Big-Endian memory
  69. and ARM has Little-Endian memory (in most cases).
  70. Now you may think you only technically have to byteswap ROM, not RAM, because
  71. 16-bit RAM reads go through a memory handler and you could just return (mem[a]<<8) | mem[a+1].
  72. This would work, but remember some systems can execute code from RAM as well as ROM, and
  73. that would fail.
  74. So it's best to use byteswapped ROM and RAM if the 68000 can access it directly.
  75. It's also faster for the memory handlers, because you can do this:
  76. return *(unsigned short *)(mem+a)
  77. Declaring Memory handlers
  78. -------------------------
  79. Before you can reset or execute 68000 opcodes you must first set up a set of memory handlers.
  80. There are 7 functions you have to set up per CPU, like this:
  81. static unsigned int MyCheckPc(unsigned int pc)
  82. static unsigned char MyRead8 (unsigned int a)
  83. static unsigned short MyRead16 (unsigned int a)
  84. static unsigned int MyRead32 (unsigned int a)
  85. static void MyWrite8 (unsigned int a,unsigned char d)
  86. static void MyWrite16(unsigned int a,unsigned short d)
  87. static void MyWrite32(unsigned int a,unsigned int d)
  88. You can think of these functions representing the 68000's memory bus.
  89. The Read and Write functions are called whenever the 68000 reads or writes memory.
  90. For example you might set MyRead8 like this:
  91. unsigned char MyRead8(unsigned int a)
  92. {
  93. a&=0xffffff; // Clip address to 24-bits
  94. if (a<RomLength) return RomData[a^1]; // ^1 because the memory is byteswapped
  95. if (a>=0xe00000) return RamData[(a^1)&0xffff];
  96. return 0xff; // Out of range memory access
  97. }
  98. The other 5 read/write functions are similar. I'll describe the CheckPc function later on.
  99. Declaring a CPU Context
  100. -----------------------
  101. To declare a CPU simple declare a struct Cyclone in your code (don't forget to include Cyclone.h).
  102. For example to declare two 68000s:
  103. struct Cyclone MyCpu;
  104. struct Cyclone MyCpu2;
  105. It's probably a good idea to initialize the memory to zero:
  106. memset(&MyCpu, 0,sizeof(MyCpu));
  107. memset(&MyCpu2,0,sizeof(MyCpu2));
  108. Next point to your memory handlers:
  109. MyCpu.checkpc=MyCheckPc;
  110. MyCpu.read8 =MyRead8;
  111. MyCpu.read16 =MyRead16;
  112. MyCpu.read32 =MyRead32;
  113. MyCpu.write8 =MyWrite8;
  114. MyCpu.write16=MyWrite16;
  115. MyCpu.write32=MyWrite32;
  116. You also need to point the fetch handlers - for most systems out there you can just
  117. point them at the read handlers:
  118. MyCpu.fetch8 =MyRead8;
  119. MyCpu.fetch16 =MyRead16;
  120. MyCpu.fetch32 =MyRead32;
  121. ( Why a different set of function pointers for fetch?
  122. Well there are some systems, the main one being CPS2, which return different data
  123. depending on whether the 'fetch' line on the 68000 bus is high or low.
  124. If this is the case, you can set up different functions for fetch reads.
  125. Generally though you don't need to. )
  126. Now you are nearly ready to reset the 68000, except a few more functions,
  127. one of them is: checkpc().
  128. The checkpc() function
  129. ----------------------
  130. When Cyclone reads opcodes, it doesn't use a memory handler every time, this would be
  131. far too slow, instead it uses a direct pointer to ARM memory.
  132. For example if your Rom image was at 0x3000000 and the program counter was $206,
  133. Cyclone's program counter would be 0x3000206.
  134. The difference between an ARM address and a 68000 address is also stored in a variable called
  135. 'membase'. In the above example it's 0x3000000. To retrieve the real 68k PC, Cyclone just
  136. subtracts 'membase'.
  137. When a long jump happens, Cyclone calls checkpc(). If the PC is in a different bank,
  138. for example Ram instead of Rom, change 'membase', recalculate the new PC and return it:
  139. static int MyCheckPc(unsigned int pc)
  140. {
  141. pc-=MyCpu.membase; // Get the real program counter
  142. if (pc<RomLength) MyCpu.membase=(int)RomMem; // Jump to Rom
  143. if (pc>=0xff0000) MyCpu.membase=(int)RamMem-0xff0000; // Jump to Ram
  144. return MyCpu.membase+pc; // New program counter
  145. }
  146. Notice that the membase is always ARM address minus 68000 address.
  147. The above example doesn't consider mirrored ram, but for an example of what to do see
  148. PicoDrive (in Memory.c).
  149. The exact cases when checkpc() is called can be configured in config.h.
  150. Initialization
  151. --------------
  152. Add a call to CycloneInit(). This is really only needed to be called once at startup
  153. if you enabled COMPRESS_JUMPTABLE in config.h, but you can add this in any case,
  154. it won't hurt.
  155. Almost there - Reset the 68000!
  156. -------------------------------
  157. Cyclone doesn't provide a reset function, so next we need to Reset the 68000 to get
  158. the initial Program Counter and Stack Pointer. This is obtained from addresses
  159. 000000 and 000004.
  160. Here is code which resets the 68000 (using your memory handlers):
  161. MyCpu.state_flags=0; // Go to default state (not stopped, halted, etc.)
  162. MyCpu.srh=0x27; // Set supervisor mode
  163. MyCpu.a[7]=MyCpu.read32(0); // Get Stack Pointer
  164. MyCpu.membase=0; // Will be set by checkpc()
  165. MyCpu.pc=MyCpu.checkpc(MyCpu.read32(4)); // Get Program Counter
  166. And that's ready to go.
  167. Executing the 68000
  168. -------------------
  169. To execute the 68000, set the 'cycles' variable to the number of cycles you wish to execute,
  170. and then call CycloneRun with a pointer to the Cyclone structure.
  171. e.g.:
  172. // Execute 1000 cycles on the 68000:
  173. MyCpu.cycles=1000; CycloneRun(&MyCpu);
  174. For each opcode, the number of cycles it took is subtracted and the function returns when
  175. it reaches negative number. The result is stored back to MyCpu.cycles.
  176. e.g.
  177. // Execute one instruction on the 68000:
  178. MyCpu.cycles=0; CycloneRun(&MyCpu);
  179. printf(" The opcode took %d cycles\n", -MyCpu.cycles);
  180. You should try to execute as many cycles as you can for maximum speed.
  181. The number actually executed may be slightly more than requested, i.e. cycles may come
  182. out with a small negative value:
  183. e.g.
  184. int todo=12000000/60; // 12Mhz, for one 60hz frame
  185. MyCpu.cycles=todo; CycloneRun(&MyCpu);
  186. printf(" Actually executed %d cycles\n", todo-MyCpu.cycles);
  187. To calculate the number of cycles executed, use this formula:
  188. Number of cycles requested - Cycle counter at the end
  189. Interrupts
  190. ----------
  191. Causing an interrupt is very simple, simply set the irq variable in the Cyclone structure
  192. to the IRQ number.
  193. To lower the IRQ line, set it to zero.
  194. e.g:
  195. MyCpu.irq=6; // Interrupt level 6
  196. MyCpu.cycles=20000; CycloneRun(&MyCpu);
  197. Note that the interrupt is not actually processed until the next call to CycloneRun,
  198. and the interrupt may not be taken until the 68000 interrupt mask is changed to allow it.
  199. If you need to force interrupt processing, you can use CycloneFlushIrq() function.
  200. It is the same as doing
  201. MyCpu.cycles=0; CycloneRun(&MyCpu);
  202. but is better optimized and doesn't update .cycles (returns them instead).
  203. This function can't be used from memory handlers and has no effect if interrupt is masked.
  204. The IRQ isn't checked on exiting from a memory handler. If you need to cause interrupt
  205. check immediately, you should change cycle counter to 0 to cause a return from CycloneRun(),
  206. and then call CycloneRun() again or just call CycloneFlushIrq(). Note that you need to
  207. enable MEMHANDLERS_CHANGE_CYCLES in config.h for this to work.
  208. If you need to do something during the interrupt acknowledge (the moment when interrupt
  209. is taken), you can set USE_INT_ACK_CALLBACK in config.h and specify IrqCallback function.
  210. This function should update the IRQ level (.irq variable in context) and return the
  211. interrupt vector number. But for most cases it should return special constant
  212. CYCLONE_INT_ACK_AUTOVECTOR so that Cyclone uses autovectors, which is what most real
  213. systems were doing. Another less commonly used option is to return CYCLONE_INT_ACK_SPURIOUS
  214. for spurious interrupt.
  215. Accessing Program Counter and registers
  216. ---------------------------------------
  217. You can read most Cyclone's registers directly from the structure at any time.
  218. However, the PC value, CCR and cycle counter are cached in ARM registers and can't
  219. be accessed from memory handlers by default. They are written back and can be
  220. accessed after execution.
  221. But if you need to access the mentioned registers during execution, you can set
  222. MEMHANDLERS_NEED_* and MEMHANDLERS_CHANGE_* options in config.h
  223. The Program Counter, should you need to read or write it, is stored with membase
  224. added on. So use this formula to calculate the real 68000 program counter:
  225. pc = MyCpu.pc - MyCpu.membase;
  226. For performance reasons Cyclone keeps the status register split into .srh
  227. (status register "high" supervisor byte), .xc for the X flag, and .flags for remaining
  228. CCR flags (in ARM order). To easily read/write the status register as normal 68k
  229. 16bit SR register, use CycloneGetSr() and CycloneSetSr() utility functions.
  230. Emulating more than one CPU
  231. ---------------------------
  232. Since everything is based on the structures, emulating more than one cpu at the same time
  233. is just a matter of declaring more than one structures and timeslicing. You can emulate
  234. as many 68000s as you want.
  235. Just set up the memory handlers for each cpu and run each cpu for a certain number of cycles.
  236. e.g.
  237. // Execute 1000 cycles on 68000 #1:
  238. MyCpu.cycles=1000; CycloneRun(&MyCpu);
  239. // Execute 1000 cycles on 68000 #2:
  240. MyCpu2.cycles=1000; CycloneRun(&MyCpu2);
  241. Quick API reference
  242. -------------------
  243. void CycloneInit(void);
  244. Initializes Cyclone. Must be called if the jumptable is compressed,
  245. doesn't matter otherwise.
  246. void CycloneRun(struct Cyclone *pcy);
  247. Runs cyclone for pcy->cycles. Writes amount of cycles left back to
  248. pcy->cycles (always negative).
  249. unsigned int CycloneGetSr(const struct Cyclone *pcy);
  250. Reads status register in internal form from pcy, converts to standard 68k SR and returns it.
  251. void CycloneSetSr(struct Cyclone *pcy, unsigned int sr);
  252. Takes standard 68k status register (sr), and updates Cyclone context with it.
  253. int CycloneFlushIrq(struct Cyclone *pcy);
  254. If .irq is greater than IRQ mask in SR, or it is equal to 7 (NMI), processes interrupt
  255. exception and returns number of cycles used. Otherwise, does nothing and returns 0.
  256. void CyclonePack(const struct Cyclone *pcy, void *save_buffer);
  257. Writes Cyclone state to save_buffer. This allows to avoid all the trouble figuring what
  258. actually needs to be saved from the Cyclone structure, as saving whole struct Cyclone
  259. to a file will also save various pointers, which may become invalid after your program
  260. is restarted, so simply reloading the structure will cause a crash. save_buffer size
  261. should be 128 bytes (now it is really using less, but this allows future expansion).
  262. void CycloneUnpack(struct Cyclone *pcy, const void *save_buffer);
  263. Reloads Cyclone state from save_buffer, which was previously saved by CyclonePack().
  264. This function uses checkpc() callback to rebase the PC, so .checkpc must be initialized
  265. before calling it.
  266. Callbacks:
  267. .checkpc
  268. unsigned int (*checkpc)(unsigned int pc);
  269. This function is called when PC changes are performed in 68k code or because of exceptions.
  270. It is passed ARM pointer and should return ARM pointer casted to int. It must also update
  271. .membase if needed. See "The checkpc() function" section above.
  272. unsigned int (*read8 )(unsigned int a);
  273. unsigned int (*read16 )(unsigned int a);
  274. unsigned int (*read32 )(unsigned int a);
  275. These are the read memory handler callbacks. They are called when 68k code reads from memory.
  276. The parameter is a 68k address in data space, return value is a data value read. Data value
  277. doesn't have to be masked to 8 or 16 bits for read8 or read16, Cyclone will do that itself
  278. if needed.
  279. unsigned int (*fetch8 )(unsigned int a);
  280. unsigned int (*fetch16)(unsigned int a);
  281. unsigned int (*fetch32)(unsigned int a);
  282. Same as above, but these are reads from program space (PC relative reads mostly).
  283. void (*write8 )(unsigned int a,unsigned char d);
  284. void (*write16)(unsigned int a,unsigned short d);
  285. void (*write32)(unsigned int a,unsigned int d);
  286. These are called when 68k code writes to data space. d is the data value.
  287. int (*IrqCallback)(int int_level);
  288. This function is called when Cyclone acknowledges an interrupt. The parameter is the IRQ
  289. level being acknowledged, and return value is exception vector to use, or one of these special
  290. values: CYCLONE_INT_ACK_AUTOVECTOR or CYCLONE_INT_ACK_SPURIOUS. Can be disabled in config.h.
  291. See "Interrupts" section for more information.
  292. void (*ResetCallback)(void);
  293. Cyclone will call this function if it encounters RESET 68k instruction.
  294. Can be disabled in config.h.
  295. int (*UnrecognizedCallback)(void);
  296. Cyclone will call this function if it encounters illegal instructions (including A-line and
  297. F-line ones). Can be tuned / disabled in config.h.
  298. Function codes
  299. --------------
  300. Cyclone doesn't pass function codes to it's memory handlers, but they can be calculated:
  301. FC2: just use supervisor state bit from status register (eg. (MyCpu.srh & 0x20) >> 5)
  302. FC1: if we are in fetch* function, then 1, else 0.
  303. FC0: if we are in read* or write*, then 1, else 0.
  304. CPU state (all FC bits set) is active in IrqCallback function.
  305. References
  306. ----------
  307. These documents were used while writing Cyclone and should be useful for those who want to
  308. understand deeper how the 68000 works.
  309. MOTOROLA M68000 FAMILY Programmer's Reference Manual
  310. common name: 68kPM.pdf
  311. M68000 8-/16-/32-Bit Microprocessors User's Manual
  312. common name: MC68000UM.pdf
  313. 68000 Undocumented Behavior Notes by Bart Trzynadlowski
  314. http://www.trzy.org/files/68knotes.txt
  315. Instruction prefetch on the Motorola 68000 processor by Jorge Cwik
  316. http://pasti.fxatari.com/68kdocs/68kPrefetch.html
  317. ARM Register Usage
  318. ------------------
  319. See source code for up to date of register usage, however a summary is here:
  320. r0-3: Temporary registers
  321. r4 : Current PC + Memory Base (i.e. pointer to next opcode)
  322. r5 : Cycles remaining
  323. r6 : Pointer to Opcode Jump table
  324. r7 : Pointer to Cpu Context
  325. r8 : Current Opcode
  326. r10 : Flags (NZCV) in highest four bits
  327. (r11 : Temporary register)
  328. Flags are mapped onto ARM flags whenever possible, which speeds up the processing of opcode.
  329. r9 is not used intentionally, because AAPCS defines it as "platform register", so it's
  330. reserved in some systems.
  331. Thanks to...
  332. ------------
  333. * All the previous code-generating assembler cpu core guys!
  334. Who are iirc... Neill Corlett, Neil Bradley, Mike Coates, Darren Olafson
  335. Karl Stenerud and Bart Trzynadlowski
  336. * Charles Macdonald, for researching just about every console ever
  337. * MameDev+FBA, for keeping on going and going and going
  338. What's New
  339. ----------
  340. v0.0099 notaz
  341. * Cyclone no longer uses r9, because AAPCS defines it as "platform register",
  342. so it's reserved in some systems.
  343. * Made SPLIT_MOVEL_PD to affect MOVEM too.
  344. v0.0088 notaz
  345. - Reduced amount of code in opcode handlers by ~23% by doing the following:
  346. - Removed duplicate opcode handlers
  347. - Optimized code to use less ARM instructions
  348. - Merged some duplicate handler endings
  349. + Cyclone now does better job avoiding pipeline interlocks.
  350. + Replaced incorrect handler of DBT with proper one.
  351. + Changed "MOVEA (An)+ An" behavior.
  352. + Fixed flag behavior of ROXR, ASL, LSR and NBCD in certain situations.
  353. Hopefully got them right now.
  354. + Cyclone no longer sets most significant bits while pushing PC to stack.
  355. Amiga Kickstart depends on this.
  356. + Added optional trace mode emulation.
  357. + Added optional address error emulation.
  358. + Additional functionality added for MAME and other ports (see config.h).
  359. + Added return value for IrqCallback to make it suitable for emulating devices which
  360. pass the vector number during interrupt acknowledge cycle. For usual autovector
  361. processing this function must return CYCLONE_INT_ACK_AUTOVECTOR, so those who are
  362. upgrading must add "return CYCLONE_INT_ACK_AUTOVECTOR;" to their IrqCallback functions.
  363. * Updated documentation.
  364. v0.0086 notaz
  365. + Cyclone now can be customized to better suit your project, see config.h .
  366. + Added an option to compress the jumptable at compile-time. Must call CycloneInit()
  367. at runtime to decompress it if enabled (see config.h).
  368. + Added missing CHK opcode handler (used by SeaQuest DSV).
  369. + Added missing TAS opcode handler (Gargoyles,Bubba N Stix,...). As in real genesis,
  370. memory write-back phase is ignored (but can be enabled in config.h if needed).
  371. + Added missing NBCD and TRAPV opcode handlers.
  372. + Added missing addressing mode for CMP/EOR.
  373. + Added some minor optimizations.
  374. - Removed 216 handlers for 2927 opcodes which were generated for invalid addressing modes.
  375. + Fixed flags for ASL, NEG, NEGX, DIVU, ADDX, SUBX, ROXR.
  376. + Bugs fixed in MOVEP, LINK, ADDQ, DIVS handlers.
  377. * Undocumented flags for CHK, ABCD, SBCD and NBCD are now emulated the same way as in Musashi.
  378. + Added Uninitialized Interrupt emulation.
  379. + Altered timing for about half of opcodes to match Musashi's.
  380. v0.0082 Reesy
  381. + Change cyclone to clear cycles before returning when halted
  382. + Added Irq call back function. This allows emulators to be notified
  383. when cyclone has taken an interrupt allowing them to set internal flags
  384. which can help fix timing problems.
  385. v0.0081 notaz
  386. + .asm version was broken and did not compile with armasm. Fixed.
  387. + Finished implementing Stop opcode. Now it really stops the processor.
  388. v0.0080 notaz
  389. + Added real cmpm opcode, it was using eor handler before this.
  390. Fixes Dune and Sensible Soccer.
  391. v0.0078 notaz
  392. note: these bugs were actually found Reesy, I reimplemented these by
  393. using his changelog as a guide.
  394. + Fixed a problem with divu which was using long divisor instead of word.
  395. Fixes gear switching in Top Gear 2.
  396. + Fixed btst opcode, The bit to test should shifted a max of 31 or 7
  397. depending on if a register or memory location is being tested.
  398. + Fixed abcd,sbcd. They did bad decimal correction on invalid BCD numbers
  399. Score counters in Streets of Rage level end work now.
  400. + Changed flag handling of abcd,sbcd,addx,subx,asl,lsl,...
  401. Some ops did not have flag handling at all.
  402. Some ops must not change Z flag when result is zero, but they did.
  403. Shift ops must not change X if shift count is zero, but they did.
  404. There are probably still some flag problems left.
  405. + Patially implemented Stop and Reset opcodes - Fixes Thunderforce IV
  406. v0.0075 notaz
  407. + Added missing displacement addressing mode for movem (Fantastic Dizzy)
  408. + Added OSP <-> A7 swapping code in opcodes, which change privilege mode
  409. + Implemented privilege violation, line emulator and divide by zero exceptions
  410. + Added negx opcode (Shining Force works!)
  411. + Added overflow detection for divs/divu
  412. v0.0072 notaz
  413. note: I could only get v0.0069 cyclone, so I had to implement these myself using Dave's
  414. changelog as a guide.
  415. + Fixed a problem with divs - remainder should be negative when divident is negative
  416. + Added movep opcode (Sonic 3 works)
  417. + Fixed a problem with DBcc incorrectly decrementing if the condition is true (Shadow of the Beast)
  418. v0.0069
  419. + Added SBCD and the flags for ABCD/SBCD. Score and time now works in games such as
  420. Rolling Thunder 2, Ghouls 'N Ghosts
  421. + Fixed a problem with addx and subx with 8-bit and 16-bit values.
  422. Ghouls 'N' Ghosts now works!
  423. v0.0068
  424. + Added ABCD opcode (Streets of Rage works now!)
  425. v0.0067
  426. + Added dbCC (After Burner)
  427. + Added asr EA (Sonic 1 Boss/Labyrinth Zone)
  428. + Added andi/ori/eori ccr (Altered Beast)
  429. + Added trap (After Burner)
  430. + Added special case for move.b (a7)+ and -(a7), stepping by 2
  431. After Burner is playable! Eternal Champions shows more
  432. + Fixed lsr.b/w zero flag (Ghostbusters)
  433. Rolling Thunder 2 now works!
  434. + Fixed N flag for .b and .w arithmetic. Golden Axe works!
  435. v0.0066
  436. + Fixed a stupid typo for exg (orr r10,r10, not orr r10,r8), which caused alignment
  437. crashes on Strider
  438. v0.0065
  439. + Fixed a problem with immediate values - they weren't being shifted up correctly for some
  440. opcodes. Spiderman works, After Burner shows a bit of graphics.
  441. + Fixed a problem with EA:"110nnn" extension word. 32-bit offsets were being decoded as 8-bit
  442. offsets by mistake. Castlevania Bloodlines seems fine now.
  443. + Added exg opcode
  444. + Fixed asr opcode (Sonic jumping left is fixed)
  445. + Fixed a problem with the carry bit in rol.b (Marble Madness)
  446. v0.0064
  447. + Added rtr
  448. + Fixed addq/subq.l (all An opcodes are 32-bit) (Road Rash)
  449. + Fixed various little timings
  450. v0.0063
  451. + Added link/unlk opcodes
  452. + Fixed various little timings
  453. + Fixed a problem with dbCC opcode being emitted at set opcodes
  454. + Improved long register access, the EA fetch now does ldr r0,[r7,r0,lsl #2] whenever
  455. possible, saving 1 or 2 cycles on many opcodes, which should give a nice speed up.
  456. + May have fixed N flag on ext opcode?
  457. + Added dasm for link opcode.
  458. v0.0062
  459. * I was a bit too keen with the Arithmetic opcodes! Some of them should have been abcd,
  460. exg and addx. Removed the incorrect opcodes, pending re-adding them as abcd, exg and addx.
  461. + Changed unknown opcodes to act as nops.
  462. Not very technical, but fun - a few more games show more graphics ;)
  463. v0.0060
  464. + Fixed divu (EA intro)
  465. + Added sf (set false) opcode - SOR2
  466. * Todo: pea/link/unlk opcodes
  467. v0.0059: Added remainder to divide opcodes.