ssp16.c 33 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212
  1. // basic, incomplete SSP160x (SSP1601?) interpreter
  2. // with SVP memory controller emu
  3. // (c) Copyright 2008, Grazvydas "notaz" Ignotas
  4. // Free for non-commercial use.
  5. // For commercial use, separate licencing terms must be obtained.
  6. #include "../../PicoInt.h"
  7. /*
  8. * Register info
  9. *
  10. * 0. "-"
  11. * size: 16
  12. * desc: Constant register with all bits set (0xffff).
  13. *
  14. * 1. "X"
  15. * size: 16
  16. * desc: Generic register. When set, updates P (P = X * Y * 2)
  17. *
  18. * 2. "Y"
  19. * size: 16
  20. * desc: Generic register. When set, updates P (P = X * Y * 2)
  21. *
  22. * 3. "A"
  23. * size: 32
  24. * desc: Accumulator.
  25. *
  26. * 4. "ST"
  27. * size: 16
  28. * desc: Status register. From MAME: bits 0-9 are CONTROL, other FLAG
  29. * fedc ba98 7654 3210
  30. * 210 - RPL (?) "Loop size". If non-zero, makes (rX+) and (rX-) respectively
  31. * modulo-increment and modulo-decrement. The value shows which
  32. * power of 2 to use, i.e. 4 means modulo by 16.
  33. * (e: fir16_32.sc, IIR_4B.SC, DECIM.SC)
  34. * 43 - RB (?)
  35. * 5 - GP0_0 (ST5?) Changed before acessing PM0 (affects banking?).
  36. * 6 - GP0_1 (ST6?) Cleared before acessing PM0 (affects banking?). Set after.
  37. * datasheet says these (5,6) bits correspond to hardware pins.
  38. * 7 - IE (?) Not directly used by SVP code (never set, but preserved)?
  39. * 8 - OP (?) Not used by SVP code (only cleared)? (MAME: saturated value
  40. * (probably means clamping? i.e. 0x7ffc + 9 -> 0x7fff))
  41. * 9 - MACS (?) Not used by SVP code (only cleared)? (e: "mac shift")
  42. * a - GPI_0 Interrupt 0 enable/status?
  43. * b - GPI_1 Interrupt 1 enable/status?
  44. * c - L L flag. Carry?
  45. * d - Z Zero flag.
  46. * e - OV Overflow flag.
  47. * f - N Negative flag.
  48. * seen directly changing code sequences:
  49. * ldi ST, 0 ld A, ST ld A, ST ld A, ST ldi st, 20h
  50. * ldi ST, 60h ori A, 60h and A, E8h and A, E8h
  51. * ld ST, A ld ST, A ori 3
  52. * ld ST, A
  53. *
  54. * 5. "STACK"
  55. * size: 16
  56. * desc: hw stack of 6 levels (according to datasheet)
  57. *
  58. * 6. "PC"
  59. * size: 16
  60. * desc: Program counter.
  61. *
  62. * 7. "P"
  63. * size: 32
  64. * desc: multiply result register. P = X * Y * 2
  65. * probably affected by MACS bit in ST.
  66. *
  67. * 8. "PM0" (PM from PMAR name from Tasco's docs)
  68. * size: 16?
  69. * desc: Programmable Memory access register.
  70. * On reset, or when one (both?) GP0 bits are clear,
  71. * acts as status for XST, mapped at 015004 at 68k side:
  72. * bit0: ssp has written something to XST (cleared when 015004 is read)
  73. * bit1: 68k has written something through a1500{0|2} (cleared on PM0 read)
  74. *
  75. * 9. "PM1"
  76. * size: 16?
  77. * desc: Programmable Memory access register.
  78. * This reg. is only used as PMAR.
  79. *
  80. * 10. "PM2"
  81. * size: 16?
  82. * desc: Programmable Memory access register.
  83. * This reg. is only used as PMAR.
  84. *
  85. * 11. "XST"
  86. * size: 16?
  87. * desc: eXternal STate. Mapped to a15000 and a15002 at 68k side.
  88. * Can be programmed as PMAR? (only seen in test mode code)
  89. * Affects PM0 when written to?
  90. *
  91. * 12. "PM4"
  92. * size: 16?
  93. * desc: Programmable Memory access register.
  94. * This reg. is only used as PMAR. The most used PMAR by VR.
  95. *
  96. * 13. (unused by VR)
  97. *
  98. * 14. "PMC" (PMC from PMAC name from Tasco's docs)
  99. * size: 32?
  100. * desc: Programmable Memory access Control. Set using 2 16bit writes,
  101. * first address, then mode word. After setting PMAC, PMAR sould
  102. * be blind accessed (ld -, PMx or ld PMx, -) to program it for
  103. * reading and writing respectively.
  104. * Reading the register also shifts it's state (from "waiting for
  105. * address" to "waiting for mode" and back). Reads always return
  106. * address related to last PMx register accressed.
  107. * (note: addresses do not wrap).
  108. *
  109. * 15. "AL"
  110. * size: 16
  111. * desc: Accumulator Low. 16 least significant bits of accumulator.
  112. * (normally reading acc (ld X, A) you get 16 most significant bits).
  113. *
  114. *
  115. * There are 8 8-bit pointer registers rX. r0-r3 (ri) point to RAM0, r4-r7 (rj) point to RAM1.
  116. * They can be accessed directly, or 2 indirection levels can be used [ (rX), ((rX)) ],
  117. * which work similar to * and ** operators in C, only they use different memory banks and
  118. * ((rX)) also does post-increment. First indirection level (rX) accesses RAMx, second accesses
  119. * program memory at address read from (rX), and increments value in (rX).
  120. *
  121. * r0,r1,r2,r4,r5,r6 can be modified [ex: ldi r0, 5].
  122. * 3 modifiers can be applied (optional):
  123. * + : post-increment [ex: ld a, (r0+) ]. Can be made modulo-increment by setting RPL bits in ST.
  124. * - : post-decrement. Can be made modulo-decrement by setting RPL bits in ST (not sure).
  125. * +!: post-increment, unaffected by RPL (probably).
  126. * These are only used on 1st indirection level, so things like [ld a, ((r0+))] and [ld X, r6-]
  127. * ar probably invalid.
  128. *
  129. * r3 and r7 are special and can not be changed (at least Samsung samples and SVP code never do).
  130. * They are fixed to the start of their RAM banks. (They are probably changeable for ssp1605+,
  131. * Samsung's old DSP page claims that).
  132. * 1 of these 4 modifiers must be used (short form direct addressing?):
  133. * |00: RAMx[0] [ex: (r3|00), 0] (based on sample code)
  134. * |01: RAMx[1]
  135. * |10: RAMx[2] ? maybe 10h? accortding to Div_c_dp.sc, 2
  136. * |11: RAMx[3]
  137. *
  138. *
  139. * Instruction notes
  140. *
  141. * ld a, * doesn't affect flags! (e: A_LAW.SC, Div_c_dp.sc)
  142. *
  143. * mld (rj), (ri) [, b]
  144. * operation: A = 0; P = (rj) * (ri)
  145. * notes: based on IIR_4B.SC sample. flags? what is b???
  146. *
  147. * mpya (rj), (ri) [, b]
  148. * name: multiply and add?
  149. * operation: A += P; P = (rj) * (ri)
  150. *
  151. * mpys (rj), (ri), b
  152. * name: multiply and subtract?
  153. * notes: not used by VR code.
  154. *
  155. * mod cond, op
  156. * mod cond, shr does arithmetic shift
  157. *
  158. * 'ld -, AL' and probably 'ld AL, -' are for dummy assigns
  159. *
  160. * memory map:
  161. * 000000 - 1fffff ROM, accessable by both
  162. * 200000 - 2fffff unused?
  163. * 300000 - 31ffff DRAM, both
  164. * 320000 - 38ffff unused?
  165. * 390000 - 3907ff IRAM. can only be accessed by ssp?
  166. * 390000 - 39ffff similar mapping to "cell arrange" in Sega CD, 68k only?
  167. * 3a0000 - 3affff similar mapping to "cell arrange" in Sega CD, a bit different
  168. *
  169. * 30fe02 - 0 if SVP busy, 1 if done (set by SVP, checked and cleared by 68k)
  170. * 30fe06 - also sync related.
  171. * 30fe08 - job number [1-12] for SVP. 0 means no job. Set by 68k, read-cleared by SVP.
  172. *
  173. * + figure out if 'op A, P' is 32bit (nearly sure it is)
  174. * * does mld, mpya load their operands into X and Y?
  175. * * OP simm
  176. *
  177. * Assumptions in this code
  178. * P is not directly writeable
  179. * flags correspond to full 32bit accumulator
  180. * only Z and N status flags are emulated (others unused by SVP)
  181. * modifiers for 'OP a, ri' are ignored (invalid?/not used by SVP)
  182. */
  183. #include "../../PicoInt.h"
  184. #define u32 unsigned int
  185. //#define USE_DEBUGGER
  186. // 0
  187. #define rX ssp->gr[SSP_X].h
  188. #define rY ssp->gr[SSP_Y].h
  189. #define rA ssp->gr[SSP_A].h
  190. #define rST ssp->gr[SSP_ST].h // 4
  191. #define rSTACK ssp->gr[SSP_STACK].h
  192. #define rPC ssp->gr[SSP_PC].h
  193. #define rP ssp->gr[SSP_P]
  194. #define rPM0 ssp->gr[SSP_PM0].h // 8
  195. #define rPM1 ssp->gr[SSP_PM1].h
  196. #define rPM2 ssp->gr[SSP_PM2].h
  197. #define rXST ssp->gr[SSP_XST].h
  198. #define rPM4 ssp->gr[SSP_PM4].h // 12
  199. // 13
  200. #define rPMC ssp->gr[SSP_PMC] // will keep addr in .l, mode in .h
  201. #define rAL ssp->gr[SSP_A].l
  202. #define rA32 ssp->gr[SSP_A].v
  203. #define rIJ ssp->r
  204. #define IJind (((op>>6)&4)|(op&3))
  205. #ifndef EMBED_INTERPRETER
  206. #define GET_PC() (PC - (unsigned short *)svp->iram_rom)
  207. #define GET_PPC_OFFS() ((unsigned int)PC - (unsigned int)svp->iram_rom - 2)
  208. #define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d
  209. #endif
  210. #define REG_READ(r) (((r) <= 4) ? ssp->gr[r].h : read_handlers[r]())
  211. #define REG_WRITE(r,d) { \
  212. int r1 = r; \
  213. if (r1 >= 4) write_handlers[r1](d); \
  214. else if (r1 > 0) ssp->gr[r1].h = d; \
  215. }
  216. // flags
  217. #define SSP_FLAG_L (1<<0xc)
  218. #define SSP_FLAG_Z (1<<0xd)
  219. #define SSP_FLAG_V (1<<0xe)
  220. #define SSP_FLAG_N (1<<0xf)
  221. // update ZN according to 32bit ACC.
  222. #define UPD_ACC_ZN \
  223. rST &= ~(SSP_FLAG_Z|SSP_FLAG_N); \
  224. if (!rA32) rST |= SSP_FLAG_Z; \
  225. else rST |= (rA32>>16)&SSP_FLAG_N;
  226. // it seems SVP code never checks for L and OV, so we leave them out.
  227. // rST |= (t>>4)&SSP_FLAG_L;
  228. #define UPD_LZVN \
  229. rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
  230. if (!rA32) rST |= SSP_FLAG_Z; \
  231. else rST |= (rA32>>16)&SSP_FLAG_N;
  232. // standard cond processing.
  233. // again, only Z and N is checked, as SVP doesn't seem to use any other conds.
  234. #define COND_CHECK \
  235. switch (op&0xf0) { \
  236. case 0x00: cond = 1; break; /* always true */ \
  237. case 0x50: cond = !((rST ^ (op<<5)) & SSP_FLAG_Z); break; /* Z matches f(?) bit */ \
  238. case 0x70: cond = !((rST ^ (op<<7)) & SSP_FLAG_N); break; /* N matches f(?) bit */ \
  239. default:elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unimplemented cond @ %04x", GET_PPC_OFFS()); break; \
  240. }
  241. // ops with accumulator.
  242. // how is low word really affected by these?
  243. // nearly sure 'ld A' doesn't affect flags
  244. #define OP_LDA(x) \
  245. ssp->gr[SSP_A].h = x
  246. #define OP_LDA32(x) \
  247. rA32 = x
  248. #define OP_SUBA(x) { \
  249. rA32 -= (x) << 16; \
  250. UPD_LZVN \
  251. }
  252. #define OP_SUBA32(x) { \
  253. rA32 -= (x); \
  254. UPD_LZVN \
  255. }
  256. #define OP_CMPA(x) { \
  257. u32 t = rA32 - ((x) << 16); \
  258. rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
  259. if (!t) rST |= SSP_FLAG_Z; \
  260. else rST |= (t>>16)&SSP_FLAG_N; \
  261. }
  262. #define OP_CMPA32(x) { \
  263. u32 t = rA32 - (x); \
  264. rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
  265. if (!t) rST |= SSP_FLAG_Z; \
  266. else rST |= (t>>16)&SSP_FLAG_N; \
  267. }
  268. #define OP_ADDA(x) { \
  269. rA32 += (x) << 16; \
  270. UPD_LZVN \
  271. }
  272. #define OP_ADDA32(x) { \
  273. rA32 += (x); \
  274. UPD_LZVN \
  275. }
  276. #define OP_ANDA(x) \
  277. rA32 &= (x) << 16; \
  278. UPD_ACC_ZN
  279. #define OP_ANDA32(x) \
  280. rA32 &= (x); \
  281. UPD_ACC_ZN
  282. #define OP_ORA(x) \
  283. rA32 |= (x) << 16; \
  284. UPD_ACC_ZN
  285. #define OP_ORA32(x) \
  286. rA32 |= (x); \
  287. UPD_ACC_ZN
  288. #define OP_EORA(x) \
  289. rA32 ^= (x) << 16; \
  290. UPD_ACC_ZN
  291. #define OP_EORA32(x) \
  292. rA32 ^= (x); \
  293. UPD_ACC_ZN
  294. #define OP_CHECK32(OP) \
  295. if ((op & 0x0f) == SSP_P) { /* A <- P */ \
  296. read_P(); /* update P */ \
  297. OP(rP.v); \
  298. break; \
  299. }
  300. static ssp1601_t *ssp = NULL;
  301. static unsigned short *PC;
  302. static int g_cycles;
  303. #ifdef USE_DEBUGGER
  304. static int running = 0;
  305. static int last_iram = 0;
  306. #endif
  307. #ifdef EMBED_INTERPRETER
  308. static int iram_dirty = 0;
  309. #endif
  310. // -----------------------------------------------------
  311. // register i/o handlers
  312. // 0-4, 13
  313. static u32 read_unknown(void)
  314. {
  315. elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown read @ %04x", GET_PPC_OFFS());
  316. return 0;
  317. }
  318. static void write_unknown(u32 d)
  319. {
  320. elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown write @ %04x", GET_PPC_OFFS());
  321. }
  322. // 4
  323. static void write_ST(u32 d)
  324. {
  325. //if ((rST ^ d) & 0x0007) elprintf(EL_SVP, "ssp RPL %i -> %i @ %04x", rST&7, d&7, GET_PPC_OFFS());
  326. if ((rST ^ d) & 0x0f98) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME ST %04x -> %04x @ %04x", rST, d, GET_PPC_OFFS());
  327. rST = d;
  328. }
  329. // 5
  330. static u32 read_STACK(void)
  331. {
  332. --rSTACK;
  333. if ((short)rSTACK < 0) {
  334. rSTACK = 5;
  335. elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack underflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
  336. }
  337. return ssp->stack[rSTACK];
  338. }
  339. static void write_STACK(u32 d)
  340. {
  341. if (rSTACK >= 6) {
  342. elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack overflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
  343. rSTACK = 0;
  344. }
  345. ssp->stack[rSTACK++] = d;
  346. }
  347. // 6
  348. static u32 read_PC(void)
  349. {
  350. return GET_PC();
  351. }
  352. static void write_PC(u32 d)
  353. {
  354. SET_PC(d);
  355. g_cycles--;
  356. }
  357. // 7
  358. static u32 read_P(void)
  359. {
  360. int m1 = (signed short)rX;
  361. int m2 = (signed short)rY;
  362. rP.v = (m1 * m2 * 2);
  363. return rP.h;
  364. }
  365. // -----------------------------------------------------
  366. static int get_inc(int mode)
  367. {
  368. int inc = (mode >> 11) & 7;
  369. if (inc != 0) {
  370. if (inc != 7) inc--;
  371. inc = 1 << inc; // 0 1 2 4 8 16 32 128
  372. if (mode & 0x8000) inc = -inc; // decrement mode
  373. }
  374. return inc;
  375. }
  376. #define overwite_write(dst, d) \
  377. { \
  378. if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
  379. if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
  380. if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
  381. if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
  382. }
  383. static u32 pm_io(int reg, int write, u32 d)
  384. {
  385. if (ssp->emu_status & SSP_PMC_SET)
  386. {
  387. // this MUST be blind r or w
  388. if ((*(PC-1) & 0xff0f) && (*(PC-1) & 0xfff0)) {
  389. elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: tried to set PM%i (%c) with non-blind i/o %08x @ %04x",
  390. reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
  391. ssp->emu_status &= ~SSP_PMC_SET;
  392. return 0;
  393. }
  394. elprintf(EL_SVP, "PM%i (%c) set to %08x @ %04x", reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
  395. ssp->pmac_read[write ? reg + 6 : reg] = rPMC.v;
  396. ssp->emu_status &= ~SSP_PMC_SET;
  397. if ((rPMC.v & 0x7fffff) == 0x1c8000 || (rPMC.v & 0x7fffff) == 0x1c8240) {
  398. elprintf(EL_SVP, "ssp IRAM copy from %06x", (ssp->RAM1[0]-1)<<1);
  399. #ifdef USE_DEBUGGER
  400. last_iram = (ssp->RAM1[0]-1)<<1;
  401. #endif
  402. #ifdef EMBED_INTERPRETER
  403. iram_dirty = 1;
  404. #endif
  405. }
  406. return 0;
  407. }
  408. // just in case
  409. if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
  410. elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i (%c) with only addr set @ %04x",
  411. reg, write ? 'w' : 'r', GET_PPC_OFFS());
  412. ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
  413. }
  414. if (reg == 4 || (rST & 0x60))
  415. {
  416. #define CADDR ((((mode<<16)&0x7f0000)|addr)<<1)
  417. unsigned short *dram = (unsigned short *)svp->dram;
  418. if (write)
  419. {
  420. int mode = ssp->pmac_write[reg]>>16;
  421. int addr = ssp->pmac_write[reg]&0xffff;
  422. if ((mode & 0xb800) == 0xb800)
  423. elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: mode %04x", mode);
  424. if ((mode & 0x43ff) == 0x0018) // DRAM
  425. {
  426. int inc = get_inc(mode);
  427. elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (inc %i, ovrw %i)",
  428. reg, CADDR, d, inc, (mode>>10)&1);
  429. if (mode & 0x0400) {
  430. overwite_write(dram[addr], d);
  431. } else dram[addr] = d;
  432. ssp->pmac_write[reg] += inc;
  433. }
  434. else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
  435. {
  436. elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (cell inc, ovrw %i) @ %04x",
  437. reg, CADDR, d, (mode>>10)&1, GET_PPC_OFFS());
  438. if (mode & 0x0400) {
  439. overwite_write(dram[addr], d);
  440. } else dram[addr] = d;
  441. ssp->pmac_write[reg] += (addr&1) ? 31 : 1;
  442. }
  443. else if ((mode & 0x47ff) == 0x001c) // IRAM
  444. {
  445. int inc = get_inc(mode);
  446. if ((addr&0xfc00) != 0x8000)
  447. elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid IRAM addr: %04x", addr<<1);
  448. elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc);
  449. ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
  450. ssp->pmac_write[reg] += inc;
  451. }
  452. else
  453. {
  454. elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled write mode %04x, [%06x] %04x @ %04x",
  455. reg, mode, CADDR, d, GET_PPC_OFFS());
  456. }
  457. }
  458. else
  459. {
  460. int mode = ssp->pmac_read[reg]>>16;
  461. int addr = ssp->pmac_read[reg]&0xffff;
  462. if ((mode & 0xfff0) == 0x0800) // ROM, inc 1, verified to be correct
  463. {
  464. elprintf(EL_SVP, "ssp ROM r [%06x] %04x", CADDR,
  465. ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)]);
  466. ssp->pmac_read[reg] += 1;
  467. d = ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)];
  468. }
  469. else if ((mode & 0x47ff) == 0x0018) // DRAM
  470. {
  471. int inc = get_inc(mode);
  472. elprintf(EL_SVP, "ssp PM%i DRAM r [%06x] %04x (inc %i)", reg, CADDR, dram[addr]);
  473. d = dram[addr];
  474. ssp->pmac_read[reg] += inc;
  475. }
  476. else
  477. {
  478. elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled read mode %04x, [%06x] @ %04x",
  479. reg, mode, CADDR, GET_PPC_OFFS());
  480. d = 0;
  481. }
  482. }
  483. // PMC value corresponds to last PMR accessed (not sure).
  484. rPMC.v = ssp->pmac_read[write ? reg + 6 : reg];
  485. return d;
  486. }
  487. return (u32)-1;
  488. }
  489. // 8
  490. static u32 read_PM0(void)
  491. {
  492. u32 d = pm_io(0, 0, 0);
  493. if (d != (u32)-1) return d;
  494. elprintf(EL_SVP, "PM0 raw r %04x @ %04x", rPM0, GET_PPC_OFFS());
  495. d = rPM0;
  496. #ifndef EMBED_INTERPRETER
  497. if (!(d & 2) && (GET_PPC_OFFS() == 0x800 || GET_PPC_OFFS() == 0x1851E)) {
  498. ssp->emu_status |= SSP_WAIT_PM0; elprintf(EL_SVP, "det TIGHT loop: PM0");
  499. }
  500. #endif
  501. rPM0 &= ~2; // ?
  502. return d;
  503. }
  504. static void write_PM0(u32 d)
  505. {
  506. u32 r = pm_io(0, 1, d);
  507. if (r != (u32)-1) return;
  508. elprintf(EL_SVP, "PM0 raw w %04x @ %04x", d, GET_PPC_OFFS());
  509. rPM0 = d;
  510. }
  511. // 9
  512. static u32 read_PM1(void)
  513. {
  514. u32 d = pm_io(1, 0, 0);
  515. if (d != (u32)-1) return d;
  516. // can be removed?
  517. elprintf(EL_SVP|EL_ANOMALY, "PM1 raw r %04x @ %04x", rPM1, GET_PPC_OFFS());
  518. return rPM1;
  519. }
  520. static void write_PM1(u32 d)
  521. {
  522. u32 r = pm_io(1, 1, d);
  523. if (r != (u32)-1) return;
  524. // can be removed?
  525. elprintf(EL_SVP|EL_ANOMALY, "PM1 raw w %04x @ %04x", d, GET_PPC_OFFS());
  526. rPM1 = d;
  527. }
  528. // 10
  529. static u32 read_PM2(void)
  530. {
  531. u32 d = pm_io(2, 0, 0);
  532. if (d != (u32)-1) return d;
  533. // can be removed?
  534. elprintf(EL_SVP|EL_ANOMALY, "PM2 raw r %04x @ %04x", rPM2, GET_PPC_OFFS());
  535. return rPM2;
  536. }
  537. static void write_PM2(u32 d)
  538. {
  539. u32 r = pm_io(2, 1, d);
  540. if (r != (u32)-1) return;
  541. // can be removed?
  542. elprintf(EL_SVP|EL_ANOMALY, "PM2 raw w %04x @ %04x", d, GET_PPC_OFFS());
  543. rPM2 = d;
  544. }
  545. // 11
  546. static u32 read_XST(void)
  547. {
  548. // can be removed?
  549. u32 d = pm_io(3, 0, 0);
  550. if (d != (u32)-1) return d;
  551. elprintf(EL_SVP, "XST raw r %04x @ %04x", rXST, GET_PPC_OFFS());
  552. return rXST;
  553. }
  554. static void write_XST(u32 d)
  555. {
  556. // can be removed?
  557. u32 r = pm_io(3, 1, d);
  558. if (r != (u32)-1) return;
  559. elprintf(EL_SVP, "XST raw w %04x @ %04x", d, GET_PPC_OFFS());
  560. rPM0 |= 1;
  561. rXST = d;
  562. }
  563. // 12
  564. static u32 read_PM4(void)
  565. {
  566. u32 d = pm_io(4, 0, 0);
  567. #ifndef EMBED_INTERPRETER
  568. if (d == 0) {
  569. switch (GET_PPC_OFFS()) {
  570. case 0x0854: ssp->emu_status |= SSP_WAIT_30FE08; elprintf(EL_SVP, "det TIGHT loop: [30fe08]"); break;
  571. case 0x4f12: ssp->emu_status |= SSP_WAIT_30FE06; elprintf(EL_SVP, "det TIGHT loop: [30fe06]"); break;
  572. }
  573. }
  574. #endif
  575. if (d != (u32)-1) return d;
  576. // can be removed?
  577. elprintf(EL_SVP|EL_ANOMALY, "PM4 raw r %04x @ %04x", rPM4, GET_PPC_OFFS());
  578. return rPM4;
  579. }
  580. static void write_PM4(u32 d)
  581. {
  582. u32 r = pm_io(4, 1, d);
  583. if (r != (u32)-1) return;
  584. // can be removed?
  585. elprintf(EL_SVP|EL_ANOMALY, "PM4 raw w %04x @ %04x", d, GET_PPC_OFFS());
  586. rPM4 = d;
  587. }
  588. // 14
  589. static u32 read_PMC(void)
  590. {
  591. elprintf(EL_SVP, "PMC r a %04x (st %c) @ %04x", rPMC.l,
  592. (ssp->emu_status & SSP_PMC_HAVE_ADDR) ? 'm' : 'a', GET_PPC_OFFS());
  593. if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
  594. //if (ssp->emu_status & SSP_PMC_SET)
  595. // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
  596. ssp->emu_status |= SSP_PMC_SET;
  597. ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
  598. return ((rPMC.l << 4) & 0xfff0) | ((rPMC.l >> 4) & 0xf);
  599. } else {
  600. ssp->emu_status |= SSP_PMC_HAVE_ADDR;
  601. return rPMC.l;
  602. }
  603. }
  604. static void write_PMC(u32 d)
  605. {
  606. if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
  607. //if (ssp->emu_status & SSP_PMC_SET)
  608. // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
  609. ssp->emu_status |= SSP_PMC_SET;
  610. ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
  611. rPMC.h = d;
  612. elprintf(EL_SVP, "PMC w m %04x @ %04x", rPMC.h, GET_PPC_OFFS());
  613. } else {
  614. ssp->emu_status |= SSP_PMC_HAVE_ADDR;
  615. rPMC.l = d;
  616. elprintf(EL_SVP, "PMC w a %04x @ %04x", rPMC.l, GET_PPC_OFFS());
  617. }
  618. }
  619. // 15
  620. static u32 read_AL(void)
  621. {
  622. if (*(PC-1) == 0x000f) {
  623. elprintf(EL_SVP, "ssp dummy PM assign %08x @ %04x", rPMC.v, GET_PPC_OFFS());
  624. ssp->emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); // ?
  625. }
  626. return rAL;
  627. }
  628. static void write_AL(u32 d)
  629. {
  630. rAL = d;
  631. }
  632. typedef u32 (*read_func_t)(void);
  633. typedef void (*write_func_t)(u32 d);
  634. static read_func_t read_handlers[16] =
  635. {
  636. read_unknown, read_unknown, read_unknown, read_unknown, // -, X, Y, A
  637. read_unknown, // 4 ST
  638. read_STACK,
  639. read_PC,
  640. read_P,
  641. read_PM0, // 8
  642. read_PM1,
  643. read_PM2,
  644. read_XST,
  645. read_PM4, // 12
  646. read_unknown, // 13 gr13
  647. read_PMC,
  648. read_AL
  649. };
  650. static write_func_t write_handlers[16] =
  651. {
  652. write_unknown, write_unknown, write_unknown, write_unknown, // -, X, Y, A
  653. // write_unknown, // 4 ST
  654. write_ST, // 4 ST (debug hook)
  655. write_STACK,
  656. write_PC,
  657. write_unknown, // 7 P
  658. write_PM0, // 8
  659. write_PM1,
  660. write_PM2,
  661. write_XST,
  662. write_PM4, // 12
  663. write_unknown, // 13 gr13
  664. write_PMC,
  665. write_AL
  666. };
  667. // -----------------------------------------------------
  668. // pointer register handlers
  669. //
  670. #define ptr1_read(op) ptr1_read_(op&3,(op>>6)&4,(op<<1)&0x18)
  671. static u32 ptr1_read_(int ri, int isj2, int modi3)
  672. {
  673. //int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
  674. u32 mask, add = 0, t = ri | isj2 | modi3;
  675. unsigned char *rp = NULL;
  676. switch (t)
  677. {
  678. // mod=0 (00)
  679. case 0x00:
  680. case 0x01:
  681. case 0x02: return ssp->RAM0[ssp->r0[t&3]];
  682. case 0x03: return ssp->RAM0[0];
  683. case 0x04:
  684. case 0x05:
  685. case 0x06: return ssp->RAM1[ssp->r1[t&3]];
  686. case 0x07: return ssp->RAM1[0];
  687. // mod=1 (01), "+!"
  688. case 0x08:
  689. case 0x09:
  690. case 0x0a: return ssp->RAM0[ssp->r0[t&3]++];
  691. case 0x0b: return ssp->RAM0[1];
  692. case 0x0c:
  693. case 0x0d:
  694. case 0x0e: return ssp->RAM1[ssp->r1[t&3]++];
  695. case 0x0f: return ssp->RAM1[1];
  696. // mod=2 (10), "-"
  697. case 0x10:
  698. case 0x11:
  699. case 0x12: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
  700. if (!(rST&7)) { (*rp)--; return t; }
  701. add = -1; goto modulo;
  702. case 0x13: return ssp->RAM0[2];
  703. case 0x14:
  704. case 0x15:
  705. case 0x16: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
  706. if (!(rST&7)) { (*rp)--; return t; }
  707. add = -1; goto modulo;
  708. case 0x17: return ssp->RAM1[2];
  709. // mod=3 (11), "+"
  710. case 0x18:
  711. case 0x19:
  712. case 0x1a: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
  713. if (!(rST&7)) { (*rp)++; return t; }
  714. add = 1; goto modulo;
  715. case 0x1b: return ssp->RAM0[3];
  716. case 0x1c:
  717. case 0x1d:
  718. case 0x1e: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
  719. if (!(rST&7)) { (*rp)++; return t; }
  720. add = 1; goto modulo;
  721. case 0x1f: return ssp->RAM1[3];
  722. }
  723. return 0;
  724. modulo:
  725. mask = (1 << (rST&7)) - 1;
  726. *rp = (*rp & ~mask) | ((*rp + add) & mask);
  727. return t;
  728. }
  729. static void ptr1_write(int op, u32 d)
  730. {
  731. int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
  732. switch (t)
  733. {
  734. // mod=0 (00)
  735. case 0x00:
  736. case 0x01:
  737. case 0x02: ssp->RAM0[ssp->r0[t&3]] = d; return;
  738. case 0x03: ssp->RAM0[0] = d; return;
  739. case 0x04:
  740. case 0x05:
  741. case 0x06: ssp->RAM1[ssp->r1[t&3]] = d; return;
  742. case 0x07: ssp->RAM1[0] = d; return;
  743. // mod=1 (01), "+!"
  744. // mod=3, "+"
  745. case 0x08:
  746. case 0x18:
  747. case 0x09:
  748. case 0x19:
  749. case 0x0a:
  750. case 0x1a: ssp->RAM0[ssp->r0[t&3]++] = d; return;
  751. case 0x0b: ssp->RAM0[1] = d; return;
  752. case 0x0c:
  753. case 0x1c:
  754. case 0x0d:
  755. case 0x1d:
  756. case 0x0e:
  757. case 0x1e: ssp->RAM1[ssp->r1[t&3]++] = d; return;
  758. case 0x0f: ssp->RAM1[1] = d; return;
  759. // mod=2 (10), "-"
  760. case 0x10:
  761. case 0x11:
  762. case 0x12: ssp->RAM0[ssp->r0[t&3]--] = d; return;
  763. case 0x13: ssp->RAM0[2] = d; return;
  764. case 0x14:
  765. case 0x15:
  766. case 0x16: ssp->RAM1[ssp->r1[t&3]--] = d; return;
  767. case 0x17: ssp->RAM1[2] = d; return;
  768. // mod=3 (11)
  769. case 0x1b: ssp->RAM0[3] = d; return;
  770. case 0x1f: ssp->RAM1[3] = d; return;
  771. }
  772. }
  773. static u32 ptr2_read(int op)
  774. {
  775. int mv = 0, t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
  776. switch (t)
  777. {
  778. // mod=0 (00)
  779. case 0x00:
  780. case 0x01:
  781. case 0x02: mv = ssp->RAM0[ssp->r0[t&3]]++; break;
  782. case 0x03: mv = ssp->RAM0[0]++; break;
  783. case 0x04:
  784. case 0x05:
  785. case 0x06: mv = ssp->RAM1[ssp->r1[t&3]]++; break;
  786. case 0x07: mv = ssp->RAM1[0]++; break;
  787. // mod=1 (01)
  788. case 0x0b: mv = ssp->RAM0[1]++; break;
  789. case 0x0f: mv = ssp->RAM1[1]++; break;
  790. // mod=2 (10)
  791. case 0x13: mv = ssp->RAM0[2]++; break;
  792. case 0x17: mv = ssp->RAM1[2]++; break;
  793. // mod=3 (11)
  794. case 0x1b: mv = ssp->RAM0[3]++; break;
  795. case 0x1f: mv = ssp->RAM1[3]++; break;
  796. default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid mod in ((rX))? @ %04x", GET_PPC_OFFS());
  797. return 0;
  798. }
  799. return ((unsigned short *)svp->iram_rom)[mv];
  800. }
  801. // -----------------------------------------------------
  802. #if defined(USE_DEBUGGER) //|| defined(EMBED_INTERPRETER)
  803. static void debug_dump2file(const char *fname, void *mem, int len)
  804. {
  805. FILE *f = fopen(fname, "wb");
  806. unsigned short *p = mem;
  807. int i;
  808. if (f) {
  809. for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
  810. fwrite(mem, 1, len, f);
  811. fclose(f);
  812. for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
  813. printf("dumped to %s\n", fname);
  814. }
  815. else
  816. printf("dump failed\n");
  817. }
  818. #endif
  819. #ifdef USE_DEBUGGER
  820. static void debug_dump(void)
  821. {
  822. printf("GR0: %04x X: %04x Y: %04x A: %08x\n", ssp->gr[SSP_GR0].h, rX, rY, ssp->gr[SSP_A].v);
  823. printf("PC: %04x (%04x) P: %08x\n", GET_PC(), GET_PC() << 1, rP.v);
  824. printf("PM0: %04x PM1: %04x PM2: %04x\n", rPM0, rPM1, rPM2);
  825. printf("XST: %04x PM4: %04x PMC: %08x\n", rXST, rPM4, rPMC.v);
  826. printf(" ST: %04x %c%c%c%c, GP0_0 %i, GP0_1 %i\n", rST, rST&SSP_FLAG_N?'N':'n', rST&SSP_FLAG_V?'V':'v',
  827. rST&SSP_FLAG_Z?'Z':'z', rST&SSP_FLAG_L?'L':'l', (rST>>5)&1, (rST>>6)&1);
  828. printf("STACK: %i %04x %04x %04x %04x %04x %04x\n", rSTACK, ssp->stack[0], ssp->stack[1],
  829. ssp->stack[2], ssp->stack[3], ssp->stack[4], ssp->stack[5]);
  830. printf("r0-r2: %02x %02x %02x r4-r6: %02x %02x %02x\n", rIJ[0], rIJ[1], rIJ[2], rIJ[4], rIJ[5], rIJ[6]);
  831. elprintf(EL_SVP, "cycles: %i, emu_status: %x", g_cycles, ssp->emu_status);
  832. }
  833. static void debug_dump_mem(void)
  834. {
  835. int h, i;
  836. printf("RAM0\n");
  837. for (h = 0; h < 32; h++)
  838. {
  839. if (h == 16) printf("RAM1\n");
  840. printf("%03x:", h*16);
  841. for (i = 0; i < 16; i++)
  842. printf(" %04x", ssp->RAM[h*16+i]);
  843. printf("\n");
  844. }
  845. }
  846. static int bpts[10] = { 0, };
  847. static void debug(unsigned int pc, unsigned int op)
  848. {
  849. static char buffo[64] = {0,};
  850. char buff[64] = {0,};
  851. int i;
  852. if (running) {
  853. for (i = 0; i < 10; i++)
  854. if (pc != 0 && bpts[i] == pc) {
  855. printf("breakpoint %i\n", i);
  856. running = 0;
  857. break;
  858. }
  859. }
  860. if (running) return;
  861. printf("%04x (%02x) @ %04x\n", op, op >> 9, pc<<1);
  862. while (1)
  863. {
  864. printf("dbg> ");
  865. fflush(stdout);
  866. fgets(buff, sizeof(buff), stdin);
  867. if (buff[0] == '\n') strcpy(buff, buffo);
  868. else strcpy(buffo, buff);
  869. switch (buff[0]) {
  870. case 0: exit(0);
  871. case 'c':
  872. case 'r': running = 1; return;
  873. case 's':
  874. case 'n': return;
  875. case 'x': debug_dump(); break;
  876. case 'm': debug_dump_mem(); break;
  877. case 'b': {
  878. char *baddr = buff + 2;
  879. i = 0;
  880. if (buff[3] == ' ') { i = buff[2] - '0'; baddr = buff + 4; }
  881. bpts[i] = strtol(baddr, NULL, 16) >> 1;
  882. printf("breakpoint %i set @ %04x\n", i, bpts[i]<<1);
  883. break;
  884. }
  885. case 'd':
  886. sprintf(buff, "iramrom_%04x.bin", last_iram);
  887. debug_dump2file(buff, svp->iram_rom, sizeof(svp->iram_rom));
  888. debug_dump2file("dram.bin", svp->dram, sizeof(svp->dram));
  889. break;
  890. default: printf("unknown command\n"); break;
  891. }
  892. }
  893. }
  894. #endif // USE_DEBUGGER
  895. #ifdef EMBED_INTERPRETER
  896. static
  897. #endif
  898. void ssp1601_reset(ssp1601_t *l_ssp)
  899. {
  900. ssp = l_ssp;
  901. ssp->emu_status = 0;
  902. ssp->gr[SSP_GR0].v = 0xffff0000;
  903. rPC = 0x400;
  904. rSTACK = 0; // ? using ascending stack
  905. rST = 0;
  906. }
  907. #ifdef EMBED_INTERPRETER
  908. static
  909. #endif
  910. void ssp1601_run(int cycles)
  911. {
  912. #ifndef EMBED_INTERPRETER
  913. SET_PC(rPC);
  914. #endif
  915. g_cycles = cycles;
  916. while (g_cycles > 0 && !(ssp->emu_status & SSP_WAIT_MASK))
  917. {
  918. int op;
  919. u32 tmpv;
  920. op = *PC++;
  921. #ifdef USE_DEBUGGER
  922. debug(GET_PC()-1, op);
  923. #endif
  924. switch (op >> 9)
  925. {
  926. // ld d, s
  927. case 0x00:
  928. if (op == 0) break; // nop
  929. if (op == ((SSP_A<<4)|SSP_P)) { // A <- P
  930. // not sure. MAME claims that only hi word is transfered.
  931. read_P(); // update P
  932. rA32 = rP.v;
  933. }
  934. else
  935. {
  936. tmpv = REG_READ(op & 0x0f);
  937. REG_WRITE((op & 0xf0) >> 4, tmpv);
  938. }
  939. break;
  940. // ld d, (ri)
  941. case 0x01: tmpv = ptr1_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
  942. // ld (ri), s
  943. case 0x02: tmpv = REG_READ((op & 0xf0) >> 4); ptr1_write(op, tmpv); break;
  944. // ldi d, imm
  945. case 0x04: tmpv = *PC++; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
  946. // ld d, ((ri))
  947. case 0x05: tmpv = ptr2_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
  948. // ldi (ri), imm
  949. case 0x06: tmpv = *PC++; ptr1_write(op, tmpv); break;
  950. // ld adr, a
  951. case 0x07: ssp->RAM[op & 0x1ff] = rA; break;
  952. // ld d, ri
  953. case 0x09: tmpv = rIJ[(op&3)|((op>>6)&4)]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
  954. // ld ri, s
  955. case 0x0a: rIJ[(op&3)|((op>>6)&4)] = REG_READ((op & 0xf0) >> 4); break;
  956. // ldi ri, simm
  957. case 0x0c:
  958. case 0x0d:
  959. case 0x0e:
  960. case 0x0f: rIJ[(op>>8)&7] = op; break;
  961. // call cond, addr
  962. case 0x24: {
  963. int cond = 0;
  964. COND_CHECK
  965. if (cond) { int new_PC = *PC++; write_STACK(GET_PC()); write_PC(new_PC); }
  966. else PC++;
  967. break;
  968. }
  969. // ld d, (a)
  970. case 0x25: tmpv = ((unsigned short *)svp->iram_rom)[rA]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
  971. // bra cond, addr
  972. case 0x26: {
  973. int cond = 0;
  974. COND_CHECK
  975. if (cond) { int new_PC = *PC++; write_PC(new_PC); }
  976. else PC++;
  977. break;
  978. }
  979. // mod cond, op
  980. case 0x48: {
  981. int cond = 0;
  982. COND_CHECK
  983. if (cond) {
  984. switch (op & 7) {
  985. case 2: rA32 = (signed int)rA32 >> 1; break; // shr (arithmetic)
  986. case 3: rA32 <<= 1; break; // shl
  987. case 6: rA32 = -(signed int)rA32; break; // neg
  988. case 7: if ((int)rA32 < 0) rA32 = -(signed int)rA32; break; // abs
  989. default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unhandled mod %i @ %04x",
  990. op&7, GET_PPC_OFFS());
  991. }
  992. UPD_ACC_ZN // ?
  993. }
  994. break;
  995. }
  996. // mpys?
  997. case 0x1b:
  998. read_P(); // update P
  999. rA32 -= rP.v; // maybe only upper word?
  1000. UPD_ACC_ZN // there checking flags after this
  1001. rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
  1002. rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
  1003. break;
  1004. // mpya (rj), (ri), b
  1005. case 0x4b:
  1006. read_P(); // update P
  1007. rA32 += rP.v; // confirmed to be 32bit
  1008. UPD_ACC_ZN // ?
  1009. rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
  1010. rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
  1011. break;
  1012. // mld (rj), (ri), b
  1013. case 0x5b:
  1014. rA32 = 0;
  1015. rST &= 0x0fff; // ?
  1016. rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
  1017. rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
  1018. break;
  1019. // OP a, s
  1020. case 0x10: OP_CHECK32(OP_SUBA32); tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break;
  1021. case 0x30: OP_CHECK32(OP_CMPA32); tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break;
  1022. case 0x40: OP_CHECK32(OP_ADDA32); tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break;
  1023. case 0x50: OP_CHECK32(OP_ANDA32); tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break;
  1024. case 0x60: OP_CHECK32(OP_ORA32 ); tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break;
  1025. case 0x70: OP_CHECK32(OP_EORA32); tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break;
  1026. // OP a, (ri)
  1027. case 0x11: tmpv = ptr1_read(op); OP_SUBA(tmpv); break;
  1028. case 0x31: tmpv = ptr1_read(op); OP_CMPA(tmpv); break;
  1029. case 0x41: tmpv = ptr1_read(op); OP_ADDA(tmpv); break;
  1030. case 0x51: tmpv = ptr1_read(op); OP_ANDA(tmpv); break;
  1031. case 0x61: tmpv = ptr1_read(op); OP_ORA (tmpv); break;
  1032. case 0x71: tmpv = ptr1_read(op); OP_EORA(tmpv); break;
  1033. // OP a, adr
  1034. case 0x03: tmpv = ssp->RAM[op & 0x1ff]; OP_LDA (tmpv); break;
  1035. case 0x13: tmpv = ssp->RAM[op & 0x1ff]; OP_SUBA(tmpv); break;
  1036. case 0x33: tmpv = ssp->RAM[op & 0x1ff]; OP_CMPA(tmpv); break;
  1037. case 0x43: tmpv = ssp->RAM[op & 0x1ff]; OP_ADDA(tmpv); break;
  1038. case 0x53: tmpv = ssp->RAM[op & 0x1ff]; OP_ANDA(tmpv); break;
  1039. case 0x63: tmpv = ssp->RAM[op & 0x1ff]; OP_ORA (tmpv); break;
  1040. case 0x73: tmpv = ssp->RAM[op & 0x1ff]; OP_EORA(tmpv); break;
  1041. // OP a, imm
  1042. case 0x14: tmpv = *PC++; OP_SUBA(tmpv); break;
  1043. case 0x34: tmpv = *PC++; OP_CMPA(tmpv); break;
  1044. case 0x44: tmpv = *PC++; OP_ADDA(tmpv); break;
  1045. case 0x54: tmpv = *PC++; OP_ANDA(tmpv); break;
  1046. case 0x64: tmpv = *PC++; OP_ORA (tmpv); break;
  1047. case 0x74: tmpv = *PC++; OP_EORA(tmpv); break;
  1048. // OP a, ((ri))
  1049. case 0x15: tmpv = ptr2_read(op); OP_SUBA(tmpv); break;
  1050. case 0x35: tmpv = ptr2_read(op); OP_CMPA(tmpv); break;
  1051. case 0x45: tmpv = ptr2_read(op); OP_ADDA(tmpv); break;
  1052. case 0x55: tmpv = ptr2_read(op); OP_ANDA(tmpv); break;
  1053. case 0x65: tmpv = ptr2_read(op); OP_ORA (tmpv); break;
  1054. case 0x75: tmpv = ptr2_read(op); OP_EORA(tmpv); break;
  1055. // OP a, ri
  1056. case 0x19: tmpv = rIJ[IJind]; OP_SUBA(tmpv); break;
  1057. case 0x39: tmpv = rIJ[IJind]; OP_CMPA(tmpv); break;
  1058. case 0x49: tmpv = rIJ[IJind]; OP_ADDA(tmpv); break;
  1059. case 0x59: tmpv = rIJ[IJind]; OP_ANDA(tmpv); break;
  1060. case 0x69: tmpv = rIJ[IJind]; OP_ORA (tmpv); break;
  1061. case 0x79: tmpv = rIJ[IJind]; OP_EORA(tmpv); break;
  1062. // OP simm
  1063. case 0x1c: OP_SUBA(op & 0xff); break;
  1064. case 0x3c: OP_CMPA(op & 0xff); break;
  1065. case 0x4c: OP_ADDA(op & 0xff); break;
  1066. // MAME code only does LSB of top word, but this looks wrong to me.
  1067. case 0x5c: OP_ANDA(op & 0xff); break;
  1068. case 0x6c: OP_ORA (op & 0xff); break;
  1069. case 0x7c: OP_EORA(op & 0xff); break;
  1070. #ifdef EMBED_INTERPRETER
  1071. case 0x7f: goto interp_end; /* pseudo op */
  1072. #endif
  1073. default:
  1074. elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME unhandled op %04x @ %04x", op, GET_PPC_OFFS());
  1075. break;
  1076. }
  1077. g_cycles--;
  1078. }
  1079. rPC = GET_PC();
  1080. #ifdef EMBED_INTERPRETER
  1081. interp_end:
  1082. #endif
  1083. read_P(); // update P
  1084. if (ssp->gr[SSP_GR0].v != 0xffff0000)
  1085. elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: REG 0 corruption! %08x", ssp->gr[SSP_GR0].v);
  1086. }