compiler.c 46 KB

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  1. /*
  2. * SSP1601 to ARM recompiler
  3. * (C) notaz, 2008,2009,2010
  4. *
  5. * This work is licensed under the terms of MAME license.
  6. * See COPYING file in the top-level directory.
  7. */
  8. #include "../../pico_int.h"
  9. #include "../../../cpu/drc/cmn.h"
  10. #include "compiler.h"
  11. // FIXME: asm has these hardcoded
  12. #define SSP_BLOCKTAB_ENTS (0x5090/2)
  13. #define SSP_BLOCKTAB_IRAM_ONE (0x800/2) // table entries
  14. #define SSP_BLOCKTAB_IRAM_ENTS (15*SSP_BLOCKTAB_IRAM_ONE)
  15. static u32 **ssp_block_table; // [0x5090/2];
  16. static u32 **ssp_block_table_iram; // [15][0x800/2];
  17. static u32 *tcache_ptr = NULL;
  18. static int nblocks = 0;
  19. static int n_in_ops = 0;
  20. extern ssp1601_t *ssp;
  21. #define rPC ssp->gr[SSP_PC].h
  22. #define rPMC ssp->gr[SSP_PMC]
  23. #define SSP_FLAG_Z (1<<0xd)
  24. #define SSP_FLAG_N (1<<0xf)
  25. #ifndef __arm__
  26. //#define DUMP_BLOCK 0x0c9a
  27. void ssp_drc_next(void){}
  28. void ssp_drc_next_patch(void){}
  29. void ssp_drc_end(void){}
  30. #endif
  31. #define COUNT_OP
  32. #include "../../../cpu/drc/emit_arm.c"
  33. // -----------------------------------------------------
  34. static int get_inc(int mode)
  35. {
  36. int inc = (mode >> 11) & 7;
  37. if (inc != 0) {
  38. if (inc != 7) inc--;
  39. inc = 1 << inc; // 0 1 2 4 8 16 32 128
  40. if (mode & 0x8000) inc = -inc; // decrement mode
  41. }
  42. return inc;
  43. }
  44. u32 ssp_pm_read(int reg)
  45. {
  46. u32 d = 0, mode;
  47. if (ssp->emu_status & SSP_PMC_SET)
  48. {
  49. ssp->pmac_read[reg] = rPMC.v;
  50. ssp->emu_status &= ~SSP_PMC_SET;
  51. return 0;
  52. }
  53. // just in case
  54. ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
  55. mode = ssp->pmac_read[reg]>>16;
  56. if ((mode & 0xfff0) == 0x0800) // ROM
  57. {
  58. d = ((unsigned short *)Pico.rom)[ssp->pmac_read[reg]&0xfffff];
  59. ssp->pmac_read[reg] += 1;
  60. }
  61. else if ((mode & 0x47ff) == 0x0018) // DRAM
  62. {
  63. unsigned short *dram = (unsigned short *)svp->dram;
  64. int inc = get_inc(mode);
  65. d = dram[ssp->pmac_read[reg]&0xffff];
  66. ssp->pmac_read[reg] += inc;
  67. }
  68. // PMC value corresponds to last PMR accessed
  69. rPMC.v = ssp->pmac_read[reg];
  70. return d;
  71. }
  72. #define overwrite_write(dst, d) \
  73. { \
  74. if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
  75. if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
  76. if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
  77. if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
  78. }
  79. void ssp_pm_write(u32 d, int reg)
  80. {
  81. unsigned short *dram;
  82. int mode, addr;
  83. if (ssp->emu_status & SSP_PMC_SET)
  84. {
  85. ssp->pmac_write[reg] = rPMC.v;
  86. ssp->emu_status &= ~SSP_PMC_SET;
  87. return;
  88. }
  89. // just in case
  90. ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
  91. dram = (unsigned short *)svp->dram;
  92. mode = ssp->pmac_write[reg]>>16;
  93. addr = ssp->pmac_write[reg]&0xffff;
  94. if ((mode & 0x43ff) == 0x0018) // DRAM
  95. {
  96. int inc = get_inc(mode);
  97. if (mode & 0x0400) {
  98. overwrite_write(dram[addr], d);
  99. } else dram[addr] = d;
  100. ssp->pmac_write[reg] += inc;
  101. }
  102. else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
  103. {
  104. if (mode & 0x0400) {
  105. overwrite_write(dram[addr], d);
  106. } else dram[addr] = d;
  107. ssp->pmac_write[reg] += (addr&1) ? 0x1f : 1;
  108. }
  109. else if ((mode & 0x47ff) == 0x001c) // IRAM
  110. {
  111. int inc = get_inc(mode);
  112. ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
  113. ssp->pmac_write[reg] += inc;
  114. ssp->drc.iram_dirty = 1;
  115. }
  116. rPMC.v = ssp->pmac_write[reg];
  117. }
  118. // -----------------------------------------------------
  119. // 14 IRAM blocks
  120. static unsigned char iram_context_map[] =
  121. {
  122. 0, 0, 0, 0, 1, 0, 0, 0, // 04
  123. 0, 0, 0, 0, 0, 0, 2, 0, // 0e
  124. 0, 0, 0, 0, 0, 3, 0, 4, // 15 17
  125. 5, 0, 0, 6, 0, 7, 0, 0, // 18 1b 1d
  126. 8, 9, 0, 0, 0,10, 0, 0, // 20 21 25
  127. 0, 0, 0, 0, 0, 0, 0, 0,
  128. 0, 0,11, 0, 0,12, 0, 0, // 32 35
  129. 13,14, 0, 0, 0, 0, 0, 0 // 38 39
  130. };
  131. int ssp_get_iram_context(void)
  132. {
  133. unsigned char *ir = (unsigned char *)svp->iram_rom;
  134. int val1, val = ir[0x083^1] + ir[0x4FA^1] + ir[0x5F7^1] + ir[0x47B^1];
  135. val1 = iram_context_map[(val>>1)&0x3f];
  136. if (val1 == 0) {
  137. elprintf(EL_ANOMALY, "svp: iram ctx val: %02x PC=%04x\n", (val>>1)&0x3f, rPC);
  138. //debug_dump2file(name, svp->iram_rom, 0x800);
  139. //exit(1);
  140. }
  141. return val1;
  142. }
  143. // -----------------------------------------------------
  144. /* regs with known values */
  145. static struct
  146. {
  147. ssp_reg_t gr[8];
  148. unsigned char r[8];
  149. unsigned int pmac_read[5];
  150. unsigned int pmac_write[5];
  151. ssp_reg_t pmc;
  152. unsigned int emu_status;
  153. } known_regs;
  154. #define KRREG_X (1 << SSP_X)
  155. #define KRREG_Y (1 << SSP_Y)
  156. #define KRREG_A (1 << SSP_A) /* AH only */
  157. #define KRREG_ST (1 << SSP_ST)
  158. #define KRREG_STACK (1 << SSP_STACK)
  159. #define KRREG_PC (1 << SSP_PC)
  160. #define KRREG_P (1 << SSP_P)
  161. #define KRREG_PR0 (1 << 8)
  162. #define KRREG_PR4 (1 << 12)
  163. #define KRREG_AL (1 << 16)
  164. #define KRREG_PMCM (1 << 18) /* only mode word of PMC */
  165. #define KRREG_PMC (1 << 19)
  166. #define KRREG_PM0R (1 << 20)
  167. #define KRREG_PM1R (1 << 21)
  168. #define KRREG_PM2R (1 << 22)
  169. #define KRREG_PM3R (1 << 23)
  170. #define KRREG_PM4R (1 << 24)
  171. #define KRREG_PM0W (1 << 25)
  172. #define KRREG_PM1W (1 << 26)
  173. #define KRREG_PM2W (1 << 27)
  174. #define KRREG_PM3W (1 << 28)
  175. #define KRREG_PM4W (1 << 29)
  176. /* bitfield of known register values */
  177. static u32 known_regb = 0;
  178. /* known vals, which need to be flushed
  179. * (only ST, P, r0-r7, PMCx, PMxR, PMxW)
  180. * ST means flags are being held in ARM PSR
  181. * P means that it needs to be recalculated
  182. */
  183. static u32 dirty_regb = 0;
  184. /* known values of host regs.
  185. * -1 - unknown
  186. * 000000-00ffff - 16bit value
  187. * 100000-10ffff - base reg (r7) + 16bit val
  188. * 0r0000 - means reg (low) eq gr[r].h, r != AL
  189. */
  190. static int hostreg_r[4];
  191. static void hostreg_clear(void)
  192. {
  193. int i;
  194. for (i = 0; i < 4; i++)
  195. hostreg_r[i] = -1;
  196. }
  197. static void hostreg_sspreg_changed(int sspreg)
  198. {
  199. int i;
  200. for (i = 0; i < 4; i++)
  201. if (hostreg_r[i] == (sspreg<<16)) hostreg_r[i] = -1;
  202. }
  203. #define PROGRAM(x) ((unsigned short *)svp->iram_rom)[x]
  204. #define PROGRAM_P(x) ((unsigned short *)svp->iram_rom + (x))
  205. void tr_unhandled(void)
  206. {
  207. //FILE *f = fopen("tcache.bin", "wb");
  208. //fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
  209. //fclose(f);
  210. elprintf(EL_ANOMALY, "unhandled @ %04x\n", known_regs.gr[SSP_PC].h<<1);
  211. //exit(1);
  212. }
  213. /* update P, if needed. Trashes r0 */
  214. static void tr_flush_dirty_P(void)
  215. {
  216. // TODO: const regs
  217. if (!(dirty_regb & KRREG_P)) return;
  218. EOP_MOV_REG_ASR(10, 4, 16); // mov r10, r4, asr #16
  219. EOP_MOV_REG_LSL( 0, 4, 16); // mov r0, r4, lsl #16
  220. EOP_MOV_REG_ASR( 0, 0, 15); // mov r0, r0, asr #15
  221. EOP_MUL(10, 0, 10); // mul r10, r0, r10
  222. dirty_regb &= ~KRREG_P;
  223. hostreg_r[0] = -1;
  224. }
  225. /* write dirty pr to host reg. Nothing is trashed */
  226. static void tr_flush_dirty_pr(int r)
  227. {
  228. int ror = 0, reg;
  229. if (!(dirty_regb & (1 << (r+8)))) return;
  230. switch (r&3) {
  231. case 0: ror = 0; break;
  232. case 1: ror = 24/2; break;
  233. case 2: ror = 16/2; break;
  234. }
  235. reg = (r < 4) ? 8 : 9;
  236. EOP_BIC_IMM(reg,reg,ror,0xff);
  237. if (known_regs.r[r] != 0)
  238. EOP_ORR_IMM(reg,reg,ror,known_regs.r[r]);
  239. dirty_regb &= ~(1 << (r+8));
  240. }
  241. /* write all dirty pr0-pr7 to host regs. Nothing is trashed */
  242. static void tr_flush_dirty_prs(void)
  243. {
  244. int i, ror = 0, reg;
  245. int dirty = dirty_regb >> 8;
  246. if ((dirty&7) == 7) {
  247. emith_move_r_imm(8, known_regs.r[0]|(known_regs.r[1]<<8)|(known_regs.r[2]<<16));
  248. dirty &= ~7;
  249. }
  250. if ((dirty&0x70) == 0x70) {
  251. emith_move_r_imm(9, known_regs.r[4]|(known_regs.r[5]<<8)|(known_regs.r[6]<<16));
  252. dirty &= ~0x70;
  253. }
  254. /* r0-r7 */
  255. for (i = 0; dirty && i < 8; i++, dirty >>= 1)
  256. {
  257. if (!(dirty&1)) continue;
  258. switch (i&3) {
  259. case 0: ror = 0; break;
  260. case 1: ror = 24/2; break;
  261. case 2: ror = 16/2; break;
  262. }
  263. reg = (i < 4) ? 8 : 9;
  264. EOP_BIC_IMM(reg,reg,ror,0xff);
  265. if (known_regs.r[i] != 0)
  266. EOP_ORR_IMM(reg,reg,ror,known_regs.r[i]);
  267. }
  268. dirty_regb &= ~0xff00;
  269. }
  270. /* write dirty pr and "forget" it. Nothing is trashed. */
  271. static void tr_release_pr(int r)
  272. {
  273. tr_flush_dirty_pr(r);
  274. known_regb &= ~(1 << (r+8));
  275. }
  276. /* fush ARM PSR to r6. Trashes r1 */
  277. static void tr_flush_dirty_ST(void)
  278. {
  279. if (!(dirty_regb & KRREG_ST)) return;
  280. EOP_BIC_IMM(6,6,0,0x0f);
  281. EOP_MRS(1);
  282. EOP_ORR_REG_LSR(6,6,1,28);
  283. dirty_regb &= ~KRREG_ST;
  284. hostreg_r[1] = -1;
  285. }
  286. /* inverse of above. Trashes r1 */
  287. static void tr_make_dirty_ST(void)
  288. {
  289. if (dirty_regb & KRREG_ST) return;
  290. if (known_regb & KRREG_ST) {
  291. int flags = 0;
  292. if (known_regs.gr[SSP_ST].h & SSP_FLAG_N) flags |= 8;
  293. if (known_regs.gr[SSP_ST].h & SSP_FLAG_Z) flags |= 4;
  294. EOP_MSR_IMM(4/2, flags);
  295. } else {
  296. EOP_MOV_REG_LSL(1, 6, 28);
  297. EOP_MSR_REG(1);
  298. hostreg_r[1] = -1;
  299. }
  300. dirty_regb |= KRREG_ST;
  301. }
  302. /* load 16bit val into host reg r0-r3. Nothing is trashed */
  303. static void tr_mov16(int r, int val)
  304. {
  305. if (hostreg_r[r] != val) {
  306. emith_move_r_imm(r, val);
  307. hostreg_r[r] = val;
  308. }
  309. }
  310. static void tr_mov16_cond(int cond, int r, int val)
  311. {
  312. emith_op_imm(cond, 0, A_OP_MOV, r, val);
  313. hostreg_r[r] = -1;
  314. }
  315. /* trashes r1 */
  316. static void tr_flush_dirty_pmcrs(void)
  317. {
  318. u32 i, val = (u32)-1;
  319. if (!(dirty_regb & 0x3ff80000)) return;
  320. if (dirty_regb & KRREG_PMC) {
  321. val = known_regs.pmc.v;
  322. emith_move_r_imm(1, val);
  323. EOP_STR_IMM(1,7,0x400+SSP_PMC*4);
  324. if (known_regs.emu_status & (SSP_PMC_SET|SSP_PMC_HAVE_ADDR)) {
  325. elprintf(EL_ANOMALY, "!! SSP_PMC_SET|SSP_PMC_HAVE_ADDR set on flush\n");
  326. tr_unhandled();
  327. }
  328. }
  329. for (i = 0; i < 5; i++)
  330. {
  331. if (dirty_regb & (1 << (20+i))) {
  332. if (val != known_regs.pmac_read[i]) {
  333. val = known_regs.pmac_read[i];
  334. emith_move_r_imm(1, val);
  335. }
  336. EOP_STR_IMM(1,7,0x454+i*4); // pmac_read
  337. }
  338. if (dirty_regb & (1 << (25+i))) {
  339. if (val != known_regs.pmac_write[i]) {
  340. val = known_regs.pmac_write[i];
  341. emith_move_r_imm(1, val);
  342. }
  343. EOP_STR_IMM(1,7,0x46c+i*4); // pmac_write
  344. }
  345. }
  346. dirty_regb &= ~0x3ff80000;
  347. hostreg_r[1] = -1;
  348. }
  349. /* read bank word to r0 (upper bits zero). Thrashes r1. */
  350. static void tr_bank_read(int addr) /* word addr 0-0x1ff */
  351. {
  352. int breg = 7;
  353. if (addr > 0x7f) {
  354. if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
  355. EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1); // add r1, r7, ((op&0x180)<<1)
  356. hostreg_r[1] = 0x100000|((addr&0x180)<<1);
  357. }
  358. breg = 1;
  359. }
  360. EOP_LDRH_IMM(0,breg,(addr&0x7f)<<1); // ldrh r0, [r1, (op&0x7f)<<1]
  361. hostreg_r[0] = -1;
  362. }
  363. /* write r0 to bank. Trashes r1. */
  364. static void tr_bank_write(int addr)
  365. {
  366. int breg = 7;
  367. if (addr > 0x7f) {
  368. if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
  369. EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1); // add r1, r7, ((op&0x180)<<1)
  370. hostreg_r[1] = 0x100000|((addr&0x180)<<1);
  371. }
  372. breg = 1;
  373. }
  374. EOP_STRH_IMM(0,breg,(addr&0x7f)<<1); // strh r0, [r1, (op&0x7f)<<1]
  375. }
  376. /* handle RAM bank pointer modifiers. if need_modulo, trash r1-r3, else nothing */
  377. static void tr_ptrr_mod(int r, int mod, int need_modulo, int count)
  378. {
  379. int modulo_shift = -1; /* unknown */
  380. if (mod == 0) return;
  381. if (!need_modulo || mod == 1) // +!
  382. modulo_shift = 8;
  383. else if (need_modulo && (known_regb & KRREG_ST)) {
  384. modulo_shift = known_regs.gr[SSP_ST].h & 7;
  385. if (modulo_shift == 0) modulo_shift = 8;
  386. }
  387. if (modulo_shift == -1)
  388. {
  389. int reg = (r < 4) ? 8 : 9;
  390. tr_release_pr(r);
  391. if (dirty_regb & KRREG_ST) {
  392. // avoid flushing ARM flags
  393. EOP_AND_IMM(1, 6, 0, 0x70);
  394. EOP_SUB_IMM(1, 1, 0, 0x10);
  395. EOP_AND_IMM(1, 1, 0, 0x70);
  396. EOP_ADD_IMM(1, 1, 0, 0x10);
  397. } else {
  398. EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,1,6,1,0,0x70); // ands r1, r6, #0x70
  399. EOP_C_DOP_IMM(A_COND_EQ,A_OP_MOV,0,0,1,0,0x80); // moveq r1, #0x80
  400. }
  401. EOP_MOV_REG_LSR(1, 1, 4); // mov r1, r1, lsr #4
  402. EOP_RSB_IMM(2, 1, 0, 8); // rsb r1, r1, #8
  403. EOP_MOV_IMM(3, 8/2, count); // mov r3, #0x01000000
  404. if (r&3)
  405. EOP_ADD_IMM(1, 1, 0, (r&3)*8); // add r1, r1, #(r&3)*8
  406. EOP_MOV_REG2_ROR(reg,reg,1); // mov reg, reg, ror r1
  407. if (mod == 2)
  408. EOP_SUB_REG2_LSL(reg,reg,3,2); // sub reg, reg, #0x01000000 << r2
  409. else EOP_ADD_REG2_LSL(reg,reg,3,2);
  410. EOP_RSB_IMM(1, 1, 0, 32); // rsb r1, r1, #32
  411. EOP_MOV_REG2_ROR(reg,reg,1); // mov reg, reg, ror r1
  412. hostreg_r[1] = hostreg_r[2] = hostreg_r[3] = -1;
  413. }
  414. else if (known_regb & (1 << (r + 8)))
  415. {
  416. int modulo = (1 << modulo_shift) - 1;
  417. if (mod == 2)
  418. known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] - count) & modulo);
  419. else known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] + count) & modulo);
  420. }
  421. else
  422. {
  423. int reg = (r < 4) ? 8 : 9;
  424. int ror = ((r&3) + 1)*8 - (8 - modulo_shift);
  425. EOP_MOV_REG_ROR(reg,reg,ror);
  426. // {add|sub} reg, reg, #1<<shift
  427. EOP_C_DOP_IMM(A_COND_AL,(mod==2)?A_OP_SUB:A_OP_ADD,0,reg,reg, 8/2, count << (8 - modulo_shift));
  428. EOP_MOV_REG_ROR(reg,reg,32-ror);
  429. }
  430. }
  431. /* handle writes r0 to (rX). Trashes r1.
  432. * fortunately we can ignore modulo increment modes for writes. */
  433. static void tr_rX_write(int op)
  434. {
  435. if ((op&3) == 3)
  436. {
  437. int mod = (op>>2) & 3; // direct addressing
  438. tr_bank_write((op & 0x100) + mod);
  439. }
  440. else
  441. {
  442. int r = (op&3) | ((op>>6)&4);
  443. if (known_regb & (1 << (r + 8))) {
  444. tr_bank_write((op&0x100) | known_regs.r[r]);
  445. } else {
  446. int reg = (r < 4) ? 8 : 9;
  447. int ror = ((4 - (r&3))*8) & 0x1f;
  448. EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
  449. if (r >= 4)
  450. EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
  451. if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
  452. else EOP_ADD_REG_LSL(1,7,1,1);
  453. EOP_STRH_SIMPLE(0,1); // strh r0, [r1]
  454. hostreg_r[1] = -1;
  455. }
  456. tr_ptrr_mod(r, (op>>2) & 3, 0, 1);
  457. }
  458. }
  459. /* read (rX) to r0. Trashes r1-r3. */
  460. static void tr_rX_read(int r, int mod)
  461. {
  462. if ((r&3) == 3)
  463. {
  464. tr_bank_read(((r << 6) & 0x100) + mod); // direct addressing
  465. }
  466. else
  467. {
  468. if (known_regb & (1 << (r + 8))) {
  469. tr_bank_read(((r << 6) & 0x100) | known_regs.r[r]);
  470. } else {
  471. int reg = (r < 4) ? 8 : 9;
  472. int ror = ((4 - (r&3))*8) & 0x1f;
  473. EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
  474. if (r >= 4)
  475. EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
  476. if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
  477. else EOP_ADD_REG_LSL(1,7,1,1);
  478. EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1]
  479. hostreg_r[0] = hostreg_r[1] = -1;
  480. }
  481. tr_ptrr_mod(r, mod, 1, 1);
  482. }
  483. }
  484. /* read ((rX)) to r0. Trashes r1,r2. */
  485. static void tr_rX_read2(int op)
  486. {
  487. int r = (op&3) | ((op>>6)&4); // src
  488. if ((r&3) == 3) {
  489. tr_bank_read((op&0x100) | ((op>>2)&3));
  490. } else if (known_regb & (1 << (r+8))) {
  491. tr_bank_read((op&0x100) | known_regs.r[r]);
  492. } else {
  493. int reg = (r < 4) ? 8 : 9;
  494. int ror = ((4 - (r&3))*8) & 0x1f;
  495. EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
  496. if (r >= 4)
  497. EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
  498. if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
  499. else EOP_ADD_REG_LSL(1,7,1,1);
  500. EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1]
  501. }
  502. EOP_LDR_IMM(2,7,0x48c); // ptr_iram_rom
  503. EOP_ADD_REG_LSL(2,2,0,1); // add r2, r2, r0, lsl #1
  504. EOP_ADD_IMM(0,0,0,1); // add r0, r0, #1
  505. if ((r&3) == 3) {
  506. tr_bank_write((op&0x100) | ((op>>2)&3));
  507. } else if (known_regb & (1 << (r+8))) {
  508. tr_bank_write((op&0x100) | known_regs.r[r]);
  509. } else {
  510. EOP_STRH_SIMPLE(0,1); // strh r0, [r1]
  511. hostreg_r[1] = -1;
  512. }
  513. EOP_LDRH_SIMPLE(0,2); // ldrh r0, [r2]
  514. hostreg_r[0] = hostreg_r[2] = -1;
  515. }
  516. // check if AL is going to be used later in block
  517. static int tr_predict_al_need(void)
  518. {
  519. int tmpv, tmpv2, op, pc = known_regs.gr[SSP_PC].h;
  520. while (1)
  521. {
  522. op = PROGRAM(pc);
  523. switch (op >> 9)
  524. {
  525. // ld d, s
  526. case 0x00:
  527. tmpv2 = (op >> 4) & 0xf; // dst
  528. tmpv = op & 0xf; // src
  529. if ((tmpv2 == SSP_A && tmpv == SSP_P) || tmpv2 == SSP_AL) // ld A, P; ld AL, *
  530. return 0;
  531. break;
  532. // ld (ri), s
  533. case 0x02:
  534. // ld ri, s
  535. case 0x0a:
  536. // OP a, s
  537. case 0x10: case 0x30: case 0x40: case 0x60: case 0x70:
  538. tmpv = op & 0xf; // src
  539. if (tmpv == SSP_AL) // OP *, AL
  540. return 1;
  541. break;
  542. case 0x04:
  543. case 0x06:
  544. case 0x14:
  545. case 0x34:
  546. case 0x44:
  547. case 0x64:
  548. case 0x74: pc++; break;
  549. // call cond, addr
  550. case 0x24:
  551. // bra cond, addr
  552. case 0x26:
  553. // mod cond, op
  554. case 0x48:
  555. // mpys?
  556. case 0x1b:
  557. // mpya (rj), (ri), b
  558. case 0x4b: return 1;
  559. // mld (rj), (ri), b
  560. case 0x5b: return 0; // cleared anyway
  561. // and A, *
  562. case 0x50:
  563. tmpv = op & 0xf; // src
  564. if (tmpv == SSP_AL) return 1;
  565. case 0x51: case 0x53: case 0x54: case 0x55: case 0x59: case 0x5c:
  566. return 0;
  567. }
  568. pc++;
  569. }
  570. }
  571. /* get ARM cond which would mean that SSP cond is satisfied. No trash. */
  572. static int tr_cond_check(int op)
  573. {
  574. int f = (op & 0x100) >> 8;
  575. switch (op&0xf0) {
  576. case 0x00: return A_COND_AL; /* always true */
  577. case 0x50: /* Z matches f(?) bit */
  578. if (dirty_regb & KRREG_ST) return f ? A_COND_EQ : A_COND_NE;
  579. EOP_TST_IMM(6, 0, 4);
  580. return f ? A_COND_NE : A_COND_EQ;
  581. case 0x70: /* N matches f(?) bit */
  582. if (dirty_regb & KRREG_ST) return f ? A_COND_MI : A_COND_PL;
  583. EOP_TST_IMM(6, 0, 8);
  584. return f ? A_COND_NE : A_COND_EQ;
  585. default:
  586. elprintf(EL_ANOMALY, "unimplemented cond?\n");
  587. tr_unhandled();
  588. return 0;
  589. }
  590. }
  591. static int tr_neg_cond(int cond)
  592. {
  593. switch (cond) {
  594. case A_COND_AL: elprintf(EL_ANOMALY, "neg for AL?\n"); exit(1);
  595. case A_COND_EQ: return A_COND_NE;
  596. case A_COND_NE: return A_COND_EQ;
  597. case A_COND_MI: return A_COND_PL;
  598. case A_COND_PL: return A_COND_MI;
  599. default: elprintf(EL_ANOMALY, "bad cond for neg\n"); exit(1);
  600. }
  601. return 0;
  602. }
  603. static int tr_aop_ssp2arm(int op)
  604. {
  605. switch (op) {
  606. case 1: return A_OP_SUB;
  607. case 3: return A_OP_CMP;
  608. case 4: return A_OP_ADD;
  609. case 5: return A_OP_AND;
  610. case 6: return A_OP_ORR;
  611. case 7: return A_OP_EOR;
  612. }
  613. tr_unhandled();
  614. return 0;
  615. }
  616. // -----------------------------------------------------
  617. //@ r4: XXYY
  618. //@ r5: A
  619. //@ r6: STACK and emu flags
  620. //@ r7: SSP context
  621. //@ r10: P
  622. // read general reg to r0. Trashes r1
  623. static void tr_GR0_to_r0(int op)
  624. {
  625. tr_mov16(0, 0xffff);
  626. }
  627. static void tr_X_to_r0(int op)
  628. {
  629. if (hostreg_r[0] != (SSP_X<<16)) {
  630. EOP_MOV_REG_LSR(0, 4, 16); // mov r0, r4, lsr #16
  631. hostreg_r[0] = SSP_X<<16;
  632. }
  633. }
  634. static void tr_Y_to_r0(int op)
  635. {
  636. if (hostreg_r[0] != (SSP_Y<<16)) {
  637. EOP_MOV_REG_SIMPLE(0, 4); // mov r0, r4
  638. hostreg_r[0] = SSP_Y<<16;
  639. }
  640. }
  641. static void tr_A_to_r0(int op)
  642. {
  643. if (hostreg_r[0] != (SSP_A<<16)) {
  644. EOP_MOV_REG_LSR(0, 5, 16); // mov r0, r5, lsr #16 @ AH
  645. hostreg_r[0] = SSP_A<<16;
  646. }
  647. }
  648. static void tr_ST_to_r0(int op)
  649. {
  650. // VR doesn't need much accuracy here..
  651. EOP_MOV_REG_LSR(0, 6, 4); // mov r0, r6, lsr #4
  652. EOP_AND_IMM(0, 0, 0, 0x67); // and r0, r0, #0x67
  653. hostreg_r[0] = -1;
  654. }
  655. static void tr_STACK_to_r0(int op)
  656. {
  657. // 448
  658. EOP_SUB_IMM(6, 6, 8/2, 0x20); // sub r6, r6, #1<<29
  659. EOP_ADD_IMM(1, 7, 24/2, 0x04); // add r1, r7, 0x400
  660. EOP_ADD_IMM(1, 1, 0, 0x48); // add r1, r1, 0x048
  661. EOP_ADD_REG_LSR(1, 1, 6, 28); // add r1, r1, r6, lsr #28
  662. EOP_LDRH_SIMPLE(0, 1); // ldrh r0, [r1]
  663. hostreg_r[0] = hostreg_r[1] = -1;
  664. }
  665. static void tr_PC_to_r0(int op)
  666. {
  667. tr_mov16(0, known_regs.gr[SSP_PC].h);
  668. }
  669. static void tr_P_to_r0(int op)
  670. {
  671. tr_flush_dirty_P();
  672. EOP_MOV_REG_LSR(0, 10, 16); // mov r0, r10, lsr #16
  673. hostreg_r[0] = -1;
  674. }
  675. static void tr_AL_to_r0(int op)
  676. {
  677. if (op == 0x000f) {
  678. if (known_regb & KRREG_PMC) {
  679. known_regs.emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR);
  680. } else {
  681. EOP_LDR_IMM(0,7,0x484); // ldr r1, [r7, #0x484] // emu_status
  682. EOP_BIC_IMM(0,0,0,SSP_PMC_SET|SSP_PMC_HAVE_ADDR);
  683. EOP_STR_IMM(0,7,0x484);
  684. }
  685. }
  686. if (hostreg_r[0] != (SSP_AL<<16)) {
  687. EOP_MOV_REG_SIMPLE(0, 5); // mov r0, r5
  688. hostreg_r[0] = SSP_AL<<16;
  689. }
  690. }
  691. static void tr_PMX_to_r0(int reg)
  692. {
  693. if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET))
  694. {
  695. known_regs.pmac_read[reg] = known_regs.pmc.v;
  696. known_regs.emu_status &= ~SSP_PMC_SET;
  697. known_regb |= 1 << (20+reg);
  698. dirty_regb |= 1 << (20+reg);
  699. return;
  700. }
  701. if ((known_regb & KRREG_PMC) && (known_regb & (1 << (20+reg))))
  702. {
  703. u32 pmcv = known_regs.pmac_read[reg];
  704. int mode = pmcv>>16;
  705. known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
  706. if ((mode & 0xfff0) == 0x0800)
  707. {
  708. EOP_LDR_IMM(1,7,0x488); // rom_ptr
  709. emith_move_r_imm(0, (pmcv&0xfffff)<<1);
  710. EOP_LDRH_REG(0,1,0); // ldrh r0, [r1, r0]
  711. known_regs.pmac_read[reg] += 1;
  712. }
  713. else if ((mode & 0x47ff) == 0x0018) // DRAM
  714. {
  715. int inc = get_inc(mode);
  716. EOP_LDR_IMM(1,7,0x490); // dram_ptr
  717. emith_move_r_imm(0, (pmcv&0xffff)<<1);
  718. EOP_LDRH_REG(0,1,0); // ldrh r0, [r1, r0]
  719. if (reg == 4 && (pmcv == 0x187f03 || pmcv == 0x187f04)) // wait loop detection
  720. {
  721. int flag = (pmcv == 0x187f03) ? SSP_WAIT_30FE06 : SSP_WAIT_30FE08;
  722. tr_flush_dirty_ST();
  723. EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
  724. EOP_TST_REG_SIMPLE(0,0);
  725. EOP_C_DOP_IMM(A_COND_EQ,A_OP_SUB,0,11,11,22/2,1); // subeq r11, r11, #1024
  726. EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,flag>>8); // orreq r1, r1, #SSP_WAIT_30FE08
  727. EOP_STR_IMM(1,7,0x484); // str r1, [r7, #0x484] // emu_status
  728. }
  729. known_regs.pmac_read[reg] += inc;
  730. }
  731. else
  732. {
  733. tr_unhandled();
  734. }
  735. known_regs.pmc.v = known_regs.pmac_read[reg];
  736. //known_regb |= KRREG_PMC;
  737. dirty_regb |= KRREG_PMC;
  738. dirty_regb |= 1 << (20+reg);
  739. hostreg_r[0] = hostreg_r[1] = -1;
  740. return;
  741. }
  742. known_regb &= ~KRREG_PMC;
  743. dirty_regb &= ~KRREG_PMC;
  744. known_regb &= ~(1 << (20+reg));
  745. dirty_regb &= ~(1 << (20+reg));
  746. // call the C code to handle this
  747. tr_flush_dirty_ST();
  748. //tr_flush_dirty_pmcrs();
  749. tr_mov16(0, reg);
  750. emith_call(ssp_pm_read);
  751. hostreg_clear();
  752. }
  753. static void tr_PM0_to_r0(int op)
  754. {
  755. tr_PMX_to_r0(0);
  756. }
  757. static void tr_PM1_to_r0(int op)
  758. {
  759. tr_PMX_to_r0(1);
  760. }
  761. static void tr_PM2_to_r0(int op)
  762. {
  763. tr_PMX_to_r0(2);
  764. }
  765. static void tr_XST_to_r0(int op)
  766. {
  767. EOP_ADD_IMM(0, 7, 24/2, 4); // add r0, r7, #0x400
  768. EOP_LDRH_IMM(0, 0, SSP_XST*4+2);
  769. }
  770. static void tr_PM4_to_r0(int op)
  771. {
  772. tr_PMX_to_r0(4);
  773. }
  774. static void tr_PMC_to_r0(int op)
  775. {
  776. if (known_regb & KRREG_PMC)
  777. {
  778. if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) {
  779. known_regs.emu_status |= SSP_PMC_SET;
  780. known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
  781. // do nothing - this is handled elsewhere
  782. } else {
  783. tr_mov16(0, known_regs.pmc.l);
  784. known_regs.emu_status |= SSP_PMC_HAVE_ADDR;
  785. }
  786. }
  787. else
  788. {
  789. EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
  790. tr_flush_dirty_ST();
  791. if (op != 0x000e)
  792. EOP_LDR_IMM(0, 7, 0x400+SSP_PMC*4);
  793. EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR);
  794. EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #..
  795. EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #..
  796. EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET); // orrne r1, r1, #..
  797. EOP_STR_IMM(1,7,0x484);
  798. hostreg_r[0] = hostreg_r[1] = -1;
  799. }
  800. }
  801. typedef void (tr_read_func)(int op);
  802. static tr_read_func *tr_read_funcs[16] =
  803. {
  804. tr_GR0_to_r0,
  805. tr_X_to_r0,
  806. tr_Y_to_r0,
  807. tr_A_to_r0,
  808. tr_ST_to_r0,
  809. tr_STACK_to_r0,
  810. tr_PC_to_r0,
  811. tr_P_to_r0,
  812. tr_PM0_to_r0,
  813. tr_PM1_to_r0,
  814. tr_PM2_to_r0,
  815. tr_XST_to_r0,
  816. tr_PM4_to_r0,
  817. (tr_read_func *)tr_unhandled,
  818. tr_PMC_to_r0,
  819. tr_AL_to_r0
  820. };
  821. // write r0 to general reg handlers. Trashes r1
  822. #define TR_WRITE_R0_TO_REG(reg) \
  823. { \
  824. hostreg_sspreg_changed(reg); \
  825. hostreg_r[0] = (reg)<<16; \
  826. if (const_val != -1) { \
  827. known_regs.gr[reg].h = const_val; \
  828. known_regb |= 1 << (reg); \
  829. } else { \
  830. known_regb &= ~(1 << (reg)); \
  831. } \
  832. }
  833. static void tr_r0_to_GR0(int const_val)
  834. {
  835. // do nothing
  836. }
  837. static void tr_r0_to_X(int const_val)
  838. {
  839. EOP_MOV_REG_LSL(4, 4, 16); // mov r4, r4, lsl #16
  840. EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16
  841. EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16
  842. dirty_regb |= KRREG_P; // touching X or Y makes P dirty.
  843. TR_WRITE_R0_TO_REG(SSP_X);
  844. }
  845. static void tr_r0_to_Y(int const_val)
  846. {
  847. EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16
  848. EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16
  849. EOP_MOV_REG_ROR(4, 4, 16); // mov r4, r4, ror #16
  850. dirty_regb |= KRREG_P;
  851. TR_WRITE_R0_TO_REG(SSP_Y);
  852. }
  853. static void tr_r0_to_A(int const_val)
  854. {
  855. if (tr_predict_al_need()) {
  856. EOP_MOV_REG_LSL(5, 5, 16); // mov r5, r5, lsl #16
  857. EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsr #16 @ AL
  858. EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16
  859. }
  860. else
  861. EOP_MOV_REG_LSL(5, 0, 16);
  862. TR_WRITE_R0_TO_REG(SSP_A);
  863. }
  864. static void tr_r0_to_ST(int const_val)
  865. {
  866. // VR doesn't need much accuracy here..
  867. EOP_AND_IMM(1, 0, 0, 0x67); // and r1, r0, #0x67
  868. EOP_AND_IMM(6, 6, 8/2, 0xe0); // and r6, r6, #7<<29 @ preserve STACK
  869. EOP_ORR_REG_LSL(6, 6, 1, 4); // orr r6, r6, r1, lsl #4
  870. TR_WRITE_R0_TO_REG(SSP_ST);
  871. hostreg_r[1] = -1;
  872. dirty_regb &= ~KRREG_ST;
  873. }
  874. static void tr_r0_to_STACK(int const_val)
  875. {
  876. // 448
  877. EOP_ADD_IMM(1, 7, 24/2, 0x04); // add r1, r7, 0x400
  878. EOP_ADD_IMM(1, 1, 0, 0x48); // add r1, r1, 0x048
  879. EOP_ADD_REG_LSR(1, 1, 6, 28); // add r1, r1, r6, lsr #28
  880. EOP_STRH_SIMPLE(0, 1); // strh r0, [r1]
  881. EOP_ADD_IMM(6, 6, 8/2, 0x20); // add r6, r6, #1<<29
  882. hostreg_r[1] = -1;
  883. }
  884. static void tr_r0_to_PC(int const_val)
  885. {
  886. /*
  887. * do nothing - dispatcher will take care of this
  888. EOP_MOV_REG_LSL(1, 0, 16); // mov r1, r0, lsl #16
  889. EOP_STR_IMM(1,7,0x400+6*4); // str r1, [r7, #(0x400+6*8)]
  890. hostreg_r[1] = -1;
  891. */
  892. }
  893. static void tr_r0_to_AL(int const_val)
  894. {
  895. EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsr #16
  896. EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16
  897. EOP_MOV_REG_ROR(5, 5, 16); // mov r5, r5, ror #16
  898. hostreg_sspreg_changed(SSP_AL);
  899. if (const_val != -1) {
  900. known_regs.gr[SSP_A].l = const_val;
  901. known_regb |= 1 << SSP_AL;
  902. } else
  903. known_regb &= ~(1 << SSP_AL);
  904. }
  905. static void tr_r0_to_PMX(int reg)
  906. {
  907. if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET))
  908. {
  909. known_regs.pmac_write[reg] = known_regs.pmc.v;
  910. known_regs.emu_status &= ~SSP_PMC_SET;
  911. known_regb |= 1 << (25+reg);
  912. dirty_regb |= 1 << (25+reg);
  913. return;
  914. }
  915. if ((known_regb & KRREG_PMC) && (known_regb & (1 << (25+reg))))
  916. {
  917. int mode, addr;
  918. known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
  919. mode = known_regs.pmac_write[reg]>>16;
  920. addr = known_regs.pmac_write[reg]&0xffff;
  921. if ((mode & 0x43ff) == 0x0018) // DRAM
  922. {
  923. int inc = get_inc(mode);
  924. if (mode & 0x0400) tr_unhandled();
  925. EOP_LDR_IMM(1,7,0x490); // dram_ptr
  926. emith_move_r_imm(2, addr << 1);
  927. EOP_STRH_REG(0,1,2); // strh r0, [r1, r2]
  928. known_regs.pmac_write[reg] += inc;
  929. }
  930. else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
  931. {
  932. if (mode & 0x0400) tr_unhandled();
  933. EOP_LDR_IMM(1,7,0x490); // dram_ptr
  934. emith_move_r_imm(2, addr << 1);
  935. EOP_STRH_REG(0,1,2); // strh r0, [r1, r2]
  936. known_regs.pmac_write[reg] += (addr&1) ? 31 : 1;
  937. }
  938. else if ((mode & 0x47ff) == 0x001c) // IRAM
  939. {
  940. int inc = get_inc(mode);
  941. EOP_LDR_IMM(1,7,0x48c); // iram_ptr
  942. emith_move_r_imm(2, (addr&0x3ff) << 1);
  943. EOP_STRH_REG(0,1,2); // strh r0, [r1, r2]
  944. EOP_MOV_IMM(1,0,1);
  945. EOP_STR_IMM(1,7,0x494); // iram_dirty
  946. known_regs.pmac_write[reg] += inc;
  947. }
  948. else
  949. tr_unhandled();
  950. known_regs.pmc.v = known_regs.pmac_write[reg];
  951. //known_regb |= KRREG_PMC;
  952. dirty_regb |= KRREG_PMC;
  953. dirty_regb |= 1 << (25+reg);
  954. hostreg_r[1] = hostreg_r[2] = -1;
  955. return;
  956. }
  957. known_regb &= ~KRREG_PMC;
  958. dirty_regb &= ~KRREG_PMC;
  959. known_regb &= ~(1 << (25+reg));
  960. dirty_regb &= ~(1 << (25+reg));
  961. // call the C code to handle this
  962. tr_flush_dirty_ST();
  963. //tr_flush_dirty_pmcrs();
  964. tr_mov16(1, reg);
  965. emith_call(ssp_pm_write);
  966. hostreg_clear();
  967. }
  968. static void tr_r0_to_PM0(int const_val)
  969. {
  970. tr_r0_to_PMX(0);
  971. }
  972. static void tr_r0_to_PM1(int const_val)
  973. {
  974. tr_r0_to_PMX(1);
  975. }
  976. static void tr_r0_to_PM2(int const_val)
  977. {
  978. tr_r0_to_PMX(2);
  979. }
  980. static void tr_r0_to_PM4(int const_val)
  981. {
  982. tr_r0_to_PMX(4);
  983. }
  984. static void tr_r0_to_PMC(int const_val)
  985. {
  986. if ((known_regb & KRREG_PMC) && const_val != -1)
  987. {
  988. if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) {
  989. known_regs.emu_status |= SSP_PMC_SET;
  990. known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
  991. known_regs.pmc.h = const_val;
  992. } else {
  993. known_regs.emu_status |= SSP_PMC_HAVE_ADDR;
  994. known_regs.pmc.l = const_val;
  995. }
  996. }
  997. else
  998. {
  999. tr_flush_dirty_ST();
  1000. if (known_regb & KRREG_PMC) {
  1001. emith_move_r_imm(1, known_regs.pmc.v);
  1002. EOP_STR_IMM(1,7,0x400+SSP_PMC*4);
  1003. known_regb &= ~KRREG_PMC;
  1004. dirty_regb &= ~KRREG_PMC;
  1005. }
  1006. EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
  1007. EOP_ADD_IMM(2,7,24/2,4); // add r2, r7, #0x400
  1008. EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR);
  1009. EOP_C_AM3_IMM(A_COND_EQ,1,0,2,0,0,1,SSP_PMC*4); // strxx r0, [r2, #SSP_PMC]
  1010. EOP_C_AM3_IMM(A_COND_NE,1,0,2,0,0,1,SSP_PMC*4+2);
  1011. EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #..
  1012. EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #..
  1013. EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET); // orrne r1, r1, #..
  1014. EOP_STR_IMM(1,7,0x484);
  1015. hostreg_r[1] = hostreg_r[2] = -1;
  1016. }
  1017. }
  1018. typedef void (tr_write_func)(int const_val);
  1019. static tr_write_func *tr_write_funcs[16] =
  1020. {
  1021. tr_r0_to_GR0,
  1022. tr_r0_to_X,
  1023. tr_r0_to_Y,
  1024. tr_r0_to_A,
  1025. tr_r0_to_ST,
  1026. tr_r0_to_STACK,
  1027. tr_r0_to_PC,
  1028. (tr_write_func *)tr_unhandled,
  1029. tr_r0_to_PM0,
  1030. tr_r0_to_PM1,
  1031. tr_r0_to_PM2,
  1032. (tr_write_func *)tr_unhandled,
  1033. tr_r0_to_PM4,
  1034. (tr_write_func *)tr_unhandled,
  1035. tr_r0_to_PMC,
  1036. tr_r0_to_AL
  1037. };
  1038. static void tr_mac_load_XY(int op)
  1039. {
  1040. tr_rX_read(op&3, (op>>2)&3); // X
  1041. EOP_MOV_REG_LSL(4, 0, 16);
  1042. tr_rX_read(((op>>4)&3)|4, (op>>6)&3); // Y
  1043. EOP_ORR_REG_SIMPLE(4, 0);
  1044. dirty_regb |= KRREG_P;
  1045. hostreg_sspreg_changed(SSP_X);
  1046. hostreg_sspreg_changed(SSP_Y);
  1047. known_regb &= ~KRREG_X;
  1048. known_regb &= ~KRREG_Y;
  1049. }
  1050. // -----------------------------------------------------
  1051. static int tr_detect_set_pm(unsigned int op, int *pc, int imm)
  1052. {
  1053. u32 pmcv, tmpv;
  1054. if (!((op&0xfef0) == 0x08e0 && (PROGRAM(*pc)&0xfef0) == 0x08e0)) return 0;
  1055. // programming PMC:
  1056. // ldi PMC, imm1
  1057. // ldi PMC, imm2
  1058. (*pc)++;
  1059. pmcv = imm | (PROGRAM((*pc)++) << 16);
  1060. known_regs.pmc.v = pmcv;
  1061. known_regb |= KRREG_PMC;
  1062. dirty_regb |= KRREG_PMC;
  1063. known_regs.emu_status |= SSP_PMC_SET;
  1064. n_in_ops++;
  1065. // check for possible reg programming
  1066. tmpv = PROGRAM(*pc);
  1067. if ((tmpv & 0xfff8) == 0x08 || (tmpv & 0xff8f) == 0x80)
  1068. {
  1069. int is_write = (tmpv & 0xff8f) == 0x80;
  1070. int reg = is_write ? ((tmpv>>4)&0x7) : (tmpv&0x7);
  1071. if (reg > 4) tr_unhandled();
  1072. if ((tmpv & 0x0f) != 0 && (tmpv & 0xf0) != 0) tr_unhandled();
  1073. if (is_write)
  1074. known_regs.pmac_write[reg] = pmcv;
  1075. else
  1076. known_regs.pmac_read[reg] = pmcv;
  1077. known_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20));
  1078. dirty_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20));
  1079. known_regs.emu_status &= ~SSP_PMC_SET;
  1080. (*pc)++;
  1081. n_in_ops++;
  1082. return 5;
  1083. }
  1084. tr_unhandled();
  1085. return 4;
  1086. }
  1087. static const short pm0_block_seq[] = { 0x0880, 0, 0x0880, 0, 0x0840, 0x60 };
  1088. static int tr_detect_pm0_block(unsigned int op, int *pc, int imm)
  1089. {
  1090. // ldi ST, 0
  1091. // ldi PM0, 0
  1092. // ldi PM0, 0
  1093. // ldi ST, 60h
  1094. unsigned short *pp;
  1095. if (op != 0x0840 || imm != 0) return 0;
  1096. pp = PROGRAM_P(*pc);
  1097. if (memcmp(pp, pm0_block_seq, sizeof(pm0_block_seq)) != 0) return 0;
  1098. EOP_AND_IMM(6, 6, 8/2, 0xe0); // and r6, r6, #7<<29 @ preserve STACK
  1099. EOP_ORR_IMM(6, 6, 24/2, 6); // orr r6, r6, 0x600
  1100. hostreg_sspreg_changed(SSP_ST);
  1101. known_regs.gr[SSP_ST].h = 0x60;
  1102. known_regb |= 1 << SSP_ST;
  1103. dirty_regb &= ~KRREG_ST;
  1104. (*pc) += 3*2;
  1105. n_in_ops += 3;
  1106. return 4*2;
  1107. }
  1108. static int tr_detect_rotate(unsigned int op, int *pc, int imm)
  1109. {
  1110. // @ 3DA2 and 426A
  1111. // ld PMC, (r3|00)
  1112. // ld (r3|00), PMC
  1113. // ld -, AL
  1114. if (op != 0x02e3 || PROGRAM(*pc) != 0x04e3 || PROGRAM(*pc + 1) != 0x000f) return 0;
  1115. tr_bank_read(0);
  1116. EOP_MOV_REG_LSL(0, 0, 4);
  1117. EOP_ORR_REG_LSR(0, 0, 0, 16);
  1118. tr_bank_write(0);
  1119. (*pc) += 2;
  1120. n_in_ops += 2;
  1121. return 3;
  1122. }
  1123. // -----------------------------------------------------
  1124. static int translate_op(unsigned int op, int *pc, int imm, int *end_cond, int *jump_pc)
  1125. {
  1126. u32 tmpv, tmpv2, tmpv3;
  1127. int ret = 0;
  1128. known_regs.gr[SSP_PC].h = *pc;
  1129. switch (op >> 9)
  1130. {
  1131. // ld d, s
  1132. case 0x00:
  1133. if (op == 0) { ret++; break; } // nop
  1134. tmpv = op & 0xf; // src
  1135. tmpv2 = (op >> 4) & 0xf; // dst
  1136. if (tmpv2 == SSP_A && tmpv == SSP_P) { // ld A, P
  1137. tr_flush_dirty_P();
  1138. EOP_MOV_REG_SIMPLE(5, 10);
  1139. hostreg_sspreg_changed(SSP_A);
  1140. known_regb &= ~(KRREG_A|KRREG_AL);
  1141. ret++; break;
  1142. }
  1143. tr_read_funcs[tmpv](op);
  1144. tr_write_funcs[tmpv2]((known_regb & (1 << tmpv)) ? known_regs.gr[tmpv].h : -1);
  1145. if (tmpv2 == SSP_PC) {
  1146. ret |= 0x10000;
  1147. *end_cond = -A_COND_AL;
  1148. }
  1149. ret++; break;
  1150. // ld d, (ri)
  1151. case 0x01: {
  1152. int r = (op&3) | ((op>>6)&4);
  1153. int mod = (op>>2)&3;
  1154. tmpv = (op >> 4) & 0xf; // dst
  1155. ret = tr_detect_rotate(op, pc, imm);
  1156. if (ret > 0) break;
  1157. if (tmpv != 0)
  1158. tr_rX_read(r, mod);
  1159. else {
  1160. int cnt = 1;
  1161. while (PROGRAM(*pc) == op) {
  1162. (*pc)++; cnt++; ret++;
  1163. n_in_ops++;
  1164. }
  1165. tr_ptrr_mod(r, mod, 1, cnt); // skip
  1166. }
  1167. tr_write_funcs[tmpv](-1);
  1168. if (tmpv == SSP_PC) {
  1169. ret |= 0x10000;
  1170. *end_cond = -A_COND_AL;
  1171. }
  1172. ret++; break;
  1173. }
  1174. // ld (ri), s
  1175. case 0x02:
  1176. tmpv = (op >> 4) & 0xf; // src
  1177. tr_read_funcs[tmpv](op);
  1178. tr_rX_write(op);
  1179. ret++; break;
  1180. // ld a, adr
  1181. case 0x03:
  1182. tr_bank_read(op&0x1ff);
  1183. tr_r0_to_A(-1);
  1184. ret++; break;
  1185. // ldi d, imm
  1186. case 0x04:
  1187. tmpv = (op & 0xf0) >> 4; // dst
  1188. ret = tr_detect_pm0_block(op, pc, imm);
  1189. if (ret > 0) break;
  1190. ret = tr_detect_set_pm(op, pc, imm);
  1191. if (ret > 0) break;
  1192. tr_mov16(0, imm);
  1193. tr_write_funcs[tmpv](imm);
  1194. if (tmpv == SSP_PC) {
  1195. ret |= 0x10000;
  1196. *jump_pc = imm;
  1197. }
  1198. ret += 2; break;
  1199. // ld d, ((ri))
  1200. case 0x05:
  1201. tmpv2 = (op >> 4) & 0xf; // dst
  1202. tr_rX_read2(op);
  1203. tr_write_funcs[tmpv2](-1);
  1204. if (tmpv2 == SSP_PC) {
  1205. ret |= 0x10000;
  1206. *end_cond = -A_COND_AL;
  1207. }
  1208. ret += 3; break;
  1209. // ldi (ri), imm
  1210. case 0x06:
  1211. tr_mov16(0, imm);
  1212. tr_rX_write(op);
  1213. ret += 2; break;
  1214. // ld adr, a
  1215. case 0x07:
  1216. tr_A_to_r0(op);
  1217. tr_bank_write(op&0x1ff);
  1218. ret++; break;
  1219. // ld d, ri
  1220. case 0x09: {
  1221. int r;
  1222. r = (op&3) | ((op>>6)&4); // src
  1223. tmpv2 = (op >> 4) & 0xf; // dst
  1224. if ((r&3) == 3) tr_unhandled();
  1225. if (known_regb & (1 << (r+8))) {
  1226. tr_mov16(0, known_regs.r[r]);
  1227. tr_write_funcs[tmpv2](known_regs.r[r]);
  1228. } else {
  1229. int reg = (r < 4) ? 8 : 9;
  1230. if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8); // mov r0, r{7,8}, lsr #lsr
  1231. EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff); // and r0, r{7,8}, <mask>
  1232. hostreg_r[0] = -1;
  1233. tr_write_funcs[tmpv2](-1);
  1234. }
  1235. ret++; break;
  1236. }
  1237. // ld ri, s
  1238. case 0x0a: {
  1239. int r;
  1240. r = (op&3) | ((op>>6)&4); // dst
  1241. tmpv = (op >> 4) & 0xf; // src
  1242. if ((r&3) == 3) tr_unhandled();
  1243. if (known_regb & (1 << tmpv)) {
  1244. known_regs.r[r] = known_regs.gr[tmpv].h;
  1245. known_regb |= 1 << (r + 8);
  1246. dirty_regb |= 1 << (r + 8);
  1247. } else {
  1248. int reg = (r < 4) ? 8 : 9;
  1249. int ror = ((4 - (r&3))*8) & 0x1f;
  1250. tr_read_funcs[tmpv](op);
  1251. EOP_BIC_IMM(reg, reg, ror/2, 0xff); // bic r{7,8}, r{7,8}, <mask>
  1252. EOP_AND_IMM(0, 0, 0, 0xff); // and r0, r0, 0xff
  1253. EOP_ORR_REG_LSL(reg, reg, 0, (r&3)*8); // orr r{7,8}, r{7,8}, r0, lsl #lsl
  1254. hostreg_r[0] = -1;
  1255. known_regb &= ~(1 << (r+8));
  1256. dirty_regb &= ~(1 << (r+8));
  1257. }
  1258. ret++; break;
  1259. }
  1260. // ldi ri, simm
  1261. case 0x0c: case 0x0d: case 0x0e: case 0x0f:
  1262. tmpv = (op>>8)&7;
  1263. known_regs.r[tmpv] = op;
  1264. known_regb |= 1 << (tmpv + 8);
  1265. dirty_regb |= 1 << (tmpv + 8);
  1266. ret++; break;
  1267. // call cond, addr
  1268. case 0x24: {
  1269. u32 *jump_op = NULL;
  1270. tmpv = tr_cond_check(op);
  1271. if (tmpv != A_COND_AL) {
  1272. jump_op = tcache_ptr;
  1273. EOP_MOV_IMM(0, 0, 0); // placeholder for branch
  1274. }
  1275. tr_mov16(0, *pc);
  1276. tr_r0_to_STACK(*pc);
  1277. if (tmpv != A_COND_AL) {
  1278. u32 *real_ptr = tcache_ptr;
  1279. tcache_ptr = jump_op;
  1280. EOP_C_B(tr_neg_cond(tmpv),0,real_ptr - jump_op - 2);
  1281. tcache_ptr = real_ptr;
  1282. }
  1283. tr_mov16_cond(tmpv, 0, imm);
  1284. if (tmpv != A_COND_AL)
  1285. tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
  1286. tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
  1287. ret |= 0x10000;
  1288. *end_cond = tmpv;
  1289. *jump_pc = imm;
  1290. ret += 2; break;
  1291. }
  1292. // ld d, (a)
  1293. case 0x25:
  1294. tmpv2 = (op >> 4) & 0xf; // dst
  1295. tr_A_to_r0(op);
  1296. EOP_LDR_IMM(1,7,0x48c); // ptr_iram_rom
  1297. EOP_ADD_REG_LSL(0,1,0,1); // add r0, r1, r0, lsl #1
  1298. EOP_LDRH_SIMPLE(0,0); // ldrh r0, [r0]
  1299. hostreg_r[0] = hostreg_r[1] = -1;
  1300. tr_write_funcs[tmpv2](-1);
  1301. if (tmpv2 == SSP_PC) {
  1302. ret |= 0x10000;
  1303. *end_cond = -A_COND_AL;
  1304. }
  1305. ret += 3; break;
  1306. // bra cond, addr
  1307. case 0x26:
  1308. tmpv = tr_cond_check(op);
  1309. tr_mov16_cond(tmpv, 0, imm);
  1310. if (tmpv != A_COND_AL)
  1311. tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
  1312. tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
  1313. ret |= 0x10000;
  1314. *end_cond = tmpv;
  1315. *jump_pc = imm;
  1316. ret += 2; break;
  1317. // mod cond, op
  1318. case 0x48: {
  1319. // check for repeats of this op
  1320. tmpv = 1; // count
  1321. while (PROGRAM(*pc) == op && (op & 7) != 6) {
  1322. (*pc)++; tmpv++;
  1323. n_in_ops++;
  1324. }
  1325. if ((op&0xf0) != 0) // !always
  1326. tr_make_dirty_ST();
  1327. tmpv2 = tr_cond_check(op);
  1328. switch (op & 7) {
  1329. case 2: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_ASR,5); break; // shr (arithmetic)
  1330. case 3: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_LSL,5); break; // shl
  1331. case 6: EOP_C_DOP_IMM(tmpv2,A_OP_RSB,1,5,5,0,0); break; // neg
  1332. case 7: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_EOR,0,5,1,31,A_AM1_ASR,5); // eor r1, r5, r5, asr #31
  1333. EOP_C_DOP_REG_XIMM(tmpv2,A_OP_ADD,1,1,5,31,A_AM1_LSR,5); // adds r5, r1, r5, lsr #31
  1334. hostreg_r[1] = -1; break; // abs
  1335. default: tr_unhandled();
  1336. }
  1337. hostreg_sspreg_changed(SSP_A);
  1338. dirty_regb |= KRREG_ST;
  1339. known_regb &= ~KRREG_ST;
  1340. known_regb &= ~(KRREG_A|KRREG_AL);
  1341. ret += tmpv; break;
  1342. }
  1343. // mpys?
  1344. case 0x1b:
  1345. tr_flush_dirty_P();
  1346. tr_mac_load_XY(op);
  1347. tr_make_dirty_ST();
  1348. EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_SUB,1,5,5,0,A_AM1_LSL,10); // subs r5, r5, r10
  1349. hostreg_sspreg_changed(SSP_A);
  1350. known_regb &= ~(KRREG_A|KRREG_AL);
  1351. dirty_regb |= KRREG_ST;
  1352. ret++; break;
  1353. // mpya (rj), (ri), b
  1354. case 0x4b:
  1355. tr_flush_dirty_P();
  1356. tr_mac_load_XY(op);
  1357. tr_make_dirty_ST();
  1358. EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ADD,1,5,5,0,A_AM1_LSL,10); // adds r5, r5, r10
  1359. hostreg_sspreg_changed(SSP_A);
  1360. known_regb &= ~(KRREG_A|KRREG_AL);
  1361. dirty_regb |= KRREG_ST;
  1362. ret++; break;
  1363. // mld (rj), (ri), b
  1364. case 0x5b:
  1365. EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,1,0,5,0,0); // movs r5, #0
  1366. hostreg_sspreg_changed(SSP_A);
  1367. known_regs.gr[SSP_A].v = 0;
  1368. known_regb |= (KRREG_A|KRREG_AL);
  1369. dirty_regb |= KRREG_ST;
  1370. tr_mac_load_XY(op);
  1371. ret++; break;
  1372. // OP a, s
  1373. case 0x10:
  1374. case 0x30:
  1375. case 0x40:
  1376. case 0x50:
  1377. case 0x60:
  1378. case 0x70:
  1379. tmpv = op & 0xf; // src
  1380. tmpv2 = tr_aop_ssp2arm(op>>13); // op
  1381. tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
  1382. if (tmpv == SSP_P) {
  1383. tr_flush_dirty_P();
  1384. EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL,10); // OPs r5, r5, r10
  1385. } else if (tmpv == SSP_A) {
  1386. EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL, 5); // OPs r5, r5, r5
  1387. } else {
  1388. tr_read_funcs[tmpv](op);
  1389. EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL, 0); // OPs r5, r5, r0, lsl #16
  1390. }
  1391. hostreg_sspreg_changed(SSP_A);
  1392. known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
  1393. dirty_regb |= KRREG_ST;
  1394. ret++; break;
  1395. // OP a, (ri)
  1396. case 0x11:
  1397. case 0x31:
  1398. case 0x41:
  1399. case 0x51:
  1400. case 0x61:
  1401. case 0x71:
  1402. tmpv2 = tr_aop_ssp2arm(op>>13); // op
  1403. tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
  1404. tr_rX_read((op&3)|((op>>6)&4), (op>>2)&3);
  1405. EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
  1406. hostreg_sspreg_changed(SSP_A);
  1407. known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
  1408. dirty_regb |= KRREG_ST;
  1409. ret++; break;
  1410. // OP a, adr
  1411. case 0x13:
  1412. case 0x33:
  1413. case 0x43:
  1414. case 0x53:
  1415. case 0x63:
  1416. case 0x73:
  1417. tmpv2 = tr_aop_ssp2arm(op>>13); // op
  1418. tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
  1419. tr_bank_read(op&0x1ff);
  1420. EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
  1421. hostreg_sspreg_changed(SSP_A);
  1422. known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
  1423. dirty_regb |= KRREG_ST;
  1424. ret++; break;
  1425. // OP a, imm
  1426. case 0x14:
  1427. case 0x34:
  1428. case 0x44:
  1429. case 0x54:
  1430. case 0x64:
  1431. case 0x74:
  1432. tmpv = (op & 0xf0) >> 4;
  1433. tmpv2 = tr_aop_ssp2arm(op>>13); // op
  1434. tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
  1435. tr_mov16(0, imm);
  1436. EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
  1437. hostreg_sspreg_changed(SSP_A);
  1438. known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
  1439. dirty_regb |= KRREG_ST;
  1440. ret += 2; break;
  1441. // OP a, ((ri))
  1442. case 0x15:
  1443. case 0x35:
  1444. case 0x45:
  1445. case 0x55:
  1446. case 0x65:
  1447. case 0x75:
  1448. tmpv2 = tr_aop_ssp2arm(op>>13); // op
  1449. tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
  1450. tr_rX_read2(op);
  1451. EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
  1452. hostreg_sspreg_changed(SSP_A);
  1453. known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
  1454. dirty_regb |= KRREG_ST;
  1455. ret += 3; break;
  1456. // OP a, ri
  1457. case 0x19:
  1458. case 0x39:
  1459. case 0x49:
  1460. case 0x59:
  1461. case 0x69:
  1462. case 0x79: {
  1463. int r;
  1464. tmpv2 = tr_aop_ssp2arm(op>>13); // op
  1465. tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
  1466. r = (op&3) | ((op>>6)&4); // src
  1467. if ((r&3) == 3) tr_unhandled();
  1468. if (known_regb & (1 << (r+8))) {
  1469. EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,known_regs.r[r]); // OPs r5, r5, #val<<16
  1470. } else {
  1471. int reg = (r < 4) ? 8 : 9;
  1472. if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8); // mov r0, r{7,8}, lsr #lsr
  1473. EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff); // and r0, r{7,8}, <mask>
  1474. EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
  1475. hostreg_r[0] = -1;
  1476. }
  1477. hostreg_sspreg_changed(SSP_A);
  1478. known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
  1479. dirty_regb |= KRREG_ST;
  1480. ret++; break;
  1481. }
  1482. // OP simm
  1483. case 0x1c:
  1484. case 0x3c:
  1485. case 0x4c:
  1486. case 0x5c:
  1487. case 0x6c:
  1488. case 0x7c:
  1489. tmpv2 = tr_aop_ssp2arm(op>>13); // op
  1490. tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
  1491. EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,op & 0xff); // OPs r5, r5, #val<<16
  1492. hostreg_sspreg_changed(SSP_A);
  1493. known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
  1494. dirty_regb |= KRREG_ST;
  1495. ret++; break;
  1496. }
  1497. n_in_ops++;
  1498. return ret;
  1499. }
  1500. static void emit_block_prologue(void)
  1501. {
  1502. // check if there are enough cycles..
  1503. // note: r0 must contain PC of current block
  1504. EOP_CMP_IMM(11,0,0); // cmp r11, #0
  1505. emith_jump_cond(A_COND_LE, ssp_drc_end);
  1506. }
  1507. /* cond:
  1508. * >0: direct (un)conditional jump
  1509. * <0: indirect jump
  1510. */
  1511. static void emit_block_epilogue(int cycles, int cond, int pc, int end_pc)
  1512. {
  1513. if (cycles > 0xff) { elprintf(EL_ANOMALY, "large cycle count: %i\n", cycles); cycles = 0xff; }
  1514. EOP_SUB_IMM(11,11,0,cycles); // sub r11, r11, #cycles
  1515. if (cond < 0 || (end_pc >= 0x400 && pc < 0x400)) {
  1516. // indirect jump, or rom -> iram jump, must use dispatcher
  1517. emith_jump(ssp_drc_next);
  1518. }
  1519. else if (cond == A_COND_AL) {
  1520. u32 *target = (pc < 0x400) ?
  1521. ssp_block_table_iram[ssp->drc.iram_context * SSP_BLOCKTAB_IRAM_ONE + pc] :
  1522. ssp_block_table[pc];
  1523. if (target != NULL)
  1524. emith_jump(target);
  1525. else {
  1526. int ops = emith_jump(ssp_drc_next);
  1527. // cause the next block to be emitted over jump instruction
  1528. tcache_ptr -= ops;
  1529. }
  1530. }
  1531. else {
  1532. u32 *target1 = (pc < 0x400) ?
  1533. ssp_block_table_iram[ssp->drc.iram_context * SSP_BLOCKTAB_IRAM_ONE + pc] :
  1534. ssp_block_table[pc];
  1535. u32 *target2 = (end_pc < 0x400) ?
  1536. ssp_block_table_iram[ssp->drc.iram_context * SSP_BLOCKTAB_IRAM_ONE + end_pc] :
  1537. ssp_block_table[end_pc];
  1538. if (target1 != NULL)
  1539. emith_jump_cond(cond, target1);
  1540. if (target2 != NULL)
  1541. emith_jump_cond(tr_neg_cond(cond), target2); // neg_cond, to be able to swap jumps if needed
  1542. #ifndef __EPOC32__
  1543. // emit patchable branches
  1544. if (target1 == NULL)
  1545. emith_call_cond(cond, ssp_drc_next_patch);
  1546. if (target2 == NULL)
  1547. emith_call_cond(tr_neg_cond(cond), ssp_drc_next_patch);
  1548. #else
  1549. // won't patch indirect jumps
  1550. if (target1 == NULL || target2 == NULL)
  1551. emith_jump(ssp_drc_next);
  1552. #endif
  1553. }
  1554. }
  1555. void *ssp_translate_block(int pc)
  1556. {
  1557. unsigned int op, op1, imm, ccount = 0;
  1558. unsigned int *block_start;
  1559. int ret, end_cond = A_COND_AL, jump_pc = -1;
  1560. //printf("translate %04x -> %04x\n", pc<<1, (tcache_ptr-tcache)<<2);
  1561. block_start = tcache_ptr;
  1562. known_regb = 0;
  1563. dirty_regb = KRREG_P;
  1564. known_regs.emu_status = 0;
  1565. hostreg_clear();
  1566. emit_block_prologue();
  1567. for (; ccount < 100;)
  1568. {
  1569. op = PROGRAM(pc++);
  1570. op1 = op >> 9;
  1571. imm = (u32)-1;
  1572. if ((op1 & 0xf) == 4 || (op1 & 0xf) == 6)
  1573. imm = PROGRAM(pc++); // immediate
  1574. ret = translate_op(op, &pc, imm, &end_cond, &jump_pc);
  1575. if (ret <= 0)
  1576. {
  1577. elprintf(EL_ANOMALY, "NULL func! op=%08x (%02x)\n", op, op1);
  1578. //exit(1);
  1579. }
  1580. ccount += ret & 0xffff;
  1581. if (ret & 0x10000) break;
  1582. }
  1583. if (ccount >= 100) {
  1584. end_cond = A_COND_AL;
  1585. jump_pc = pc;
  1586. emith_move_r_imm(0, pc);
  1587. }
  1588. tr_flush_dirty_prs();
  1589. tr_flush_dirty_ST();
  1590. tr_flush_dirty_pmcrs();
  1591. emit_block_epilogue(ccount, end_cond, jump_pc, pc);
  1592. if (tcache_ptr - (u32 *)tcache > DRC_TCACHE_SIZE/4) {
  1593. elprintf(EL_ANOMALY|EL_STATUS|EL_SVP, "tcache overflow!\n");
  1594. fflush(stdout);
  1595. exit(1);
  1596. }
  1597. // stats
  1598. nblocks++;
  1599. //printf("%i blocks, %i bytes, k=%.3f\n", nblocks, (tcache_ptr - tcache)*4,
  1600. // (double)(tcache_ptr - tcache) / (double)n_in_ops);
  1601. #ifdef DUMP_BLOCK
  1602. {
  1603. FILE *f = fopen("tcache.bin", "wb");
  1604. fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
  1605. fclose(f);
  1606. }
  1607. printf("dumped tcache.bin\n");
  1608. exit(0);
  1609. #endif
  1610. #ifdef __arm__
  1611. cache_flush_d_inval_i(tcache, tcache_ptr);
  1612. #endif
  1613. return block_start;
  1614. }
  1615. // -----------------------------------------------------
  1616. static void ssp1601_state_load(void)
  1617. {
  1618. ssp->drc.iram_dirty = 1;
  1619. ssp->drc.iram_context = 0;
  1620. }
  1621. void ssp1601_dyn_exit(void)
  1622. {
  1623. free(ssp_block_table);
  1624. free(ssp_block_table_iram);
  1625. ssp_block_table = ssp_block_table_iram = NULL;
  1626. drc_cmn_cleanup();
  1627. }
  1628. int ssp1601_dyn_startup(void)
  1629. {
  1630. drc_cmn_init();
  1631. ssp_block_table = calloc(sizeof(ssp_block_table[0]), SSP_BLOCKTAB_ENTS);
  1632. if (ssp_block_table == NULL)
  1633. return -1;
  1634. ssp_block_table_iram = calloc(sizeof(ssp_block_table_iram[0]), SSP_BLOCKTAB_IRAM_ENTS);
  1635. if (ssp_block_table_iram == NULL) {
  1636. free(ssp_block_table);
  1637. return -1;
  1638. }
  1639. memset(tcache, 0, DRC_TCACHE_SIZE);
  1640. tcache_ptr = (void *)tcache;
  1641. PicoLoadStateHook = ssp1601_state_load;
  1642. n_in_ops = 0;
  1643. #ifdef __arm__
  1644. // hle'd blocks
  1645. ssp_block_table[0x800/2] = (void *) ssp_hle_800;
  1646. ssp_block_table[0x902/2] = (void *) ssp_hle_902;
  1647. ssp_block_table_iram[ 7 * SSP_BLOCKTAB_IRAM_ONE + 0x030/2] = (void *) ssp_hle_07_030;
  1648. ssp_block_table_iram[ 7 * SSP_BLOCKTAB_IRAM_ONE + 0x036/2] = (void *) ssp_hle_07_036;
  1649. ssp_block_table_iram[ 7 * SSP_BLOCKTAB_IRAM_ONE + 0x6d6/2] = (void *) ssp_hle_07_6d6;
  1650. ssp_block_table_iram[11 * SSP_BLOCKTAB_IRAM_ONE + 0x12c/2] = (void *) ssp_hle_11_12c;
  1651. ssp_block_table_iram[11 * SSP_BLOCKTAB_IRAM_ONE + 0x384/2] = (void *) ssp_hle_11_384;
  1652. ssp_block_table_iram[11 * SSP_BLOCKTAB_IRAM_ONE + 0x38a/2] = (void *) ssp_hle_11_38a;
  1653. #endif
  1654. return 0;
  1655. }
  1656. void ssp1601_dyn_reset(ssp1601_t *ssp)
  1657. {
  1658. ssp1601_reset(ssp);
  1659. ssp->drc.iram_dirty = 1;
  1660. ssp->drc.iram_context = 0;
  1661. // must do this here because ssp is not available @ startup()
  1662. ssp->drc.ptr_rom = (u32) Pico.rom;
  1663. ssp->drc.ptr_iram_rom = (u32) svp->iram_rom;
  1664. ssp->drc.ptr_dram = (u32) svp->dram;
  1665. ssp->drc.ptr_btable = (u32) ssp_block_table;
  1666. ssp->drc.ptr_btable_iram = (u32) ssp_block_table_iram;
  1667. // prevent new versions of IRAM from appearing
  1668. memset(svp->iram_rom, 0, 0x800);
  1669. }
  1670. void ssp1601_dyn_run(int cycles)
  1671. {
  1672. if (ssp->emu_status & SSP_WAIT_MASK) return;
  1673. #ifdef DUMP_BLOCK
  1674. ssp_translate_block(DUMP_BLOCK >> 1);
  1675. #endif
  1676. #ifdef __arm__
  1677. ssp_drc_entry(cycles);
  1678. #endif
  1679. }