memory.c 55 KB

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  1. /*
  2. * PicoDrive
  3. * (C) notaz, 2009,2010,2013
  4. *
  5. * This work is licensed under the terms of MAME license.
  6. * See COPYING file in the top-level directory.
  7. *
  8. * Register map:
  9. * a15100 F....... R.....EA F.....AC N...VHMP 4000 // Fm Ren nrEs Aden Cart heN V H cMd Pwm
  10. * a15102 ........ ......SM ? 4002 // intS intM
  11. * a15104 ........ ......10 ........ hhhhhhhh 4004 // bk1 bk0 Hint
  12. * a15106 ........ F....SDR UE...... .....SDR 4006 // Full 68S Dma Rv fUll[fb] Empt[fb]
  13. * a15108 (32bit DREQ src) 4008
  14. * a1510c (32bit DREQ dst) 400c
  15. * a15110 llllllll llllll00 4010 // DREQ Len
  16. * a15112 (16bit FIFO reg) 4012
  17. * a15114 0 (16bit VRES clr) 4014
  18. * a15116 0 (16bit Vint clr) 4016
  19. * a15118 0 (16bit Hint clr) 4018
  20. * a1511a .......? .......C (16bit CMD clr) 401a // TV Cm
  21. * a1511c 0 (16bit PWM clr) 401c
  22. * a1511e 0 ? 401e
  23. * a15120 (16 bytes comm) 2020
  24. * a15130 (PWM) 2030
  25. *
  26. * SH2 addr lines:
  27. * iii. .cc. ..xx * // Internal, Cs, x
  28. *
  29. * sh2 map, wait/bus cycles (from docs):
  30. * r w
  31. * rom 0000000-0003fff 1 -
  32. * sys reg 0004000-00040ff 1 1
  33. * vdp reg 0004100-00041ff 5 5
  34. * vdp pal 0004200-00043ff 5 5
  35. * cart 2000000-23fffff 6-15
  36. * dram/fb 4000000-401ffff 5-12 1-3
  37. * fb ovr 4020000-403ffff
  38. * sdram 6000000-603ffff 12 2 (cycles)
  39. * d.a. c0000000-?
  40. */
  41. #include "../pico_int.h"
  42. #include "../memory.h"
  43. #include "../../cpu/sh2/compiler.h"
  44. DRC_DECLARE_SR;
  45. static const char str_mars[] = "MARS";
  46. void *p32x_bios_g, *p32x_bios_m, *p32x_bios_s;
  47. struct Pico32xMem *Pico32xMem;
  48. static void bank_switch_rom_68k(int b);
  49. static void (*m68k_write8_io)(u32 a, u32 d);
  50. static void (*m68k_write16_io)(u32 a, u32 d);
  51. // addressing byte in 16bit reg
  52. #define REG8IN16(ptr, offs) ((u8 *)ptr)[(offs) ^ 1]
  53. // poll detection
  54. #define POLL_THRESHOLD 3
  55. static struct {
  56. u32 addr, cycles;
  57. int cnt;
  58. } m68k_poll;
  59. static int m68k_poll_detect(u32 a, u32 cycles, u32 flags)
  60. {
  61. int ret = 0;
  62. if (a - 2 <= m68k_poll.addr && m68k_poll.addr <= a + 2
  63. && cycles - m68k_poll.cycles <= 64 && !SekNotPolling)
  64. {
  65. if (m68k_poll.cnt++ > POLL_THRESHOLD) {
  66. if (!(Pico32x.emu_flags & flags)) {
  67. elprintf(EL_32X, "m68k poll addr %08x, cyc %u",
  68. a, cycles - m68k_poll.cycles);
  69. ret = 1;
  70. }
  71. Pico32x.emu_flags |= flags;
  72. }
  73. }
  74. else {
  75. m68k_poll.cnt = 0;
  76. m68k_poll.addr = a;
  77. SekNotPolling = 0;
  78. }
  79. m68k_poll.cycles = cycles;
  80. return ret;
  81. }
  82. void p32x_m68k_poll_event(u32 flags)
  83. {
  84. if (Pico32x.emu_flags & flags) {
  85. elprintf(EL_32X, "m68k poll %02x -> %02x", Pico32x.emu_flags,
  86. Pico32x.emu_flags & ~flags);
  87. Pico32x.emu_flags &= ~flags;
  88. SekSetStop(0);
  89. }
  90. m68k_poll.addr = m68k_poll.cnt = 0;
  91. }
  92. static void sh2_poll_detect(SH2 *sh2, u32 a, u32 flags, int maxcnt)
  93. {
  94. int cycles_left = sh2_cycles_left(sh2);
  95. if (a == sh2->poll_addr && sh2->poll_cycles - cycles_left <= 10) {
  96. if (sh2->poll_cnt++ > maxcnt) {
  97. if (!(sh2->state & flags))
  98. elprintf_sh2(sh2, EL_32X, "state: %02x->%02x",
  99. sh2->state, sh2->state | flags);
  100. sh2->state |= flags;
  101. sh2_end_run(sh2, 1);
  102. pevt_log_sh2(sh2, EVT_POLL_START);
  103. return;
  104. }
  105. }
  106. else
  107. sh2->poll_cnt = 0;
  108. sh2->poll_addr = a;
  109. sh2->poll_cycles = cycles_left;
  110. }
  111. void p32x_sh2_poll_event(SH2 *sh2, u32 flags, u32 m68k_cycles)
  112. {
  113. if (sh2->state & flags) {
  114. elprintf_sh2(sh2, EL_32X, "state: %02x->%02x", sh2->state,
  115. sh2->state & ~flags);
  116. if (sh2->m68krcycles_done < m68k_cycles)
  117. sh2->m68krcycles_done = m68k_cycles;
  118. pevt_log_sh2_o(sh2, EVT_POLL_END);
  119. }
  120. sh2->state &= ~flags;
  121. sh2->poll_addr = sh2->poll_cycles = sh2->poll_cnt = 0;
  122. }
  123. static void sh2s_sync_on_read(SH2 *sh2)
  124. {
  125. int cycles;
  126. if (sh2->poll_cnt != 0)
  127. return;
  128. cycles = sh2_cycles_done(sh2);
  129. if (cycles > 600)
  130. p32x_sync_other_sh2(sh2, sh2->m68krcycles_done + C_SH2_TO_M68K(sh2, cycles));
  131. }
  132. // SH2 faking
  133. //#define FAKE_SH2
  134. #ifdef FAKE_SH2
  135. static int p32x_csum_faked;
  136. static const u16 comm_fakevals[] = {
  137. 0x4d5f, 0x4f4b, // M_OK
  138. 0x535f, 0x4f4b, // S_OK
  139. 0x4D41, 0x5346, // MASF - Brutal Unleashed
  140. 0x5331, 0x4d31, // Darxide
  141. 0x5332, 0x4d32,
  142. 0x5333, 0x4d33,
  143. 0x0000, 0x0000, // eq for doom
  144. 0x0002, // Mortal Kombat
  145. // 0, // pad
  146. };
  147. static u32 sh2_comm_faker(u32 a)
  148. {
  149. static int f = 0;
  150. if (a == 0x28 && !p32x_csum_faked) {
  151. p32x_csum_faked = 1;
  152. return *(unsigned short *)(Pico.rom + 0x18e);
  153. }
  154. if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0]))
  155. f = 0;
  156. return comm_fakevals[f++];
  157. }
  158. #endif
  159. // ------------------------------------------------------------------
  160. // 68k regs
  161. static u32 p32x_reg_read16(u32 a)
  162. {
  163. a &= 0x3e;
  164. #if 0
  165. if ((a & 0x30) == 0x20)
  166. return sh2_comm_faker(a);
  167. #else
  168. if ((a & 0x30) == 0x20) {
  169. unsigned int cycles = SekCyclesDone();
  170. int comreg = 1 << (a & 0x0f) / 2;
  171. if (cycles - msh2.m68krcycles_done > 244
  172. || (Pico32x.comm_dirty & comreg))
  173. p32x_sync_sh2s(cycles);
  174. if (m68k_poll_detect(a, cycles, P32XF_68KCPOLL)) {
  175. SekSetStop(1);
  176. SekEndRun(16);
  177. }
  178. goto out;
  179. }
  180. #endif
  181. if (a == 2) { // INTM, INTS
  182. unsigned int cycles = SekCyclesDone();
  183. if (cycles - msh2.m68krcycles_done > 64)
  184. p32x_sync_sh2s(cycles);
  185. goto out;
  186. }
  187. if ((a & 0x30) == 0x30)
  188. return p32x_pwm_read16(a, NULL, SekCyclesDone());
  189. out:
  190. return Pico32x.regs[a / 2];
  191. }
  192. static void dreq0_write(u16 *r, u32 d)
  193. {
  194. if (!(r[6 / 2] & P32XS_68S)) {
  195. elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?");
  196. return; // ignored - tested
  197. }
  198. if (Pico32x.dmac0_fifo_ptr < DMAC_FIFO_LEN) {
  199. Pico32x.dmac_fifo[Pico32x.dmac0_fifo_ptr++] = d;
  200. if (Pico32x.dmac0_fifo_ptr == DMAC_FIFO_LEN)
  201. r[6 / 2] |= P32XS_FULL;
  202. // tested: len register decrements and 68S clears
  203. // even if SH2s/DMAC aren't active..
  204. r[0x10 / 2]--;
  205. if (r[0x10 / 2] == 0)
  206. r[6 / 2] &= ~P32XS_68S;
  207. if ((Pico32x.dmac0_fifo_ptr & 3) == 0) {
  208. p32x_sync_sh2s(SekCyclesDone());
  209. p32x_dreq0_trigger();
  210. }
  211. }
  212. else
  213. elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO overflow!");
  214. }
  215. // writable bits tested
  216. static void p32x_reg_write8(u32 a, u32 d)
  217. {
  218. u16 *r = Pico32x.regs;
  219. a &= 0x3f;
  220. // for things like bset on comm port
  221. m68k_poll.cnt = 0;
  222. switch (a) {
  223. case 0x00: // adapter ctl: FM writable
  224. REG8IN16(r, 0x00) = d & 0x80;
  225. return;
  226. case 0x01: // adapter ctl: RES and ADEN writable
  227. if ((d ^ r[0]) & d & P32XS_nRES)
  228. p32x_reset_sh2s();
  229. REG8IN16(r, 0x01) &= ~(P32XS_nRES|P32XS_ADEN);
  230. REG8IN16(r, 0x01) |= d & (P32XS_nRES|P32XS_ADEN);
  231. return;
  232. case 0x02: // ignored, always 0
  233. return;
  234. case 0x03: // irq ctl
  235. if ((d ^ r[0x02 / 2]) & 3) {
  236. int cycles = SekCyclesDone();
  237. p32x_sync_sh2s(cycles);
  238. r[0x02 / 2] = d & 3;
  239. p32x_update_cmd_irq(NULL, cycles);
  240. }
  241. return;
  242. case 0x04: // ignored, always 0
  243. return;
  244. case 0x05: // bank
  245. d &= 3;
  246. if (r[0x04 / 2] != d) {
  247. r[0x04 / 2] = d;
  248. bank_switch_rom_68k(d);
  249. }
  250. return;
  251. case 0x06: // ignored, always 0
  252. return;
  253. case 0x07: // DREQ ctl
  254. REG8IN16(r, 0x07) &= ~(P32XS_68S|P32XS_DMA|P32XS_RV);
  255. if (!(d & P32XS_68S)) {
  256. Pico32x.dmac0_fifo_ptr = 0;
  257. REG8IN16(r, 0x07) &= ~P32XS_FULL;
  258. }
  259. REG8IN16(r, 0x07) |= d & (P32XS_68S|P32XS_DMA|P32XS_RV);
  260. return;
  261. case 0x08: // ignored, always 0
  262. return;
  263. case 0x09: // DREQ src
  264. REG8IN16(r, 0x09) = d;
  265. return;
  266. case 0x0a:
  267. REG8IN16(r, 0x0a) = d;
  268. return;
  269. case 0x0b:
  270. REG8IN16(r, 0x0b) = d & 0xfe;
  271. return;
  272. case 0x0c: // ignored, always 0
  273. return;
  274. case 0x0d: // DREQ dest
  275. case 0x0e:
  276. case 0x0f:
  277. case 0x10: // DREQ len
  278. REG8IN16(r, a) = d;
  279. return;
  280. case 0x11:
  281. REG8IN16(r, a) = d & 0xfc;
  282. return;
  283. // DREQ FIFO - writes to odd addr go to fifo
  284. // do writes to even work? Reads return 0
  285. case 0x12:
  286. REG8IN16(r, a) = d;
  287. return;
  288. case 0x13:
  289. d = (REG8IN16(r, 0x12) << 8) | (d & 0xff);
  290. REG8IN16(r, 0x12) = 0;
  291. dreq0_write(r, d);
  292. return;
  293. case 0x14: // ignored, always 0
  294. case 0x15:
  295. case 0x16:
  296. case 0x17:
  297. case 0x18:
  298. case 0x19:
  299. return;
  300. case 0x1a: // what's this?
  301. elprintf(EL_32X|EL_ANOMALY, "mystery w8 %02x %02x", a, d);
  302. REG8IN16(r, a) = d & 0x01;
  303. return;
  304. case 0x1b: // TV
  305. REG8IN16(r, a) = d & 0x01;
  306. return;
  307. case 0x1c: // ignored, always 0
  308. case 0x1d:
  309. case 0x1e:
  310. case 0x1f:
  311. case 0x30:
  312. return;
  313. case 0x31: // PWM control
  314. REG8IN16(r, a) &= ~0x0f;
  315. REG8IN16(r, a) |= d & 0x0f;
  316. d = r[0x30 / 2];
  317. goto pwm_write;
  318. case 0x32: // PWM cycle
  319. REG8IN16(r, a) = d & 0x0f;
  320. d = r[0x32 / 2];
  321. goto pwm_write;
  322. case 0x33:
  323. REG8IN16(r, a) = d;
  324. d = r[0x32 / 2];
  325. goto pwm_write;
  326. // PWM pulse regs.. Only writes to odd address send a value
  327. // to FIFO; reads are 0 (except status bits)
  328. case 0x34:
  329. case 0x36:
  330. case 0x38:
  331. REG8IN16(r, a) = d;
  332. return;
  333. case 0x35:
  334. case 0x37:
  335. case 0x39:
  336. d = (REG8IN16(r, a ^ 1) << 8) | (d & 0xff);
  337. REG8IN16(r, a ^ 1) = 0;
  338. goto pwm_write;
  339. case 0x3a: // ignored, always 0
  340. case 0x3b:
  341. case 0x3c:
  342. case 0x3d:
  343. case 0x3e:
  344. case 0x3f:
  345. return;
  346. pwm_write:
  347. p32x_pwm_write16(a & ~1, d, NULL, SekCyclesDone());
  348. return;
  349. }
  350. if ((a & 0x30) == 0x20) {
  351. int cycles = SekCyclesDone();
  352. int comreg;
  353. if (REG8IN16(r, a) == d)
  354. return;
  355. p32x_sync_sh2s(cycles);
  356. REG8IN16(r, a) = d;
  357. p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
  358. p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
  359. comreg = 1 << (a & 0x0f) / 2;
  360. Pico32x.comm_dirty |= comreg;
  361. return;
  362. }
  363. }
  364. static void p32x_reg_write16(u32 a, u32 d)
  365. {
  366. u16 *r = Pico32x.regs;
  367. a &= 0x3e;
  368. // for things like bset on comm port
  369. m68k_poll.cnt = 0;
  370. switch (a) {
  371. case 0x00: // adapter ctl
  372. if ((d ^ r[0]) & d & P32XS_nRES)
  373. p32x_reset_sh2s();
  374. r[0] &= ~(P32XS_FM|P32XS_nRES|P32XS_ADEN);
  375. r[0] |= d & (P32XS_FM|P32XS_nRES|P32XS_ADEN);
  376. return;
  377. case 0x08: // DREQ src
  378. r[a / 2] = d & 0xff;
  379. return;
  380. case 0x0a:
  381. r[a / 2] = d & ~1;
  382. return;
  383. case 0x0c: // DREQ dest
  384. r[a / 2] = d & 0xff;
  385. return;
  386. case 0x0e:
  387. r[a / 2] = d;
  388. return;
  389. case 0x10: // DREQ len
  390. r[a / 2] = d & ~3;
  391. return;
  392. case 0x12: // FIFO reg
  393. dreq0_write(r, d);
  394. return;
  395. case 0x1a: // TV + mystery bit
  396. r[a / 2] = d & 0x0101;
  397. return;
  398. case 0x30: // PWM control
  399. d = (r[a / 2] & ~0x0f) | (d & 0x0f);
  400. r[a / 2] = d;
  401. p32x_pwm_write16(a, d, NULL, SekCyclesDone());
  402. return;
  403. }
  404. // comm port
  405. if ((a & 0x30) == 0x20) {
  406. int cycles = SekCyclesDone();
  407. int comreg;
  408. if (r[a / 2] == d)
  409. return;
  410. p32x_sync_sh2s(cycles);
  411. r[a / 2] = d;
  412. p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
  413. p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
  414. comreg = 1 << (a & 0x0f) / 2;
  415. Pico32x.comm_dirty |= comreg;
  416. return;
  417. }
  418. // PWM
  419. else if ((a & 0x30) == 0x30) {
  420. p32x_pwm_write16(a, d, NULL, SekCyclesDone());
  421. return;
  422. }
  423. p32x_reg_write8(a + 1, d);
  424. }
  425. // ------------------------------------------------------------------
  426. // VDP regs
  427. static u32 p32x_vdp_read16(u32 a)
  428. {
  429. u32 d;
  430. a &= 0x0e;
  431. d = Pico32x.vdp_regs[a / 2];
  432. if (a == 0x0a) {
  433. // tested: FEN seems to be randomly pulsing on hcnt 0x80-0xf0,
  434. // most often at 0xb1-0xb5, even during vblank,
  435. // what's the deal with that?
  436. // we'll just fake it along with hblank for now
  437. Pico32x.vdp_fbcr_fake++;
  438. if (Pico32x.vdp_fbcr_fake & 4)
  439. d |= P32XV_HBLK;
  440. if ((Pico32x.vdp_fbcr_fake & 7) == 0)
  441. d |= P32XV_nFEN;
  442. }
  443. return d;
  444. }
  445. static void p32x_vdp_write8(u32 a, u32 d)
  446. {
  447. u16 *r = Pico32x.vdp_regs;
  448. a &= 0x0f;
  449. // TODO: verify what's writeable
  450. switch (a) {
  451. case 0x01:
  452. // priority inversion is handled in palette
  453. if ((r[0] ^ d) & P32XV_PRI)
  454. Pico32x.dirty_pal = 1;
  455. r[0] = (r[0] & P32XV_nPAL) | (d & 0xff);
  456. break;
  457. case 0x03: // shift (for pp mode)
  458. r[2 / 2] = d & 1;
  459. break;
  460. case 0x05: // fill len
  461. r[4 / 2] = d & 0xff;
  462. break;
  463. case 0x0b:
  464. d &= 1;
  465. Pico32x.pending_fb = d;
  466. // if we are blanking and FS bit is changing
  467. if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) {
  468. r[0x0a/2] ^= P32XV_FS;
  469. Pico32xSwapDRAM(d ^ 1);
  470. elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS);
  471. }
  472. break;
  473. }
  474. }
  475. static void p32x_vdp_write16(u32 a, u32 d, SH2 *sh2)
  476. {
  477. a &= 0x0e;
  478. if (a == 6) { // fill start
  479. Pico32x.vdp_regs[6 / 2] = d;
  480. return;
  481. }
  482. if (a == 8) { // fill data
  483. u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
  484. int len = Pico32x.vdp_regs[4 / 2] + 1;
  485. int len1 = len;
  486. a = Pico32x.vdp_regs[6 / 2];
  487. while (len1--) {
  488. dram[a] = d;
  489. a = (a & 0xff00) | ((a + 1) & 0xff);
  490. }
  491. Pico32x.vdp_regs[0x06 / 2] = a;
  492. Pico32x.vdp_regs[0x08 / 2] = d;
  493. if (sh2 != NULL && len > 4) {
  494. Pico32x.vdp_regs[0x0a / 2] |= P32XV_nFEN;
  495. // supposedly takes 3 bus/6 sh2 cycles? or 3 sh2 cycles?
  496. p32x_event_schedule_sh2(sh2, P32X_EVENT_FILLEND, 3 + len);
  497. }
  498. return;
  499. }
  500. p32x_vdp_write8(a | 1, d);
  501. }
  502. // ------------------------------------------------------------------
  503. // SH2 regs
  504. static u32 p32x_sh2reg_read16(u32 a, SH2 *sh2)
  505. {
  506. u16 *r = Pico32x.regs;
  507. a &= 0x3e;
  508. switch (a) {
  509. case 0x00: // adapter/irq ctl
  510. return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0]
  511. | Pico32x.sh2irq_mask[sh2->is_slave];
  512. case 0x04: // H count (often as comm too)
  513. sh2_poll_detect(sh2, a, SH2_STATE_CPOLL, 3);
  514. sh2s_sync_on_read(sh2);
  515. return Pico32x.sh2_regs[4 / 2];
  516. case 0x06:
  517. return (r[a / 2] & ~P32XS_FULL) | 0x4000;
  518. case 0x08: // DREQ src
  519. case 0x0a:
  520. case 0x0c: // DREQ dst
  521. case 0x0e:
  522. case 0x10: // DREQ len
  523. return r[a / 2];
  524. case 0x12: // DREQ FIFO - does this work on hw?
  525. if (Pico32x.dmac0_fifo_ptr > 0) {
  526. Pico32x.dmac0_fifo_ptr--;
  527. r[a / 2] = Pico32x.dmac_fifo[0];
  528. memmove(&Pico32x.dmac_fifo[0], &Pico32x.dmac_fifo[1],
  529. Pico32x.dmac0_fifo_ptr * 2);
  530. }
  531. return r[a / 2];
  532. case 0x14:
  533. case 0x16:
  534. case 0x18:
  535. case 0x1a:
  536. case 0x1c:
  537. return 0; // ?
  538. }
  539. // comm port
  540. if ((a & 0x30) == 0x20) {
  541. sh2_poll_detect(sh2, a, SH2_STATE_CPOLL, 3);
  542. sh2s_sync_on_read(sh2);
  543. return r[a / 2];
  544. }
  545. if ((a & 0x30) == 0x30)
  546. return p32x_pwm_read16(a, sh2, sh2_cycles_done_m68k(sh2));
  547. elprintf_sh2(sh2, EL_32X|EL_ANOMALY,
  548. "unhandled sysreg r16 [%02x] @%08x", a, sh2_pc(sh2));
  549. return 0;
  550. }
  551. static void p32x_sh2reg_write8(u32 a, u32 d, SH2 *sh2)
  552. {
  553. u16 *r = Pico32x.regs;
  554. u32 old;
  555. a &= 0x3f;
  556. sh2->poll_addr = 0;
  557. switch (a) {
  558. case 0x00: // FM
  559. r[0] &= ~P32XS_FM;
  560. r[0] |= (d << 8) & P32XS_FM;
  561. return;
  562. case 0x01: // HEN/irq masks
  563. old = Pico32x.sh2irq_mask[sh2->is_slave];
  564. if ((d ^ old) & 1)
  565. p32x_pwm_sync_to_sh2(sh2);
  566. Pico32x.sh2irq_mask[sh2->is_slave] = d & 0x0f;
  567. Pico32x.sh2_regs[0] &= ~0x80;
  568. Pico32x.sh2_regs[0] |= d & 0x80;
  569. if ((d ^ old) & 1)
  570. p32x_pwm_schedule_sh2(sh2);
  571. if ((old ^ d) & 2)
  572. p32x_update_cmd_irq(sh2, 0);
  573. if ((old ^ d) & 4)
  574. p32x_schedule_hint(sh2, 0);
  575. return;
  576. case 0x04: // ignored?
  577. return;
  578. case 0x05: // H count
  579. d &= 0xff;
  580. if (Pico32x.sh2_regs[4 / 2] != d) {
  581. Pico32x.sh2_regs[4 / 2] = d;
  582. p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
  583. sh2_cycles_done_m68k(sh2));
  584. sh2_end_run(sh2, 4);
  585. }
  586. return;
  587. case 0x30:
  588. REG8IN16(r, a) = d & 0x0f;
  589. d = r[0x30 / 2];
  590. goto pwm_write;
  591. case 0x31: // PWM control
  592. REG8IN16(r, a) = d & 0x8f;
  593. d = r[0x30 / 2];
  594. goto pwm_write;
  595. case 0x32: // PWM cycle
  596. REG8IN16(r, a) = d & 0x0f;
  597. d = r[0x32 / 2];
  598. goto pwm_write;
  599. case 0x33:
  600. REG8IN16(r, a) = d;
  601. d = r[0x32 / 2];
  602. goto pwm_write;
  603. // PWM pulse regs.. Only writes to odd address send a value
  604. // to FIFO; reads are 0 (except status bits)
  605. case 0x34:
  606. case 0x36:
  607. case 0x38:
  608. REG8IN16(r, a) = d;
  609. return;
  610. case 0x35:
  611. case 0x37:
  612. case 0x39:
  613. d = (REG8IN16(r, a ^ 1) << 8) | (d & 0xff);
  614. REG8IN16(r, a ^ 1) = 0;
  615. goto pwm_write;
  616. case 0x3a: // ignored, always 0?
  617. case 0x3b:
  618. case 0x3c:
  619. case 0x3d:
  620. case 0x3e:
  621. case 0x3f:
  622. return;
  623. pwm_write:
  624. p32x_pwm_write16(a & ~1, d, sh2, sh2_cycles_done_m68k(sh2));
  625. return;
  626. }
  627. if ((a & 0x30) == 0x20) {
  628. int comreg;
  629. if (REG8IN16(r, a) == d)
  630. return;
  631. REG8IN16(r, a) = d;
  632. p32x_m68k_poll_event(P32XF_68KCPOLL);
  633. p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
  634. sh2_cycles_done_m68k(sh2));
  635. comreg = 1 << (a & 0x0f) / 2;
  636. Pico32x.comm_dirty |= comreg;
  637. return;
  638. }
  639. elprintf(EL_32X|EL_ANOMALY,
  640. "unhandled sysreg w8 [%02x] %02x @%08x", a, d, sh2_pc(sh2));
  641. }
  642. static void p32x_sh2reg_write16(u32 a, u32 d, SH2 *sh2)
  643. {
  644. a &= 0x3e;
  645. sh2->poll_addr = 0;
  646. // comm
  647. if ((a & 0x30) == 0x20) {
  648. int comreg;
  649. if (Pico32x.regs[a / 2] == d)
  650. return;
  651. Pico32x.regs[a / 2] = d;
  652. p32x_m68k_poll_event(P32XF_68KCPOLL);
  653. p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
  654. sh2_cycles_done_m68k(sh2));
  655. comreg = 1 << (a & 0x0f) / 2;
  656. Pico32x.comm_dirty |= comreg;
  657. return;
  658. }
  659. // PWM
  660. else if ((a & 0x30) == 0x30) {
  661. p32x_pwm_write16(a, d, sh2, sh2_cycles_done_m68k(sh2));
  662. return;
  663. }
  664. switch (a) {
  665. case 0: // FM
  666. Pico32x.regs[0] &= ~P32XS_FM;
  667. Pico32x.regs[0] |= d & P32XS_FM;
  668. break;
  669. case 0x14:
  670. Pico32x.sh2irqs &= ~P32XI_VRES;
  671. goto irls;
  672. case 0x16:
  673. Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_VINT;
  674. goto irls;
  675. case 0x18:
  676. Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_HINT;
  677. goto irls;
  678. case 0x1a:
  679. Pico32x.regs[2 / 2] &= ~(1 << sh2->is_slave);
  680. p32x_update_cmd_irq(sh2, 0);
  681. return;
  682. case 0x1c:
  683. p32x_pwm_sync_to_sh2(sh2);
  684. Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_PWM;
  685. p32x_pwm_schedule_sh2(sh2);
  686. goto irls;
  687. }
  688. p32x_sh2reg_write8(a | 1, d, sh2);
  689. return;
  690. irls:
  691. p32x_update_irls(sh2, 0);
  692. }
  693. // ------------------------------------------------------------------
  694. // 32x 68k handlers
  695. // after ADEN
  696. static u32 PicoRead8_32x_on(u32 a)
  697. {
  698. u32 d = 0;
  699. if ((a & 0xffc0) == 0x5100) { // a15100
  700. d = p32x_reg_read16(a);
  701. goto out_16to8;
  702. }
  703. if ((a & 0xfc00) != 0x5000) {
  704. if (PicoIn.AHW & PAHW_MCD)
  705. return PicoRead8_mcd_io(a);
  706. else
  707. return PicoRead8_io(a);
  708. }
  709. if ((a & 0xfff0) == 0x5180) { // a15180
  710. d = p32x_vdp_read16(a);
  711. goto out_16to8;
  712. }
  713. if ((a & 0xfe00) == 0x5200) { // a15200
  714. d = Pico32xMem->pal[(a & 0x1ff) / 2];
  715. goto out_16to8;
  716. }
  717. if ((a & 0xfffc) == 0x30ec) { // a130ec
  718. d = str_mars[a & 3];
  719. goto out;
  720. }
  721. elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
  722. return d;
  723. out_16to8:
  724. if (a & 1)
  725. d &= 0xff;
  726. else
  727. d >>= 8;
  728. out:
  729. elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
  730. return d;
  731. }
  732. static u32 PicoRead16_32x_on(u32 a)
  733. {
  734. u32 d = 0;
  735. if ((a & 0xffc0) == 0x5100) { // a15100
  736. d = p32x_reg_read16(a);
  737. goto out;
  738. }
  739. if ((a & 0xfc00) != 0x5000) {
  740. if (PicoIn.AHW & PAHW_MCD)
  741. return PicoRead16_mcd_io(a);
  742. else
  743. return PicoRead16_io(a);
  744. }
  745. if ((a & 0xfff0) == 0x5180) { // a15180
  746. d = p32x_vdp_read16(a);
  747. goto out;
  748. }
  749. if ((a & 0xfe00) == 0x5200) { // a15200
  750. d = Pico32xMem->pal[(a & 0x1ff) / 2];
  751. goto out;
  752. }
  753. if ((a & 0xfffc) == 0x30ec) { // a130ec
  754. d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
  755. goto out;
  756. }
  757. elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
  758. return d;
  759. out:
  760. elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
  761. return d;
  762. }
  763. static void PicoWrite8_32x_on(u32 a, u32 d)
  764. {
  765. if ((a & 0xfc00) == 0x5000)
  766. elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
  767. if ((a & 0xffc0) == 0x5100) { // a15100
  768. p32x_reg_write8(a, d);
  769. return;
  770. }
  771. if ((a & 0xfc00) != 0x5000) {
  772. m68k_write8_io(a, d);
  773. return;
  774. }
  775. if (!(Pico32x.regs[0] & P32XS_FM)) {
  776. if ((a & 0xfff0) == 0x5180) { // a15180
  777. p32x_vdp_write8(a, d);
  778. return;
  779. }
  780. // TODO: verify
  781. if ((a & 0xfe00) == 0x5200) { // a15200
  782. elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
  783. ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d;
  784. Pico32x.dirty_pal = 1;
  785. return;
  786. }
  787. }
  788. elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
  789. }
  790. static void PicoWrite8_32x_on_io(u32 a, u32 d)
  791. {
  792. PicoWrite8_io(a, d);
  793. if (a == 0xa130f1)
  794. bank_switch_rom_68k(Pico32x.regs[4 / 2]);
  795. }
  796. static void PicoWrite8_32x_on_io_cd(u32 a, u32 d)
  797. {
  798. PicoWrite8_mcd_io(a, d);
  799. if (a == 0xa130f1)
  800. bank_switch_rom_68k(Pico32x.regs[4 / 2]);
  801. }
  802. static void PicoWrite8_32x_on_io_ssf2(u32 a, u32 d)
  803. {
  804. carthw_ssf2_write8(a, d);
  805. if ((a & ~0x0e) == 0xa130f1)
  806. bank_switch_rom_68k(Pico32x.regs[4 / 2]);
  807. }
  808. static void PicoWrite16_32x_on(u32 a, u32 d)
  809. {
  810. if ((a & 0xfc00) == 0x5000)
  811. elprintf(EL_32X, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
  812. if ((a & 0xffc0) == 0x5100) { // a15100
  813. p32x_reg_write16(a, d);
  814. return;
  815. }
  816. if ((a & 0xfc00) != 0x5000) {
  817. m68k_write16_io(a, d);
  818. return;
  819. }
  820. if (!(Pico32x.regs[0] & P32XS_FM)) {
  821. if ((a & 0xfff0) == 0x5180) { // a15180
  822. p32x_vdp_write16(a, d, NULL); // FIXME?
  823. return;
  824. }
  825. if ((a & 0xfe00) == 0x5200) { // a15200
  826. Pico32xMem->pal[(a & 0x1ff) / 2] = d;
  827. Pico32x.dirty_pal = 1;
  828. return;
  829. }
  830. }
  831. elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
  832. }
  833. static void PicoWrite16_32x_on_io(u32 a, u32 d)
  834. {
  835. PicoWrite16_io(a, d);
  836. if (a == 0xa130f0)
  837. bank_switch_rom_68k(Pico32x.regs[4 / 2]);
  838. }
  839. static void PicoWrite16_32x_on_io_cd(u32 a, u32 d)
  840. {
  841. PicoWrite16_mcd_io(a, d);
  842. if (a == 0xa130f0)
  843. bank_switch_rom_68k(Pico32x.regs[4 / 2]);
  844. }
  845. static void PicoWrite16_32x_on_io_ssf2(u32 a, u32 d)
  846. {
  847. PicoWrite16_io(a, d);
  848. if ((a & ~0x0f) == 0xa130f0) {
  849. carthw_ssf2_write8(a + 1, d);
  850. bank_switch_rom_68k(Pico32x.regs[4 / 2]);
  851. }
  852. }
  853. // before ADEN
  854. u32 PicoRead8_32x(u32 a)
  855. {
  856. u32 d = 0;
  857. if (PicoIn.opt & POPT_EN_32X) {
  858. if ((a & 0xffc0) == 0x5100) { // a15100
  859. // regs are always readable
  860. d = ((u8 *)Pico32x.regs)[(a & 0x3f) ^ 1];
  861. goto out;
  862. }
  863. if ((a & 0xfffc) == 0x30ec) { // a130ec
  864. d = str_mars[a & 3];
  865. goto out;
  866. }
  867. }
  868. elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
  869. return d;
  870. out:
  871. elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
  872. return d;
  873. }
  874. u32 PicoRead16_32x(u32 a)
  875. {
  876. u32 d = 0;
  877. if (PicoIn.opt & POPT_EN_32X) {
  878. if ((a & 0xffc0) == 0x5100) { // a15100
  879. d = Pico32x.regs[(a & 0x3f) / 2];
  880. goto out;
  881. }
  882. if ((a & 0xfffc) == 0x30ec) { // a130ec
  883. d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
  884. goto out;
  885. }
  886. }
  887. elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
  888. return d;
  889. out:
  890. elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
  891. return d;
  892. }
  893. void PicoWrite8_32x(u32 a, u32 d)
  894. {
  895. if ((PicoIn.opt & POPT_EN_32X) && (a & 0xffc0) == 0x5100) // a15100
  896. {
  897. u16 *r = Pico32x.regs;
  898. elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
  899. a &= 0x3f;
  900. if (a == 1) {
  901. if ((d ^ r[0]) & d & P32XS_ADEN) {
  902. Pico32xStartup();
  903. r[0] &= ~P32XS_nRES; // causes reset if specified by this write
  904. r[0] |= P32XS_ADEN;
  905. p32x_reg_write8(a, d); // forward for reset processing
  906. }
  907. return;
  908. }
  909. // allow only COMM for now
  910. if ((a & 0x30) == 0x20) {
  911. u8 *r8 = (u8 *)r;
  912. r8[a ^ 1] = d;
  913. }
  914. return;
  915. }
  916. elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
  917. }
  918. void PicoWrite16_32x(u32 a, u32 d)
  919. {
  920. if ((PicoIn.opt & POPT_EN_32X) && (a & 0xffc0) == 0x5100) // a15100
  921. {
  922. u16 *r = Pico32x.regs;
  923. elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
  924. a &= 0x3e;
  925. if (a == 0) {
  926. if ((d ^ r[0]) & d & P32XS_ADEN) {
  927. Pico32xStartup();
  928. r[0] &= ~P32XS_nRES; // causes reset if specified by this write
  929. r[0] |= P32XS_ADEN;
  930. p32x_reg_write16(a, d); // forward for reset processing
  931. }
  932. return;
  933. }
  934. // allow only COMM for now
  935. if ((a & 0x30) == 0x20)
  936. r[a / 2] = d;
  937. return;
  938. }
  939. elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
  940. }
  941. /* quirk: in both normal and overwrite areas only nonzero values go through */
  942. #define sh2_write8_dramN(p, a, d) \
  943. if ((d & 0xff) != 0) { \
  944. u8 *dram = (u8 *)p; \
  945. dram[(a & 0x1ffff) ^ 1] = d; \
  946. }
  947. static void m68k_write8_dram0_ow(u32 a, u32 d)
  948. {
  949. sh2_write8_dramN(Pico32xMem->dram[0], a, d);
  950. }
  951. static void m68k_write8_dram1_ow(u32 a, u32 d)
  952. {
  953. sh2_write8_dramN(Pico32xMem->dram[1], a, d);
  954. }
  955. #define sh2_write16_dramN(p, a, d) \
  956. u16 *pd = &((u16 *)p)[(a & 0x1ffff) / 2]; \
  957. if (!(a & 0x20000)) { \
  958. *pd = d; \
  959. } else { \
  960. u16 v = *pd; /* overwrite */ \
  961. if (!(d & 0x00ff)) d |= v & 0x00ff; \
  962. if (!(d & 0xff00)) d |= v & 0xff00; \
  963. *pd = d; \
  964. }
  965. static void m68k_write16_dram0_ow(u32 a, u32 d)
  966. {
  967. sh2_write16_dramN(Pico32xMem->dram[0], a, d);
  968. }
  969. static void m68k_write16_dram1_ow(u32 a, u32 d)
  970. {
  971. sh2_write16_dramN(Pico32xMem->dram[1], a, d);
  972. }
  973. // -----------------------------------------------------------------
  974. // hint vector is writeable
  975. static void PicoWrite8_hint(u32 a, u32 d)
  976. {
  977. if ((a & 0xfffc) == 0x0070) {
  978. Pico32xMem->m68k_rom[a ^ 1] = d;
  979. return;
  980. }
  981. elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x",
  982. a, d & 0xff, SekPc);
  983. }
  984. static void PicoWrite16_hint(u32 a, u32 d)
  985. {
  986. if ((a & 0xfffc) == 0x0070) {
  987. ((u16 *)Pico32xMem->m68k_rom)[a/2] = d;
  988. return;
  989. }
  990. elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x",
  991. a, d & 0xffff, SekPc);
  992. }
  993. // normally not writable, but somebody could make a RAM cart
  994. static void PicoWrite8_cart(u32 a, u32 d)
  995. {
  996. elprintf(EL_UIO, "m68k w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
  997. a &= 0xfffff;
  998. m68k_write8(a, d);
  999. }
  1000. static void PicoWrite16_cart(u32 a, u32 d)
  1001. {
  1002. elprintf(EL_UIO, "m68k w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
  1003. a &= 0xfffff;
  1004. m68k_write16(a, d);
  1005. }
  1006. // same with bank, but save ram is sometimes here
  1007. static u32 PicoRead8_bank(u32 a)
  1008. {
  1009. a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
  1010. return m68k_read8(a);
  1011. }
  1012. static u32 PicoRead16_bank(u32 a)
  1013. {
  1014. a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
  1015. return m68k_read16(a);
  1016. }
  1017. static void PicoWrite8_bank(u32 a, u32 d)
  1018. {
  1019. if (!(Pico.m.sram_reg & SRR_MAPPED))
  1020. elprintf(EL_UIO, "m68k w8 [%06x] %02x @%06x",
  1021. a, d & 0xff, SekPc);
  1022. a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
  1023. m68k_write8(a, d);
  1024. }
  1025. static void PicoWrite16_bank(u32 a, u32 d)
  1026. {
  1027. if (!(Pico.m.sram_reg & SRR_MAPPED))
  1028. elprintf(EL_UIO, "m68k w16 [%06x] %04x @%06x",
  1029. a, d & 0xffff, SekPc);
  1030. a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
  1031. m68k_write16(a, d);
  1032. }
  1033. static void bank_map_handler(void)
  1034. {
  1035. cpu68k_map_set(m68k_read8_map, 0x900000, 0x9fffff, PicoRead8_bank, 1);
  1036. cpu68k_map_set(m68k_read16_map, 0x900000, 0x9fffff, PicoRead16_bank, 1);
  1037. }
  1038. static void bank_switch_rom_68k(int b)
  1039. {
  1040. unsigned int rs, bank, bank2;
  1041. if (Pico.m.ncart_in)
  1042. return;
  1043. bank = b << 20;
  1044. if ((Pico.m.sram_reg & SRR_MAPPED) && bank == Pico.sv.start) {
  1045. bank_map_handler();
  1046. return;
  1047. }
  1048. if (bank >= Pico.romsize) {
  1049. elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank);
  1050. bank_map_handler();
  1051. return;
  1052. }
  1053. // 32X ROM (XXX: consider mirroring?)
  1054. rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
  1055. if (!carthw_ssf2_active) {
  1056. rs -= bank;
  1057. if (rs > 0x100000)
  1058. rs = 0x100000;
  1059. cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
  1060. cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
  1061. elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank);
  1062. }
  1063. else {
  1064. bank = bank >> 19;
  1065. bank2 = carthw_ssf2_banks[bank + 0] << 19;
  1066. cpu68k_map_set(m68k_read8_map, 0x900000, 0x97ffff, Pico.rom + bank2, 0);
  1067. cpu68k_map_set(m68k_read16_map, 0x900000, 0x97ffff, Pico.rom + bank2, 0);
  1068. bank2 = carthw_ssf2_banks[bank + 1] << 19;
  1069. cpu68k_map_set(m68k_read8_map, 0x980000, 0x9fffff, Pico.rom + bank2, 0);
  1070. cpu68k_map_set(m68k_read16_map, 0x980000, 0x9fffff, Pico.rom + bank2, 0);
  1071. }
  1072. }
  1073. // -----------------------------------------------------------------
  1074. // SH2
  1075. // -----------------------------------------------------------------
  1076. // read8
  1077. static REGPARM(2) u32 sh2_read8_unmapped(u32 a, SH2 *sh2)
  1078. {
  1079. elprintf_sh2(sh2, EL_32X, "unmapped r8 [%08x] %02x @%06x",
  1080. a, 0, sh2_pc(sh2));
  1081. return 0;
  1082. }
  1083. static u32 REGPARM(2) sh2_read8_cs0(u32 a, SH2 *sh2)
  1084. {
  1085. u32 d = 0;
  1086. DRC_SAVE_SR(sh2);
  1087. sh2_burn_cycles(sh2, 1*2);
  1088. // 0x3ffc0 is veridied
  1089. if ((a & 0x3ffc0) == 0x4000) {
  1090. d = p32x_sh2reg_read16(a, sh2);
  1091. goto out_16to8;
  1092. }
  1093. if ((a & 0x3fff0) == 0x4100) {
  1094. d = p32x_vdp_read16(a);
  1095. sh2_poll_detect(sh2, a, SH2_STATE_VPOLL, 7);
  1096. goto out_16to8;
  1097. }
  1098. if ((a & 0x3fe00) == 0x4200) {
  1099. d = Pico32xMem->pal[(a & 0x1ff) / 2];
  1100. goto out_16to8;
  1101. }
  1102. // TODO: mirroring?
  1103. if (!sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_m))
  1104. d = Pico32xMem->sh2_rom_m.b[a ^ 1];
  1105. else if (sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_s))
  1106. d = Pico32xMem->sh2_rom_s.b[a ^ 1];
  1107. else
  1108. d = sh2_read8_unmapped(a, sh2);
  1109. goto out;
  1110. out_16to8:
  1111. if (a & 1)
  1112. d &= 0xff;
  1113. else
  1114. d >>= 8;
  1115. out:
  1116. elprintf_sh2(sh2, EL_32X, "r8 [%08x] %02x @%06x",
  1117. a, d, sh2_pc(sh2));
  1118. DRC_RESTORE_SR(sh2);
  1119. return d;
  1120. }
  1121. static u32 REGPARM(2) sh2_read8_da(u32 a, SH2 *sh2)
  1122. {
  1123. return sh2->data_array[(a & 0xfff) ^ 1];
  1124. }
  1125. // for ssf2
  1126. static u32 REGPARM(2) sh2_read8_rom(u32 a, SH2 *sh2)
  1127. {
  1128. u32 bank = carthw_ssf2_banks[(a >> 19) & 7] << 19;
  1129. u8 *p = sh2->p_rom;
  1130. return p[(bank + (a & 0x7ffff)) ^ 1];
  1131. }
  1132. // read16
  1133. static u32 REGPARM(2) sh2_read16_unmapped(u32 a, SH2 *sh2)
  1134. {
  1135. elprintf_sh2(sh2, EL_32X, "unmapped r16 [%08x] %04x @%06x",
  1136. a, 0, sh2_pc(sh2));
  1137. return 0;
  1138. }
  1139. static u32 REGPARM(2) sh2_read16_cs0(u32 a, SH2 *sh2)
  1140. {
  1141. u32 d = 0;
  1142. DRC_SAVE_SR(sh2);
  1143. sh2_burn_cycles(sh2, 1*2);
  1144. if ((a & 0x3ffc0) == 0x4000) {
  1145. d = p32x_sh2reg_read16(a, sh2);
  1146. if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM
  1147. goto out_noprint;
  1148. goto out;
  1149. }
  1150. if ((a & 0x3fff0) == 0x4100) {
  1151. d = p32x_vdp_read16(a);
  1152. sh2_poll_detect(sh2, a, SH2_STATE_VPOLL, 7);
  1153. goto out;
  1154. }
  1155. if ((a & 0x3fe00) == 0x4200) {
  1156. d = Pico32xMem->pal[(a & 0x1ff) / 2];
  1157. goto out;
  1158. }
  1159. if (!sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_m))
  1160. d = Pico32xMem->sh2_rom_m.w[a / 2];
  1161. else if (sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_s))
  1162. d = Pico32xMem->sh2_rom_s.w[a / 2];
  1163. else
  1164. d = sh2_read16_unmapped(a, sh2);
  1165. out:
  1166. elprintf_sh2(sh2, EL_32X, "r16 [%08x] %04x @%06x",
  1167. a, d, sh2_pc(sh2));
  1168. out_noprint:
  1169. DRC_RESTORE_SR(sh2);
  1170. return d;
  1171. }
  1172. static u32 REGPARM(2) sh2_read16_da(u32 a, SH2 *sh2)
  1173. {
  1174. return ((u16 *)sh2->data_array)[(a & 0xffe) / 2];
  1175. }
  1176. static u32 REGPARM(2) sh2_read16_rom(u32 a, SH2 *sh2)
  1177. {
  1178. u32 bank = carthw_ssf2_banks[(a >> 19) & 7] << 19;
  1179. u16 *p = sh2->p_rom;
  1180. return p[(bank + (a & 0x7fffe)) / 2];
  1181. }
  1182. static u32 REGPARM(2) sh2_read32_unmapped(u32 a, SH2 *sh2)
  1183. {
  1184. elprintf_sh2(sh2, EL_32X, "unmapped r32 [%08x] %08x @%06x",
  1185. a, 0, sh2_pc(sh2));
  1186. return 0;
  1187. }
  1188. static u32 REGPARM(2) sh2_read32_cs0(u32 a, SH2 *sh2)
  1189. {
  1190. return (sh2_read16_cs0(a, sh2) << 16) | sh2_read16_cs0(a + 2, sh2);
  1191. }
  1192. static u32 REGPARM(2) sh2_read32_da(u32 a, SH2 *sh2)
  1193. {
  1194. u32 d = *((u32 *)sh2->data_array + (a & 0xffc)/4);
  1195. return (d << 16) | (d >> 16);
  1196. }
  1197. static u32 REGPARM(2) sh2_read32_rom(u32 a, SH2 *sh2)
  1198. {
  1199. u32 bank = carthw_ssf2_banks[(a >> 19) & 7] << 19;
  1200. u32 *p = sh2->p_rom;
  1201. u32 d = p[(bank + (a & 0x7fffc)) / 4];
  1202. return (d << 16) | (d >> 16);
  1203. }
  1204. // writes
  1205. static void REGPARM(3) sh2_write_ignore(u32 a, u32 d, SH2 *sh2)
  1206. {
  1207. }
  1208. // write8
  1209. static void REGPARM(3) sh2_write8_unmapped(u32 a, u32 d, SH2 *sh2)
  1210. {
  1211. elprintf_sh2(sh2, EL_32X, "unmapped w8 [%08x] %02x @%06x",
  1212. a, d & 0xff, sh2_pc(sh2));
  1213. }
  1214. static void REGPARM(3) sh2_write8_cs0(u32 a, u32 d, SH2 *sh2)
  1215. {
  1216. DRC_SAVE_SR(sh2);
  1217. elprintf_sh2(sh2, EL_32X, "w8 [%08x] %02x @%06x",
  1218. a, d & 0xff, sh2_pc(sh2));
  1219. if (Pico32x.regs[0] & P32XS_FM) {
  1220. if ((a & 0x3fff0) == 0x4100) {
  1221. sh2->poll_addr = 0;
  1222. p32x_vdp_write8(a, d);
  1223. goto out;
  1224. }
  1225. if ((a & 0x3fe00) == 0x4200) {
  1226. ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d;
  1227. Pico32x.dirty_pal = 1;
  1228. goto out;
  1229. }
  1230. }
  1231. if ((a & 0x3ffc0) == 0x4000) {
  1232. p32x_sh2reg_write8(a, d, sh2);
  1233. goto out;
  1234. }
  1235. sh2_write8_unmapped(a, d, sh2);
  1236. out:
  1237. DRC_RESTORE_SR(sh2);
  1238. }
  1239. static void REGPARM(3) sh2_write8_dram(u32 a, u32 d, SH2 *sh2)
  1240. {
  1241. sh2_write8_dramN(sh2->p_dram, a, d);
  1242. }
  1243. static void REGPARM(3) sh2_write8_sdram(u32 a, u32 d, SH2 *sh2)
  1244. {
  1245. u32 a1 = a & 0x3ffff;
  1246. #ifdef DRC_SH2
  1247. u8 *p = sh2->p_drcblk_ram;
  1248. int t = p[a1 >> SH2_DRCBLK_RAM_SHIFT];
  1249. if (t)
  1250. sh2_drc_wcheck_ram(a, t, sh2);
  1251. #endif
  1252. ((u8 *)sh2->p_sdram)[a1 ^ 1] = d;
  1253. }
  1254. static void REGPARM(3) sh2_write8_sdram_wt(u32 a, u32 d, SH2 *sh2)
  1255. {
  1256. // xmen sync hack..
  1257. if (a < 0x26000200) {
  1258. DRC_SAVE_SR(sh2);
  1259. sh2_end_run(sh2, 32);
  1260. DRC_RESTORE_SR(sh2);
  1261. }
  1262. sh2_write8_sdram(a, d, sh2);
  1263. }
  1264. static void REGPARM(3) sh2_write8_da(u32 a, u32 d, SH2 *sh2)
  1265. {
  1266. u32 a1 = a & 0xfff;
  1267. #ifdef DRC_SH2
  1268. u8 *p = sh2->p_drcblk_da;
  1269. int t = p[a1 >> SH2_DRCBLK_DA_SHIFT];
  1270. if (t)
  1271. sh2_drc_wcheck_da(a, t, sh2);
  1272. #endif
  1273. sh2->data_array[a1 ^ 1] = d;
  1274. }
  1275. // write16
  1276. static void REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, SH2 *sh2)
  1277. {
  1278. elprintf_sh2(sh2, EL_32X, "unmapped w16 [%08x] %04x @%06x",
  1279. a, d & 0xffff, sh2_pc(sh2));
  1280. }
  1281. static void REGPARM(3) sh2_write16_cs0(u32 a, u32 d, SH2 *sh2)
  1282. {
  1283. DRC_SAVE_SR(sh2);
  1284. if (((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
  1285. elprintf_sh2(sh2, EL_32X, "w16 [%08x] %04x @%06x",
  1286. a, d & 0xffff, sh2_pc(sh2));
  1287. if (Pico32x.regs[0] & P32XS_FM) {
  1288. if ((a & 0x3fff0) == 0x4100) {
  1289. sh2->poll_addr = 0;
  1290. p32x_vdp_write16(a, d, sh2);
  1291. goto out;
  1292. }
  1293. if ((a & 0x3fe00) == 0x4200) {
  1294. Pico32xMem->pal[(a & 0x1ff) / 2] = d;
  1295. Pico32x.dirty_pal = 1;
  1296. goto out;
  1297. }
  1298. }
  1299. if ((a & 0x3ffc0) == 0x4000) {
  1300. p32x_sh2reg_write16(a, d, sh2);
  1301. goto out;
  1302. }
  1303. sh2_write16_unmapped(a, d, sh2);
  1304. out:
  1305. DRC_RESTORE_SR(sh2);
  1306. }
  1307. static void REGPARM(3) sh2_write16_dram(u32 a, u32 d, SH2 *sh2)
  1308. {
  1309. sh2_write16_dramN(sh2->p_dram, a, d);
  1310. }
  1311. static void REGPARM(3) sh2_write16_sdram(u32 a, u32 d, SH2 *sh2)
  1312. {
  1313. u32 a1 = a & 0x3fffe;
  1314. #ifdef DRC_SH2
  1315. u8 *p = sh2->p_drcblk_ram;
  1316. int t = p[a1 >> SH2_DRCBLK_RAM_SHIFT];
  1317. if (t)
  1318. sh2_drc_wcheck_ram(a, t, sh2);
  1319. #endif
  1320. ((u16 *)sh2->p_sdram)[a1 / 2] = d;
  1321. }
  1322. static void REGPARM(3) sh2_write16_da(u32 a, u32 d, SH2 *sh2)
  1323. {
  1324. u32 a1 = a & 0xffe;
  1325. #ifdef DRC_SH2
  1326. u8 *p = sh2->p_drcblk_da;
  1327. int t = p[a1 >> SH2_DRCBLK_DA_SHIFT];
  1328. if (t)
  1329. sh2_drc_wcheck_da(a, t, sh2);
  1330. #endif
  1331. ((u16 *)sh2->data_array)[a1 / 2] = d;
  1332. }
  1333. static void REGPARM(3) sh2_write16_rom(u32 a, u32 d, SH2 *sh2)
  1334. {
  1335. u32 a1 = a & 0x3ffffe;
  1336. // tweak for WWF Raw: does writes to ROM area, and it doesn't work without
  1337. // allowing this.
  1338. // Presumably the write goes to the CPU cache and is read back from there,
  1339. // but it would be extremely costly to emulate cache behaviour. Just allow
  1340. // writes to that region, hoping that the original ROM values are never used.
  1341. if ((a1 & 0x3e0000) == 0x3e0000)
  1342. ((u16 *)sh2->p_rom)[a1 / 2] = d;
  1343. else
  1344. sh2_write16_unmapped(a, d, sh2);
  1345. }
  1346. static void REGPARM(3) sh2_write32_unmapped(u32 a, u32 d, SH2 *sh2)
  1347. {
  1348. elprintf_sh2(sh2, EL_32X, "unmapped w32 [%08x] %08x @%06x",
  1349. a, d, sh2_pc(sh2));
  1350. }
  1351. static void REGPARM(3) sh2_write32_cs0(u32 a, u32 d, SH2 *sh2)
  1352. {
  1353. sh2_write16_cs0(a, d >> 16, sh2);
  1354. sh2_write16_cs0(a + 2, d, sh2);
  1355. }
  1356. #define sh2_write32_dramN(p, a, d) \
  1357. u32 *pd = &((u32 *)p)[(a & 0x1ffff) / 4]; \
  1358. if (!(a & 0x20000)) { \
  1359. *pd = (d << 16) | (d >> 16); \
  1360. } else { \
  1361. /* overwrite */ \
  1362. u32 v = *pd, m = 0; d = (d << 16) | (d >> 16) ; \
  1363. if (!(d & 0x000000ff)) m |= 0x000000ff; \
  1364. if (!(d & 0x0000ff00)) m |= 0x0000ff00; \
  1365. if (!(d & 0x00ff0000)) m |= 0x00ff0000; \
  1366. if (!(d & 0xff000000)) m |= 0xff000000; \
  1367. *pd = d | (v&m); \
  1368. }
  1369. static void REGPARM(3) sh2_write32_dram(u32 a, u32 d, SH2 *sh2)
  1370. {
  1371. sh2_write32_dramN(sh2->p_dram, a, d);
  1372. }
  1373. static void REGPARM(3) sh2_write32_sdram(u32 a, u32 d, SH2 *sh2)
  1374. {
  1375. u32 a1 = a & 0x3fffc;
  1376. #ifdef DRC_SH2
  1377. u8 *p = sh2->p_drcblk_ram;
  1378. int t = p[a1 >> SH2_DRCBLK_RAM_SHIFT];
  1379. if (t)
  1380. sh2_drc_wcheck_ram(a, t, sh2);
  1381. int u = p[(a1+2) >> SH2_DRCBLK_RAM_SHIFT];
  1382. if (u)
  1383. sh2_drc_wcheck_ram(a+2, u, sh2);
  1384. #endif
  1385. *(u32 *)(sh2->p_sdram + a1) = (d << 16) | (d >> 16);
  1386. }
  1387. static void REGPARM(3) sh2_write32_da(u32 a, u32 d, SH2 *sh2)
  1388. {
  1389. u32 a1 = a & 0xffc;
  1390. #ifdef DRC_SH2
  1391. u8 *p = sh2->p_drcblk_da;
  1392. int t = p[a1 >> SH2_DRCBLK_DA_SHIFT];
  1393. if (t)
  1394. sh2_drc_wcheck_da(a, t, sh2);
  1395. int u = p[(a1+2) >> SH2_DRCBLK_DA_SHIFT];
  1396. if (u)
  1397. sh2_drc_wcheck_da(a+2, u, sh2);
  1398. #endif
  1399. *((u32 *)sh2->data_array + a1/4) = (d << 16) | (d >> 16);
  1400. }
  1401. static void REGPARM(3) sh2_write32_rom(u32 a, u32 d, SH2 *sh2)
  1402. {
  1403. sh2_write16_rom(a, d >> 16, sh2);
  1404. sh2_write16_rom(a + 2, d, sh2);
  1405. }
  1406. typedef u32 (sh2_read_handler)(u32 a, SH2 *sh2);
  1407. typedef void REGPARM(3) (sh2_write_handler)(u32 a, u32 d, SH2 *sh2);
  1408. #define SH2MAP_ADDR2OFFS_R(a) \
  1409. ((u32)(a) >> SH2_READ_SHIFT)
  1410. #define SH2MAP_ADDR2OFFS_W(a) \
  1411. ((u32)(a) >> SH2_WRITE_SHIFT)
  1412. u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2)
  1413. {
  1414. const sh2_memmap *sh2_map = sh2->read8_map;
  1415. uptr p;
  1416. sh2_map += SH2MAP_ADDR2OFFS_R(a);
  1417. p = sh2_map->addr;
  1418. if (map_flag_set(p))
  1419. return ((sh2_read_handler *)(p << 1))(a, sh2);
  1420. else
  1421. return *(u8 *)((p << 1) + ((a & sh2_map->mask) ^ 1));
  1422. }
  1423. u32 REGPARM(2) p32x_sh2_read16(u32 a, SH2 *sh2)
  1424. {
  1425. const sh2_memmap *sh2_map = sh2->read16_map;
  1426. uptr p;
  1427. sh2_map += SH2MAP_ADDR2OFFS_R(a);
  1428. p = sh2_map->addr;
  1429. if (map_flag_set(p))
  1430. return ((sh2_read_handler *)(p << 1))(a, sh2);
  1431. else
  1432. return *(u16 *)((p << 1) + (a & sh2_map->mask));
  1433. }
  1434. u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2)
  1435. {
  1436. const sh2_memmap *sh2_map = sh2->read32_map;
  1437. uptr p;
  1438. sh2_map += SH2MAP_ADDR2OFFS_R(a);
  1439. p = sh2_map->addr;
  1440. if (!map_flag_set(p)) {
  1441. u32 *pd = (u32 *)((p << 1) + (a & sh2_map->mask));
  1442. return (*pd << 16) | (*pd >> 16);
  1443. } else
  1444. return ((sh2_read_handler *)(p << 1))(a, sh2);
  1445. }
  1446. void REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
  1447. {
  1448. const void **sh2_wmap = sh2->write8_tab;
  1449. sh2_write_handler *wh;
  1450. wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
  1451. wh(a, d, sh2);
  1452. }
  1453. void REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
  1454. {
  1455. const void **sh2_wmap = sh2->write16_tab;
  1456. sh2_write_handler *wh;
  1457. wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
  1458. wh(a, d, sh2);
  1459. }
  1460. void REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
  1461. {
  1462. const void **sh2_wmap = sh2->write32_tab;
  1463. sh2_write_handler *wh;
  1464. wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
  1465. wh(a, d, sh2);
  1466. }
  1467. // -----------------------------------------------------------------
  1468. static void z80_md_bank_write_32x(unsigned int a, unsigned char d)
  1469. {
  1470. unsigned int addr68k;
  1471. addr68k = Pico.m.z80_bank68k << 15;
  1472. addr68k += a & 0x7fff;
  1473. if ((addr68k & 0xfff000) == 0xa15000)
  1474. Pico32x.emu_flags |= P32XF_Z80_32X_IO;
  1475. elprintf(EL_Z80BNK, "z80->68k w8 [%06x] %02x", addr68k, d);
  1476. m68k_write8(addr68k, d);
  1477. }
  1478. // -----------------------------------------------------------------
  1479. static const u16 msh2_code[] = {
  1480. // trap instructions
  1481. 0xaffe, // 200 bra <self>
  1482. 0x0009, // 202 nop
  1483. // have to wait a bit until m68k initial program finishes clearing stuff
  1484. // to avoid races with game SH2 code, like in Tempo
  1485. 0xd406, // 204 mov.l @(_m_ok,pc), r4
  1486. 0xc400, // 206 mov.b @(h'0,gbr),r0
  1487. 0xc801, // 208 tst #1, r0
  1488. 0x8b0f, // 20a bf cd_start
  1489. 0xd105, // 20c mov.l @(_cnt,pc), r1
  1490. 0xd206, // 20e mov.l @(_start,pc), r2
  1491. 0x71ff, // 210 add #-1, r1
  1492. 0x4115, // 212 cmp/pl r1
  1493. 0x89fc, // 214 bt -2
  1494. 0x6043, // 216 mov r4, r0
  1495. 0xc208, // 218 mov.l r0, @(h'20,gbr)
  1496. 0x6822, // 21a mov.l @r2, r8
  1497. 0x482b, // 21c jmp @r8
  1498. 0x0009, // 21e nop
  1499. ('M'<<8)|'_', ('O'<<8)|'K', // 220 _m_ok
  1500. 0x0001, 0x0000, // 224 _cnt
  1501. 0x2200, 0x03e0, // master start pointer in ROM
  1502. // cd_start:
  1503. 0xd20d, // 22c mov.l @(__cd_,pc), r2
  1504. 0xc608, // 22e mov.l @(h'20,gbr), r0
  1505. 0x3200, // 230 cmp/eq r0, r2
  1506. 0x8bfc, // 232 bf #-2
  1507. 0xe000, // 234 mov #0, r0
  1508. 0xcf80, // 236 or.b #0x80,@(r0,gbr)
  1509. 0xd80b, // 238 mov.l @(_start_cd,pc), r8 // 24000018
  1510. 0xd30c, // 23a mov.l @(_max_len,pc), r3
  1511. 0x5b84, // 23c mov.l @(h'10,r8), r11 // master vbr
  1512. 0x5a82, // 23e mov.l @(8,r8), r10 // entry
  1513. 0x5081, // 240 mov.l @(4,r8), r0 // len
  1514. 0x5980, // 242 mov.l @(0,r8), r9 // dst
  1515. 0x3036, // 244 cmp/hi r3,r0
  1516. 0x8b00, // 246 bf #1
  1517. 0x6033, // 248 mov r3,r0
  1518. 0x7820, // 24a add #0x20, r8
  1519. // ipl_copy:
  1520. 0x6286, // 24c mov.l @r8+, r2
  1521. 0x2922, // 24e mov.l r2, @r9
  1522. 0x7904, // 250 add #4, r9
  1523. 0x70fc, // 252 add #-4, r0
  1524. 0x8800, // 254 cmp/eq #0, r0
  1525. 0x8bf9, // 256 bf #-5
  1526. //
  1527. 0x4b2e, // 258 ldc r11, vbr
  1528. 0x6043, // 25a mov r4, r0 // M_OK
  1529. 0xc208, // 25c mov.l r0, @(h'20,gbr)
  1530. 0x4a2b, // 25e jmp @r10
  1531. 0x0009, // 260 nop
  1532. 0x0009, // 262 nop // pad
  1533. ('_'<<8)|'C', ('D'<<8)|'_', // 264 __cd_
  1534. 0x2400, 0x0018, // 268 _start_cd
  1535. 0x0001, 0xffe0, // 26c _max_len
  1536. };
  1537. static const u16 ssh2_code[] = {
  1538. 0xaffe, // 200 bra <self>
  1539. 0x0009, // 202 nop
  1540. // code to wait for master, in case authentic master BIOS is used
  1541. 0xd106, // 204 mov.l @(_m_ok,pc), r1
  1542. 0xd208, // 206 mov.l @(_start,pc), r2
  1543. 0xc608, // 208 mov.l @(h'20,gbr), r0
  1544. 0x3100, // 20a cmp/eq r0, r1
  1545. 0x8bfc, // 20c bf #-2
  1546. 0xc400, // 20e mov.b @(h'0,gbr),r0
  1547. 0xc801, // 210 tst #1, r0
  1548. 0xd004, // 212 mov.l @(_s_ok,pc), r0
  1549. 0x8b0a, // 214 bf cd_start
  1550. 0xc209, // 216 mov.l r0, @(h'24,gbr)
  1551. 0x6822, // 218 mov.l @r2, r8
  1552. 0x482b, // 21a jmp @r8
  1553. 0x0009, // 21c nop
  1554. 0x0009, // 21e nop
  1555. ('M'<<8)|'_', ('O'<<8)|'K', // 220
  1556. ('S'<<8)|'_', ('O'<<8)|'K', // 224
  1557. 0x2200, 0x03e4, // slave start pointer in ROM
  1558. // cd_start:
  1559. 0xd803, // 22c mov.l @(_start_cd,pc), r8 // 24000018
  1560. 0x5b85, // 22e mov.l @(h'14,r8), r11 // slave vbr
  1561. 0x5a83, // 230 mov.l @(h'0c,r8), r10 // entry
  1562. 0x4b2e, // 232 ldc r11, vbr
  1563. 0xc209, // 234 mov.l r0, @(h'24,gbr) // write S_OK
  1564. 0x4a2b, // 236 jmp @r10
  1565. 0x0009, // 238 nop
  1566. 0x0009, // 23a nop
  1567. 0x2400, 0x0018, // 23c _start_cd
  1568. };
  1569. #define HWSWAP(x) (((u16)(x) << 16) | ((x) >> 16))
  1570. static void get_bios(void)
  1571. {
  1572. u16 *ps;
  1573. u32 *pl;
  1574. int i;
  1575. // M68K ROM
  1576. if (p32x_bios_g != NULL) {
  1577. elprintf(EL_STATUS|EL_32X, "32x: using supplied 68k BIOS");
  1578. Byteswap(Pico32xMem->m68k_rom, p32x_bios_g, sizeof(Pico32xMem->m68k_rom));
  1579. }
  1580. else {
  1581. static const u16 andb[] = { 0x0239, 0x00fe, 0x00a1, 0x5107 };
  1582. static const u16 p_d4[] = {
  1583. 0x48e7, 0x8040, // movem.l d0/a1, -(sp)
  1584. 0x227c, 0x00a1, 0x30f1, // movea.l #0xa130f1, a1
  1585. 0x7007, // moveq.l #7, d0
  1586. 0x12d8, //0: move.b (a0)+, (a1)+
  1587. 0x5289, // addq.l #1, a1
  1588. 0x51c8, 0xfffa, // dbra d0, 0b
  1589. 0x0239, 0x00fe, 0x00a1, // and.b #0xfe, (0xa15107).l
  1590. 0x5107,
  1591. 0x4cdf, 0x0201 // movem.l (sp)+, d0/a1
  1592. };
  1593. // generate 68k ROM
  1594. ps = (u16 *)Pico32xMem->m68k_rom;
  1595. pl = (u32 *)ps;
  1596. for (i = 1; i < 0xc0/4; i++)
  1597. pl[i] = HWSWAP(0x880200 + (i - 1) * 6);
  1598. pl[0x70/4] = 0;
  1599. // fill with nops
  1600. for (i = 0xc0/2; i < 0x100/2; i++)
  1601. ps[i] = 0x4e71;
  1602. // c0: don't need to care about RV - not emulated
  1603. ps[0xc8/2] = 0x1280; // move.b d0, (a1)
  1604. memcpy(ps + 0xca/2, andb, sizeof(andb)); // and.b #0xfe, (a15107)
  1605. ps[0xd2/2] = 0x4e75; // rts
  1606. // d4:
  1607. memcpy(ps + 0xd4/2, p_d4, sizeof(p_d4));
  1608. ps[0xfe/2] = 0x4e75; // rts
  1609. }
  1610. // fill remaining m68k_rom page with game ROM
  1611. memcpy(Pico32xMem->m68k_rom_bank + sizeof(Pico32xMem->m68k_rom),
  1612. Pico.rom + sizeof(Pico32xMem->m68k_rom),
  1613. sizeof(Pico32xMem->m68k_rom_bank) - sizeof(Pico32xMem->m68k_rom));
  1614. // MSH2
  1615. if (p32x_bios_m != NULL) {
  1616. elprintf(EL_STATUS|EL_32X, "32x: using supplied master SH2 BIOS");
  1617. Byteswap(&Pico32xMem->sh2_rom_m, p32x_bios_m, sizeof(Pico32xMem->sh2_rom_m));
  1618. }
  1619. else {
  1620. pl = (u32 *)&Pico32xMem->sh2_rom_m;
  1621. // fill exception vector table to our trap address
  1622. for (i = 0; i < 128; i++)
  1623. pl[i] = HWSWAP(0x200);
  1624. // start
  1625. pl[0] = pl[2] = HWSWAP(0x204);
  1626. // reset SP
  1627. pl[1] = pl[3] = HWSWAP(0x6040000);
  1628. // startup code
  1629. memcpy(&Pico32xMem->sh2_rom_m.b[0x200], msh2_code, sizeof(msh2_code));
  1630. }
  1631. // SSH2
  1632. if (p32x_bios_s != NULL) {
  1633. elprintf(EL_STATUS|EL_32X, "32x: using supplied slave SH2 BIOS");
  1634. Byteswap(&Pico32xMem->sh2_rom_s, p32x_bios_s, sizeof(Pico32xMem->sh2_rom_s));
  1635. }
  1636. else {
  1637. pl = (u32 *)&Pico32xMem->sh2_rom_s;
  1638. // fill exception vector table to our trap address
  1639. for (i = 0; i < 128; i++)
  1640. pl[i] = HWSWAP(0x200);
  1641. // start
  1642. pl[0] = pl[2] = HWSWAP(0x204);
  1643. // reset SP
  1644. pl[1] = pl[3] = HWSWAP(0x603f800);
  1645. // startup code
  1646. memcpy(&Pico32xMem->sh2_rom_s.b[0x200], ssh2_code, sizeof(ssh2_code));
  1647. }
  1648. }
  1649. #define MAP_MEMORY(m) ((uptr)(m) >> 1)
  1650. #define MAP_HANDLER(h) ( ((uptr)(h) >> 1) | ((uptr)1 << (sizeof(uptr) * 8 - 1)) )
  1651. static sh2_memmap sh2_read8_map[0x80], sh2_read16_map[0x80], sh2_read32_map[0x80];
  1652. // for writes we are using handlers only
  1653. static sh2_write_handler *sh2_write8_map[0x80], *sh2_write16_map[0x80], *sh2_write32_map[0x80];
  1654. void Pico32xSwapDRAM(int b)
  1655. {
  1656. cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
  1657. cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
  1658. cpu68k_map_set(m68k_read8_map, 0x860000, 0x87ffff, Pico32xMem->dram[b], 0);
  1659. cpu68k_map_set(m68k_read16_map, 0x860000, 0x87ffff, Pico32xMem->dram[b], 0);
  1660. cpu68k_map_set(m68k_write8_map, 0x840000, 0x87ffff,
  1661. b ? m68k_write8_dram1_ow : m68k_write8_dram0_ow, 1);
  1662. cpu68k_map_set(m68k_write16_map, 0x840000, 0x87ffff,
  1663. b ? m68k_write16_dram1_ow : m68k_write16_dram0_ow, 1);
  1664. // SH2
  1665. sh2_read8_map[0x04/2].addr = sh2_read8_map[0x24/2].addr =
  1666. sh2_read16_map[0x04/2].addr = sh2_read16_map[0x24/2].addr =
  1667. sh2_read32_map[0x04/2].addr = sh2_read32_map[0x24/2].addr = MAP_MEMORY(Pico32xMem->dram[b]);
  1668. msh2.p_dram = ssh2.p_dram = Pico32xMem->dram[b]; // DRC conveniance ptr
  1669. }
  1670. static void bank_switch_rom_sh2(void)
  1671. {
  1672. if (!carthw_ssf2_active) {
  1673. // easy
  1674. sh2_read8_map[0x02/2].addr = sh2_read8_map[0x22/2].addr =
  1675. sh2_read16_map[0x02/2].addr = sh2_read16_map[0x22/2].addr =
  1676. sh2_read32_map[0x02/2].addr = sh2_read32_map[0x22/2].addr = MAP_MEMORY(Pico.rom);
  1677. }
  1678. else {
  1679. sh2_read8_map[0x02/2].addr = sh2_read8_map[0x22/2].addr = MAP_HANDLER(sh2_read8_rom);
  1680. sh2_read16_map[0x02/2].addr = sh2_read16_map[0x22/2].addr = MAP_HANDLER(sh2_read16_rom);
  1681. sh2_read32_map[0x02/2].addr = sh2_read32_map[0x22/2].addr = MAP_HANDLER(sh2_read32_rom);
  1682. }
  1683. }
  1684. void PicoMemSetup32x(void)
  1685. {
  1686. unsigned int rs;
  1687. int i;
  1688. Pico32xMem = plat_mmap(0x06000000, sizeof(*Pico32xMem), 0, 0);
  1689. if (Pico32xMem == NULL) {
  1690. elprintf(EL_STATUS, "OOM");
  1691. return;
  1692. }
  1693. get_bios();
  1694. // cartridge area becomes unmapped
  1695. // XXX: we take the easy way and don't unmap ROM,
  1696. // so that we can avoid handling the RV bit.
  1697. // m68k_map_unmap(0x000000, 0x3fffff);
  1698. if (!Pico.m.ncart_in) {
  1699. // MD ROM area
  1700. rs = sizeof(Pico32xMem->m68k_rom_bank);
  1701. cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
  1702. cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
  1703. cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify
  1704. cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1);
  1705. // 32X ROM (unbanked, XXX: consider mirroring?)
  1706. rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
  1707. if (rs > 0x80000)
  1708. rs = 0x80000;
  1709. cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
  1710. cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
  1711. cpu68k_map_set(m68k_write8_map, 0x880000, 0x880000 + rs - 1, PicoWrite8_cart, 1);
  1712. cpu68k_map_set(m68k_write16_map, 0x880000, 0x880000 + rs - 1, PicoWrite16_cart, 1);
  1713. // 32X ROM (banked)
  1714. bank_switch_rom_68k(0);
  1715. cpu68k_map_set(m68k_write8_map, 0x900000, 0x9fffff, PicoWrite8_bank, 1);
  1716. cpu68k_map_set(m68k_write16_map, 0x900000, 0x9fffff, PicoWrite16_bank, 1);
  1717. }
  1718. // SYS regs
  1719. cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_32x_on, 1);
  1720. cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_32x_on, 1);
  1721. cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_32x_on, 1);
  1722. cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_32x_on, 1);
  1723. // TODO: cd + carthw
  1724. if (PicoIn.AHW & PAHW_MCD) {
  1725. m68k_write8_io = PicoWrite8_32x_on_io_cd;
  1726. m68k_write16_io = PicoWrite16_32x_on_io_cd;
  1727. }
  1728. else if (carthw_ssf2_active) {
  1729. m68k_write8_io = PicoWrite8_32x_on_io_ssf2;
  1730. m68k_write16_io = PicoWrite16_32x_on_io_ssf2;
  1731. }
  1732. else {
  1733. m68k_write8_io = PicoWrite8_32x_on_io;
  1734. m68k_write16_io = PicoWrite16_32x_on_io;
  1735. }
  1736. // SH2 maps: A31,A30,A29,CS1,CS0
  1737. // all unmapped by default
  1738. for (i = 0; i < ARRAY_SIZE(sh2_read8_map); i++) {
  1739. sh2_read8_map[i].addr = MAP_HANDLER(sh2_read8_unmapped);
  1740. sh2_read16_map[i].addr = MAP_HANDLER(sh2_read16_unmapped);
  1741. sh2_read32_map[i].addr = MAP_HANDLER(sh2_read32_unmapped);
  1742. }
  1743. for (i = 0; i < ARRAY_SIZE(sh2_write8_map); i++) {
  1744. sh2_write8_map[i] = sh2_write8_unmapped;
  1745. sh2_write16_map[i] = sh2_write16_unmapped;
  1746. sh2_write32_map[i] = sh2_write32_unmapped;
  1747. }
  1748. // "purge area"
  1749. for (i = 0x40; i <= 0x5f; i++) {
  1750. sh2_write8_map[i >> 1] =
  1751. sh2_write16_map[i >> 1] =
  1752. sh2_write32_map[i >> 1] = sh2_write_ignore;
  1753. }
  1754. // CS0
  1755. sh2_read8_map[0x00/2].addr = sh2_read8_map[0x20/2].addr = MAP_HANDLER(sh2_read8_cs0);
  1756. sh2_read16_map[0x00/2].addr = sh2_read16_map[0x20/2].addr = MAP_HANDLER(sh2_read16_cs0);
  1757. sh2_read32_map[0x00/2].addr = sh2_read32_map[0x20/2].addr = MAP_HANDLER(sh2_read32_cs0);
  1758. sh2_write8_map[0x00/2] = sh2_write8_map[0x20/2] = sh2_write8_cs0;
  1759. sh2_write16_map[0x00/2] = sh2_write16_map[0x20/2] = sh2_write16_cs0;
  1760. sh2_write32_map[0x00/2] = sh2_write32_map[0x20/2] = sh2_write32_cs0;
  1761. // CS1 - ROM
  1762. bank_switch_rom_sh2();
  1763. sh2_read8_map[0x02/2].mask = sh2_read8_map[0x22/2].mask = 0x3fffff; // FIXME
  1764. sh2_read16_map[0x02/2].mask = sh2_read16_map[0x22/2].mask = 0x3ffffe; // FIXME
  1765. sh2_read32_map[0x02/2].mask = sh2_read32_map[0x22/2].mask = 0x3ffffc; // FIXME
  1766. sh2_write16_map[0x02/2] = sh2_write16_map[0x22/2] = sh2_write16_rom;
  1767. sh2_write32_map[0x02/2] = sh2_write32_map[0x22/2] = sh2_write32_rom;
  1768. // CS2 - DRAM
  1769. sh2_read8_map[0x04/2].mask = sh2_read8_map[0x24/2].mask = 0x01ffff;
  1770. sh2_read16_map[0x04/2].mask = sh2_read16_map[0x24/2].mask = 0x01fffe;
  1771. sh2_read32_map[0x04/2].mask = sh2_read32_map[0x24/2].mask = 0x01fffc;
  1772. sh2_write8_map[0x04/2] = sh2_write8_map[0x24/2] = sh2_write8_dram;
  1773. sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = sh2_write16_dram;
  1774. sh2_write32_map[0x04/2] = sh2_write32_map[0x24/2] = sh2_write32_dram;
  1775. // CS3 - SDRAM
  1776. sh2_read8_map[0x06/2].addr = sh2_read8_map[0x26/2].addr =
  1777. sh2_read16_map[0x06/2].addr = sh2_read16_map[0x26/2].addr =
  1778. sh2_read32_map[0x06/2].addr = sh2_read32_map[0x26/2].addr = MAP_MEMORY(Pico32xMem->sdram);
  1779. sh2_write8_map[0x06/2] = sh2_write8_sdram;
  1780. sh2_write8_map[0x26/2] = sh2_write8_sdram_wt;
  1781. sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram;
  1782. sh2_write32_map[0x06/2] = sh2_write32_map[0x26/2] = sh2_write32_sdram;
  1783. sh2_read8_map[0x06/2].mask = sh2_read8_map[0x26/2].mask = 0x03ffff;
  1784. sh2_read16_map[0x06/2].mask = sh2_read16_map[0x26/2].mask = 0x03fffe;
  1785. sh2_read32_map[0x06/2].mask = sh2_read32_map[0x26/2].mask = 0x03fffc;
  1786. // SH2 data array
  1787. sh2_read8_map[0xc0/2].addr = MAP_HANDLER(sh2_read8_da);
  1788. sh2_read16_map[0xc0/2].addr = MAP_HANDLER(sh2_read16_da);
  1789. sh2_read32_map[0xc0/2].addr = MAP_HANDLER(sh2_read32_da);
  1790. sh2_write8_map[0xc0/2] = sh2_write8_da;
  1791. sh2_write16_map[0xc0/2] = sh2_write16_da;
  1792. sh2_write32_map[0xc0/2] = sh2_write32_da;
  1793. // SH2 IO
  1794. sh2_read8_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read8);
  1795. sh2_read16_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read16);
  1796. sh2_read32_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read32);
  1797. sh2_write8_map[0xff/2] = sh2_peripheral_write8;
  1798. sh2_write16_map[0xff/2] = sh2_peripheral_write16;
  1799. sh2_write32_map[0xff/2] = sh2_peripheral_write32;
  1800. // map DRAM area, both 68k and SH2
  1801. Pico32xSwapDRAM(1);
  1802. msh2.read8_map = ssh2.read8_map = sh2_read8_map;
  1803. msh2.read16_map = ssh2.read16_map = sh2_read16_map;
  1804. msh2.read32_map = ssh2.read32_map = sh2_read32_map;
  1805. msh2.write8_tab = ssh2.write8_tab = (const void **)(void *)sh2_write8_map;
  1806. msh2.write16_tab = ssh2.write16_tab = (const void **)(void *)sh2_write16_map;
  1807. msh2.write32_tab = ssh2.write32_tab = (const void **)(void *)sh2_write32_map;
  1808. sh2_drc_mem_setup(&msh2);
  1809. sh2_drc_mem_setup(&ssh2);
  1810. // z80 hack
  1811. z80_map_set(z80_write_map, 0x8000, 0xffff, z80_md_bank_write_32x, 1);
  1812. }
  1813. void p32x_update_banks(void)
  1814. {
  1815. bank_switch_rom_68k(Pico32x.regs[4 / 2]);
  1816. bank_switch_rom_sh2();
  1817. if (Pico32x.emu_flags & P32XF_DRC_ROM_C)
  1818. sh2_drc_flush_all();
  1819. }
  1820. void Pico32xMemStateLoaded(void)
  1821. {
  1822. bank_switch_rom_68k(Pico32x.regs[4 / 2]);
  1823. Pico32xSwapDRAM((Pico32x.vdp_regs[0x0a / 2] & P32XV_FS) ^ P32XV_FS);
  1824. memset(Pico32xMem->pwm, 0, sizeof(Pico32xMem->pwm));
  1825. Pico32x.dirty_pal = 1;
  1826. Pico32x.emu_flags &= ~(P32XF_68KCPOLL | P32XF_68KVPOLL);
  1827. memset(&m68k_poll, 0, sizeof(m68k_poll));
  1828. msh2.state = 0;
  1829. msh2.poll_addr = msh2.poll_cycles = msh2.poll_cnt = 0;
  1830. ssh2.state = 0;
  1831. ssh2.poll_addr = ssh2.poll_cycles = ssh2.poll_cnt = 0;
  1832. sh2_drc_flush_all();
  1833. }
  1834. // vim:shiftwidth=2:ts=2:expandtab