32x.c 16 KB

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  1. /*
  2. * PicoDrive
  3. * (C) notaz, 2009,2010,2013
  4. *
  5. * This work is licensed under the terms of MAME license.
  6. * See COPYING file in the top-level directory.
  7. */
  8. #include "../pico_int.h"
  9. #include "../sound/ym2612.h"
  10. #include "../../cpu/sh2/compiler.h"
  11. struct Pico32x Pico32x;
  12. SH2 sh2s[2];
  13. #define SH2_IDLE_STATES (SH2_STATE_CPOLL|SH2_STATE_VPOLL|SH2_STATE_SLEEP)
  14. static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level)
  15. {
  16. if (sh2->pending_irl > sh2->pending_int_irq) {
  17. elprintf_sh2(sh2, EL_32X, "ack/irl %d @ %08x",
  18. level, sh2_pc(sh2));
  19. return 64 + sh2->pending_irl / 2;
  20. } else {
  21. elprintf_sh2(sh2, EL_32X, "ack/int %d/%d @ %08x",
  22. level, sh2->pending_int_vector, sh2_pc(sh2));
  23. sh2->pending_int_irq = 0; // auto-clear
  24. sh2->pending_level = sh2->pending_irl;
  25. return sh2->pending_int_vector;
  26. }
  27. }
  28. // MUST specify active_sh2 when called from sh2 memhandlers
  29. void p32x_update_irls(SH2 *active_sh2, unsigned int m68k_cycles)
  30. {
  31. int irqs, mlvl = 0, slvl = 0;
  32. int mrun, srun;
  33. if (active_sh2 != NULL)
  34. m68k_cycles = sh2_cycles_done_m68k(active_sh2);
  35. // msh2
  36. irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[0];
  37. while ((irqs >>= 1))
  38. mlvl++;
  39. mlvl *= 2;
  40. // ssh2
  41. irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[1];
  42. while ((irqs >>= 1))
  43. slvl++;
  44. slvl *= 2;
  45. mrun = sh2_irl_irq(&msh2, mlvl, msh2.state & SH2_STATE_RUN);
  46. if (mrun) {
  47. p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, m68k_cycles);
  48. if (msh2.state & SH2_STATE_RUN)
  49. sh2_end_run(&msh2, 1);
  50. }
  51. srun = sh2_irl_irq(&ssh2, slvl, ssh2.state & SH2_STATE_RUN);
  52. if (srun) {
  53. p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, m68k_cycles);
  54. if (ssh2.state & SH2_STATE_RUN)
  55. sh2_end_run(&ssh2, 1);
  56. }
  57. elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun);
  58. }
  59. // the mask register is inconsistent, CMD is supposed to be a mask,
  60. // while others are actually irq trigger enables?
  61. // TODO: test on hw..
  62. void p32x_trigger_irq(SH2 *sh2, unsigned int m68k_cycles, unsigned int mask)
  63. {
  64. Pico32x.sh2irqs |= mask & P32XI_VRES;
  65. Pico32x.sh2irqi[0] |= mask & (Pico32x.sh2irq_mask[0] << 3);
  66. Pico32x.sh2irqi[1] |= mask & (Pico32x.sh2irq_mask[1] << 3);
  67. p32x_update_irls(sh2, m68k_cycles);
  68. }
  69. void p32x_update_cmd_irq(SH2 *sh2, unsigned int m68k_cycles)
  70. {
  71. if ((Pico32x.sh2irq_mask[0] & 2) && (Pico32x.regs[2 / 2] & 1))
  72. Pico32x.sh2irqi[0] |= P32XI_CMD;
  73. else
  74. Pico32x.sh2irqi[0] &= ~P32XI_CMD;
  75. if ((Pico32x.sh2irq_mask[1] & 2) && (Pico32x.regs[2 / 2] & 2))
  76. Pico32x.sh2irqi[1] |= P32XI_CMD;
  77. else
  78. Pico32x.sh2irqi[1] &= ~P32XI_CMD;
  79. p32x_update_irls(sh2, m68k_cycles);
  80. }
  81. void Pico32xStartup(void)
  82. {
  83. elprintf(EL_STATUS|EL_32X, "32X startup");
  84. // TODO: OOM handling
  85. PicoIn.AHW |= PAHW_32X;
  86. sh2_init(&msh2, 0, &ssh2);
  87. msh2.irq_callback = sh2_irq_cb;
  88. sh2_init(&ssh2, 1, &msh2);
  89. ssh2.irq_callback = sh2_irq_cb;
  90. PicoMemSetup32x();
  91. p32x_pwm_ctl_changed();
  92. p32x_timers_recalc();
  93. Pico32x.sh2_regs[0] = P32XS2_ADEN;
  94. if (Pico.m.ncart_in)
  95. Pico32x.sh2_regs[0] |= P32XS_nCART;
  96. if (!Pico.m.pal)
  97. Pico32x.vdp_regs[0] |= P32XV_nPAL;
  98. rendstatus_old = -1;
  99. emu_32x_startup();
  100. }
  101. #define HWSWAP(x) (((x) << 16) | ((x) >> 16))
  102. void p32x_reset_sh2s(void)
  103. {
  104. elprintf(EL_32X, "sh2 reset");
  105. sh2_reset(&msh2);
  106. sh2_reset(&ssh2);
  107. sh2_peripheral_reset(&msh2);
  108. sh2_peripheral_reset(&ssh2);
  109. // if we don't have BIOS set, perform it's work here.
  110. // MSH2
  111. if (p32x_bios_m == NULL) {
  112. sh2_set_gbr(0, 0x20004000);
  113. if (!(PicoIn.AHW & PAHW_MCD)) {
  114. unsigned int idl_src, idl_dst, idl_size; // initial data load
  115. unsigned int vbr;
  116. // initial data
  117. idl_src = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d4)) & ~0xf0000000;
  118. idl_dst = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d8)) & ~0xf0000000;
  119. idl_size= HWSWAP(*(unsigned int *)(Pico.rom + 0x3dc));
  120. if (idl_size > Pico.romsize || idl_src + idl_size > Pico.romsize ||
  121. idl_size > 0x40000 || idl_dst + idl_size > 0x40000 || (idl_src & 3) || (idl_dst & 3)) {
  122. elprintf(EL_STATUS|EL_ANOMALY, "32x: invalid initial data ptrs: %06x -> %06x, %06x",
  123. idl_src, idl_dst, idl_size);
  124. }
  125. else
  126. memcpy(Pico32xMem->sdram + idl_dst, Pico.rom + idl_src, idl_size);
  127. // VBR
  128. vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3e8));
  129. sh2_set_vbr(0, vbr);
  130. // checksum and M_OK
  131. Pico32x.regs[0x28 / 2] = *(unsigned short *)(Pico.rom + 0x18e);
  132. }
  133. // program will set M_OK
  134. }
  135. // SSH2
  136. if (p32x_bios_s == NULL) {
  137. unsigned int vbr;
  138. // GBR/VBR
  139. vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3ec));
  140. sh2_set_gbr(1, 0x20004000);
  141. sh2_set_vbr(1, vbr);
  142. // program will set S_OK
  143. }
  144. msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDone();
  145. }
  146. void Pico32xInit(void)
  147. {
  148. if (msh2.mult_m68k_to_sh2 == 0 || msh2.mult_sh2_to_m68k == 0)
  149. Pico32xSetClocks(PICO_MSH2_HZ, 0);
  150. if (ssh2.mult_m68k_to_sh2 == 0 || ssh2.mult_sh2_to_m68k == 0)
  151. Pico32xSetClocks(0, PICO_MSH2_HZ);
  152. }
  153. void PicoPower32x(void)
  154. {
  155. memset(&Pico32x, 0, sizeof(Pico32x));
  156. Pico32x.regs[0] = P32XS_REN|P32XS_nRES; // verified
  157. Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_PEN;
  158. }
  159. void PicoUnload32x(void)
  160. {
  161. sh2_finish(&msh2);
  162. sh2_finish(&ssh2);
  163. if (Pico32xMem != NULL)
  164. plat_munmap(Pico32xMem, sizeof(*Pico32xMem));
  165. Pico32xMem = NULL;
  166. PicoIn.AHW &= ~PAHW_32X;
  167. }
  168. void PicoReset32x(void)
  169. {
  170. if (PicoIn.AHW & PAHW_32X) {
  171. p32x_trigger_irq(NULL, SekCyclesDone(), P32XI_VRES);
  172. p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, SekCyclesDone());
  173. p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, SekCyclesDone());
  174. p32x_pwm_ctl_changed();
  175. p32x_timers_recalc();
  176. }
  177. }
  178. static void p32x_start_blank(void)
  179. {
  180. if (Pico32xDrawMode != PDM32X_OFF && !PicoIn.skipFrame) {
  181. int offs, lines;
  182. pprof_start(draw);
  183. offs = 8; lines = 224;
  184. if ((Pico.video.reg[1] & 8) && !(PicoIn.opt & POPT_ALT_RENDERER)) {
  185. offs = 0;
  186. lines = 240;
  187. }
  188. // XXX: no proper handling of 32col mode..
  189. if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0 && // 32x not blanking
  190. (Pico.video.reg[12] & 1) && // 40col mode
  191. (!(Pico.video.debug_p & PVD_KILL_32X)))
  192. {
  193. int md_bg = Pico.video.reg[7] & 0x3f;
  194. // we draw full layer (not line-by-line)
  195. PicoDraw32xLayer(offs, lines, md_bg);
  196. }
  197. else if (Pico32xDrawMode != PDM32X_32X_ONLY)
  198. PicoDraw32xLayerMdOnly(offs, lines);
  199. pprof_end(draw);
  200. }
  201. // enter vblank
  202. Pico32x.vdp_regs[0x0a/2] |= P32XV_VBLK|P32XV_PEN;
  203. // FB swap waits until vblank
  204. if ((Pico32x.vdp_regs[0x0a/2] ^ Pico32x.pending_fb) & P32XV_FS) {
  205. Pico32x.vdp_regs[0x0a/2] &= ~P32XV_FS;
  206. Pico32x.vdp_regs[0x0a/2] |= Pico32x.pending_fb;
  207. Pico32xSwapDRAM(Pico32x.pending_fb ^ 1);
  208. }
  209. p32x_trigger_irq(NULL, SekCyclesDone(), P32XI_VINT);
  210. p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, SekCyclesDone());
  211. p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, SekCyclesDone());
  212. }
  213. void p32x_schedule_hint(SH2 *sh2, unsigned int m68k_cycles)
  214. {
  215. // rather rough, 32x hint is useless in practice
  216. int after;
  217. if (!((Pico32x.sh2irq_mask[0] | Pico32x.sh2irq_mask[1]) & 4))
  218. return; // nobody cares
  219. // note: when Pico.m.scanline is 224, SH2s might
  220. // still be at scanline 93 (or so)
  221. if (!(Pico32x.sh2_regs[0] & 0x80) && Pico.m.scanline > 224)
  222. return;
  223. after = (Pico32x.sh2_regs[4 / 2] + 1) * 488;
  224. if (sh2 != NULL)
  225. p32x_event_schedule_sh2(sh2, P32X_EVENT_HINT, after);
  226. else
  227. p32x_event_schedule(m68k_cycles, P32X_EVENT_HINT, after);
  228. }
  229. /* events */
  230. static void fillend_event(unsigned int now)
  231. {
  232. Pico32x.vdp_regs[0x0a/2] &= ~P32XV_nFEN;
  233. p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, now);
  234. p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, now);
  235. }
  236. static void hint_event(unsigned int now)
  237. {
  238. p32x_trigger_irq(NULL, now, P32XI_HINT);
  239. p32x_schedule_hint(NULL, now);
  240. }
  241. typedef void (event_cb)(unsigned int now);
  242. /* times are in m68k (7.6MHz) cycles */
  243. unsigned int p32x_event_times[P32X_EVENT_COUNT];
  244. static unsigned int event_time_next;
  245. static event_cb *p32x_event_cbs[P32X_EVENT_COUNT] = {
  246. p32x_pwm_irq_event, // P32X_EVENT_PWM
  247. fillend_event, // P32X_EVENT_FILLEND
  248. hint_event, // P32X_EVENT_HINT
  249. };
  250. // schedule event at some time 'after', in m68k clocks
  251. void p32x_event_schedule(unsigned int now, enum p32x_event event, int after)
  252. {
  253. unsigned int when;
  254. when = (now + after) | 1;
  255. elprintf(EL_32X, "32x: new event #%u %u->%u", event, now, when);
  256. p32x_event_times[event] = when;
  257. if (event_time_next == 0 || CYCLES_GT(event_time_next, when))
  258. event_time_next = when;
  259. }
  260. void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after)
  261. {
  262. unsigned int now = sh2_cycles_done_m68k(sh2);
  263. int left_to_next;
  264. p32x_event_schedule(now, event, after);
  265. left_to_next = C_M68K_TO_SH2(sh2, (int)(event_time_next - now));
  266. if (sh2_cycles_left(sh2) > left_to_next) {
  267. if (left_to_next < 1)
  268. left_to_next = 1;
  269. sh2_end_run(sh2, left_to_next);
  270. }
  271. }
  272. static void p32x_run_events(unsigned int until)
  273. {
  274. int oldest, oldest_diff, time;
  275. int i, diff;
  276. while (1) {
  277. oldest = -1, oldest_diff = 0x7fffffff;
  278. for (i = 0; i < P32X_EVENT_COUNT; i++) {
  279. if (p32x_event_times[i]) {
  280. diff = p32x_event_times[i] - until;
  281. if (diff < oldest_diff) {
  282. oldest_diff = diff;
  283. oldest = i;
  284. }
  285. }
  286. }
  287. if (oldest_diff <= 0) {
  288. time = p32x_event_times[oldest];
  289. p32x_event_times[oldest] = 0;
  290. elprintf(EL_32X, "32x: run event #%d %u", oldest, time);
  291. p32x_event_cbs[oldest](time);
  292. }
  293. else if (oldest_diff < 0x7fffffff) {
  294. event_time_next = p32x_event_times[oldest];
  295. break;
  296. }
  297. else {
  298. event_time_next = 0;
  299. break;
  300. }
  301. }
  302. if (oldest != -1)
  303. elprintf(EL_32X, "32x: next event #%d at %u",
  304. oldest, event_time_next);
  305. }
  306. static void run_sh2(SH2 *sh2, unsigned int m68k_cycles)
  307. {
  308. unsigned int cycles, done;
  309. pevt_log_sh2_o(sh2, EVT_RUN_START);
  310. sh2->state |= SH2_STATE_RUN;
  311. cycles = C_M68K_TO_SH2(sh2, m68k_cycles);
  312. elprintf_sh2(sh2, EL_32X, "+run %u %d @%08x",
  313. sh2->m68krcycles_done, cycles, sh2->pc);
  314. done = sh2_execute(sh2, cycles, PicoIn.opt & POPT_EN_DRC);
  315. sh2->m68krcycles_done += C_SH2_TO_M68K(sh2, done);
  316. sh2->state &= ~SH2_STATE_RUN;
  317. pevt_log_sh2_o(sh2, EVT_RUN_END);
  318. elprintf_sh2(sh2, EL_32X, "-run %u %d",
  319. sh2->m68krcycles_done, done);
  320. }
  321. // sync other sh2 to this one
  322. // note: recursive call
  323. void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target)
  324. {
  325. SH2 *osh2 = sh2->other_sh2;
  326. int left_to_event;
  327. int m68k_cycles;
  328. if (osh2->state & SH2_STATE_RUN)
  329. return;
  330. m68k_cycles = m68k_target - osh2->m68krcycles_done;
  331. if (m68k_cycles < 200)
  332. return;
  333. if (osh2->state & SH2_IDLE_STATES) {
  334. osh2->m68krcycles_done = m68k_target;
  335. return;
  336. }
  337. elprintf_sh2(osh2, EL_32X, "sync to %u %d",
  338. m68k_target, m68k_cycles);
  339. run_sh2(osh2, m68k_cycles);
  340. // there might be new event to schedule current sh2 to
  341. if (event_time_next) {
  342. left_to_event = C_M68K_TO_SH2(sh2, (int)(event_time_next - m68k_target));
  343. if (sh2_cycles_left(sh2) > left_to_event) {
  344. if (left_to_event < 1)
  345. left_to_event = 1;
  346. sh2_end_run(sh2, left_to_event);
  347. }
  348. }
  349. }
  350. #define STEP_LS 24
  351. #define STEP_N 440
  352. #define sync_sh2s_normal p32x_sync_sh2s
  353. //#define sync_sh2s_lockstep p32x_sync_sh2s
  354. /* most timing is in 68k clock */
  355. void sync_sh2s_normal(unsigned int m68k_target)
  356. {
  357. unsigned int now, target, timer_cycles;
  358. int cycles;
  359. elprintf(EL_32X, "sh2 sync to %u", m68k_target);
  360. if (!(Pico32x.regs[0] & P32XS_nRES)) {
  361. msh2.m68krcycles_done = ssh2.m68krcycles_done = m68k_target;
  362. return; // rare
  363. }
  364. now = msh2.m68krcycles_done;
  365. if (CYCLES_GT(now, ssh2.m68krcycles_done))
  366. now = ssh2.m68krcycles_done;
  367. timer_cycles = now;
  368. pprof_start(m68k);
  369. while (CYCLES_GT(m68k_target, now))
  370. {
  371. if (event_time_next && CYCLES_GE(now, event_time_next))
  372. p32x_run_events(now);
  373. target = m68k_target;
  374. if (event_time_next && CYCLES_GT(target, event_time_next))
  375. target = event_time_next;
  376. if (CYCLES_GT(target, now + STEP_N))
  377. target = now + STEP_N;
  378. while (CYCLES_GT(target, now))
  379. {
  380. elprintf(EL_32X, "sh2 exec to %u %d,%d/%d, flags %x", target,
  381. target - msh2.m68krcycles_done, target - ssh2.m68krcycles_done,
  382. m68k_target - now, Pico32x.emu_flags);
  383. pprof_start(ssh2);
  384. if (!(ssh2.state & SH2_IDLE_STATES)) {
  385. cycles = target - ssh2.m68krcycles_done;
  386. if (cycles > 0) {
  387. run_sh2(&ssh2, cycles);
  388. if (event_time_next && CYCLES_GT(target, event_time_next))
  389. target = event_time_next;
  390. }
  391. }
  392. pprof_end(ssh2);
  393. pprof_start(msh2);
  394. if (!(msh2.state & SH2_IDLE_STATES)) {
  395. cycles = target - msh2.m68krcycles_done;
  396. if (cycles > 0) {
  397. run_sh2(&msh2, cycles);
  398. if (event_time_next && CYCLES_GT(target, event_time_next))
  399. target = event_time_next;
  400. }
  401. }
  402. pprof_end(msh2);
  403. now = target;
  404. if (!(msh2.state & SH2_IDLE_STATES)) {
  405. if (CYCLES_GT(now, msh2.m68krcycles_done))
  406. now = msh2.m68krcycles_done;
  407. }
  408. if (!(ssh2.state & SH2_IDLE_STATES)) {
  409. if (CYCLES_GT(now, ssh2.m68krcycles_done))
  410. now = ssh2.m68krcycles_done;
  411. }
  412. }
  413. p32x_timers_do(now - timer_cycles);
  414. timer_cycles = now;
  415. }
  416. pprof_end_sub(m68k);
  417. // advance idle CPUs
  418. if (msh2.state & SH2_IDLE_STATES) {
  419. if (CYCLES_GT(m68k_target, msh2.m68krcycles_done))
  420. msh2.m68krcycles_done = m68k_target;
  421. }
  422. if (ssh2.state & SH2_IDLE_STATES) {
  423. if (CYCLES_GT(m68k_target, ssh2.m68krcycles_done))
  424. ssh2.m68krcycles_done = m68k_target;
  425. }
  426. // everyone is in sync now
  427. Pico32x.comm_dirty = 0;
  428. }
  429. void sync_sh2s_lockstep(unsigned int m68k_target)
  430. {
  431. unsigned int mcycles;
  432. mcycles = msh2.m68krcycles_done;
  433. if (ssh2.m68krcycles_done < mcycles)
  434. mcycles = ssh2.m68krcycles_done;
  435. while (mcycles < m68k_target) {
  436. mcycles += STEP_LS;
  437. sync_sh2s_normal(mcycles);
  438. }
  439. }
  440. #define CPUS_RUN(m68k_cycles) do { \
  441. if (PicoIn.AHW & PAHW_MCD) \
  442. pcd_run_cpus(m68k_cycles); \
  443. else \
  444. SekRunM68k(m68k_cycles); \
  445. \
  446. if ((Pico32x.emu_flags & P32XF_Z80_32X_IO) && Pico.m.z80Run \
  447. && !Pico.m.z80_reset && (PicoIn.opt & POPT_EN_Z80)) \
  448. PicoSyncZ80(SekCyclesDone()); \
  449. if (Pico32x.emu_flags & (P32XF_68KCPOLL|P32XF_68KVPOLL)) \
  450. p32x_sync_sh2s(SekCyclesDone()); \
  451. } while (0)
  452. #define PICO_32X
  453. #define PICO_CD
  454. #include "../pico_cmn.c"
  455. void PicoFrame32x(void)
  456. {
  457. Pico.m.scanline = 0;
  458. Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank
  459. if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking
  460. Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access
  461. if (!(Pico32x.sh2_regs[0] & 0x80))
  462. p32x_schedule_hint(NULL, SekCyclesDone());
  463. p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, SekCyclesDone());
  464. p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, SekCyclesDone());
  465. if (PicoIn.AHW & PAHW_MCD)
  466. pcd_prepare_frame();
  467. PicoFrameStart();
  468. PicoFrameHints();
  469. sh2_drc_frame();
  470. elprintf(EL_32X, "poll: %02x %02x %02x",
  471. Pico32x.emu_flags & 3, msh2.state, ssh2.state);
  472. }
  473. // calculate multipliers against 68k clock (7670442)
  474. // normally * 3, but effectively slower due to high latencies everywhere
  475. // however using something lower breaks MK2 animations
  476. void Pico32xSetClocks(int msh2_hz, int ssh2_hz)
  477. {
  478. float m68k_clk = (float)(OSC_NTSC / 7);
  479. if (msh2_hz > 0) {
  480. msh2.mult_m68k_to_sh2 = (int)((float)msh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk);
  481. msh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)msh2_hz);
  482. }
  483. if (ssh2_hz > 0) {
  484. ssh2.mult_m68k_to_sh2 = (int)((float)ssh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk);
  485. ssh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)ssh2_hz);
  486. }
  487. }
  488. void Pico32xStateLoaded(int is_early)
  489. {
  490. if (is_early) {
  491. Pico32xMemStateLoaded();
  492. return;
  493. }
  494. sh2s[0].m68krcycles_done = sh2s[1].m68krcycles_done = SekCyclesDone();
  495. p32x_update_irls(NULL, SekCyclesDone());
  496. p32x_pwm_state_loaded();
  497. p32x_run_events(SekCyclesDone());
  498. }
  499. // vim:shiftwidth=2:ts=2:expandtab