emit_x86.c 28 KB

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  1. /*
  2. * Basic macros to emit x86 instructions and some utils
  3. * Copyright (C) 2008,2009,2010 notaz
  4. *
  5. * This work is licensed under the terms of MAME license.
  6. * See COPYING file in the top-level directory.
  7. *
  8. * note:
  9. * temp registers must be eax-edx due to use of SETcc and r/w 8/16.
  10. * note about silly things like emith_eor_r_r_r:
  11. * these are here because the compiler was designed
  12. * for ARM as it's primary target.
  13. */
  14. #include <stdarg.h>
  15. enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
  16. #define HOST_REGS 8
  17. #define CONTEXT_REG xBP
  18. #define RET_REG xAX
  19. #define ICOND_JO 0x00
  20. #define ICOND_JNO 0x01
  21. #define ICOND_JB 0x02
  22. #define ICOND_JAE 0x03
  23. #define ICOND_JE 0x04
  24. #define ICOND_JNE 0x05
  25. #define ICOND_JBE 0x06
  26. #define ICOND_JA 0x07
  27. #define ICOND_JS 0x08
  28. #define ICOND_JNS 0x09
  29. #define ICOND_JL 0x0c
  30. #define ICOND_JGE 0x0d
  31. #define ICOND_JLE 0x0e
  32. #define ICOND_JG 0x0f
  33. #define IOP_JMP 0xeb
  34. // unified conditions (we just use rel8 jump instructions for x86)
  35. #define DCOND_EQ ICOND_JE
  36. #define DCOND_NE ICOND_JNE
  37. #define DCOND_MI ICOND_JS // MInus
  38. #define DCOND_PL ICOND_JNS // PLus or zero
  39. #define DCOND_HI ICOND_JA // higher (unsigned)
  40. #define DCOND_HS ICOND_JAE // higher || same (unsigned)
  41. #define DCOND_LO ICOND_JB // lower (unsigned)
  42. #define DCOND_LS ICOND_JBE // lower || same (unsigned)
  43. #define DCOND_GE ICOND_JGE // greater || equal (signed)
  44. #define DCOND_GT ICOND_JG // greater (signed)
  45. #define DCOND_LE ICOND_JLE // less || equal (signed)
  46. #define DCOND_LT ICOND_JL // less (signed)
  47. #define DCOND_VS ICOND_JO // oVerflow Set
  48. #define DCOND_VC ICOND_JNO // oVerflow Clear
  49. #define DCOND_CS ICOND_JB // carry set
  50. #define DCOND_CC ICOND_JAE // carry clear
  51. #define EMIT_PTR(ptr, val, type) \
  52. *(type *)(ptr) = val
  53. #define EMIT(val, type) do { \
  54. EMIT_PTR(tcache_ptr, val, type); \
  55. tcache_ptr += sizeof(type); \
  56. } while (0)
  57. #define EMIT_OP(op) do { \
  58. COUNT_OP; \
  59. EMIT(op, u8); \
  60. } while (0)
  61. #define EMIT_MODRM(mod, r, rm) do { \
  62. assert((mod) < 4u); \
  63. assert((r) < 8u); \
  64. assert((rm) < 8u); \
  65. EMIT(((mod)<<6) | ((r)<<3) | (rm), u8); \
  66. } while (0)
  67. #define EMIT_SIB(scale, index, base) do { \
  68. assert((scale) < 4u); \
  69. assert((index) < 8u); \
  70. assert((base) < 8u); \
  71. EMIT(((scale)<<6) | ((index)<<3) | (base), u8); \
  72. } while (0)
  73. #define EMIT_SIB64(scale, index, base) \
  74. EMIT_SIB(scale, (index) & ~8u, (base) & ~8u)
  75. #define EMIT_REX(w,r,x,b) \
  76. EMIT(0x40 | ((w)<<3) | ((r)<<2) | ((x)<<1) | (b), u8)
  77. #define EMIT_OP_MODRM(op,mod,r,rm) do { \
  78. EMIT_OP(op); \
  79. EMIT_MODRM(mod, (r), rm); \
  80. } while (0)
  81. // 64bit friendly, rm when everything is converted
  82. #define EMIT_OP_MODRM64(op, mod, r, rm) \
  83. EMIT_OP_MODRM(op, mod, (r) & ~8u, (rm) & ~8u)
  84. #define JMP8_POS(ptr) \
  85. ptr = tcache_ptr; \
  86. tcache_ptr += 2
  87. #define JMP8_EMIT(op, ptr) \
  88. EMIT_PTR(ptr, 0x70|(op), u8); \
  89. EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)
  90. #define JMP8_EMIT_NC(ptr) \
  91. EMIT_PTR(ptr, IOP_JMP, u8); \
  92. EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)
  93. // _r_r
  94. #define emith_move_r_r(dst, src) \
  95. EMIT_OP_MODRM(0x8b, 3, dst, src)
  96. #define emith_move_r_r_ptr(dst, src) do { \
  97. EMIT_REX_IF(1, dst, src); \
  98. EMIT_OP_MODRM64(0x8b, 3, dst, src); \
  99. } while (0)
  100. #define emith_add_r_r(d, s) \
  101. EMIT_OP_MODRM(0x01, 3, s, d)
  102. #define emith_add_r_r_ptr(d, s) do { \
  103. EMIT_REX_IF(1, s, d); \
  104. EMIT_OP_MODRM64(0x01, 3, s, d); \
  105. } while (0)
  106. #define emith_sub_r_r(d, s) \
  107. EMIT_OP_MODRM(0x29, 3, s, d)
  108. #define emith_adc_r_r(d, s) \
  109. EMIT_OP_MODRM(0x11, 3, s, d)
  110. #define emith_sbc_r_r(d, s) \
  111. EMIT_OP_MODRM(0x19, 3, s, d) /* SBB */
  112. #define emith_or_r_r(d, s) \
  113. EMIT_OP_MODRM(0x09, 3, s, d)
  114. #define emith_and_r_r(d, s) \
  115. EMIT_OP_MODRM(0x21, 3, s, d)
  116. #define emith_eor_r_r(d, s) \
  117. EMIT_OP_MODRM(0x31, 3, s, d) /* XOR */
  118. #define emith_tst_r_r(d, s) \
  119. EMIT_OP_MODRM(0x85, 3, s, d) /* TEST */
  120. #define emith_tst_r_r_ptr(d, s) do { \
  121. EMIT_REX_IF(1, s, d); \
  122. EMIT_OP_MODRM64(0x85, 3, s, d); /* TEST */ \
  123. } while (0)
  124. #define emith_cmp_r_r(d, s) \
  125. EMIT_OP_MODRM(0x39, 3, s, d)
  126. // fake teq - test equivalence - get_flags(d ^ s)
  127. #define emith_teq_r_r(d, s) do { \
  128. emith_push(d); \
  129. emith_eor_r_r(d, s); \
  130. emith_pop(d); \
  131. } while (0)
  132. #define emith_mvn_r_r(d, s) do { \
  133. if (d != s) \
  134. emith_move_r_r(d, s); \
  135. EMIT_OP_MODRM(0xf7, 3, 2, d); /* NOT d */ \
  136. } while (0)
  137. #define emith_negc_r_r(d, s) do { \
  138. int tmp_ = rcache_get_tmp(); \
  139. emith_move_r_imm(tmp_, 0); \
  140. emith_sbc_r_r(tmp_, s); \
  141. emith_move_r_r(d, tmp_); \
  142. rcache_free_tmp(tmp_); \
  143. } while (0)
  144. #define emith_neg_r_r(d, s) do { \
  145. if (d != s) \
  146. emith_move_r_r(d, s); \
  147. EMIT_OP_MODRM(0xf7, 3, 3, d); /* NEG d */ \
  148. } while (0)
  149. // _r_r_r
  150. #define emith_add_r_r_r(d, s1, s2) do { \
  151. if (d == s1) { \
  152. emith_add_r_r(d, s2); \
  153. } else if (d == s2) { \
  154. emith_add_r_r(d, s1); \
  155. } else { \
  156. emith_move_r_r(d, s1); \
  157. emith_add_r_r(d, s2); \
  158. } \
  159. } while (0)
  160. #define emith_add_r_r_r_ptr(d, s1, s2) do { \
  161. if (d == s1) { \
  162. emith_add_r_r_ptr(d, s2); \
  163. } else if (d == s2) { \
  164. emith_add_r_r_ptr(d, s1); \
  165. } else { \
  166. emith_move_r_r_ptr(d, s1); \
  167. emith_add_r_r_ptr(d, s2); \
  168. } \
  169. } while (0)
  170. #define emith_sub_r_r_r(d, s1, s2) do { \
  171. if (d == s1) { \
  172. emith_sub_r_r(d, s2); \
  173. } else if (d == s2) { \
  174. emith_sub_r_r(d, s1); \
  175. } else { \
  176. emith_move_r_r(d, s1); \
  177. emith_sub_r_r(d, s2); \
  178. } \
  179. } while (0)
  180. #define emith_adc_r_r_r(d, s1, s2) do { \
  181. if (d == s1) { \
  182. emith_adc_r_r(d, s2); \
  183. } else if (d == s2) { \
  184. emith_adc_r_r(d, s1); \
  185. } else { \
  186. emith_move_r_r(d, s1); \
  187. emith_adc_r_r(d, s2); \
  188. } \
  189. } while (0)
  190. #define emith_sbc_r_r_r(d, s1, s2) do { \
  191. if (d == s1) { \
  192. emith_sbc_r_r(d, s2); \
  193. } else if (d == s2) { \
  194. emith_sbc_r_r(d, s1); \
  195. } else { \
  196. emith_move_r_r(d, s1); \
  197. emith_sbc_r_r(d, s2); \
  198. } \
  199. } while (0)
  200. #define emith_and_r_r_r(d, s1, s2) do { \
  201. if (d == s1) { \
  202. emith_and_r_r(d, s2); \
  203. } else if (d == s2) { \
  204. emith_and_r_r(d, s1); \
  205. } else { \
  206. emith_move_r_r(d, s1); \
  207. emith_and_r_r(d, s2); \
  208. } \
  209. } while (0)
  210. #define emith_or_r_r_r(d, s1, s2) do { \
  211. if (d == s1) { \
  212. emith_or_r_r(d, s2); \
  213. } else if (d == s2) { \
  214. emith_or_r_r(d, s1); \
  215. } else { \
  216. emith_move_r_r(d, s1); \
  217. emith_or_r_r(d, s2); \
  218. } \
  219. } while (0)
  220. #define emith_eor_r_r_r(d, s1, s2) do { \
  221. if (d == s1) { \
  222. emith_eor_r_r(d, s2); \
  223. } else if (d == s2) { \
  224. emith_eor_r_r(d, s1); \
  225. } else { \
  226. emith_move_r_r(d, s1); \
  227. emith_eor_r_r(d, s2); \
  228. } \
  229. } while (0)
  230. // _r_r_r_shift
  231. #define emith_add_r_r_r_lsl(d, s1, s2, lslimm) do { \
  232. int tmp_ = rcache_get_tmp(); \
  233. emith_lsl(tmp_, s2, lslimm); \
  234. emith_add_r_r_r(d, s1, tmp_); \
  235. rcache_free_tmp(tmp_); \
  236. } while (0)
  237. #define emith_add_r_r_r_lsl_ptr(d, s1, s2, lslimm) do { \
  238. int tmp_ = rcache_get_tmp(); \
  239. emith_lsl(tmp_, s2, lslimm); \
  240. emith_add_r_r_r_ptr(d, s1, tmp_); \
  241. rcache_free_tmp(tmp_); \
  242. } while (0)
  243. #define emith_add_r_r_r_lsr(d, s1, s2, lsrimm) do { \
  244. int tmp_ = rcache_get_tmp(); \
  245. emith_lsr(tmp_, s2, lsrimm); \
  246. emith_add_r_r_r(d, s1, tmp_); \
  247. rcache_free_tmp(tmp_); \
  248. } while (0)
  249. // _r_r_shift
  250. #define emith_or_r_r_lsl(d, s, lslimm) do { \
  251. int tmp_ = rcache_get_tmp(); \
  252. emith_lsl(tmp_, s, lslimm); \
  253. emith_or_r_r(d, tmp_); \
  254. rcache_free_tmp(tmp_); \
  255. } while (0)
  256. // d != s
  257. #define emith_eor_r_r_lsr(d, s, lsrimm) do { \
  258. emith_push(s); \
  259. emith_lsr(s, s, lsrimm); \
  260. emith_eor_r_r(d, s); \
  261. emith_pop(s); \
  262. } while (0)
  263. // _r_imm
  264. #define emith_move_r_imm(r, imm) do { \
  265. EMIT_OP(0xb8 + (r)); \
  266. EMIT(imm, u32); \
  267. } while (0)
  268. #define emith_move_r_ptr_imm(r, imm) do { \
  269. if ((uint64_t)(imm) <= UINT32_MAX) \
  270. emith_move_r_imm(r, (uintptr_t)(imm)); \
  271. else { \
  272. EMIT_REX_IF(1, 0, r); \
  273. EMIT_OP(0xb8 + (r)); \
  274. EMIT((uint64_t)(imm), uint64_t); \
  275. } \
  276. } while (0)
  277. #define emith_move_r_imm_s8(r, imm) \
  278. emith_move_r_imm(r, (u32)(signed int)(signed char)(imm))
  279. #define emith_arith_r_imm(op, r, imm) do { \
  280. EMIT_OP_MODRM(0x81, 3, op, r); \
  281. EMIT(imm, u32); \
  282. } while (0)
  283. #define emith_add_r_imm(r, imm) \
  284. emith_arith_r_imm(0, r, imm)
  285. #define emith_or_r_imm(r, imm) \
  286. emith_arith_r_imm(1, r, imm)
  287. #define emith_adc_r_imm(r, imm) \
  288. emith_arith_r_imm(2, r, imm)
  289. #define emith_sbc_r_imm(r, imm) \
  290. emith_arith_r_imm(3, r, imm) // sbb
  291. #define emith_and_r_imm(r, imm) \
  292. emith_arith_r_imm(4, r, imm)
  293. #define emith_sub_r_imm(r, imm) \
  294. emith_arith_r_imm(5, r, imm)
  295. #define emith_eor_r_imm(r, imm) \
  296. emith_arith_r_imm(6, r, imm)
  297. #define emith_cmp_r_imm(r, imm) \
  298. emith_arith_r_imm(7, r, imm)
  299. #define emith_tst_r_imm(r, imm) do { \
  300. EMIT_OP_MODRM(0xf7, 3, 0, r); \
  301. EMIT(imm, u32); \
  302. } while (0)
  303. // fake
  304. #define emith_bic_r_imm(r, imm) \
  305. emith_arith_r_imm(4, r, ~(imm))
  306. // fake conditionals (using SJMP instead)
  307. #define emith_move_r_imm_c(cond, r, imm) do { \
  308. (void)(cond); \
  309. emith_move_r_imm(r, imm); \
  310. } while (0)
  311. #define emith_add_r_imm_c(cond, r, imm) do { \
  312. (void)(cond); \
  313. emith_add_r_imm(r, imm); \
  314. } while (0)
  315. #define emith_sub_r_imm_c(cond, r, imm) do { \
  316. (void)(cond); \
  317. emith_sub_r_imm(r, imm); \
  318. } while (0)
  319. #define emith_or_r_imm_c(cond, r, imm) \
  320. emith_or_r_imm(r, imm)
  321. #define emith_eor_r_imm_c(cond, r, imm) \
  322. emith_eor_r_imm(r, imm)
  323. #define emith_bic_r_imm_c(cond, r, imm) \
  324. emith_bic_r_imm(r, imm)
  325. #define emith_tst_r_imm_c(cond, r, imm) \
  326. emith_tst_r_imm(r, imm)
  327. #define emith_ror_c(cond, d, s, cnt) \
  328. emith_ror(d, s, cnt)
  329. #define emith_and_r_r_c(cond, d, s) \
  330. emith_and_r_r(d, s);
  331. #define emith_read8_r_r_r_c(cond, r, rs, rm) \
  332. emith_read8_r_r_r(r, rs, rm)
  333. #define emith_read16_r_r_r_c(cond, r, rs, rm) \
  334. emith_read16_r_r_r(r, rs, rm)
  335. #define emith_read_r_r_r_c(cond, r, rs, rm) \
  336. emith_read_r_r_r(r, rs, rm)
  337. #define emith_read_r_r_offs_c(cond, r, rs, offs) \
  338. emith_read_r_r_offs(r, rs, offs)
  339. #define emith_read_r_r_offs_ptr_c(cond, r, rs, offs) \
  340. emith_read_r_r_offs_ptr(r, rs, offs)
  341. #define emith_write_r_r_offs_c(cond, r, rs, offs) \
  342. emith_write_r_r_offs(r, rs, offs)
  343. #define emith_write_r_r_offs_ptr_c(cond, r, rs, offs) \
  344. emith_write_r_r_offs_ptr(r, rs, offs)
  345. #define emith_read8_r_r_offs_c(cond, r, rs, offs) \
  346. emith_read8_r_r_offs(r, rs, offs)
  347. #define emith_write8_r_r_offs_c(cond, r, rs, offs) \
  348. emith_write8_r_r_offs(r, rs, offs)
  349. #define emith_read16_r_r_offs_c(cond, r, rs, offs) \
  350. emith_read16_r_r_offs(r, rs, offs)
  351. #define emith_write16_r_r_offs_c(cond, r, rs, offs) \
  352. emith_write16_r_r_offs(r, rs, offs)
  353. #define emith_jump_reg_c(cond, r) \
  354. emith_jump_reg(r)
  355. #define emith_jump_ctx_c(cond, offs) \
  356. emith_jump_ctx(offs)
  357. #define emith_ret_c(cond) \
  358. emith_ret()
  359. // _r_r_imm - use lea
  360. #define emith_add_r_r_imm(d, s, imm) do { \
  361. assert(s != xSP); \
  362. EMIT_OP_MODRM(0x8d, 2, d, s); /* lea */ \
  363. EMIT(imm, s32); \
  364. } while (0)
  365. #define emith_add_r_r_ptr_imm(d, s, imm) do { \
  366. if ((s) != xSP) { \
  367. EMIT_REX_IF(1, d, s); \
  368. EMIT_OP_MODRM64(0x8d, 2, d, s); /* lea */ \
  369. } \
  370. else { \
  371. if (d != s) \
  372. emith_move_r_r_ptr(d, s); \
  373. EMIT_REX_IF(1, 0, d); \
  374. EMIT_OP_MODRM64(0x81, 3, 0, d); /* add */ \
  375. } \
  376. EMIT(imm, s32); \
  377. } while (0)
  378. #define emith_sub_r_r_imm(d, s, imm) do { \
  379. if (d != s) \
  380. emith_move_r_r(d, s); \
  381. if ((s32)(imm) != 0) \
  382. emith_sub_r_imm(d, imm); \
  383. } while (0)
  384. #define emith_and_r_r_imm(d, s, imm) do { \
  385. if (d != s) \
  386. emith_move_r_r(d, s); \
  387. if ((s32)(imm) != -1) \
  388. emith_and_r_imm(d, imm); \
  389. } while (0)
  390. #define emith_or_r_r_imm(d, s, imm) do { \
  391. if (d != s) \
  392. emith_move_r_r(d, s); \
  393. if ((s32)(imm) != 0) \
  394. emith_or_r_imm(d, imm); \
  395. } while (0)
  396. #define emith_eor_r_r_imm(d, s, imm) do { \
  397. if (d != s) \
  398. emith_move_r_r(d, s); \
  399. if ((s32)(imm) != 0) \
  400. emith_eor_r_imm(d, imm); \
  401. } while (0)
  402. // shift
  403. #define emith_shift(op, d, s, cnt) do { \
  404. if (d != s) \
  405. emith_move_r_r(d, s); \
  406. EMIT_OP_MODRM(0xc1, 3, op, d); \
  407. EMIT(cnt, u8); \
  408. } while (0)
  409. #define emith_lsl(d, s, cnt) \
  410. emith_shift(4, d, s, cnt)
  411. #define emith_lsr(d, s, cnt) \
  412. emith_shift(5, d, s, cnt)
  413. #define emith_asr(d, s, cnt) \
  414. emith_shift(7, d, s, cnt)
  415. #define emith_rol(d, s, cnt) \
  416. emith_shift(0, d, s, cnt)
  417. #define emith_ror(d, s, cnt) \
  418. emith_shift(1, d, s, cnt)
  419. #define emith_rolc(r) \
  420. EMIT_OP_MODRM(0xd1, 3, 2, r)
  421. #define emith_rorc(r) \
  422. EMIT_OP_MODRM(0xd1, 3, 3, r)
  423. // misc
  424. #define emith_push(r) \
  425. EMIT_OP(0x50 + (r))
  426. #define emith_push_imm(imm) do { \
  427. EMIT_OP(0x68); \
  428. EMIT(imm, u32); \
  429. } while (0)
  430. #define emith_pop(r) \
  431. EMIT_OP(0x58 + (r))
  432. #define emith_neg_r(r) \
  433. EMIT_OP_MODRM(0xf7, 3, 3, r)
  434. #define emith_clear_msb(d, s, count) { \
  435. u32 t = (u32)-1; \
  436. t >>= count; \
  437. if (d != s) \
  438. emith_move_r_r(d, s); \
  439. emith_and_r_imm(d, t); \
  440. }
  441. #define emith_clear_msb_c(cond, d, s, count) { \
  442. (void)(cond); \
  443. emith_clear_msb(d, s, count); \
  444. }
  445. #define emith_sext(d, s, bits) { \
  446. emith_lsl(d, s, 32 - (bits)); \
  447. emith_asr(d, d, 32 - (bits)); \
  448. }
  449. #define emith_setc(r) do { \
  450. assert(is_abcdx(r)); \
  451. EMIT_OP(0x0f); \
  452. EMIT_OP_MODRM(0x92, 3, 0, r); /* SETC r */ \
  453. } while (0)
  454. // XXX: stupid mess
  455. #define emith_mul_(op, dlo, dhi, s1, s2) do { \
  456. int rmr; \
  457. if (dlo != xAX && dhi != xAX) \
  458. emith_push(xAX); \
  459. if (dlo != xDX && dhi != xDX) \
  460. emith_push(xDX); \
  461. if ((s1) == xAX) \
  462. rmr = s2; \
  463. else if ((s2) == xAX) \
  464. rmr = s1; \
  465. else { \
  466. emith_move_r_r(xAX, s1); \
  467. rmr = s2; \
  468. } \
  469. EMIT_OP_MODRM(0xf7, 3, op, rmr); /* xMUL rmr */ \
  470. if (dlo != xAX) \
  471. EMIT_OP(0x90 + (dlo)); /* XCHG eax, dlo */ \
  472. if (dhi != xDX && dhi != -1 && !(dhi == xAX && dlo == xDX)) \
  473. emith_move_r_r(dhi, (dlo == xDX ? xAX : xDX)); \
  474. if (dlo != xDX && dhi != xDX) \
  475. emith_pop(xDX); \
  476. if (dlo != xAX && dhi != xAX) \
  477. emith_pop(xAX); \
  478. } while (0)
  479. #define emith_mul_u64(dlo, dhi, s1, s2) \
  480. emith_mul_(4, dlo, dhi, s1, s2) /* MUL */
  481. #define emith_mul_s64(dlo, dhi, s1, s2) \
  482. emith_mul_(5, dlo, dhi, s1, s2) /* IMUL */
  483. #define emith_mul(d, s1, s2) \
  484. emith_mul_(4, d, -1, s1, s2)
  485. // (dlo,dhi) += signed(s1) * signed(s2)
  486. #define emith_mula_s64(dlo, dhi, s1, s2) do { \
  487. emith_push(dhi); \
  488. emith_push(dlo); \
  489. emith_mul_(5, dlo, dhi, s1, s2); \
  490. EMIT_OP_MODRM(0x03, 0, dlo, 4); \
  491. EMIT_SIB(0, 4, 4); /* add dlo, [xsp] */ \
  492. EMIT_OP_MODRM(0x13, 1, dhi, 4); \
  493. EMIT_SIB(0, 4, 4); \
  494. EMIT(sizeof(void *), u8); /* adc dhi, [xsp+{4,8}] */ \
  495. emith_add_r_r_ptr_imm(xSP, xSP, sizeof(void *) * 2); \
  496. } while (0)
  497. // "flag" instructions are the same
  498. #define emith_adcf_r_imm emith_adc_r_imm
  499. #define emith_subf_r_imm emith_sub_r_imm
  500. #define emith_addf_r_r emith_add_r_r
  501. #define emith_subf_r_r emith_sub_r_r
  502. #define emith_adcf_r_r emith_adc_r_r
  503. #define emith_sbcf_r_r emith_sbc_r_r
  504. #define emith_eorf_r_r emith_eor_r_r
  505. #define emith_negcf_r_r emith_negc_r_r
  506. #define emith_subf_r_r_imm emith_sub_r_r_imm
  507. #define emith_addf_r_r_r emith_add_r_r_r
  508. #define emith_subf_r_r_r emith_sub_r_r_r
  509. #define emith_adcf_r_r_r emith_adc_r_r_r
  510. #define emith_sbcf_r_r_r emith_sbc_r_r_r
  511. #define emith_eorf_r_r_r emith_eor_r_r_r
  512. #define emith_addf_r_r_r_lsr emith_add_r_r_r_lsr
  513. #define emith_lslf emith_lsl
  514. #define emith_lsrf emith_lsr
  515. #define emith_asrf emith_asr
  516. #define emith_rolf emith_rol
  517. #define emith_rorf emith_ror
  518. #define emith_rolcf emith_rolc
  519. #define emith_rorcf emith_rorc
  520. #define emith_deref_op(op, r, rs, offs) do { \
  521. /* mov r <-> [ebp+#offs] */ \
  522. if (abs(offs) >= 0x80) { \
  523. EMIT_OP_MODRM64(op, 2, r, rs); \
  524. EMIT(offs, u32); \
  525. } else { \
  526. EMIT_OP_MODRM64(op, 1, r, rs); \
  527. EMIT((u8)offs, u8); \
  528. } \
  529. } while (0)
  530. #define is_abcdx(r) (xAX <= (r) && (r) <= xDX)
  531. #define emith_read_r_r_offs(r, rs, offs) \
  532. emith_deref_op(0x8b, r, rs, offs)
  533. #define emith_read_r_r_offs_ptr(r, rs, offs) \
  534. EMIT_REX_IF(1, r, rs); \
  535. emith_deref_op(0x8b, r, rs, offs)
  536. #define emith_write_r_r_offs(r, rs, offs) \
  537. emith_deref_op(0x89, r, rs, offs)
  538. #define emith_write_r_r_offs_ptr(r, rs, offs) \
  539. EMIT_REX_IF(1, r, rs); \
  540. emith_deref_op(0x89, r, rs, offs)
  541. #define emith_read8_r_r_offs(r, rs, offs) do { \
  542. EMIT(0x0f, u8); \
  543. emith_deref_op(0xb6, r, rs, offs); \
  544. } while (0)
  545. #define emith_read8s_r_r_offs(r, rs, offs) do { \
  546. EMIT(0x0f, u8); \
  547. emith_deref_op(0xbe, r, rs, offs); \
  548. } while (0)
  549. // note: don't use prefixes on this
  550. #define emith_write8_r_r_offs(r, rs, offs) do {\
  551. int r_ = r; \
  552. if (!is_abcdx(r)) { \
  553. r_ = rcache_get_tmp(); \
  554. emith_move_r_r(r_, r); \
  555. } \
  556. emith_deref_op(0x88, r_, rs, offs); \
  557. if ((r) != r_) \
  558. rcache_free_tmp(r_); \
  559. } while (0)
  560. #define emith_read16_r_r_offs(r, rs, offs) do { \
  561. EMIT(0x0f, u8); \
  562. emith_deref_op(0xb7, r, rs, offs); \
  563. } while (0)
  564. #define emith_read16s_r_r_offs(r, rs, offs) do { \
  565. EMIT(0x0f, u8); \
  566. emith_deref_op(0xbf, r, rs, offs); \
  567. } while (0)
  568. #define emith_write16_r_r_offs(r, rs, offs) do { \
  569. EMIT(0x66, u8); \
  570. emith_write_r_r_offs(r, rs, offs); \
  571. } while (0)
  572. #define emith_read8_r_r_r(r, rs, rm) do { \
  573. EMIT(0x0f, u8); \
  574. EMIT_OP_MODRM(0xb6, 0, r, 4); \
  575. EMIT_SIB(0, rs, rm); /* mov r, [rm + rs * 1] */ \
  576. } while (0)
  577. #define emith_read16_r_r_r(r, rs, rm) do { \
  578. EMIT(0x0f, u8); \
  579. EMIT_OP_MODRM(0xb7, 0, r, 4); \
  580. EMIT_SIB(0, rs, rm); /* mov r, [rm + rs * 1] */ \
  581. } while (0)
  582. #define emith_read_r_r_r(r, rs, rm) do { \
  583. EMIT_OP_MODRM(0x8b, 0, r, 4); \
  584. EMIT_SIB(0, rs, rm); /* mov r, [rm + rs * 1] */ \
  585. } while (0)
  586. #define emith_ctx_read(r, offs) \
  587. emith_read_r_r_offs(r, CONTEXT_REG, offs)
  588. #define emith_ctx_read_c(cond, r, offs) \
  589. emith_ctx_read(r, offs)
  590. #define emith_ctx_read_ptr(r, offs) do { \
  591. EMIT_REX_IF(1, r, CONTEXT_REG); \
  592. emith_deref_op(0x8b, r, CONTEXT_REG, offs); \
  593. } while (0)
  594. #define emith_ctx_write(r, offs) \
  595. emith_write_r_r_offs(r, CONTEXT_REG, offs)
  596. #define emith_ctx_read_multiple(r, offs, cnt, tmpr) do { \
  597. int r_ = r, offs_ = offs, cnt_ = cnt; \
  598. for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
  599. emith_ctx_read(r_, offs_); \
  600. } while (0)
  601. #define emith_ctx_write_multiple(r, offs, cnt, tmpr) do { \
  602. int r_ = r, offs_ = offs, cnt_ = cnt; \
  603. for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
  604. emith_ctx_write(r_, offs_); \
  605. } while (0)
  606. // assumes EBX is free
  607. #define emith_ret_to_ctx(offs) { \
  608. emith_pop(xBX); \
  609. emith_ctx_write(xBX, offs); \
  610. }
  611. #define emith_jump(ptr) { \
  612. u32 disp = (u8 *)(ptr) - ((u8 *)tcache_ptr + 5); \
  613. EMIT_OP(0xe9); \
  614. EMIT(disp, u32); \
  615. }
  616. #define emith_jump_patchable(target) \
  617. emith_jump(target)
  618. #define emith_jump_cond(cond, ptr) do { \
  619. u32 disp = (u8 *)(ptr) - ((u8 *)tcache_ptr + 6); \
  620. EMIT(0x0f, u8); \
  621. EMIT_OP(0x80 | (cond)); \
  622. EMIT(disp, u32); \
  623. } while (0)
  624. #define emith_jump_cond_patchable(cond, target) \
  625. emith_jump_cond(cond, target)
  626. #define emith_jump_patch(ptr, target) do { \
  627. u32 disp_ = (u8 *)(target) - ((u8 *)(ptr) + 4); \
  628. u32 offs_ = (*(u8 *)(ptr) == 0x0f) ? 2 : 1; \
  629. EMIT_PTR((u8 *)(ptr) + offs_, disp_ - offs_, u32); \
  630. } while (0)
  631. #define emith_jump_at(ptr, target) { \
  632. u32 disp_ = (u8 *)(target) - ((u8 *)(ptr) + 5); \
  633. EMIT_PTR(ptr, 0xe9, u8); \
  634. EMIT_PTR((u8 *)(ptr) + 1, disp_, u32); \
  635. }
  636. #define emith_call(ptr) { \
  637. u32 disp = (u8 *)(ptr) - ((u8 *)tcache_ptr + 5); \
  638. EMIT_OP(0xe8); \
  639. EMIT(disp, u32); \
  640. }
  641. #define emith_call_cond(cond, ptr) \
  642. emith_call(ptr)
  643. #define emith_call_reg(r) \
  644. EMIT_OP_MODRM(0xff, 3, 2, r)
  645. #define emith_call_ctx(offs) do { \
  646. EMIT_OP_MODRM(0xff, 2, 2, CONTEXT_REG); \
  647. EMIT(offs, u32); \
  648. } while (0)
  649. #define emith_ret() \
  650. EMIT_OP(0xc3)
  651. #define emith_jump_reg(r) \
  652. EMIT_OP_MODRM(0xff, 3, 4, r)
  653. #define emith_jump_ctx(offs) do { \
  654. EMIT_OP_MODRM(0xff, 2, 4, CONTEXT_REG); \
  655. EMIT(offs, u32); \
  656. } while (0)
  657. #define emith_push_ret()
  658. #define emith_pop_and_ret() \
  659. emith_ret()
  660. #define EMITH_JMP_START(cond) { \
  661. u8 *cond_ptr; \
  662. JMP8_POS(cond_ptr)
  663. #define EMITH_JMP_END(cond) \
  664. JMP8_EMIT(cond, cond_ptr); \
  665. }
  666. #define EMITH_JMP3_START(cond) { \
  667. u8 *cond_ptr, *else_ptr; \
  668. JMP8_POS(cond_ptr)
  669. #define EMITH_JMP3_MID(cond) \
  670. JMP8_POS(else_ptr); \
  671. JMP8_EMIT(cond, cond_ptr);
  672. #define EMITH_JMP3_END() \
  673. JMP8_EMIT_NC(else_ptr); \
  674. }
  675. // "simple" jump (no more then a few insns)
  676. // ARM will use conditional instructions here
  677. #define EMITH_SJMP_DECL_() \
  678. u8 *cond_ptr
  679. #define EMITH_SJMP_START_(cond) \
  680. JMP8_POS(cond_ptr)
  681. #define EMITH_SJMP_END_(cond) \
  682. JMP8_EMIT(cond, cond_ptr)
  683. #define EMITH_SJMP_START EMITH_JMP_START
  684. #define EMITH_SJMP_END EMITH_JMP_END
  685. #define EMITH_SJMP3_START EMITH_JMP3_START
  686. #define EMITH_SJMP3_MID EMITH_JMP3_MID
  687. #define EMITH_SJMP3_END EMITH_JMP3_END
  688. #define EMITH_SJMP2_START(cond) \
  689. EMITH_SJMP3_START(cond)
  690. #define EMITH_SJMP2_MID(cond) \
  691. EMITH_SJMP3_MID(cond)
  692. #define EMITH_SJMP2_END(cond) \
  693. EMITH_SJMP3_END()
  694. #define emith_pass_arg_r(arg, reg) do { \
  695. int rd = 7; \
  696. host_arg2reg(rd, arg); \
  697. emith_move_r_r_ptr(rd, reg); \
  698. } while (0)
  699. #define emith_pass_arg_imm(arg, imm) do { \
  700. int rd = 7; \
  701. host_arg2reg(rd, arg); \
  702. emith_move_r_imm(rd, imm); \
  703. } while (0)
  704. #define host_instructions_updated(base, end)
  705. #ifdef __x86_64__
  706. #define PTR_SCALE 3
  707. #define NA_TMP_REG xAX // non-arg tmp from reg_temp[]
  708. #define EMIT_REX_IF(w, r, rm) do { \
  709. int r_ = (r) > 7 ? 1 : 0; \
  710. int rm_ = (rm) > 7 ? 1 : 0; \
  711. if ((w) | r_ | rm_) \
  712. EMIT_REX(1, r_, 0, rm_); \
  713. } while (0)
  714. #ifndef _WIN32
  715. #define host_arg2reg(rd, arg) \
  716. switch (arg) { \
  717. case 0: rd = xDI; break; \
  718. case 1: rd = xSI; break; \
  719. case 2: rd = xDX; break; \
  720. default: rd = xCX; break; \
  721. }
  722. #define emith_sh2_drc_entry() { \
  723. emith_push(xBX); \
  724. emith_push(xBP); \
  725. emith_push(xSI); /* to align */ \
  726. }
  727. #define emith_sh2_drc_exit() { \
  728. emith_pop(xSI); \
  729. emith_pop(xBP); \
  730. emith_pop(xBX); \
  731. emith_ret(); \
  732. }
  733. #else // _WIN32
  734. #define host_arg2reg(rd, arg) \
  735. switch (arg) { \
  736. case 0: rd = xCX; break; \
  737. case 1: rd = xDX; break; \
  738. case 2: rd = 8; break; \
  739. default: rd = 9; break; \
  740. }
  741. #define emith_sh2_drc_entry() { \
  742. emith_push(xBX); \
  743. emith_push(xBP); \
  744. emith_push(xSI); \
  745. emith_push(xDI); \
  746. emith_add_r_r_ptr_imm(xSP, xSP, -8*5); \
  747. }
  748. #define emith_sh2_drc_exit() { \
  749. emith_add_r_r_ptr_imm(xSP, xSP, 8*5); \
  750. emith_pop(xDI); \
  751. emith_pop(xSI); \
  752. emith_pop(xBP); \
  753. emith_pop(xBX); \
  754. emith_ret(); \
  755. }
  756. #endif // _WIN32
  757. #else // !__x86_64__
  758. #define PTR_SCALE 2
  759. #define NA_TMP_REG xBX // non-arg tmp from reg_temp[]
  760. #define EMIT_REX_IF(w, r, rm) do { \
  761. assert((u32)(r) < 8u); \
  762. assert((u32)(rm) < 8u); \
  763. } while (0)
  764. #define host_arg2reg(rd, arg) \
  765. switch (arg) { \
  766. case 0: rd = xAX; break; \
  767. case 1: rd = xDX; break; \
  768. case 2: rd = xCX; break; \
  769. default: rd = xBX; break; \
  770. }
  771. #define emith_sh2_drc_entry() { \
  772. emith_push(xBX); \
  773. emith_push(xBP); \
  774. emith_push(xSI); \
  775. emith_push(xDI); \
  776. }
  777. #define emith_sh2_drc_exit() { \
  778. emith_pop(xDI); \
  779. emith_pop(xSI); \
  780. emith_pop(xBP); \
  781. emith_pop(xBX); \
  782. emith_ret(); \
  783. }
  784. #endif
  785. #define emith_save_caller_regs(mask) do { \
  786. if ((mask) & (1 << xAX)) emith_push(xAX); \
  787. if ((mask) & (1 << xCX)) emith_push(xCX); \
  788. if ((mask) & (1 << xDX)) emith_push(xDX); \
  789. if ((mask) & (1 << xSI)) emith_push(xSI); \
  790. if ((mask) & (1 << xDI)) emith_push(xDI); \
  791. } while (0)
  792. #define emith_restore_caller_regs(mask) do { \
  793. if ((mask) & (1 << xDI)) emith_pop(xDI); \
  794. if ((mask) & (1 << xSI)) emith_pop(xSI); \
  795. if ((mask) & (1 << xDX)) emith_pop(xDX); \
  796. if ((mask) & (1 << xCX)) emith_pop(xCX); \
  797. if ((mask) & (1 << xAX)) emith_pop(xAX); \
  798. } while (0)
  799. #define emith_sh2_rcall(a, tab, func, mask) { \
  800. emith_lsr(mask, a, SH2_READ_SHIFT); \
  801. EMIT_REX_IF(1, mask, tab); \
  802. EMIT_OP_MODRM64(0x8d, 0, tab, 4); \
  803. EMIT_SIB64(PTR_SCALE, mask, tab); /* lea tab, [tab + mask * {4,8}] */ \
  804. EMIT_REX_IF(1, mask, tab); \
  805. EMIT_OP_MODRM64(0x8d, 0, tab, 4); \
  806. EMIT_SIB64(PTR_SCALE, mask, tab); /* lea tab, [tab + mask * {4,8}] */ \
  807. EMIT_REX_IF(1, func, tab); \
  808. EMIT_OP_MODRM64(0x8b, 0, func, tab); /* mov func, [tab] */ \
  809. EMIT_OP_MODRM64(0x8b, 1, mask, tab); \
  810. EMIT(1 << PTR_SCALE, u8); /* mov mask, [tab + {4,8}] */ \
  811. emith_add_r_r_ptr(func, func); \
  812. }
  813. #define emith_sh2_wcall(a, val, tab, func) { \
  814. int arg2_; \
  815. host_arg2reg(arg2_, 2); \
  816. emith_lsr(func, a, SH2_WRITE_SHIFT); /* tmp = a >> WRT_SHIFT */ \
  817. EMIT_REX_IF(1, func, tab); \
  818. EMIT_OP_MODRM64(0x8b, 0, func, 4); \
  819. EMIT_SIB64(PTR_SCALE, func, tab); /* mov tmp, [tab + tmp * {4,8}] */ \
  820. emith_move_r_r_ptr(arg2_, CONTEXT_REG); \
  821. emith_jump_reg(func); \
  822. }
  823. #define emith_sh2_dtbf_loop() { \
  824. u8 *jmp0; /* negative cycles check */ \
  825. u8 *jmp1; /* unsinged overflow check */ \
  826. int cr, rn; \
  827. int tmp_ = rcache_get_tmp(); \
  828. cr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
  829. rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW);\
  830. emith_sub_r_imm(rn, 1); \
  831. emith_sub_r_imm(cr, (cycles+1) << 12); \
  832. cycles = 0; \
  833. emith_asr(tmp_, cr, 2+12); \
  834. JMP8_POS(jmp0); /* no negative cycles */ \
  835. emith_move_r_imm(tmp_, 0); \
  836. JMP8_EMIT(ICOND_JNS, jmp0); \
  837. emith_and_r_imm(cr, 0xffe); \
  838. emith_subf_r_r(rn, tmp_); \
  839. JMP8_POS(jmp1); /* no overflow */ \
  840. emith_neg_r(rn); /* count left */ \
  841. emith_lsl(rn, rn, 2+12); \
  842. emith_or_r_r(cr, rn); \
  843. emith_or_r_imm(cr, 1); \
  844. emith_move_r_imm(rn, 0); \
  845. JMP8_EMIT(ICOND_JA, jmp1); \
  846. rcache_free_tmp(tmp_); \
  847. }
  848. #define emith_write_sr(sr, srcr) { \
  849. int tmp_ = rcache_get_tmp(); \
  850. emith_clear_msb(tmp_, srcr, 22); \
  851. emith_bic_r_imm(sr, 0x3ff); \
  852. emith_or_r_r(sr, tmp_); \
  853. rcache_free_tmp(tmp_); \
  854. }
  855. #define emith_tpop_carry(sr, is_sub) \
  856. emith_lsr(sr, sr, 1)
  857. #define emith_tpush_carry(sr, is_sub) \
  858. emith_adc_r_r(sr, sr)
  859. /*
  860. * if Q
  861. * t = carry(Rn += Rm)
  862. * else
  863. * t = carry(Rn -= Rm)
  864. * T ^= t
  865. */
  866. #define emith_sh2_div1_step(rn, rm, sr) { \
  867. u8 *jmp0, *jmp1; \
  868. int tmp_ = rcache_get_tmp(); \
  869. emith_eor_r_r(tmp_, tmp_); \
  870. emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
  871. JMP8_POS(jmp0); /* je do_sub */ \
  872. emith_add_r_r(rn, rm); \
  873. JMP8_POS(jmp1); /* jmp done */ \
  874. JMP8_EMIT(ICOND_JE, jmp0); /* do_sub: */ \
  875. emith_sub_r_r(rn, rm); \
  876. JMP8_EMIT_NC(jmp1); /* done: */ \
  877. emith_adc_r_r(tmp_, tmp_); \
  878. emith_eor_r_r(sr, tmp_); \
  879. rcache_free_tmp(tmp_); \
  880. }
  881. /* mh:ml += rn*rm, does saturation if required by S bit. rn, rm must be TEMP */
  882. #define emith_sh2_macl(ml, mh, rn, rm, sr) do { \
  883. emith_tst_r_imm(sr, S); \
  884. EMITH_SJMP_START(DCOND_EQ); \
  885. /* MACH top 16 bits unused if saturated. sign ext for overfl detect */ \
  886. emith_sext(mh, mh, 16); \
  887. EMITH_SJMP_END(DCOND_EQ); \
  888. emith_mula_s64(ml, mh, rn, rm); \
  889. emith_tst_r_imm(sr, S); \
  890. EMITH_SJMP_START(DCOND_EQ); \
  891. /* overflow if top 17 bits of MACH aren't all 1 or 0 */ \
  892. /* to check: add MACH[15] to MACH[31:16]. this is 0 if no overflow */ \
  893. emith_asrf(rn, mh, 16); /* sum = (MACH>>16) + ((MACH>>15)&1) */ \
  894. emith_adcf_r_imm(rn, 0); /* (MACH>>15) is in carry after shift */ \
  895. EMITH_SJMP_START(DCOND_EQ); /* sum != 0 -> ov */ \
  896. emith_move_r_imm_c(DCOND_NE, ml, 0x0000); /* -overflow */ \
  897. emith_move_r_imm_c(DCOND_NE, mh, 0x8000); \
  898. EMITH_SJMP_START(DCOND_LE); /* sum > 0 -> +ovl */ \
  899. emith_sub_r_imm_c(DCOND_GT, ml, 1); /* 0xffffffff */ \
  900. emith_sub_r_imm_c(DCOND_GT, mh, 1); /* 0x00007fff */ \
  901. EMITH_SJMP_END(DCOND_LE); \
  902. EMITH_SJMP_END(DCOND_EQ); \
  903. EMITH_SJMP_END(DCOND_EQ); \
  904. } while (0)
  905. /* mh:ml += rn*rm, does saturation if required by S bit. rn, rm must be TEMP */
  906. #define emith_sh2_macw(ml, mh, rn, rm, sr) do { \
  907. emith_sext(rn, rn, 16); \
  908. emith_sext(rm, rm, 16); \
  909. emith_tst_r_imm(sr, S); \
  910. EMITH_SJMP_START(DCOND_EQ); \
  911. /* XXX: MACH should be untouched when S is set? */ \
  912. emith_asr(mh, ml, 31); /* sign ext MACL to MACH for ovrfl check */ \
  913. EMITH_SJMP_END(DCOND_EQ); \
  914. emith_mula_s64(ml, mh, rn, rm); \
  915. emith_tst_r_imm(sr, S); \
  916. EMITH_SJMP_START(DCOND_EQ); \
  917. /* overflow if top 33 bits of MACH:MACL aren't all 1 or 0 */ \
  918. /* to check: add MACL[31] to MACH. this is 0 if no overflow */ \
  919. emith_lsr(rn, ml, 31); \
  920. emith_addf_r_r(rn, mh); /* sum = MACH + ((MACL>>31)&1) */ \
  921. EMITH_SJMP_START(DCOND_EQ); /* sum != 0 -> overflow */ \
  922. /* XXX: LSB signalling only in SH1, or in SH2 too? */ \
  923. emith_move_r_imm_c(DCOND_NE, mh, 0x00000001); /* LSB of MACH */ \
  924. emith_move_r_imm_c(DCOND_NE, ml, 0x80000000); /* negative ovrfl */ \
  925. EMITH_SJMP_START(DCOND_LE); /* sum > 0 -> positive ovrfl */ \
  926. emith_sub_r_imm_c(DCOND_GT, ml, 1); /* 0x7fffffff */ \
  927. EMITH_SJMP_END(DCOND_LE); \
  928. EMITH_SJMP_END(DCOND_EQ); \
  929. EMITH_SJMP_END(DCOND_EQ); \
  930. } while (0)