emit_arm.c 35 KB

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  1. /*
  2. * Basic macros to emit ARM instructions and some utils
  3. * Copyright (C) 2008,2009,2010 notaz
  4. *
  5. * This work is licensed under the terms of MAME license.
  6. * See COPYING file in the top-level directory.
  7. */
  8. #define HOST_REGS 16
  9. #define CONTEXT_REG 11
  10. #define RET_REG 0
  11. // XXX: tcache_ptr type for SVP and SH2 compilers differs..
  12. #define EMIT_PTR(ptr, x) \
  13. do { \
  14. *(u32 *)ptr = x; \
  15. ptr = (void *)((u8 *)ptr + sizeof(u32)); \
  16. COUNT_OP; \
  17. } while (0)
  18. #define EMIT(x) EMIT_PTR(tcache_ptr, x)
  19. #define A_R4M (1 << 4)
  20. #define A_R5M (1 << 5)
  21. #define A_R6M (1 << 6)
  22. #define A_R7M (1 << 7)
  23. #define A_R8M (1 << 8)
  24. #define A_R9M (1 << 9)
  25. #define A_R10M (1 << 10)
  26. #define A_R11M (1 << 11)
  27. #define A_R12M (1 << 12)
  28. #define A_R14M (1 << 14)
  29. #define A_R15M (1 << 15)
  30. #define A_COND_AL 0xe
  31. #define A_COND_EQ 0x0
  32. #define A_COND_NE 0x1
  33. #define A_COND_HS 0x2
  34. #define A_COND_LO 0x3
  35. #define A_COND_MI 0x4
  36. #define A_COND_PL 0x5
  37. #define A_COND_VS 0x6
  38. #define A_COND_VC 0x7
  39. #define A_COND_HI 0x8
  40. #define A_COND_LS 0x9
  41. #define A_COND_GE 0xa
  42. #define A_COND_LT 0xb
  43. #define A_COND_GT 0xc
  44. #define A_COND_LE 0xd
  45. #define A_COND_CS A_COND_HS
  46. #define A_COND_CC A_COND_LO
  47. /* unified conditions */
  48. #define DCOND_EQ A_COND_EQ
  49. #define DCOND_NE A_COND_NE
  50. #define DCOND_MI A_COND_MI
  51. #define DCOND_PL A_COND_PL
  52. #define DCOND_HI A_COND_HI
  53. #define DCOND_HS A_COND_HS
  54. #define DCOND_LO A_COND_LO
  55. #define DCOND_GE A_COND_GE
  56. #define DCOND_GT A_COND_GT
  57. #define DCOND_LT A_COND_LT
  58. #define DCOND_LS A_COND_LS
  59. #define DCOND_LE A_COND_LE
  60. #define DCOND_VS A_COND_VS
  61. #define DCOND_VC A_COND_VC
  62. #define DCOND_CS A_COND_HS
  63. #define DCOND_CC A_COND_LO
  64. /* addressing mode 1 */
  65. #define A_AM1_LSL 0
  66. #define A_AM1_LSR 1
  67. #define A_AM1_ASR 2
  68. #define A_AM1_ROR 3
  69. #define A_AM1_IMM(ror2,imm8) (((ror2)<<8) | (imm8) | 0x02000000)
  70. #define A_AM1_REG_XIMM(shift_imm,shift_op,rm) (((shift_imm)<<7) | ((shift_op)<<5) | (rm))
  71. #define A_AM1_REG_XREG(rs,shift_op,rm) (((rs)<<8) | ((shift_op)<<5) | 0x10 | (rm))
  72. /* data processing op */
  73. #define A_OP_AND 0x0
  74. #define A_OP_EOR 0x1
  75. #define A_OP_SUB 0x2
  76. #define A_OP_RSB 0x3
  77. #define A_OP_ADD 0x4
  78. #define A_OP_ADC 0x5
  79. #define A_OP_SBC 0x6
  80. #define A_OP_RSC 0x7
  81. #define A_OP_TST 0x8
  82. #define A_OP_TEQ 0x9
  83. #define A_OP_CMP 0xa
  84. #define A_OP_CMN 0xb
  85. #define A_OP_ORR 0xc
  86. #define A_OP_MOV 0xd
  87. #define A_OP_BIC 0xe
  88. #define A_OP_MVN 0xf
  89. #define EOP_C_DOP_X(cond,op,s,rn,rd,shifter_op) \
  90. EMIT(((cond)<<28) | ((op)<< 21) | ((s)<<20) | ((rn)<<16) | ((rd)<<12) | (shifter_op))
  91. #define EOP_C_DOP_IMM( cond,op,s,rn,rd,ror2,imm8) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_IMM(ror2,imm8))
  92. #define EOP_C_DOP_REG_XIMM(cond,op,s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XIMM(shift_imm,shift_op,rm))
  93. #define EOP_C_DOP_REG_XREG(cond,op,s,rn,rd,rs, shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XREG(rs, shift_op,rm))
  94. #define EOP_MOV_IMM(rd, ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,0, 0,rd,ror2,imm8)
  95. #define EOP_MVN_IMM(rd, ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_MVN,0, 0,rd,ror2,imm8)
  96. #define EOP_ORR_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ORR,0,rn,rd,ror2,imm8)
  97. #define EOP_EOR_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_EOR,0,rn,rd,ror2,imm8)
  98. #define EOP_ADD_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ADD,0,rn,rd,ror2,imm8)
  99. #define EOP_BIC_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_BIC,0,rn,rd,ror2,imm8)
  100. #define EOP_AND_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,0,rn,rd,ror2,imm8)
  101. #define EOP_SUB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_SUB,0,rn,rd,ror2,imm8)
  102. #define EOP_TST_IMM( rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_TST,1,rn, 0,ror2,imm8)
  103. #define EOP_CMP_IMM( rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_CMP,1,rn, 0,ror2,imm8)
  104. #define EOP_RSB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_RSB,0,rn,rd,ror2,imm8)
  105. #define EOP_MOV_IMM_C(cond,rd, ror2,imm8) EOP_C_DOP_IMM(cond,A_OP_MOV,0, 0,rd,ror2,imm8)
  106. #define EOP_ORR_IMM_C(cond,rd,rn,ror2,imm8) EOP_C_DOP_IMM(cond,A_OP_ORR,0,rn,rd,ror2,imm8)
  107. #define EOP_RSB_IMM_C(cond,rd,rn,ror2,imm8) EOP_C_DOP_IMM(cond,A_OP_RSB,0,rn,rd,ror2,imm8)
  108. #define EOP_MOV_REG(cond,s,rd, rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_MOV,s, 0,rd,shift_imm,shift_op,rm)
  109. #define EOP_MVN_REG(cond,s,rd, rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_MVN,s, 0,rd,shift_imm,shift_op,rm)
  110. #define EOP_ORR_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_ORR,s,rn,rd,shift_imm,shift_op,rm)
  111. #define EOP_ADD_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_ADD,s,rn,rd,shift_imm,shift_op,rm)
  112. #define EOP_ADC_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_ADC,s,rn,rd,shift_imm,shift_op,rm)
  113. #define EOP_SUB_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_SUB,s,rn,rd,shift_imm,shift_op,rm)
  114. #define EOP_SBC_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_SBC,s,rn,rd,shift_imm,shift_op,rm)
  115. #define EOP_AND_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_AND,s,rn,rd,shift_imm,shift_op,rm)
  116. #define EOP_EOR_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_EOR,s,rn,rd,shift_imm,shift_op,rm)
  117. #define EOP_CMP_REG(cond, rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_CMP,1,rn, 0,shift_imm,shift_op,rm)
  118. #define EOP_TST_REG(cond, rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_TST,1,rn, 0,shift_imm,shift_op,rm)
  119. #define EOP_TEQ_REG(cond, rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_TEQ,1,rn, 0,shift_imm,shift_op,rm)
  120. #define EOP_MOV_REG2(s,rd, rm,shift_op,rs) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_MOV,s, 0,rd,rs,shift_op,rm)
  121. #define EOP_ADD_REG2(s,rd,rn,rm,shift_op,rs) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_ADD,s,rn,rd,rs,shift_op,rm)
  122. #define EOP_SUB_REG2(s,rd,rn,rm,shift_op,rs) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_SUB,s,rn,rd,rs,shift_op,rm)
  123. #define EOP_MOV_REG_SIMPLE(rd,rm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_LSL,0)
  124. #define EOP_MOV_REG_LSL(rd, rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_LSL,shift_imm)
  125. #define EOP_MOV_REG_LSR(rd, rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_LSR,shift_imm)
  126. #define EOP_MOV_REG_ASR(rd, rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_ASR,shift_imm)
  127. #define EOP_MOV_REG_ROR(rd, rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_ROR,shift_imm)
  128. #define EOP_ORR_REG_SIMPLE(rd,rm) EOP_ORR_REG(A_COND_AL,0,rd,rd,rm,A_AM1_LSL,0)
  129. #define EOP_ORR_REG_LSL(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSL,shift_imm)
  130. #define EOP_ORR_REG_LSR(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSR,shift_imm)
  131. #define EOP_ORR_REG_ASR(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_ASR,shift_imm)
  132. #define EOP_ORR_REG_ROR(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_ROR,shift_imm)
  133. #define EOP_ADD_REG_SIMPLE(rd,rm) EOP_ADD_REG(A_COND_AL,0,rd,rd,rm,A_AM1_LSL,0)
  134. #define EOP_ADD_REG_LSL(rd,rn,rm,shift_imm) EOP_ADD_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSL,shift_imm)
  135. #define EOP_ADD_REG_LSR(rd,rn,rm,shift_imm) EOP_ADD_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSR,shift_imm)
  136. #define EOP_TST_REG_SIMPLE(rn,rm) EOP_TST_REG(A_COND_AL, rn, 0,A_AM1_LSL,rm)
  137. #define EOP_MOV_REG2_LSL(rd, rm,rs) EOP_MOV_REG2(0,rd, rm,A_AM1_LSL,rs)
  138. #define EOP_MOV_REG2_ROR(rd, rm,rs) EOP_MOV_REG2(0,rd, rm,A_AM1_ROR,rs)
  139. #define EOP_ADD_REG2_LSL(rd,rn,rm,rs) EOP_ADD_REG2(0,rd,rn,rm,A_AM1_LSL,rs)
  140. #define EOP_SUB_REG2_LSL(rd,rn,rm,rs) EOP_SUB_REG2(0,rd,rn,rm,A_AM1_LSL,rs)
  141. /* addressing mode 2 */
  142. #define EOP_C_AM2_IMM(cond,u,b,l,rn,rd,offset_12) \
  143. EMIT(((cond)<<28) | 0x05000000 | ((u)<<23) | ((b)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | (offset_12))
  144. #define EOP_C_AM2_REG(cond,u,b,l,rn,rd,shift_imm,shift_op,rm) \
  145. EMIT(((cond)<<28) | 0x07000000 | ((u)<<23) | ((b)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | \
  146. ((shift_imm)<<7) | ((shift_op)<<5) | (rm))
  147. /* addressing mode 3 */
  148. #define EOP_C_AM3(cond,u,r,l,rn,rd,s,h,immed_reg) \
  149. EMIT(((cond)<<28) | 0x01000090 | ((u)<<23) | ((r)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | \
  150. ((s)<<6) | ((h)<<5) | (immed_reg))
  151. #define EOP_C_AM3_IMM(cond,u,l,rn,rd,s,h,offset_8) EOP_C_AM3(cond,u,1,l,rn,rd,s,h,(((offset_8)&0xf0)<<4)|((offset_8)&0xf))
  152. #define EOP_C_AM3_REG(cond,u,l,rn,rd,s,h,rm) EOP_C_AM3(cond,u,0,l,rn,rd,s,h,rm)
  153. /* ldr and str */
  154. #define EOP_LDR_IMM2(cond,rd,rn,offset_12) EOP_C_AM2_IMM(cond,(offset_12) >= 0,0,1,rn,rd,abs(offset_12))
  155. #define EOP_LDRB_IMM2(cond,rd,rn,offset_12) EOP_C_AM2_IMM(cond,(offset_12) >= 0,1,1,rn,rd,abs(offset_12))
  156. #define EOP_STR_IMM2(cond,rd,rn,offset_12) EOP_C_AM2_IMM(cond,(offset_12) >= 0,0,0,rn,rd,abs(offset_12))
  157. #define EOP_LDR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,(offset_12) >= 0,0,1,rn,rd,abs(offset_12))
  158. #define EOP_LDR_SIMPLE(rd,rn) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,0)
  159. #define EOP_STR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,(offset_12) >= 0,0,0,rn,rd,abs(offset_12))
  160. #define EOP_STR_SIMPLE(rd,rn) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,0)
  161. #define EOP_LDR_REG_LSL(cond,rd,rn,rm,shift_imm) EOP_C_AM2_REG(cond,1,0,1,rn,rd,shift_imm,A_AM1_LSL,rm)
  162. #define EOP_LDRB_REG_LSL(cond,rd,rn,rm,shift_imm) EOP_C_AM2_REG(cond,1,1,1,rn,rd,shift_imm,A_AM1_LSL,rm);
  163. #define EOP_LDRH_IMM2(cond,rd,rn,offset_8) EOP_C_AM3_IMM(cond,(offset_8) >= 0,1,rn,rd,0,1,abs(offset_8))
  164. #define EOP_LDRH_REG2(cond,rd,rn,rm) EOP_C_AM3_REG(cond,1,1,rn,rd,0,1,rm)
  165. #define EOP_LDRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,(offset_8) >= 0,1,rn,rd,0,1,abs(offset_8))
  166. #define EOP_LDRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,0)
  167. #define EOP_LDRH_REG( rd,rn,rm) EOP_C_AM3_REG(A_COND_AL,1,1,rn,rd,0,1,rm)
  168. #define EOP_STRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,(offset_8) >= 0,0,rn,rd,0,1,abs(offset_8))
  169. #define EOP_STRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,0)
  170. #define EOP_STRH_REG( rd,rn,rm) EOP_C_AM3_REG(A_COND_AL,1,0,rn,rd,0,1,rm)
  171. #define EOP_LDRSB_IMM2(cond,rd,rn,offset_8) EOP_C_AM3_IMM(cond,(offset_8) >= 0,1,rn,rd,1,0,abs(offset_8))
  172. #define EOP_LDRSB_REG2(cond,rd,rn,rm) EOP_C_AM3_REG(cond,1,1,rn,rd,1,0,rm)
  173. #define EOP_LDRSH_IMM2(cond,rd,rn,offset_8) EOP_C_AM3_IMM(cond,(offset_8) >= 0,1,rn,rd,1,1,abs(offset_8))
  174. #define EOP_LDRSH_REG2(cond,rd,rn,rm) EOP_C_AM3_REG(cond,1,1,rn,rd,1,1,rm)
  175. /* ldm and stm */
  176. #define EOP_XXM(cond,p,u,s,w,l,rn,list) \
  177. EMIT(((cond)<<28) | (1<<27) | ((p)<<24) | ((u)<<23) | ((s)<<22) | ((w)<<21) | ((l)<<20) | ((rn)<<16) | (list))
  178. #define EOP_STMIA(rb,list) EOP_XXM(A_COND_AL,0,1,0,0,0,rb,list)
  179. #define EOP_LDMIA(rb,list) EOP_XXM(A_COND_AL,0,1,0,0,1,rb,list)
  180. #define EOP_STMFD_SP(list) EOP_XXM(A_COND_AL,1,0,0,1,0,13,list)
  181. #define EOP_LDMFD_SP(list) EOP_XXM(A_COND_AL,0,1,0,1,1,13,list)
  182. /* branches */
  183. #define EOP_C_BX(cond,rm) \
  184. EMIT(((cond)<<28) | 0x012fff10 | (rm))
  185. #define EOP_C_B_PTR(ptr,cond,l,signed_immed_24) \
  186. EMIT_PTR(ptr, ((cond)<<28) | 0x0a000000 | ((l)<<24) | (signed_immed_24))
  187. #define EOP_C_B(cond,l,signed_immed_24) \
  188. EOP_C_B_PTR(tcache_ptr,cond,l,signed_immed_24)
  189. #define EOP_B( signed_immed_24) EOP_C_B(A_COND_AL,0,signed_immed_24)
  190. #define EOP_BL(signed_immed_24) EOP_C_B(A_COND_AL,1,signed_immed_24)
  191. /* misc */
  192. #define EOP_C_MUL(cond,s,rd,rs,rm) \
  193. EMIT(((cond)<<28) | ((s)<<20) | ((rd)<<16) | ((rs)<<8) | 0x90 | (rm))
  194. #define EOP_C_UMULL(cond,s,rdhi,rdlo,rs,rm) \
  195. EMIT(((cond)<<28) | 0x00800000 | ((s)<<20) | ((rdhi)<<16) | ((rdlo)<<12) | ((rs)<<8) | 0x90 | (rm))
  196. #define EOP_C_SMULL(cond,s,rdhi,rdlo,rs,rm) \
  197. EMIT(((cond)<<28) | 0x00c00000 | ((s)<<20) | ((rdhi)<<16) | ((rdlo)<<12) | ((rs)<<8) | 0x90 | (rm))
  198. #define EOP_C_SMLAL(cond,s,rdhi,rdlo,rs,rm) \
  199. EMIT(((cond)<<28) | 0x00e00000 | ((s)<<20) | ((rdhi)<<16) | ((rdlo)<<12) | ((rs)<<8) | 0x90 | (rm))
  200. #define EOP_MUL(rd,rm,rs) EOP_C_MUL(A_COND_AL,0,rd,rs,rm) // note: rd != rm
  201. #define EOP_C_MRS(cond,rd) \
  202. EMIT(((cond)<<28) | 0x010f0000 | ((rd)<<12))
  203. #define EOP_C_MSR_IMM(cond,ror2,imm) \
  204. EMIT(((cond)<<28) | 0x0328f000 | ((ror2)<<8) | (imm)) // cpsr_f
  205. #define EOP_C_MSR_REG(cond,rm) \
  206. EMIT(((cond)<<28) | 0x0128f000 | (rm)) // cpsr_f
  207. #define EOP_MRS(rd) EOP_C_MRS(A_COND_AL,rd)
  208. #define EOP_MSR_IMM(ror2,imm) EOP_C_MSR_IMM(A_COND_AL,ror2,imm)
  209. #define EOP_MSR_REG(rm) EOP_C_MSR_REG(A_COND_AL,rm)
  210. #define EOP_MOVW(rd,imm) \
  211. EMIT(0xe3000000 | ((rd)<<12) | ((imm)&0xfff) | (((imm)<<4)&0xf0000))
  212. #define EOP_MOVT(rd,imm) \
  213. EMIT(0xe3400000 | ((rd)<<12) | (((imm)>>16)&0xfff) | (((imm)>>12)&0xf0000))
  214. static int count_bits(unsigned val)
  215. {
  216. val = (val & 0x55555555) + ((val >> 1) & 0x55555555);
  217. val = (val & 0x33333333) + ((val >> 2) & 0x33333333);
  218. val = (val & 0x0f0f0f0f) + ((val >> 4) & 0x0f0f0f0f);
  219. val = (val & 0x00ff00ff) + ((val >> 8) & 0x00ff00ff);
  220. return (val & 0xffff) + (val >> 16);
  221. }
  222. // XXX: RSB, *S will break if 1 insn is not enough
  223. static void emith_op_imm2(int cond, int s, int op, int rd, int rn, unsigned int imm)
  224. {
  225. int ror2;
  226. u32 v;
  227. switch (op) {
  228. case A_OP_MOV:
  229. rn = 0;
  230. // count bits in imm and use MVN if more bits 1 than 0
  231. if (count_bits(imm) > 16) {
  232. imm = ~imm;
  233. op = A_OP_MVN;
  234. }
  235. #ifdef HAVE_ARMV7
  236. for (v = imm, ror2 = 0; v && !(v & 3); v >>= 2)
  237. ror2--;
  238. if (v >> 8) {
  239. /* 2+ insns needed - prefer movw/movt */
  240. if (op == A_OP_MVN)
  241. imm = ~imm;
  242. EOP_MOVW(rd, imm);
  243. if (imm & 0xffff0000)
  244. EOP_MOVT(rd, imm);
  245. return;
  246. }
  247. #endif
  248. break;
  249. case A_OP_SUB:
  250. case A_OP_ADD:
  251. // count bits in imm and swap ADD and SUB if more bits 1 than 0
  252. if (s == 0 && count_bits(imm) > 16) {
  253. imm = -imm;
  254. op ^= (A_OP_ADD^A_OP_SUB);
  255. }
  256. case A_OP_EOR:
  257. case A_OP_ORR:
  258. case A_OP_BIC:
  259. if (s == 0 && imm == 0 && rd == rn)
  260. return;
  261. break;
  262. }
  263. again:
  264. v = imm, ror2 = 32/2; // arm imm shift is ROR, so rotate for best fit
  265. while ((v >> 24) && !(v & 0xc0))
  266. v = (v << 2) | (v >> 30), ror2++;
  267. do {
  268. // shift down to get 'best' rot2
  269. while (v > 0xff && !(v & 3))
  270. v >>= 2, ror2--;
  271. // AND must fit into 1 insn. if not, use BIC
  272. if (op == A_OP_AND && v != (v & 0xff)) {
  273. imm = ~imm;
  274. op = A_OP_BIC;
  275. goto again;
  276. }
  277. EOP_C_DOP_IMM(cond, op, s, rn, rd, ror2 & 0xf, v & 0xff);
  278. switch (op) {
  279. case A_OP_MOV: op = A_OP_ORR; break;
  280. case A_OP_MVN: op = A_OP_BIC; break;
  281. case A_OP_ADC: op = A_OP_ADD; break;
  282. case A_OP_SBC: op = A_OP_SUB; break;
  283. }
  284. rn = rd;
  285. v >>= 8, ror2 -= 8/2;
  286. } while (v);
  287. }
  288. #define emith_op_imm(cond, s, op, r, imm) \
  289. emith_op_imm2(cond, s, op, r, r, imm)
  290. // test op
  291. #define emith_top_imm(cond, op, r, imm) do { \
  292. u32 ror2, v; \
  293. for (ror2 = 0, v = imm; v && !(v & 3); v >>= 2) \
  294. ror2--; \
  295. EOP_C_DOP_IMM(cond, op, 1, r, 0, ror2 & 0x0f, v & 0xff); \
  296. } while (0)
  297. #define is_offset_24(val) \
  298. ((val) >= (int)0xff000000 && (val) <= 0x00ffffff)
  299. static int emith_xbranch(int cond, void *target, int is_call)
  300. {
  301. int val = (u32 *)target - (u32 *)tcache_ptr - 2;
  302. int direct = is_offset_24(val);
  303. u32 *start_ptr = (u32 *)tcache_ptr;
  304. if (direct)
  305. {
  306. EOP_C_B(cond,is_call,val & 0xffffff); // b, bl target
  307. }
  308. else
  309. {
  310. #ifdef __EPOC32__
  311. // elprintf(EL_SVP, "emitting indirect jmp %08x->%08x", tcache_ptr, target);
  312. if (is_call)
  313. EOP_ADD_IMM(14,15,0,8); // add lr,pc,#8
  314. EOP_C_AM2_IMM(cond,1,0,1,15,15,0); // ldrcc pc,[pc]
  315. EOP_MOV_REG_SIMPLE(15,15); // mov pc, pc
  316. EMIT((u32)target);
  317. #else
  318. // should never happen
  319. elprintf(EL_STATUS|EL_SVP|EL_ANOMALY, "indirect jmp %08x->%08x", target, tcache_ptr);
  320. exit(1);
  321. #endif
  322. }
  323. return (u32 *)tcache_ptr - start_ptr;
  324. }
  325. #define JMP_POS(ptr) \
  326. ptr = tcache_ptr; \
  327. tcache_ptr += sizeof(u32)
  328. #define JMP_EMIT(cond, ptr) { \
  329. u32 val_ = (u32 *)tcache_ptr - (u32 *)(ptr) - 2; \
  330. EOP_C_B_PTR(ptr, cond, 0, val_ & 0xffffff); \
  331. }
  332. #define EMITH_JMP_START(cond) { \
  333. void *cond_ptr; \
  334. JMP_POS(cond_ptr)
  335. #define EMITH_JMP_END(cond) \
  336. JMP_EMIT(cond, cond_ptr); \
  337. }
  338. // fake "simple" or "short" jump - using cond insns instead
  339. #define EMITH_NOTHING1(cond) \
  340. (void)(cond)
  341. #define EMITH_SJMP_DECL_()
  342. #define EMITH_SJMP_START_(cond) EMITH_NOTHING1(cond)
  343. #define EMITH_SJMP_END_(cond) EMITH_NOTHING1(cond)
  344. #define EMITH_SJMP_START(cond) EMITH_NOTHING1(cond)
  345. #define EMITH_SJMP_END(cond) EMITH_NOTHING1(cond)
  346. #define EMITH_SJMP2_START(cond) EMITH_NOTHING1(cond)
  347. #define EMITH_SJMP2_MID(cond) EMITH_JMP_START((cond)^1) // inverse cond
  348. #define EMITH_SJMP2_END(cond) EMITH_JMP_END((cond)^1)
  349. #define EMITH_SJMP3_START(cond) EMITH_NOTHING1(cond)
  350. #define EMITH_SJMP3_MID(cond) EMITH_NOTHING1(cond)
  351. #define EMITH_SJMP3_END()
  352. #define emith_move_r_r(d, s) \
  353. EOP_MOV_REG_SIMPLE(d, s)
  354. #define emith_move_r_r_ptr(d, s) \
  355. emith_move_r_r(d, s)
  356. #define emith_mvn_r_r(d, s) \
  357. EOP_MVN_REG(A_COND_AL,0,d,s,A_AM1_LSL,0)
  358. #define emith_add_r_r_r_lsl(d, s1, s2, lslimm) \
  359. EOP_ADD_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSL,lslimm)
  360. #define emith_add_r_r_r_lsl_ptr(d, s1, s2, lslimm) \
  361. emith_add_r_r_r_lsl(d, s1, s2, lslimm)
  362. #define emith_addf_r_r_r_lsl(d, s1, s2, lslimm) \
  363. EOP_ADD_REG(A_COND_AL,1,d,s1,s2,A_AM1_LSL,lslimm)
  364. #define emith_addf_r_r_r_lsr(d, s1, s2, lslimm) \
  365. EOP_ADD_REG(A_COND_AL,1,d,s1,s2,A_AM1_LSR,lslimm)
  366. #define emith_adcf_r_r_r_lsl(d, s1, s2, lslimm) \
  367. EOP_ADC_REG(A_COND_AL,1,d,s1,s2,A_AM1_LSL,lslimm)
  368. #define emith_sub_r_r_r_lsl(d, s1, s2, lslimm) \
  369. EOP_SUB_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSL,lslimm)
  370. #define emith_subf_r_r_r_lsl(d, s1, s2, lslimm) \
  371. EOP_SUB_REG(A_COND_AL,1,d,s1,s2,A_AM1_LSL,lslimm)
  372. #define emith_sbcf_r_r_r_lsl(d, s1, s2, lslimm) \
  373. EOP_SBC_REG(A_COND_AL,1,d,s1,s2,A_AM1_LSL,lslimm)
  374. #define emith_or_r_r_r_lsl(d, s1, s2, lslimm) \
  375. EOP_ORR_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSL,lslimm)
  376. #define emith_eor_r_r_r_lsl(d, s1, s2, lslimm) \
  377. EOP_EOR_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSL,lslimm)
  378. #define emith_eor_r_r_r_lsr(d, s1, s2, lsrimm) \
  379. EOP_EOR_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSR,lsrimm)
  380. #define emith_and_r_r_r_lsl(d, s1, s2, lslimm) \
  381. EOP_AND_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSL,lslimm)
  382. #define emith_or_r_r_lsl(d, s, lslimm) \
  383. emith_or_r_r_r_lsl(d, d, s, lslimm)
  384. #define emith_eor_r_r_lsr(d, s, lsrimm) \
  385. emith_eor_r_r_r_lsr(d, d, s, lsrimm)
  386. #define emith_add_r_r_r(d, s1, s2) \
  387. emith_add_r_r_r_lsl(d, s1, s2, 0)
  388. #define emith_addf_r_r_r(d, s1, s2) \
  389. emith_addf_r_r_r_lsl(d, s1, s2, 0)
  390. #define emith_adcf_r_r_r(d, s1, s2) \
  391. emith_adcf_r_r_r_lsl(d, s1, s2, 0)
  392. #define emith_sub_r_r_r(d, s1, s2) \
  393. emith_sub_r_r_r_lsl(d, s1, s2, 0)
  394. #define emith_subf_r_r_r(d, s1, s2) \
  395. emith_subf_r_r_r_lsl(d, s1, s2, 0)
  396. #define emith_sbcf_r_r_r(d, s1, s2) \
  397. emith_sbcf_r_r_r_lsl(d, s1, s2, 0)
  398. #define emith_or_r_r_r(d, s1, s2) \
  399. emith_or_r_r_r_lsl(d, s1, s2, 0)
  400. #define emith_eor_r_r_r(d, s1, s2) \
  401. emith_eor_r_r_r_lsl(d, s1, s2, 0)
  402. #define emith_and_r_r_r(d, s1, s2) \
  403. emith_and_r_r_r_lsl(d, s1, s2, 0)
  404. #define emith_add_r_r(d, s) \
  405. emith_add_r_r_r(d, d, s)
  406. #define emith_add_r_r_ptr(d, s) \
  407. emith_add_r_r_r(d, d, s)
  408. #define emith_sub_r_r(d, s) \
  409. emith_sub_r_r_r(d, d, s)
  410. #define emith_adc_r_r(d, s) \
  411. EOP_ADC_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
  412. #define emith_and_r_r_c(cond, d, s) \
  413. EOP_AND_REG(cond,0,d,d,s,A_AM1_LSL,0)
  414. #define emith_and_r_r(d, s) \
  415. EOP_AND_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
  416. #define emith_or_r_r(d, s) \
  417. emith_or_r_r_r(d, d, s)
  418. #define emith_eor_r_r(d, s) \
  419. emith_eor_r_r_r(d, d, s)
  420. #define emith_tst_r_r(d, s) \
  421. EOP_TST_REG(A_COND_AL,d,s,A_AM1_LSL,0)
  422. #define emith_tst_r_r_ptr(d, s) \
  423. emith_tst_r_r(d, s)
  424. #define emith_teq_r_r(d, s) \
  425. EOP_TEQ_REG(A_COND_AL,d,s,A_AM1_LSL,0)
  426. #define emith_cmp_r_r(d, s) \
  427. EOP_CMP_REG(A_COND_AL,d,s,A_AM1_LSL,0)
  428. #define emith_addf_r_r(d, s) \
  429. EOP_ADD_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
  430. #define emith_subf_r_r(d, s) \
  431. EOP_SUB_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
  432. #define emith_adcf_r_r(d, s) \
  433. EOP_ADC_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
  434. #define emith_sbcf_r_r(d, s) \
  435. EOP_SBC_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
  436. #define emith_eorf_r_r(d, s) \
  437. EOP_EOR_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
  438. #define emith_move_r_imm(r, imm) \
  439. emith_op_imm(A_COND_AL, 0, A_OP_MOV, r, imm)
  440. #define emith_move_r_ptr_imm(r, imm) \
  441. emith_move_r_imm(r, (u32)(imm))
  442. #define emith_add_r_imm(r, imm) \
  443. emith_op_imm(A_COND_AL, 0, A_OP_ADD, r, imm)
  444. #define emith_adc_r_imm(r, imm) \
  445. emith_op_imm(A_COND_AL, 0, A_OP_ADC, r, imm)
  446. #define emith_adcf_r_imm(r, imm) \
  447. emith_op_imm(A_COND_AL, 1, A_OP_ADC, r, imm)
  448. #define emith_sub_r_imm(r, imm) \
  449. emith_op_imm(A_COND_AL, 0, A_OP_SUB, r, imm)
  450. #define emith_bic_r_imm(r, imm) \
  451. emith_op_imm(A_COND_AL, 0, A_OP_BIC, r, imm)
  452. #define emith_and_r_imm(r, imm) \
  453. emith_op_imm(A_COND_AL, 0, A_OP_AND, r, imm)
  454. #define emith_or_r_imm(r, imm) \
  455. emith_op_imm(A_COND_AL, 0, A_OP_ORR, r, imm)
  456. #define emith_eor_r_imm(r, imm) \
  457. emith_op_imm(A_COND_AL, 0, A_OP_EOR, r, imm)
  458. // note: only use 8bit imm for these
  459. #define emith_tst_r_imm(r, imm) \
  460. emith_top_imm(A_COND_AL, A_OP_TST, r, imm)
  461. #define emith_cmp_r_imm(r, imm) { \
  462. u32 op_ = A_OP_CMP, imm_ = (u8)imm; \
  463. if ((s8)imm_ < 0) { \
  464. imm_ = (u8)-imm_; \
  465. op_ = A_OP_CMN; \
  466. } \
  467. emith_top_imm(A_COND_AL, op_, r, imm_); \
  468. }
  469. #define emith_subf_r_imm(r, imm) \
  470. emith_op_imm(A_COND_AL, 1, A_OP_SUB, r, imm)
  471. #define emith_move_r_imm_c(cond, r, imm) \
  472. emith_op_imm(cond, 0, A_OP_MOV, r, imm)
  473. #define emith_add_r_imm_c(cond, r, imm) \
  474. emith_op_imm(cond, 0, A_OP_ADD, r, imm)
  475. #define emith_sub_r_imm_c(cond, r, imm) \
  476. emith_op_imm(cond, 0, A_OP_SUB, r, imm)
  477. #define emith_or_r_imm_c(cond, r, imm) \
  478. emith_op_imm(cond, 0, A_OP_ORR, r, imm)
  479. #define emith_eor_r_imm_c(cond, r, imm) \
  480. emith_op_imm(cond, 0, A_OP_EOR, r, imm)
  481. #define emith_bic_r_imm_c(cond, r, imm) \
  482. emith_op_imm(cond, 0, A_OP_BIC, r, imm)
  483. #define emith_tst_r_imm_c(cond, r, imm) \
  484. emith_top_imm(cond, A_OP_TST, r, imm)
  485. #define emith_move_r_imm_s8(r, imm) { \
  486. if ((s8)(imm) < 0) \
  487. EOP_MVN_IMM(r, 0, ((u8)(imm) ^ 0xff)); \
  488. else \
  489. EOP_MOV_IMM(r, 0, (u8)imm); \
  490. }
  491. #define emith_and_r_r_imm(d, s, imm) \
  492. emith_op_imm2(A_COND_AL, 0, A_OP_AND, d, s, imm)
  493. #define emith_add_r_r_imm(d, s, imm) \
  494. emith_op_imm2(A_COND_AL, 0, A_OP_ADD, d, s, imm)
  495. #define emith_add_r_r_ptr_imm(d, s, imm) \
  496. emith_add_r_r_imm(d, s, imm)
  497. #define emith_sub_r_r_imm(d, s, imm) \
  498. emith_op_imm2(A_COND_AL, 0, A_OP_SUB, d, s, imm)
  499. #define emith_subf_r_r_imm(d, s, imm) \
  500. emith_op_imm2(A_COND_AL, 1, A_OP_SUB, d, s, imm)
  501. #define emith_or_r_r_imm(d, s, imm) \
  502. emith_op_imm2(A_COND_AL, 0, A_OP_ORR, d, s, imm)
  503. #define emith_eor_r_r_imm(d, s, imm) \
  504. emith_op_imm2(A_COND_AL, 0, A_OP_EOR, d, s, imm)
  505. #define emith_neg_r_r(d, s) \
  506. EOP_RSB_IMM(d, s, 0, 0)
  507. #define emith_lsl(d, s, cnt) \
  508. EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_LSL,cnt)
  509. #define emith_lsr(d, s, cnt) \
  510. EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_LSR,cnt)
  511. #define emith_asr(d, s, cnt) \
  512. EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ASR,cnt)
  513. #define emith_ror_c(cond, d, s, cnt) \
  514. EOP_MOV_REG(cond,0,d,s,A_AM1_ROR,cnt)
  515. #define emith_ror(d, s, cnt) \
  516. emith_ror_c(A_COND_AL, d, s, cnt)
  517. #define emith_rol(d, s, cnt) \
  518. EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ROR,32-(cnt)); \
  519. #define emith_lslf(d, s, cnt) \
  520. EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_LSL,cnt)
  521. #define emith_lsrf(d, s, cnt) \
  522. EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_LSR,cnt)
  523. #define emith_asrf(d, s, cnt) \
  524. EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_ASR,cnt)
  525. // note: only C flag updated correctly
  526. #define emith_rolf(d, s, cnt) { \
  527. EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_ROR,32-(cnt)); \
  528. /* we don't have ROL so we shift to get the right carry */ \
  529. EOP_TST_REG(A_COND_AL,d,d,A_AM1_LSR,1); \
  530. }
  531. #define emith_rorf(d, s, cnt) \
  532. EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_ROR,cnt)
  533. #define emith_rolcf(d) \
  534. emith_adcf_r_r(d, d)
  535. #define emith_rorcf(d) \
  536. EOP_MOV_REG(A_COND_AL,1,d,d,A_AM1_ROR,0) /* ROR #0 -> RRX */
  537. #define emith_negcf_r_r(d, s) \
  538. EOP_C_DOP_IMM(A_COND_AL,A_OP_RSC,1,s,d,0,0)
  539. #define emith_mul(d, s1, s2) { \
  540. if ((d) != (s1)) /* rd != rm limitation */ \
  541. EOP_MUL(d, s1, s2); \
  542. else \
  543. EOP_MUL(d, s2, s1); \
  544. }
  545. #define emith_mul_u64(dlo, dhi, s1, s2) \
  546. EOP_C_UMULL(A_COND_AL,0,dhi,dlo,s1,s2)
  547. #define emith_mul_s64(dlo, dhi, s1, s2) \
  548. EOP_C_SMULL(A_COND_AL,0,dhi,dlo,s1,s2)
  549. #define emith_mula_s64_c(cond, dlo, dhi, s1, s2) \
  550. EOP_C_SMLAL(cond,0,dhi,dlo,s1,s2)
  551. #define emith_mula_s64(dlo, dhi, s1, s2) \
  552. EOP_C_SMLAL(A_COND_AL,0,dhi,dlo,s1,s2)
  553. // misc
  554. #define emith_read_r_r_offs_c(cond, r, rs, offs) \
  555. EOP_LDR_IMM2(cond, r, rs, offs)
  556. #define emith_read_r_r_offs_ptr_c(cond, r, rs, offs) \
  557. emith_read_r_r_offs_c(cond, r, rs, offs)
  558. #define emith_read_r_r_r_c(cond, r, rs, rm) \
  559. EOP_LDR_REG_LSL(cond, r, rs, rm, 0)
  560. #define emith_read_r_r_r(r, rs, rm) \
  561. EOP_LDR_REG_LSL(A_COND_AL, r, rs, rm, 0)
  562. #define emith_read8_r_r_offs_c(cond, r, rs, offs) \
  563. EOP_LDRB_IMM2(cond, r, rs, offs)
  564. #define emith_read8_r_r_r_c(cond, r, rs, rm) \
  565. EOP_LDRB_REG_LSL(cond, r, rs, rm, 0)
  566. #define emith_read8_r_r_r(r, rs, rm) \
  567. EOP_LDRB_REG_LSL(A_COND_AL, r, rs, rm, 0)
  568. #define emith_read16_r_r_offs_c(cond, r, rs, offs) \
  569. EOP_LDRH_IMM2(cond, r, rs, offs)
  570. #define emith_read16_r_r_r_c(cond, r, rs, rm) \
  571. EOP_LDRH_REG2(cond, r, rs, rm)
  572. #define emith_read16_r_r_r(r, rs, rm) \
  573. EOP_LDRH_REG2(A_COND_AL, r, rs, rm)
  574. #define emith_read_r_r_offs(r, rs, offs) \
  575. emith_read_r_r_offs_c(A_COND_AL, r, rs, offs)
  576. #define emith_read8s_r_r_offs(r, rs, offs) \
  577. EOP_LDRSB_IMM2(A_COND_AL, r, rs, offs)
  578. #define emith_read8_r_r_offs(r, rs, offs) \
  579. emith_read8_r_r_offs_c(A_COND_AL, r, rs, offs)
  580. #define emith_read16s_r_r_offs(r, rs, offs) \
  581. EOP_LDRSH_IMM2(A_COND_AL, r, rs, offs)
  582. #define emith_read16_r_r_offs(r, rs, offs) \
  583. emith_read16_r_r_offs_c(A_COND_AL, r, rs, offs)
  584. #define emith_write_r_r_offs_c(cond, r, rs, offs) \
  585. EOP_STR_IMM2(cond, r, rs, offs)
  586. #define emith_write_r_r_offs_ptr_c(cond, r, rs, offs) \
  587. emith_write_r_r_offs_c(cond, r, rs, offs)
  588. #define emith_ctx_read_c(cond, r, offs) \
  589. emith_read_r_r_offs_c(cond, r, CONTEXT_REG, offs)
  590. #define emith_ctx_read(r, offs) \
  591. emith_ctx_read_c(A_COND_AL, r, offs)
  592. #define emith_ctx_read_ptr(r, offs) \
  593. emith_ctx_read(r, offs)
  594. #define emith_ctx_write(r, offs) \
  595. EOP_STR_IMM(r, CONTEXT_REG, offs)
  596. #define emith_ctx_do_multiple(op, r, offs, count, tmpr) do { \
  597. int v_, r_ = r, c_ = count, b_ = CONTEXT_REG; \
  598. for (v_ = 0; c_; c_--, r_++) \
  599. v_ |= 1 << r_; \
  600. if ((offs) != 0) { \
  601. EOP_ADD_IMM(tmpr,CONTEXT_REG,30/2,(offs)>>2);\
  602. b_ = tmpr; \
  603. } \
  604. op(b_,v_); \
  605. } while(0)
  606. #define emith_ctx_read_multiple(r, offs, count, tmpr) \
  607. emith_ctx_do_multiple(EOP_LDMIA, r, offs, count, tmpr)
  608. #define emith_ctx_write_multiple(r, offs, count, tmpr) \
  609. emith_ctx_do_multiple(EOP_STMIA, r, offs, count, tmpr)
  610. #define emith_clear_msb_c(cond, d, s, count) { \
  611. u32 t; \
  612. if ((count) <= 8) { \
  613. t = 8 - (count); \
  614. t = (0xff << t) & 0xff; \
  615. EOP_C_DOP_IMM(cond,A_OP_BIC,0,s,d,8/2,t); \
  616. } else if ((count) >= 24) { \
  617. t = (count) - 24; \
  618. t = 0xff >> t; \
  619. EOP_C_DOP_IMM(cond,A_OP_AND,0,s,d,0,t); \
  620. } else { \
  621. EOP_MOV_REG(cond,0,d,s,A_AM1_LSL,count); \
  622. EOP_MOV_REG(cond,0,d,d,A_AM1_LSR,count); \
  623. } \
  624. }
  625. #define emith_clear_msb(d, s, count) \
  626. emith_clear_msb_c(A_COND_AL, d, s, count)
  627. #define emith_sext(d, s, bits) { \
  628. EOP_MOV_REG_LSL(d,s,32 - (bits)); \
  629. EOP_MOV_REG_ASR(d,d,32 - (bits)); \
  630. }
  631. #define emith_do_caller_regs(mask, func) { \
  632. u32 _reg_mask = (mask) & 0x500f; \
  633. if (_reg_mask) { \
  634. if (__builtin_parity(_reg_mask) == 1) \
  635. _reg_mask |= 0x10; /* eabi align */ \
  636. func(_reg_mask); \
  637. } \
  638. }
  639. #define emith_save_caller_regs(mask) \
  640. emith_do_caller_regs(mask, EOP_STMFD_SP)
  641. #define emith_restore_caller_regs(mask) \
  642. emith_do_caller_regs(mask, EOP_LDMFD_SP)
  643. // upto 4 args
  644. #define emith_pass_arg_r(arg, reg) \
  645. EOP_MOV_REG_SIMPLE(arg, reg)
  646. #define emith_pass_arg_imm(arg, imm) \
  647. emith_move_r_imm(arg, imm)
  648. #define emith_jump(target) \
  649. emith_jump_cond(A_COND_AL, target)
  650. #define emith_jump_patchable(target) \
  651. emith_jump(target)
  652. #define emith_jump_cond(cond, target) \
  653. emith_xbranch(cond, target, 0)
  654. #define emith_jump_cond_patchable(cond, target) \
  655. emith_jump_cond(cond, target)
  656. #define emith_jump_patch(ptr, target) do { \
  657. u32 *ptr_ = ptr; \
  658. u32 val_ = (u32 *)(target) - ptr_ - 2; \
  659. *ptr_ = (*ptr_ & 0xff000000) | (val_ & 0x00ffffff); \
  660. } while (0)
  661. #define emith_jump_at(ptr, target) { \
  662. u32 val_ = (u32 *)(target) - (u32 *)(ptr) - 2; \
  663. EOP_C_B_PTR(ptr, A_COND_AL, 0, val_ & 0xffffff); \
  664. }
  665. #define emith_jump_reg_c(cond, r) \
  666. EOP_C_BX(cond, r)
  667. #define emith_jump_reg(r) \
  668. emith_jump_reg_c(A_COND_AL, r)
  669. #define emith_jump_ctx_c(cond, offs) \
  670. EOP_LDR_IMM2(cond,15,CONTEXT_REG,offs)
  671. #define emith_jump_ctx(offs) \
  672. emith_jump_ctx_c(A_COND_AL, offs)
  673. #define emith_call_cond(cond, target) \
  674. emith_xbranch(cond, target, 1)
  675. #define emith_call(target) \
  676. emith_call_cond(A_COND_AL, target)
  677. #define emith_call_ctx(offs) { \
  678. emith_move_r_r(14, 15); \
  679. emith_jump_ctx(offs); \
  680. }
  681. #define emith_ret_c(cond) \
  682. emith_jump_reg_c(cond, 14)
  683. #define emith_ret() \
  684. emith_ret_c(A_COND_AL)
  685. #define emith_ret_to_ctx(offs) \
  686. emith_ctx_write(14, offs)
  687. #define emith_push_ret() \
  688. EOP_STMFD_SP(A_R14M)
  689. #define emith_pop_and_ret() \
  690. EOP_LDMFD_SP(A_R15M)
  691. #define host_instructions_updated(base, end) \
  692. cache_flush_d_inval_i(base, end)
  693. #define host_arg2reg(rd, arg) \
  694. rd = arg
  695. /* SH2 drc specific */
  696. /* pushes r12 for eabi alignment */
  697. #define emith_sh2_drc_entry() \
  698. EOP_STMFD_SP(A_R4M|A_R5M|A_R6M|A_R7M|A_R8M|A_R9M|A_R10M|A_R11M|A_R12M|A_R14M)
  699. #define emith_sh2_drc_exit() \
  700. EOP_LDMFD_SP(A_R4M|A_R5M|A_R6M|A_R7M|A_R8M|A_R9M|A_R10M|A_R11M|A_R12M|A_R15M)
  701. // assumes a is in arg0, tab, func and mask are temp
  702. #define emith_sh2_rcall(a, tab, func, mask) { \
  703. emith_lsr(mask, a, SH2_READ_SHIFT); \
  704. EOP_ADD_REG_LSL(tab, tab, mask, 3); \
  705. if (func < mask) EOP_LDMIA(tab, (1<<func)|(1<<mask)); /* ldm if possible */ \
  706. else { emith_read_r_r_offs(func, tab, 0); \
  707. emith_read_r_r_offs(mask, tab, 4); } \
  708. emith_addf_r_r_r(func,func,func); \
  709. }
  710. // assumes a, val are in arg0 and arg1, tab and func are temp
  711. #define emith_sh2_wcall(a, val, tab, func) { \
  712. emith_lsr(func, a, SH2_WRITE_SHIFT); \
  713. EOP_LDR_REG_LSL(A_COND_AL,func,tab,func,2); \
  714. emith_move_r_r(2, CONTEXT_REG); /* arg2 */ \
  715. emith_jump_reg(func); \
  716. }
  717. #define emith_sh2_dtbf_loop() { \
  718. int cr, rn; \
  719. int tmp_ = rcache_get_tmp(); \
  720. cr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
  721. rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW); \
  722. emith_sub_r_imm(rn, 1); /* sub rn, #1 */ \
  723. emith_bic_r_imm(cr, 1); /* bic cr, #1 */ \
  724. emith_sub_r_imm(cr, (cycles+1) << 12); /* sub cr, #(cycles+1)<<12 */ \
  725. cycles = 0; \
  726. emith_asrf(tmp_, cr, 2+12); /* movs tmp_, cr, asr #2+12 */\
  727. EOP_MOV_IMM_C(A_COND_MI,tmp_,0,0); /* movmi tmp_, #0 */ \
  728. emith_lsl(cr, cr, 20); /* mov cr, cr, lsl #20 */ \
  729. emith_lsr(cr, cr, 20); /* mov cr, cr, lsr #20 */ \
  730. emith_subf_r_r(rn, tmp_); /* subs rn, tmp_ */ \
  731. EOP_RSB_IMM_C(A_COND_LS,tmp_,rn,0,0); /* rsbls tmp_, rn, #0 */ \
  732. EOP_ORR_REG(A_COND_LS,0,cr,cr,tmp_,A_AM1_LSL,12+2); /* orrls cr,tmp_,lsl #12+2 */\
  733. EOP_ORR_IMM_C(A_COND_LS,cr,cr,0,1); /* orrls cr, #1 */ \
  734. EOP_MOV_IMM_C(A_COND_LS,rn,0,0); /* movls rn, #0 */ \
  735. rcache_free_tmp(tmp_); \
  736. }
  737. #define emith_write_sr(sr, srcr) { \
  738. emith_lsr(sr, sr, 10); \
  739. emith_or_r_r_r_lsl(sr, sr, srcr, 22); \
  740. emith_ror(sr, sr, 22); \
  741. }
  742. #define emith_carry_to_t(srr, is_sub) { \
  743. if (is_sub) { /* has inverted C on ARM */ \
  744. emith_or_r_imm_c(A_COND_CC, srr, 1); \
  745. emith_bic_r_imm_c(A_COND_CS, srr, 1); \
  746. } else { \
  747. emith_or_r_imm_c(A_COND_CS, srr, 1); \
  748. emith_bic_r_imm_c(A_COND_CC, srr, 1); \
  749. } \
  750. }
  751. #define emith_tpop_carry(sr, is_sub) { \
  752. if (is_sub) \
  753. emith_eor_r_imm(sr, 1); \
  754. emith_lsrf(sr, sr, 1); \
  755. }
  756. #define emith_tpush_carry(sr, is_sub) { \
  757. emith_adc_r_r(sr, sr); \
  758. if (is_sub) \
  759. emith_eor_r_imm(sr, 1); \
  760. }
  761. /*
  762. * if Q
  763. * t = carry(Rn += Rm)
  764. * else
  765. * t = carry(Rn -= Rm)
  766. * T ^= t
  767. */
  768. #define emith_sh2_div1_step(rn, rm, sr) { \
  769. void *jmp0, *jmp1; \
  770. emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
  771. JMP_POS(jmp0); /* beq do_sub */ \
  772. emith_addf_r_r(rn, rm); \
  773. emith_eor_r_imm_c(A_COND_CS, sr, T); \
  774. JMP_POS(jmp1); /* b done */ \
  775. JMP_EMIT(A_COND_EQ, jmp0); /* do_sub: */ \
  776. emith_subf_r_r(rn, rm); \
  777. emith_eor_r_imm_c(A_COND_CC, sr, T); \
  778. JMP_EMIT(A_COND_AL, jmp1); /* done: */ \
  779. }
  780. /* mh:ml += rn*rm, does saturation if required by S bit. rn, rm must be TEMP */
  781. #define emith_sh2_macl(ml, mh, rn, rm, sr) do { \
  782. emith_tst_r_imm(sr, S); \
  783. EMITH_SJMP2_START(DCOND_NE); \
  784. emith_mula_s64_c(DCOND_EQ, ml, mh, rn, rm); \
  785. EMITH_SJMP2_MID(DCOND_NE); \
  786. /* MACH top 16 bits unused if saturated. sign ext for overfl detect */ \
  787. emith_sext(mh, mh, 16); \
  788. emith_mula_s64(ml, mh, rn, rm); \
  789. /* overflow if top 17 bits of MACH aren't all 1 or 0 */ \
  790. /* to check: add MACH[15] to MACH[31:16]. this is 0 if no overflow */ \
  791. emith_asrf(rn, mh, 16); /* sum = (MACH>>16) + ((MACH>>15)&1) */ \
  792. emith_adcf_r_imm(rn, 0); /* (MACH>>15) is in carry after shift */ \
  793. EMITH_SJMP_START(DCOND_EQ); /* sum != 0 -> ov */ \
  794. emith_move_r_imm_c(DCOND_NE, ml, 0x0000); /* -overflow */ \
  795. emith_move_r_imm_c(DCOND_NE, mh, 0x8000); \
  796. EMITH_SJMP_START(DCOND_LE); /* sum > 0 -> +ovl */ \
  797. emith_sub_r_imm_c(DCOND_GT, ml, 1); /* 0xffffffff */ \
  798. emith_sub_r_imm_c(DCOND_GT, mh, 1); /* 0x00007fff */ \
  799. EMITH_SJMP_END(DCOND_LE); \
  800. EMITH_SJMP_END(DCOND_EQ); \
  801. EMITH_SJMP2_END(DCOND_NE); \
  802. } while (0)
  803. /* mh:ml += rn*rm, does saturation if required by S bit. rn, rm must be TEMP */
  804. #define emith_sh2_macw(ml, mh, rn, rm, sr) do { \
  805. emith_sext(rn, rn, 16); \
  806. emith_sext(rm, rm, 16); \
  807. emith_tst_r_imm(sr, S); \
  808. EMITH_SJMP2_START(DCOND_NE); \
  809. emith_mula_s64_c(DCOND_EQ, ml, mh, rn, rm); \
  810. EMITH_SJMP2_MID(DCOND_NE); \
  811. /* XXX: MACH should be untouched when S is set? */ \
  812. emith_asr(mh, ml, 31); /* sign ext MACL to MACH for ovrfl check */ \
  813. emith_mula_s64(ml, mh, rn, rm); \
  814. /* overflow if top 33 bits of MACH:MACL aren't all 1 or 0 */ \
  815. /* to check: add MACL[31] to MACH. this is 0 if no overflow */ \
  816. emith_addf_r_r_r_lsr(mh, mh, ml, 31); /* sum = MACH + ((MACL>>31)&1) */\
  817. EMITH_SJMP_START(DCOND_EQ); /* sum != 0 -> overflow */ \
  818. /* XXX: LSB signalling only in SH1, or in SH2 too? */ \
  819. emith_move_r_imm_c(DCOND_NE, mh, 0x00000001); /* LSB of MACH */ \
  820. emith_move_r_imm_c(DCOND_NE, ml, 0x80000000); /* negative ovrfl */ \
  821. EMITH_SJMP_START(DCOND_LE); /* sum > 0 -> positive ovrfl */ \
  822. emith_sub_r_imm_c(DCOND_GT, ml, 1); /* 0x7fffffff */ \
  823. EMITH_SJMP_END(DCOND_LE); \
  824. EMITH_SJMP_END(DCOND_EQ); \
  825. EMITH_SJMP2_END(DCOND_NE); \
  826. } while (0)