Misc.c 13 KB

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  1. // This is part of Pico Library
  2. // (c) Copyright 2006 notaz, All rights reserved.
  3. // Free for non-commercial use.
  4. // For commercial use, separate licencing terms must be obtained.
  5. #include "PicoInt.h"
  6. // H-counter table for hvcounter reads in 40col mode
  7. // based on Gens code
  8. const unsigned char hcounts_40[] = {
  9. 0x07,0x07,0x08,0x08,0x08,0x09,0x09,0x0a,0x0a,0x0b,0x0b,0x0b,0x0c,0x0c,0x0d,0x0d,
  10. 0x0e,0x0e,0x0e,0x0f,0x0f,0x10,0x10,0x10,0x11,0x11,0x12,0x12,0x13,0x13,0x13,0x14,
  11. 0x14,0x15,0x15,0x15,0x16,0x16,0x17,0x17,0x18,0x18,0x18,0x19,0x19,0x1a,0x1a,0x1b,
  12. 0x1b,0x1b,0x1c,0x1c,0x1d,0x1d,0x1d,0x1e,0x1e,0x1f,0x1f,0x20,0x20,0x20,0x21,0x21,
  13. 0x22,0x22,0x23,0x23,0x23,0x24,0x24,0x25,0x25,0x25,0x26,0x26,0x27,0x27,0x28,0x28,
  14. 0x28,0x29,0x29,0x2a,0x2a,0x2a,0x2b,0x2b,0x2c,0x2c,0x2d,0x2d,0x2d,0x2e,0x2e,0x2f,
  15. 0x2f,0x30,0x30,0x30,0x31,0x31,0x32,0x32,0x32,0x33,0x33,0x34,0x34,0x35,0x35,0x35,
  16. 0x36,0x36,0x37,0x37,0x38,0x38,0x38,0x39,0x39,0x3a,0x3a,0x3a,0x3b,0x3b,0x3c,0x3c,
  17. 0x3d,0x3d,0x3d,0x3e,0x3e,0x3f,0x3f,0x3f,0x40,0x40,0x41,0x41,0x42,0x42,0x42,0x43,
  18. 0x43,0x44,0x44,0x45,0x45,0x45,0x46,0x46,0x47,0x47,0x47,0x48,0x48,0x49,0x49,0x4a,
  19. 0x4a,0x4a,0x4b,0x4b,0x4c,0x4c,0x4d,0x4d,0x4d,0x4e,0x4e,0x4f,0x4f,0x4f,0x50,0x50,
  20. 0x51,0x51,0x52,0x52,0x52,0x53,0x53,0x54,0x54,0x55,0x55,0x55,0x56,0x56,0x57,0x57,
  21. 0x57,0x58,0x58,0x59,0x59,0x5a,0x5a,0x5a,0x5b,0x5b,0x5c,0x5c,0x5c,0x5d,0x5d,0x5e,
  22. 0x5e,0x5f,0x5f,0x5f,0x60,0x60,0x61,0x61,0x62,0x62,0x62,0x63,0x63,0x64,0x64,0x64,
  23. 0x65,0x65,0x66,0x66,0x67,0x67,0x67,0x68,0x68,0x69,0x69,0x6a,0x6a,0x6a,0x6b,0x6b,
  24. 0x6c,0x6c,0x6c,0x6d,0x6d,0x6e,0x6e,0x6f,0x6f,0x6f,0x70,0x70,0x71,0x71,0x71,0x72,
  25. 0x72,0x73,0x73,0x74,0x74,0x74,0x75,0x75,0x76,0x76,0x77,0x77,0x77,0x78,0x78,0x79,
  26. 0x79,0x79,0x7a,0x7a,0x7b,0x7b,0x7c,0x7c,0x7c,0x7d,0x7d,0x7e,0x7e,0x7f,0x7f,0x7f,
  27. 0x80,0x80,0x81,0x81,0x81,0x82,0x82,0x83,0x83,0x84,0x84,0x84,0x85,0x85,0x86,0x86,
  28. 0x86,0x87,0x87,0x88,0x88,0x89,0x89,0x89,0x8a,0x8a,0x8b,0x8b,0x8c,0x8c,0x8c,0x8d,
  29. 0x8d,0x8e,0x8e,0x8e,0x8f,0x8f,0x90,0x90,0x91,0x91,0x91,0x92,0x92,0x93,0x93,0x94,
  30. 0x94,0x94,0x95,0x95,0x96,0x96,0x96,0x97,0x97,0x98,0x98,0x99,0x99,0x99,0x9a,0x9a,
  31. 0x9b,0x9b,0x9b,0x9c,0x9c,0x9d,0x9d,0x9e,0x9e,0x9e,0x9f,0x9f,0xa0,0xa0,0xa1,0xa1,
  32. 0xa1,0xa2,0xa2,0xa3,0xa3,0xa3,0xa4,0xa4,0xa5,0xa5,0xa6,0xa6,0xa6,0xa7,0xa7,0xa8,
  33. 0xa8,0xa9,0xa9,0xa9,0xaa,0xaa,0xab,0xab,0xab,0xac,0xac,0xad,0xad,0xae,0xae,0xae,
  34. 0xaf,0xaf,0xb0,0xb0,
  35. 0xe4,0xe4,0xe4,0xe5,0xe5,0xe6,0xe6,0xe6,0xe7,0xe7,0xe8,0xe8,0xe9,0xe9,0xe9,0xea,
  36. 0xea,0xeb,0xeb,0xeb,0xec,0xec,0xed,0xed,0xee,0xee,0xee,0xef,0xef,0xf0,0xf0,0xf1,
  37. 0xf1,0xf1,0xf2,0xf2,0xf3,0xf3,0xf3,0xf4,0xf4,0xf5,0xf5,0xf6,0xf6,0xf6,0xf7,0xf7,
  38. 0xf8,0xf8,0xf9,0xf9,0xf9,0xfa,0xfa,0xfb,0xfb,0xfb,0xfc,0xfc,0xfd,0xfd,0xfe,0xfe,
  39. 0xfe,0xff,0xff,0x00,0x00,0x00,0x01,0x01,0x02,0x02,0x03,0x03,0x03,0x04,0x04,0x05,
  40. 0x05,0x06,0x06,0x06,
  41. 0x07,0x07,0x08,0x08,0x08,0x09,0x09,0x0a,0x0a,0x0b,0x0b,0x0b,0x0c,0x0c,0x0d,0x0d,
  42. 0x0e,0x0e,0x0e,0x0f,0x0f,0x10,0x10,0x10,
  43. };
  44. // H-counter table for hvcounter reads in 32col mode
  45. const unsigned char hcounts_32[] = {
  46. 0x05,0x05,0x05,0x06,0x06,0x07,0x07,0x07,0x08,0x08,0x08,0x09,0x09,0x09,0x0a,0x0a,
  47. 0x0a,0x0b,0x0b,0x0b,0x0c,0x0c,0x0c,0x0d,0x0d,0x0d,0x0e,0x0e,0x0f,0x0f,0x0f,0x10,
  48. 0x10,0x10,0x11,0x11,0x11,0x12,0x12,0x12,0x13,0x13,0x13,0x14,0x14,0x14,0x15,0x15,
  49. 0x15,0x16,0x16,0x17,0x17,0x17,0x18,0x18,0x18,0x19,0x19,0x19,0x1a,0x1a,0x1a,0x1b,
  50. 0x1b,0x1b,0x1c,0x1c,0x1c,0x1d,0x1d,0x1d,0x1e,0x1e,0x1f,0x1f,0x1f,0x20,0x20,0x20,
  51. 0x21,0x21,0x21,0x22,0x22,0x22,0x23,0x23,0x23,0x24,0x24,0x24,0x25,0x25,0x26,0x26,
  52. 0x26,0x27,0x27,0x27,0x28,0x28,0x28,0x29,0x29,0x29,0x2a,0x2a,0x2a,0x2b,0x2b,0x2b,
  53. 0x2c,0x2c,0x2c,0x2d,0x2d,0x2e,0x2e,0x2e,0x2f,0x2f,0x2f,0x30,0x30,0x30,0x31,0x31,
  54. 0x31,0x32,0x32,0x32,0x33,0x33,0x33,0x34,0x34,0x34,0x35,0x35,0x36,0x36,0x36,0x37,
  55. 0x37,0x37,0x38,0x38,0x38,0x39,0x39,0x39,0x3a,0x3a,0x3a,0x3b,0x3b,0x3b,0x3c,0x3c,
  56. 0x3d,0x3d,0x3d,0x3e,0x3e,0x3e,0x3f,0x3f,0x3f,0x40,0x40,0x40,0x41,0x41,0x41,0x42,
  57. 0x42,0x42,0x43,0x43,0x43,0x44,0x44,0x45,0x45,0x45,0x46,0x46,0x46,0x47,0x47,0x47,
  58. 0x48,0x48,0x48,0x49,0x49,0x49,0x4a,0x4a,0x4a,0x4b,0x4b,0x4b,0x4c,0x4c,0x4d,0x4d,
  59. 0x4d,0x4e,0x4e,0x4e,0x4f,0x4f,0x4f,0x50,0x50,0x50,0x51,0x51,0x51,0x52,0x52,0x52,
  60. 0x53,0x53,0x53,0x54,0x54,0x55,0x55,0x55,0x56,0x56,0x56,0x57,0x57,0x57,0x58,0x58,
  61. 0x58,0x59,0x59,0x59,0x5a,0x5a,0x5a,0x5b,0x5b,0x5c,0x5c,0x5c,0x5d,0x5d,0x5d,0x5e,
  62. 0x5e,0x5e,0x5f,0x5f,0x5f,0x60,0x60,0x60,0x61,0x61,0x61,0x62,0x62,0x62,0x63,0x63,
  63. 0x64,0x64,0x64,0x65,0x65,0x65,0x66,0x66,0x66,0x67,0x67,0x67,0x68,0x68,0x68,0x69,
  64. 0x69,0x69,0x6a,0x6a,0x6a,0x6b,0x6b,0x6c,0x6c,0x6c,0x6d,0x6d,0x6d,0x6e,0x6e,0x6e,
  65. 0x6f,0x6f,0x6f,0x70,0x70,0x70,0x71,0x71,0x71,0x72,0x72,0x72,0x73,0x73,0x74,0x74,
  66. 0x74,0x75,0x75,0x75,0x76,0x76,0x76,0x77,0x77,0x77,0x78,0x78,0x78,0x79,0x79,0x79,
  67. 0x7a,0x7a,0x7b,0x7b,0x7b,0x7c,0x7c,0x7c,0x7d,0x7d,0x7d,0x7e,0x7e,0x7e,0x7f,0x7f,
  68. 0x7f,0x80,0x80,0x80,0x81,0x81,0x81,0x82,0x82,0x83,0x83,0x83,0x84,0x84,0x84,0x85,
  69. 0x85,0x85,0x86,0x86,0x86,0x87,0x87,0x87,0x88,0x88,0x88,0x89,0x89,0x89,0x8a,0x8a,
  70. 0x8b,0x8b,0x8b,0x8c,0x8c,0x8c,0x8d,0x8d,0x8d,0x8e,0x8e,0x8e,0x8f,0x8f,0x8f,0x90,
  71. 0x90,0x90,0x91,0x91,
  72. 0xe8,0xe8,0xe8,0xe9,0xe9,0xe9,0xea,0xea,0xea,0xeb,0xeb,0xeb,0xec,0xec,0xec,0xed,
  73. 0xed,0xed,0xee,0xee,0xee,0xef,0xef,0xf0,0xf0,0xf0,0xf1,0xf1,0xf1,0xf2,0xf2,0xf2,
  74. 0xf3,0xf3,0xf3,0xf4,0xf4,0xf4,0xf5,0xf5,0xf5,0xf6,0xf6,0xf6,0xf7,0xf7,0xf8,0xf8,
  75. 0xf8,0xf9,0xf9,0xf9,0xfa,0xfa,0xfa,0xfb,0xfb,0xfb,0xfc,0xfc,0xfc,0xfd,0xfd,0xfd,
  76. 0xfe,0xfe,0xfe,0xff,0xff,0x00,0x00,0x00,0x01,0x01,0x01,0x02,0x02,0x02,0x03,0x03,
  77. 0x03,0x04,0x04,0x04,
  78. 0x05,0x05,0x05,0x06,0x06,0x07,0x07,0x07,0x08,0x08,0x08,0x09,0x09,0x09,0x0a,0x0a,
  79. 0x0a,0x0b,0x0b,0x0b,0x0c,0x0c,0x0c,0x0d,
  80. };
  81. // rarely used EEPROM SRAM code
  82. // known games which use this:
  83. // Wonder Boy in Monster World, Megaman - The Wily Wars (X24C01, 128 bytes)
  84. // (see Genesis Plus for Wii/GC code and docs for info,
  85. // full game list and better code).
  86. unsigned int lastSSRamWrite = 0xffff0000;
  87. // sram_reg: LAtd sela (L=pending SCL, A=pending SDA, t=(unused),
  88. // d=SRAM was detected (header or by access), s=started, e=save is EEPROM, l=old SCL, a=old SDA)
  89. PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d) // ???? ??la (l=SCL, a=SDA)
  90. {
  91. unsigned int sreg = Pico.m.sram_reg, saddr = Pico.m.eeprom_addr, scyc = Pico.m.eeprom_cycle, ssa = Pico.m.eeprom_slave;
  92. elprintf(EL_EEPROM, "eeprom: scl/sda: %i/%i -> %i/%i, newtime=%i", (sreg&2)>>1, sreg&1,
  93. (d&2)>>1, d&1, SekCyclesDoneT()-lastSSRamWrite);
  94. saddr&=0x1fff;
  95. if(sreg & d & 2) {
  96. // SCL was and is still high..
  97. if((sreg & 1) && !(d&1)) {
  98. // ..and SDA went low, means it's a start command, so clear internal addr reg and clock counter
  99. elprintf(EL_EEPROM, "eeprom: -start-");
  100. //saddr = 0;
  101. scyc = 0;
  102. sreg |= 8;
  103. } else if(!(sreg & 1) && (d&1)) {
  104. // SDA went high == stop command
  105. elprintf(EL_EEPROM, "eeprom: -stop-");
  106. sreg &= ~8;
  107. }
  108. }
  109. else if((sreg & 8) && !(sreg & 2) && (d&2))
  110. {
  111. // we are started and SCL went high - next cycle
  112. scyc++; // pre-increment
  113. if(SRam.eeprom_type) {
  114. // X24C02+
  115. if((ssa&1) && scyc == 18) {
  116. scyc = 9;
  117. saddr++; // next address in read mode
  118. /*if(SRam.eeprom_type==2) saddr&=0xff; else*/ saddr&=0x1fff; // mask
  119. }
  120. else if(SRam.eeprom_type == 2 && scyc == 27) scyc = 18;
  121. else if(scyc == 36) scyc = 27;
  122. } else {
  123. // X24C01
  124. if(scyc == 18) {
  125. scyc = 9; // wrap
  126. if(saddr&1) { saddr+=2; saddr&=0xff; } // next addr in read mode
  127. }
  128. }
  129. elprintf(EL_EEPROM, "eeprom: scyc: %i", scyc);
  130. }
  131. else if((sreg & 8) && (sreg & 2) && !(d&2))
  132. {
  133. // we are started and SCL went low (falling edge)
  134. if(SRam.eeprom_type) {
  135. // X24C02+
  136. if(scyc == 9 || scyc == 18 || scyc == 27); // ACK cycles
  137. else if( (SRam.eeprom_type == 3 && scyc > 27) || (SRam.eeprom_type == 2 && scyc > 18) ) {
  138. if(!(ssa&1)) {
  139. // data write
  140. unsigned char *pm=SRam.data+saddr;
  141. *pm <<= 1; *pm |= d&1;
  142. if(scyc == 26 || scyc == 35) {
  143. saddr=(saddr&~0xf)|((saddr+1)&0xf); // only 4 (?) lowest bits are incremented
  144. elprintf(EL_EEPROM, "eeprom: write done, addr inc to: %x, last byte=%02x", saddr, *pm);
  145. }
  146. SRam.changed = 1;
  147. }
  148. } else if(scyc > 9) {
  149. if(!(ssa&1)) {
  150. // we latch another addr bit
  151. saddr<<=1;
  152. if(SRam.eeprom_type == 2) saddr&=0xff; else saddr&=0x1fff; // mask
  153. saddr|=d&1;
  154. if(scyc==17||scyc==26) {
  155. elprintf(EL_EEPROM, "eeprom: addr reg done: %x", saddr);
  156. if(scyc==17&&SRam.eeprom_type==2) { saddr&=0xff; saddr|=(ssa<<7)&0x700; } // add device bits too
  157. }
  158. }
  159. } else {
  160. // slave address
  161. ssa<<=1; ssa|=d&1;
  162. if(scyc==8) elprintf(EL_EEPROM, "eeprom: slave done: %x", ssa);
  163. }
  164. } else {
  165. // X24C01
  166. if(scyc == 9); // ACK cycle, do nothing
  167. else if(scyc > 9) {
  168. if(!(saddr&1)) {
  169. // data write
  170. unsigned char *pm=SRam.data+(saddr>>1);
  171. *pm <<= 1; *pm |= d&1;
  172. if(scyc == 17) {
  173. saddr=(saddr&0xf9)|((saddr+2)&6); // only 2 lowest bits are incremented
  174. elprintf(EL_EEPROM, "eeprom: write done, addr inc to: %x, last byte=%02x", saddr>>1, *pm);
  175. }
  176. SRam.changed = 1;
  177. }
  178. } else {
  179. // we latch another addr bit
  180. saddr<<=1; saddr|=d&1; saddr&=0xff;
  181. if(scyc==8) elprintf(EL_EEPROM, "eeprom: addr done: %x", saddr>>1);
  182. }
  183. }
  184. }
  185. sreg &= ~3; sreg |= d&3; // remember SCL and SDA
  186. Pico.m.sram_reg = (unsigned char) sreg;
  187. Pico.m.eeprom_cycle= (unsigned char) scyc;
  188. Pico.m.eeprom_slave= (unsigned char) ssa;
  189. Pico.m.eeprom_addr = (unsigned short)saddr;
  190. }
  191. PICO_INTERNAL_ASM unsigned int SRAMReadEEPROM(void)
  192. {
  193. unsigned int shift, d;
  194. unsigned int sreg, saddr, scyc, ssa, interval;
  195. // flush last pending write
  196. SRAMWriteEEPROM(Pico.m.sram_reg>>6);
  197. sreg = Pico.m.sram_reg; saddr = Pico.m.eeprom_addr&0x1fff; scyc = Pico.m.eeprom_cycle; ssa = Pico.m.eeprom_slave;
  198. interval = SekCyclesDoneT()-lastSSRamWrite;
  199. d = (sreg>>6)&1; // use SDA as "open bus"
  200. // NBA Jam is nasty enough to read <before> raising the SCL and starting the new cycle.
  201. // this is probably valid because data changes occur while SCL is low and data can be read
  202. // before it's actual cycle begins.
  203. if (!(sreg&0x80) && interval >= 24) {
  204. elprintf(EL_EEPROM, "eeprom: early read, cycles=%i", interval);
  205. scyc++;
  206. }
  207. if (!(sreg & 8)); // not started, use open bus
  208. else if (scyc == 9 || scyc == 18 || scyc == 27) {
  209. elprintf(EL_EEPROM, "eeprom: r ack");
  210. d = 0;
  211. } else if (scyc > 9 && scyc < 18) {
  212. // started and first command word received
  213. shift = 17-scyc;
  214. if (SRam.eeprom_type) {
  215. // X24C02+
  216. if (ssa&1) {
  217. elprintf(EL_EEPROM, "eeprom: read: addr %02x, cycle %i, reg %02x", saddr, scyc, sreg);
  218. if (shift==0) elprintf(EL_EEPROM, "eeprom: read done, byte %02x", SRam.data[saddr]);
  219. d = (SRam.data[saddr]>>shift)&1;
  220. }
  221. } else {
  222. // X24C01
  223. if (saddr&1) {
  224. elprintf(EL_EEPROM, "eeprom: read: addr %02x, cycle %i, reg %02x", saddr>>1, scyc, sreg);
  225. if (shift==0) elprintf(EL_EEPROM, "eeprom: read done, byte %02x", SRam.data[saddr>>1]);
  226. d = (SRam.data[saddr>>1]>>shift)&1;
  227. }
  228. }
  229. }
  230. return (d << SRam.eeprom_bit_out);
  231. }
  232. PICO_INTERNAL void SRAMUpdPending(unsigned int a, unsigned int d)
  233. {
  234. unsigned int d1, sreg = Pico.m.sram_reg;
  235. if (!((SRam.eeprom_abits^a)&1))
  236. {
  237. // SCL
  238. sreg &= ~0x80;
  239. d1 = (d >> SRam.eeprom_bit_cl) & 1;
  240. sreg |= d1<<7;
  241. }
  242. if (!(((SRam.eeprom_abits>>1)^a)&1))
  243. {
  244. // SDA in
  245. sreg &= ~0x40;
  246. d1 = (d >> SRam.eeprom_bit_in) & 1;
  247. sreg |= d1<<6;
  248. }
  249. Pico.m.sram_reg = (unsigned char) sreg;
  250. }
  251. #ifndef _ASM_MISC_C
  252. typedef struct
  253. {
  254. int b0;
  255. int b1;
  256. int b2;
  257. int b3;
  258. int b4;
  259. int b5;
  260. int b6;
  261. int b7;
  262. } intblock;
  263. PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count)
  264. {
  265. if ((((int)dest | (int)src) & 3) == 0)
  266. {
  267. if (count >= 32) {
  268. memcpy32((int *)dest, (int *)src, count/2);
  269. count&=1;
  270. } else {
  271. for (; count >= 2; count -= 2, dest+=2, src+=2)
  272. *(int *)dest = *(int *)src;
  273. }
  274. }
  275. while (count--)
  276. *dest++ = *src++;
  277. }
  278. PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count)
  279. {
  280. unsigned char *src_ = src;
  281. for (; count; count--, src_ += 2)
  282. *dest++ = (src_[0] << 8) | src_[1];
  283. }
  284. #ifndef _ASM_MISC_C_AMIPS
  285. PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count)
  286. {
  287. intblock *bd = (intblock *) dest, *bs = (intblock *) src;
  288. for (; count >= sizeof(*bd)/4; count -= sizeof(*bd)/4)
  289. *bd++ = *bs++;
  290. dest = (int *)bd; src = (int *)bs;
  291. while (count--)
  292. *dest++ = *src++;
  293. }
  294. PICO_INTERNAL_ASM void memset32(int *dest, int c, int count)
  295. {
  296. for (; count >= 8; count -= 8, dest += 8)
  297. dest[0] = dest[1] = dest[2] = dest[3] =
  298. dest[4] = dest[5] = dest[6] = dest[7] = c;
  299. while (count--)
  300. *dest++ = c;
  301. }
  302. void memset32_uncached(int *dest, int c, int count) { memset32(dest, c, count); }
  303. #endif
  304. #endif