m68k_in.c 240 KB

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  1. /*
  2. must fix:
  3. callm
  4. chk
  5. */
  6. /* ======================================================================== */
  7. /* ========================= LICENSING & COPYRIGHT ======================== */
  8. /* ======================================================================== */
  9. /*
  10. * MUSASHI
  11. * Version 3.31
  12. *
  13. * A portable Motorola M680x0 processor emulation engine.
  14. * Copyright 1998-2007 Karl Stenerud. All rights reserved.
  15. *
  16. * This code may be freely used for non-commercial purposes as long as this
  17. * copyright notice remains unaltered in the source code and any binary files
  18. * containing this code in compiled form.
  19. *
  20. * All other lisencing terms must be negotiated with the author
  21. * (Karl Stenerud).
  22. *
  23. * The latest version of this code can be obtained at:
  24. * http://kstenerud.cjb.net
  25. */
  26. /* Special thanks to Bart Trzynadlowski for his insight into the
  27. * undocumented features of this chip:
  28. *
  29. * http://dynarec.com/~bart/files/68knotes.txt
  30. */
  31. /* Input file for m68kmake
  32. * -----------------------
  33. *
  34. * All sections begin with 80 X's in a row followed by an end-of-line
  35. * sequence.
  36. * After this, m68kmake will expect to find one of the following section
  37. * identifiers:
  38. * M68KMAKE_PROTOTYPE_HEADER - header for opcode handler prototypes
  39. * M68KMAKE_PROTOTYPE_FOOTER - footer for opcode handler prototypes
  40. * M68KMAKE_TABLE_HEADER - header for opcode handler jumptable
  41. * M68KMAKE_TABLE_FOOTER - footer for opcode handler jumptable
  42. * M68KMAKE_TABLE_BODY - the table itself
  43. * M68KMAKE_OPCODE_HANDLER_HEADER - header for opcode handler implementation
  44. * M68KMAKE_OPCODE_HANDLER_FOOTER - footer for opcode handler implementation
  45. * M68KMAKE_OPCODE_HANDLER_BODY - body section for opcode handler implementation
  46. *
  47. * NOTE: M68KMAKE_OPCODE_HANDLER_BODY must be last in the file and
  48. * M68KMAKE_TABLE_BODY must be second last in the file.
  49. *
  50. * The M68KMAKE_OPHANDLER_BODY section contains the opcode handler
  51. * primitives themselves. Each opcode handler begins with:
  52. * M68KMAKE_OP(A, B, C, D)
  53. *
  54. * where A is the opcode handler name, B is the size of the operation,
  55. * C denotes any special processing mode, and D denotes a specific
  56. * addressing mode.
  57. * For C and D where nothing is specified, use "."
  58. *
  59. * Example:
  60. * M68KMAKE_OP(abcd, 8, rr, .) abcd, size 8, register to register, default EA
  61. * M68KMAKE_OP(abcd, 8, mm, ax7) abcd, size 8, memory to memory, register X is A7
  62. * M68KMAKE_OP(tst, 16, ., pcix) tst, size 16, PCIX addressing
  63. *
  64. * All opcode handler primitives end with a closing curly brace "}" at column 1
  65. *
  66. * NOTE: Do not place a M68KMAKE_OP() directive inside the opcode handler,
  67. * and do not put a closing curly brace at column 1 unless it is
  68. * marking the end of the handler!
  69. *
  70. * Inside the handler, m68kmake will recognize M68KMAKE_GET_OPER_xx_xx,
  71. * M68KMAKE_GET_EA_xx_xx, and M68KMAKE_CC directives, and create multiple
  72. * opcode handlers to handle variations in the opcode handler.
  73. * Note: M68KMAKE_CC will only be interpreted in condition code opcodes.
  74. * As well, M68KMAKE_GET_EA_xx_xx and M68KMAKE_GET_OPER_xx_xx will only
  75. * be interpreted on instructions where the corresponding table entry
  76. * specifies multiple effective addressing modes.
  77. * Example:
  78. * clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4
  79. *
  80. * This table entry says that the clr.l opcde has 7 variations (A+-DXWL).
  81. * It is run in user or supervisor mode for all CPUs, and uses 12 cycles for
  82. * 68000, 6 cycles for 68010, and 4 cycles for 68020.
  83. */
  84. XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  85. M68KMAKE_PROTOTYPE_HEADER
  86. #ifndef M68KOPS__HEADER
  87. #define M68KOPS__HEADER
  88. /* ======================================================================== */
  89. /* ============================ OPCODE HANDLERS =========================== */
  90. /* ======================================================================== */
  91. XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  92. M68KMAKE_PROTOTYPE_FOOTER
  93. /* Build the opcode handler table */
  94. void m68ki_build_opcode_table(void);
  95. extern void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
  96. extern unsigned char m68ki_cycles[][0x10000];
  97. /* ======================================================================== */
  98. /* ============================== END OF FILE ============================= */
  99. /* ======================================================================== */
  100. #endif /* M68KOPS__HEADER */
  101. XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  102. M68KMAKE_TABLE_HEADER
  103. /* ======================================================================== */
  104. /* ========================= OPCODE TABLE BUILDER ========================= */
  105. /* ======================================================================== */
  106. #include "m68kops.h"
  107. #define NUM_CPU_TYPES 4
  108. void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
  109. unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */
  110. /* This is used to generate the opcode handler jump table */
  111. typedef struct
  112. {
  113. void (*opcode_handler)(void); /* handler function */
  114. unsigned int mask; /* mask on opcode */
  115. unsigned int match; /* what to match after masking */
  116. unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */
  117. } opcode_handler_struct;
  118. /* Opcode handler table */
  119. static opcode_handler_struct m68k_opcode_handler_table[] =
  120. {
  121. /* function mask match 000 010 020 040 */
  122. XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  123. M68KMAKE_TABLE_FOOTER
  124. {0, 0, 0, {0, 0, 0, 0}}
  125. };
  126. /* Build the opcode handler jump table */
  127. void m68ki_build_opcode_table(void)
  128. {
  129. opcode_handler_struct *ostruct;
  130. int instr;
  131. int i;
  132. int j;
  133. int k;
  134. for(i = 0; i < 0x10000; i++)
  135. {
  136. /* default to illegal */
  137. m68ki_instruction_jump_table[i] = m68k_op_illegal;
  138. for(k=0;k<NUM_CPU_TYPES;k++)
  139. m68ki_cycles[k][i] = 0;
  140. }
  141. ostruct = m68k_opcode_handler_table;
  142. while(ostruct->mask != 0xff00)
  143. {
  144. for(i = 0;i < 0x10000;i++)
  145. {
  146. if((i & ostruct->mask) == ostruct->match)
  147. {
  148. m68ki_instruction_jump_table[i] = ostruct->opcode_handler;
  149. for(k=0;k<NUM_CPU_TYPES;k++)
  150. m68ki_cycles[k][i] = ostruct->cycles[k];
  151. }
  152. }
  153. ostruct++;
  154. }
  155. while(ostruct->mask == 0xff00)
  156. {
  157. for(i = 0;i <= 0xff;i++)
  158. {
  159. m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
  160. for(k=0;k<NUM_CPU_TYPES;k++)
  161. m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
  162. }
  163. ostruct++;
  164. }
  165. while(ostruct->mask == 0xf1f8)
  166. {
  167. for(i = 0;i < 8;i++)
  168. {
  169. for(j = 0;j < 8;j++)
  170. {
  171. instr = ostruct->match | (i << 9) | j;
  172. m68ki_instruction_jump_table[instr] = ostruct->opcode_handler;
  173. for(k=0;k<NUM_CPU_TYPES;k++)
  174. m68ki_cycles[k][instr] = ostruct->cycles[k];
  175. }
  176. }
  177. ostruct++;
  178. }
  179. while(ostruct->mask == 0xfff0)
  180. {
  181. for(i = 0;i <= 0x0f;i++)
  182. {
  183. m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
  184. for(k=0;k<NUM_CPU_TYPES;k++)
  185. m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
  186. }
  187. ostruct++;
  188. }
  189. while(ostruct->mask == 0xf1ff)
  190. {
  191. for(i = 0;i <= 0x07;i++)
  192. {
  193. m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler;
  194. for(k=0;k<NUM_CPU_TYPES;k++)
  195. m68ki_cycles[k][ostruct->match | (i << 9)] = ostruct->cycles[k];
  196. }
  197. ostruct++;
  198. }
  199. while(ostruct->mask == 0xfff8)
  200. {
  201. for(i = 0;i <= 0x07;i++)
  202. {
  203. m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
  204. for(k=0;k<NUM_CPU_TYPES;k++)
  205. m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
  206. }
  207. ostruct++;
  208. }
  209. while(ostruct->mask == 0xffff)
  210. {
  211. m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler;
  212. for(k=0;k<NUM_CPU_TYPES;k++)
  213. m68ki_cycles[k][ostruct->match] = ostruct->cycles[k];
  214. ostruct++;
  215. }
  216. }
  217. /* ======================================================================== */
  218. /* ============================== END OF FILE ============================= */
  219. /* ======================================================================== */
  220. XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  221. M68KMAKE_OPCODE_HANDLER_HEADER
  222. #include "m68kcpu.h"
  223. extern void m68040_fpu_op0(void);
  224. extern void m68040_fpu_op1(void);
  225. /* ======================================================================== */
  226. /* ========================= INSTRUCTION HANDLERS ========================= */
  227. /* ======================================================================== */
  228. XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  229. M68KMAKE_OPCODE_HANDLER_FOOTER
  230. /* ======================================================================== */
  231. /* ============================== END OF FILE ============================= */
  232. /* ======================================================================== */
  233. XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  234. M68KMAKE_TABLE_BODY
  235. The following table is arranged as follows:
  236. name: Opcode mnemonic
  237. size: Operation size
  238. spec proc: Special processing mode:
  239. .: normal
  240. s: static operand
  241. r: register operand
  242. rr: register to register
  243. mm: memory to memory
  244. er: effective address to register
  245. re: register to effective address
  246. dd: data register to data register
  247. da: data register to address register
  248. aa: address register to address register
  249. cr: control register to register
  250. rc: register to control register
  251. toc: to condition code register
  252. tos: to status register
  253. tou: to user stack pointer
  254. frc: from condition code register
  255. frs: from status register
  256. fru: from user stack pointer
  257. * for move.x, the special processing mode is a specific
  258. destination effective addressing mode.
  259. spec ea: Specific effective addressing mode:
  260. .: normal
  261. i: immediate
  262. d: data register
  263. a: address register
  264. ai: address register indirect
  265. pi: address register indirect with postincrement
  266. pd: address register indirect with predecrement
  267. di: address register indirect with displacement
  268. ix: address register indirect with index
  269. aw: absolute word address
  270. al: absolute long address
  271. pcdi: program counter relative with displacement
  272. pcix: program counter relative with index
  273. a7: register specified in instruction is A7
  274. ax7: register field X of instruction is A7
  275. ay7: register field Y of instruction is A7
  276. axy7: register fields X and Y of instruction are A7
  277. bit pattern: Pattern to recognize this opcode. "." means don't care.
  278. allowed ea: List of allowed addressing modes:
  279. .: not present
  280. A: address register indirect
  281. +: ARI (address register indirect) with postincrement
  282. -: ARI with predecrement
  283. D: ARI with displacement
  284. X: ARI with index
  285. W: absolute word address
  286. L: absolute long address
  287. d: program counter indirect with displacement
  288. x: program counter indirect with index
  289. I: immediate
  290. mode: CPU operating mode for each cpu type. U = user or supervisor,
  291. S = supervisor only, "." = opcode not present.
  292. cpu cycles: Base number of cycles required to execute this opcode on the
  293. specified CPU type.
  294. Use "." if CPU does not have this opcode.
  295. spec spec allowed ea mode cpu cycles
  296. name size proc ea bit pattern A+-DXWLdxI 0 1 2 4 000 010 020 040 comments
  297. ====== ==== ==== ==== ================ ========== = = = = === === === === =============
  298. M68KMAKE_TABLE_START
  299. 1010 0 . . 1010............ .......... U U U U 4 4 4 4
  300. 1111 0 . . 1111............ .......... U U U U 4 4 4 4
  301. 040fpu0 32 . . 11110010........ .......... . . . U . . . 0
  302. 040fpu1 32 . . 11110011........ .......... . . . U . . . 0
  303. abcd 8 rr . 1100...100000... .......... U U U U 6 6 4 4
  304. abcd 8 mm ax7 1100111100001... .......... U U U U 18 18 16 16
  305. abcd 8 mm ay7 1100...100001111 .......... U U U U 18 18 16 16
  306. abcd 8 mm axy7 1100111100001111 .......... U U U U 18 18 16 16
  307. abcd 8 mm . 1100...100001... .......... U U U U 18 18 16 16
  308. add 8 er d 1101...000000... .......... U U U U 4 4 2 2
  309. add 8 er . 1101...000...... A+-DXWLdxI U U U U 4 4 2 2
  310. add 16 er d 1101...001000... .......... U U U U 4 4 2 2
  311. add 16 er a 1101...001001... .......... U U U U 4 4 2 2
  312. add 16 er . 1101...001...... A+-DXWLdxI U U U U 4 4 2 2
  313. add 32 er d 1101...010000... .......... U U U U 6 6 2 2
  314. add 32 er a 1101...010001... .......... U U U U 6 6 2 2
  315. add 32 er . 1101...010...... A+-DXWLdxI U U U U 6 6 2 2
  316. add 8 re . 1101...100...... A+-DXWL... U U U U 8 8 4 4
  317. add 16 re . 1101...101...... A+-DXWL... U U U U 8 8 4 4
  318. add 32 re . 1101...110...... A+-DXWL... U U U U 12 12 4 4
  319. adda 16 . d 1101...011000... .......... U U U U 8 8 2 2
  320. adda 16 . a 1101...011001... .......... U U U U 8 8 2 2
  321. adda 16 . . 1101...011...... A+-DXWLdxI U U U U 8 8 2 2
  322. adda 32 . d 1101...111000... .......... U U U U 6 6 2 2
  323. adda 32 . a 1101...111001... .......... U U U U 6 6 2 2
  324. adda 32 . . 1101...111...... A+-DXWLdxI U U U U 6 6 2 2
  325. addi 8 . d 0000011000000... .......... U U U U 8 8 2 2
  326. addi 8 . . 0000011000...... A+-DXWL... U U U U 12 12 4 4
  327. addi 16 . d 0000011001000... .......... U U U U 8 8 2 2
  328. addi 16 . . 0000011001...... A+-DXWL... U U U U 12 12 4 4
  329. addi 32 . d 0000011010000... .......... U U U U 16 14 2 2
  330. addi 32 . . 0000011010...... A+-DXWL... U U U U 20 20 4 4
  331. addq 8 . d 0101...000000... .......... U U U U 4 4 2 2
  332. addq 8 . . 0101...000...... A+-DXWL... U U U U 8 8 4 4
  333. addq 16 . d 0101...001000... .......... U U U U 4 4 2 2
  334. addq 16 . a 0101...001001... .......... U U U U 4 4 2 2
  335. addq 16 . . 0101...001...... A+-DXWL... U U U U 8 8 4 4
  336. addq 32 . d 0101...010000... .......... U U U U 8 8 2 2
  337. addq 32 . a 0101...010001... .......... U U U U 8 8 2 2
  338. addq 32 . . 0101...010...... A+-DXWL... U U U U 12 12 4 4
  339. addx 8 rr . 1101...100000... .......... U U U U 4 4 2 2
  340. addx 16 rr . 1101...101000... .......... U U U U 4 4 2 2
  341. addx 32 rr . 1101...110000... .......... U U U U 8 6 2 2
  342. addx 8 mm ax7 1101111100001... .......... U U U U 18 18 12 12
  343. addx 8 mm ay7 1101...100001111 .......... U U U U 18 18 12 12
  344. addx 8 mm axy7 1101111100001111 .......... U U U U 18 18 12 12
  345. addx 8 mm . 1101...100001... .......... U U U U 18 18 12 12
  346. addx 16 mm . 1101...101001... .......... U U U U 18 18 12 12
  347. addx 32 mm . 1101...110001... .......... U U U U 30 30 12 12
  348. and 8 er d 1100...000000... .......... U U U U 4 4 2 2
  349. and 8 er . 1100...000...... A+-DXWLdxI U U U U 4 4 2 2
  350. and 16 er d 1100...001000... .......... U U U U 4 4 2 2
  351. and 16 er . 1100...001...... A+-DXWLdxI U U U U 4 4 2 2
  352. and 32 er d 1100...010000... .......... U U U U 6 6 2 2
  353. and 32 er . 1100...010...... A+-DXWLdxI U U U U 6 6 2 2
  354. and 8 re . 1100...100...... A+-DXWL... U U U U 8 8 4 4
  355. and 16 re . 1100...101...... A+-DXWL... U U U U 8 8 4 4
  356. and 32 re . 1100...110...... A+-DXWL... U U U U 12 12 4 4
  357. andi 16 toc . 0000001000111100 .......... U U U U 20 16 12 12
  358. andi 16 tos . 0000001001111100 .......... S S S S 20 16 12 12
  359. andi 8 . d 0000001000000... .......... U U U U 8 8 2 2
  360. andi 8 . . 0000001000...... A+-DXWL... U U U U 12 12 4 4
  361. andi 16 . d 0000001001000... .......... U U U U 8 8 2 2
  362. andi 16 . . 0000001001...... A+-DXWL... U U U U 12 12 4 4
  363. andi 32 . d 0000001010000... .......... U U U U 14 14 2 2
  364. andi 32 . . 0000001010...... A+-DXWL... U U U U 20 20 4 4
  365. asr 8 s . 1110...000000... .......... U U U U 6 6 6 6
  366. asr 16 s . 1110...001000... .......... U U U U 6 6 6 6
  367. asr 32 s . 1110...010000... .......... U U U U 8 8 6 6
  368. asr 8 r . 1110...000100... .......... U U U U 6 6 6 6
  369. asr 16 r . 1110...001100... .......... U U U U 6 6 6 6
  370. asr 32 r . 1110...010100... .......... U U U U 8 8 6 6
  371. asr 16 . . 1110000011...... A+-DXWL... U U U U 8 8 5 5
  372. asl 8 s . 1110...100000... .......... U U U U 6 6 8 8
  373. asl 16 s . 1110...101000... .......... U U U U 6 6 8 8
  374. asl 32 s . 1110...110000... .......... U U U U 8 8 8 8
  375. asl 8 r . 1110...100100... .......... U U U U 6 6 8 8
  376. asl 16 r . 1110...101100... .......... U U U U 6 6 8 8
  377. asl 32 r . 1110...110100... .......... U U U U 8 8 8 8
  378. asl 16 . . 1110000111...... A+-DXWL... U U U U 8 8 6 6
  379. bcc 8 . . 0110............ .......... U U U U 10 10 6 6
  380. bcc 16 . . 0110....00000000 .......... U U U U 10 10 6 6
  381. bcc 32 . . 0110....11111111 .......... U U U U 10 10 6 6
  382. bchg 8 r . 0000...101...... A+-DXWL... U U U U 8 8 4 4
  383. bchg 32 r d 0000...101000... .......... U U U U 8 8 4 4
  384. bchg 8 s . 0000100001...... A+-DXWL... U U U U 12 12 4 4
  385. bchg 32 s d 0000100001000... .......... U U U U 12 12 4 4
  386. bclr 8 r . 0000...110...... A+-DXWL... U U U U 8 10 4 4
  387. bclr 32 r d 0000...110000... .......... U U U U 10 10 4 4
  388. bclr 8 s . 0000100010...... A+-DXWL... U U U U 12 12 4 4
  389. bclr 32 s d 0000100010000... .......... U U U U 14 14 4 4
  390. bfchg 32 . d 1110101011000... .......... . . U U . . 12 12 timing not quite correct
  391. bfchg 32 . . 1110101011...... A..DXWL... . . U U . . 20 20
  392. bfclr 32 . d 1110110011000... .......... . . U U . . 12 12
  393. bfclr 32 . . 1110110011...... A..DXWL... . . U U . . 20 20
  394. bfexts 32 . d 1110101111000... .......... . . U U . . 8 8
  395. bfexts 32 . . 1110101111...... A..DXWLdx. . . U U . . 15 15
  396. bfextu 32 . d 1110100111000... .......... . . U U . . 8 8
  397. bfextu 32 . . 1110100111...... A..DXWLdx. . . U U . . 15 15
  398. bfffo 32 . d 1110110111000... .......... . . U U . . 18 18
  399. bfffo 32 . . 1110110111...... A..DXWLdx. . . U U . . 28 28
  400. bfins 32 . d 1110111111000... .......... . . U U . . 10 10
  401. bfins 32 . . 1110111111...... A..DXWL... . . U U . . 17 17
  402. bfset 32 . d 1110111011000... .......... . . U U . . 12 12
  403. bfset 32 . . 1110111011...... A..DXWL... . . U U . . 20 20
  404. bftst 32 . d 1110100011000... .......... . . U U . . 6 6
  405. bftst 32 . . 1110100011...... A..DXWLdx. . . U U . . 13 13
  406. bkpt 0 . . 0100100001001... .......... . U U U . 10 10 10
  407. bra 8 . . 01100000........ .......... U U U U 10 10 10 10
  408. bra 16 . . 0110000000000000 .......... U U U U 10 10 10 10
  409. bra 32 . . 0110000011111111 .......... U U U U 10 10 10 10
  410. bset 32 r d 0000...111000... .......... U U U U 8 8 4 4
  411. bset 8 r . 0000...111...... A+-DXWL... U U U U 8 8 4 4
  412. bset 8 s . 0000100011...... A+-DXWL... U U U U 12 12 4 4
  413. bset 32 s d 0000100011000... .......... U U U U 12 12 4 4
  414. bsr 8 . . 01100001........ .......... U U U U 18 18 7 7
  415. bsr 16 . . 0110000100000000 .......... U U U U 18 18 7 7
  416. bsr 32 . . 0110000111111111 .......... U U U U 18 18 7 7
  417. btst 8 r . 0000...100...... A+-DXWLdxI U U U U 4 4 4 4
  418. btst 32 r d 0000...100000... .......... U U U U 6 6 4 4
  419. btst 8 s . 0000100000...... A+-DXWLdx. U U U U 8 8 4 4
  420. btst 32 s d 0000100000000... .......... U U U U 10 10 4 4
  421. callm 32 . . 0000011011...... A..DXWLdx. . . U U . . 60 60 not properly emulated
  422. cas 8 . . 0000101011...... A+-DXWL... . . U U . . 12 12
  423. cas 16 . . 0000110011...... A+-DXWL... . . U U . . 12 12
  424. cas 32 . . 0000111011...... A+-DXWL... . . U U . . 12 12
  425. cas2 16 . . 0000110011111100 .......... . . U U . . 12 12
  426. cas2 32 . . 0000111011111100 .......... . . U U . . 12 12
  427. chk 16 . d 0100...110000... .......... U U U U 10 8 8 8
  428. chk 16 . . 0100...110...... A+-DXWLdxI U U U U 10 8 8 8
  429. chk 32 . d 0100...100000... .......... . . U U . . 8 8
  430. chk 32 . . 0100...100...... A+-DXWLdxI . . U U . . 8 8
  431. chk2cmp2 8 . pcdi 0000000011111010 .......... . . U U . . 23 23
  432. chk2cmp2 8 . pcix 0000000011111011 .......... . . U U . . 23 23
  433. chk2cmp2 8 . . 0000000011...... A..DXWL... . . U U . . 18 18
  434. chk2cmp2 16 . pcdi 0000001011111010 .......... . . U U . . 23 23
  435. chk2cmp2 16 . pcix 0000001011111011 .......... . . U U . . 23 23
  436. chk2cmp2 16 . . 0000001011...... A..DXWL... . . U U . . 18 18
  437. chk2cmp2 32 . pcdi 0000010011111010 .......... . . U U . . 23 23
  438. chk2cmp2 32 . pcix 0000010011111011 .......... . . U U . . 23 23
  439. chk2cmp2 32 . . 0000010011...... A..DXWL... . . U U . . 18 18
  440. clr 8 . d 0100001000000... .......... U U U U 4 4 2 2
  441. clr 8 . . 0100001000...... A+-DXWL... U U U U 6 4 4 4 notaz hack: changed 000 cycles 8 -> 6 like in starscream for Fatal Rewind
  442. clr 16 . d 0100001001000... .......... U U U U 4 4 2 2
  443. clr 16 . . 0100001001...... A+-DXWL... U U U U 6 4 4 4 notaz hack: ditto
  444. clr 32 . d 0100001010000... .......... U U U U 6 6 2 2
  445. clr 32 . . 0100001010...... A+-DXWL... U U U U 12 6 4 4
  446. cmp 8 . d 1011...000000... .......... U U U U 4 4 2 2
  447. cmp 8 . . 1011...000...... A+-DXWLdxI U U U U 4 4 2 2
  448. cmp 16 . d 1011...001000... .......... U U U U 4 4 2 2
  449. cmp 16 . a 1011...001001... .......... U U U U 4 4 2 2
  450. cmp 16 . . 1011...001...... A+-DXWLdxI U U U U 4 4 2 2
  451. cmp 32 . d 1011...010000... .......... U U U U 6 6 2 2
  452. cmp 32 . a 1011...010001... .......... U U U U 6 6 2 2
  453. cmp 32 . . 1011...010...... A+-DXWLdxI U U U U 6 6 2 2
  454. cmpa 16 . d 1011...011000... .......... U U U U 6 6 4 4
  455. cmpa 16 . a 1011...011001... .......... U U U U 6 6 4 4
  456. cmpa 16 . . 1011...011...... A+-DXWLdxI U U U U 6 6 4 4
  457. cmpa 32 . d 1011...111000... .......... U U U U 6 6 4 4
  458. cmpa 32 . a 1011...111001... .......... U U U U 6 6 4 4
  459. cmpa 32 . . 1011...111...... A+-DXWLdxI U U U U 6 6 4 4
  460. cmpi 8 . d 0000110000000... .......... U U U U 8 8 2 2
  461. cmpi 8 . . 0000110000...... A+-DXWL... U U U U 8 8 2 2
  462. cmpi 8 . pcdi 0000110000111010 .......... . . U U . . 7 7
  463. cmpi 8 . pcix 0000110000111011 .......... . . U U . . 9 9
  464. cmpi 16 . d 0000110001000... .......... U U U U 8 8 2 2
  465. cmpi 16 . . 0000110001...... A+-DXWL... U U U U 8 8 2 2
  466. cmpi 16 . pcdi 0000110001111010 .......... . . U U . . 7 7
  467. cmpi 16 . pcix 0000110001111011 .......... . . U U . . 9 9
  468. cmpi 32 . d 0000110010000... .......... U U U U 14 12 2 2
  469. cmpi 32 . . 0000110010...... A+-DXWL... U U U U 12 12 2 2
  470. cmpi 32 . pcdi 0000110010111010 .......... . . U U . . 7 7
  471. cmpi 32 . pcix 0000110010111011 .......... . . U U . . 9 9
  472. cmpm 8 . ax7 1011111100001... .......... U U U U 12 12 9 9
  473. cmpm 8 . ay7 1011...100001111 .......... U U U U 12 12 9 9
  474. cmpm 8 . axy7 1011111100001111 .......... U U U U 12 12 9 9
  475. cmpm 8 . . 1011...100001... .......... U U U U 12 12 9 9
  476. cmpm 16 . . 1011...101001... .......... U U U U 12 12 9 9
  477. cmpm 32 . . 1011...110001... .......... U U U U 20 20 9 9
  478. cpbcc 32 . . 1111...01....... .......... . . U . . . 4 . unemulated
  479. cpdbcc 32 . . 1111...001001... .......... . . U . . . 4 . unemulated
  480. cpgen 32 . . 1111...000...... .......... . . U . . . 4 . unemulated
  481. cpscc 32 . . 1111...001...... .......... . . U . . . 4 . unemulated
  482. cptrapcc 32 . . 1111...001111... .......... . . U . . . 4 . unemulated
  483. dbt 16 . . 0101000011001... .......... U U U U 12 12 6 6
  484. dbf 16 . . 0101000111001... .......... U U U U 12 12 6 6
  485. dbcc 16 . . 0101....11001... .......... U U U U 12 12 6 6
  486. divs 16 . d 1000...111000... .......... U U U U 158 122 56 56
  487. divs 16 . . 1000...111...... A+-DXWLdxI U U U U 158 122 56 56
  488. divu 16 . d 1000...011000... .......... U U U U 140 108 44 44
  489. divu 16 . . 1000...011...... A+-DXWLdxI U U U U 140 108 44 44
  490. divl 32 . d 0100110001000... .......... . . U U . . 84 84
  491. divl 32 . . 0100110001...... A+-DXWLdxI . . U U . . 84 84
  492. eor 8 . d 1011...100000... .......... U U U U 4 4 2 2
  493. eor 8 . . 1011...100...... A+-DXWL... U U U U 8 8 4 4
  494. eor 16 . d 1011...101000... .......... U U U U 4 4 2 2
  495. eor 16 . . 1011...101...... A+-DXWL... U U U U 8 8 4 4
  496. eor 32 . d 1011...110000... .......... U U U U 8 6 2 2
  497. eor 32 . . 1011...110...... A+-DXWL... U U U U 12 12 4 4
  498. eori 16 toc . 0000101000111100 .......... U U U U 20 16 12 12
  499. eori 16 tos . 0000101001111100 .......... S S S S 20 16 12 12
  500. eori 8 . d 0000101000000... .......... U U U U 8 8 2 2
  501. eori 8 . . 0000101000...... A+-DXWL... U U U U 12 12 4 4
  502. eori 16 . d 0000101001000... .......... U U U U 8 8 2 2
  503. eori 16 . . 0000101001...... A+-DXWL... U U U U 12 12 4 4
  504. eori 32 . d 0000101010000... .......... U U U U 16 14 2 2
  505. eori 32 . . 0000101010...... A+-DXWL... U U U U 20 20 4 4
  506. exg 32 dd . 1100...101000... .......... U U U U 6 6 2 2
  507. exg 32 aa . 1100...101001... .......... U U U U 6 6 2 2
  508. exg 32 da . 1100...110001... .......... U U U U 6 6 2 2
  509. ext 16 . . 0100100010000... .......... U U U U 4 4 4 4
  510. ext 32 . . 0100100011000... .......... U U U U 4 4 4 4
  511. extb 32 . . 0100100111000... .......... . . U U . . 4 4
  512. illegal 0 . . 0100101011111100 .......... U U U U 4 4 4 4
  513. jmp 32 . . 0100111011...... A..DXWLdx. U U U U 4 4 0 0
  514. jsr 32 . . 0100111010...... A..DXWLdx. U U U U 12 12 0 0
  515. lea 32 . . 0100...111...... A..DXWLdx. U U U U 0 0 2 2
  516. link 16 . a7 0100111001010111 .......... U U U U 16 16 5 5
  517. link 16 . . 0100111001010... .......... U U U U 16 16 5 5
  518. link 32 . a7 0100100000001111 .......... . . U U . . 6 6
  519. link 32 . . 0100100000001... .......... . . U U . . 6 6
  520. lsr 8 s . 1110...000001... .......... U U U U 6 6 4 4
  521. lsr 16 s . 1110...001001... .......... U U U U 6 6 4 4
  522. lsr 32 s . 1110...010001... .......... U U U U 8 8 4 4
  523. lsr 8 r . 1110...000101... .......... U U U U 6 6 6 6
  524. lsr 16 r . 1110...001101... .......... U U U U 6 6 6 6
  525. lsr 32 r . 1110...010101... .......... U U U U 8 8 6 6
  526. lsr 16 . . 1110001011...... A+-DXWL... U U U U 8 8 5 5
  527. lsl 8 s . 1110...100001... .......... U U U U 6 6 4 4
  528. lsl 16 s . 1110...101001... .......... U U U U 6 6 4 4
  529. lsl 32 s . 1110...110001... .......... U U U U 8 8 4 4
  530. lsl 8 r . 1110...100101... .......... U U U U 6 6 6 6
  531. lsl 16 r . 1110...101101... .......... U U U U 6 6 6 6
  532. lsl 32 r . 1110...110101... .......... U U U U 8 8 6 6
  533. lsl 16 . . 1110001111...... A+-DXWL... U U U U 8 8 5 5
  534. move 8 d d 0001...000000... .......... U U U U 4 4 2 2
  535. move 8 d . 0001...000...... A+-DXWLdxI U U U U 4 4 2 2
  536. move 8 ai d 0001...010000... .......... U U U U 8 8 4 4
  537. move 8 ai . 0001...010...... A+-DXWLdxI U U U U 8 8 4 4
  538. move 8 pi d 0001...011000... .......... U U U U 8 8 4 4
  539. move 8 pi . 0001...011...... A+-DXWLdxI U U U U 8 8 4 4
  540. move 8 pi7 d 0001111011000... .......... U U U U 8 8 4 4
  541. move 8 pi7 . 0001111011...... A+-DXWLdxI U U U U 8 8 4 4
  542. move 8 pd d 0001...100000... .......... U U U U 8 8 5 5
  543. move 8 pd . 0001...100...... A+-DXWLdxI U U U U 8 8 5 5
  544. move 8 pd7 d 0001111100000... .......... U U U U 8 8 5 5
  545. move 8 pd7 . 0001111100...... A+-DXWLdxI U U U U 8 8 5 5
  546. move 8 di d 0001...101000... .......... U U U U 12 12 5 5
  547. move 8 di . 0001...101...... A+-DXWLdxI U U U U 12 12 5 5
  548. move 8 ix d 0001...110000... .......... U U U U 14 14 7 7
  549. move 8 ix . 0001...110...... A+-DXWLdxI U U U U 14 14 7 7
  550. move 8 aw d 0001000111000... .......... U U U U 12 12 4 4
  551. move 8 aw . 0001000111...... A+-DXWLdxI U U U U 12 12 4 4
  552. move 8 al d 0001001111000... .......... U U U U 16 16 6 6
  553. move 8 al . 0001001111...... A+-DXWLdxI U U U U 16 16 6 6
  554. move 16 d d 0011...000000... .......... U U U U 4 4 2 2
  555. move 16 d a 0011...000001... .......... U U U U 4 4 2 2
  556. move 16 d . 0011...000...... A+-DXWLdxI U U U U 4 4 2 2
  557. move 16 ai d 0011...010000... .......... U U U U 8 8 4 4
  558. move 16 ai a 0011...010001... .......... U U U U 8 8 4 4
  559. move 16 ai . 0011...010...... A+-DXWLdxI U U U U 8 8 4 4
  560. move 16 pi d 0011...011000... .......... U U U U 8 8 4 4
  561. move 16 pi a 0011...011001... .......... U U U U 8 8 4 4
  562. move 16 pi . 0011...011...... A+-DXWLdxI U U U U 8 8 4 4
  563. move 16 pd d 0011...100000... .......... U U U U 8 8 5 5
  564. move 16 pd a 0011...100001... .......... U U U U 8 8 5 5
  565. move 16 pd . 0011...100...... A+-DXWLdxI U U U U 8 8 5 5
  566. move 16 di d 0011...101000... .......... U U U U 12 12 5 5
  567. move 16 di a 0011...101001... .......... U U U U 12 12 5 5
  568. move 16 di . 0011...101...... A+-DXWLdxI U U U U 12 12 5 5
  569. move 16 ix d 0011...110000... .......... U U U U 14 14 7 7
  570. move 16 ix a 0011...110001... .......... U U U U 14 14 7 7
  571. move 16 ix . 0011...110...... A+-DXWLdxI U U U U 14 14 7 7
  572. move 16 aw d 0011000111000... .......... U U U U 12 12 4 4
  573. move 16 aw a 0011000111001... .......... U U U U 12 12 4 4
  574. move 16 aw . 0011000111...... A+-DXWLdxI U U U U 12 12 4 4
  575. move 16 al d 0011001111000... .......... U U U U 16 16 6 6
  576. move 16 al a 0011001111001... .......... U U U U 16 16 6 6
  577. move 16 al . 0011001111...... A+-DXWLdxI U U U U 16 16 6 6
  578. move 32 d d 0010...000000... .......... U U U U 4 4 2 2
  579. move 32 d a 0010...000001... .......... U U U U 4 4 2 2
  580. move 32 d . 0010...000...... A+-DXWLdxI U U U U 4 4 2 2
  581. move 32 ai d 0010...010000... .......... U U U U 12 12 4 4
  582. move 32 ai a 0010...010001... .......... U U U U 12 12 4 4
  583. move 32 ai . 0010...010...... A+-DXWLdxI U U U U 12 12 4 4
  584. move 32 pi d 0010...011000... .......... U U U U 12 12 4 4
  585. move 32 pi a 0010...011001... .......... U U U U 12 12 4 4
  586. move 32 pi . 0010...011...... A+-DXWLdxI U U U U 12 12 4 4
  587. move 32 pd d 0010...100000... .......... U U U U 12 14 5 5
  588. move 32 pd a 0010...100001... .......... U U U U 12 14 5 5
  589. move 32 pd . 0010...100...... A+-DXWLdxI U U U U 12 14 5 5
  590. move 32 di d 0010...101000... .......... U U U U 16 16 5 5
  591. move 32 di a 0010...101001... .......... U U U U 16 16 5 5
  592. move 32 di . 0010...101...... A+-DXWLdxI U U U U 16 16 5 5
  593. move 32 ix d 0010...110000... .......... U U U U 18 18 7 7
  594. move 32 ix a 0010...110001... .......... U U U U 18 18 7 7
  595. move 32 ix . 0010...110...... A+-DXWLdxI U U U U 18 18 7 7
  596. move 32 aw d 0010000111000... .......... U U U U 16 16 4 4
  597. move 32 aw a 0010000111001... .......... U U U U 16 16 4 4
  598. move 32 aw . 0010000111...... A+-DXWLdxI U U U U 16 16 4 4
  599. move 32 al d 0010001111000... .......... U U U U 20 20 6 6
  600. move 32 al a 0010001111001... .......... U U U U 20 20 6 6
  601. move 32 al . 0010001111...... A+-DXWLdxI U U U U 20 20 6 6
  602. movea 16 . d 0011...001000... .......... U U U U 4 4 2 2
  603. movea 16 . a 0011...001001... .......... U U U U 4 4 2 2
  604. movea 16 . . 0011...001...... A+-DXWLdxI U U U U 4 4 2 2
  605. movea 32 . d 0010...001000... .......... U U U U 4 4 2 2
  606. movea 32 . a 0010...001001... .......... U U U U 4 4 2 2
  607. movea 32 . . 0010...001...... A+-DXWLdxI U U U U 4 4 2 2
  608. move 16 frc d 0100001011000... .......... . U U U . 4 4 4
  609. move 16 frc . 0100001011...... A+-DXWL... . U U U . 8 4 4
  610. move 16 toc d 0100010011000... .......... U U U U 12 12 4 4
  611. move 16 toc . 0100010011...... A+-DXWLdxI U U U U 12 12 4 4
  612. move 16 frs d 0100000011000... .......... U S S S 6 4 8 8 U only for 000
  613. move 16 frs . 0100000011...... A+-DXWL... U S S S 8 8 8 8 U only for 000
  614. move 16 tos d 0100011011000... .......... S S S S 12 12 8 8
  615. move 16 tos . 0100011011...... A+-DXWLdxI S S S S 12 12 8 8
  616. move 32 fru . 0100111001101... .......... S S S S 4 6 2 2
  617. move 32 tou . 0100111001100... .......... S S S S 4 6 2 2
  618. movec 32 cr . 0100111001111010 .......... . S S S . 12 6 6
  619. movec 32 rc . 0100111001111011 .......... . S S S . 10 12 12
  620. movem 16 re pd 0100100010100... .......... U U U U 8 8 4 4
  621. movem 16 re . 0100100010...... A..DXWL... U U U U 8 8 4 4
  622. movem 32 re pd 0100100011100... .......... U U U U 8 8 4 4
  623. movem 32 re . 0100100011...... A..DXWL... U U U U 8 8 4 4
  624. movem 16 er pi 0100110010011... .......... U U U U 12 12 8 8
  625. movem 16 er pcdi 0100110010111010 .......... U U U U 16 16 9 9
  626. movem 16 er pcix 0100110010111011 .......... U U U U 18 18 11 11
  627. movem 16 er . 0100110010...... A..DXWL... U U U U 12 12 8 8
  628. movem 32 er pi 0100110011011... .......... U U U U 12 12 8 8
  629. movem 32 er pcdi 0100110011111010 .......... U U U U 16 16 9 9
  630. movem 32 er pcix 0100110011111011 .......... U U U U 18 18 11 11
  631. movem 32 er . 0100110011...... A..DXWL... U U U U 12 12 8 8
  632. movep 16 er . 0000...100001... .......... U U U U 16 16 12 12
  633. movep 32 er . 0000...101001... .......... U U U U 24 24 18 18
  634. movep 16 re . 0000...110001... .......... U U U U 16 16 11 11
  635. movep 32 re . 0000...111001... .......... U U U U 24 24 17 17
  636. moveq 32 . . 0111...0........ .......... U U U U 4 4 2 2
  637. moves 8 . . 0000111000...... A+-DXWL... . S S S . 14 5 5
  638. moves 16 . . 0000111001...... A+-DXWL... . S S S . 14 5 5
  639. moves 32 . . 0000111010...... A+-DXWL... . S S S . 16 5 5
  640. move16 32 . . 1111011000100... .......... . . . U . . . 4 TODO: correct timing
  641. muls 16 . d 1100...111000... .......... U U U U 54 32 27 27
  642. muls 16 . . 1100...111...... A+-DXWLdxI U U U U 54 32 27 27
  643. mulu 16 . d 1100...011000... .......... U U U U 54 30 27 27
  644. mulu 16 . . 1100...011...... A+-DXWLdxI U U U U 54 30 27 27
  645. mull 32 . d 0100110000000... .......... . . U U . . 43 43
  646. mull 32 . . 0100110000...... A+-DXWLdxI . . U U . . 43 43
  647. nbcd 8 . d 0100100000000... .......... U U U U 6 6 6 6
  648. nbcd 8 . . 0100100000...... A+-DXWL... U U U U 8 8 6 6
  649. neg 8 . d 0100010000000... .......... U U U U 4 4 2 2
  650. neg 8 . . 0100010000...... A+-DXWL... U U U U 8 8 4 4
  651. neg 16 . d 0100010001000... .......... U U U U 4 4 2 2
  652. neg 16 . . 0100010001...... A+-DXWL... U U U U 8 8 4 4
  653. neg 32 . d 0100010010000... .......... U U U U 6 6 2 2
  654. neg 32 . . 0100010010...... A+-DXWL... U U U U 12 12 4 4
  655. negx 8 . d 0100000000000... .......... U U U U 4 4 2 2
  656. negx 8 . . 0100000000...... A+-DXWL... U U U U 8 8 4 4
  657. negx 16 . d 0100000001000... .......... U U U U 4 4 2 2
  658. negx 16 . . 0100000001...... A+-DXWL... U U U U 8 8 4 4
  659. negx 32 . d 0100000010000... .......... U U U U 6 6 2 2
  660. negx 32 . . 0100000010...... A+-DXWL... U U U U 12 12 4 4
  661. nop 0 . . 0100111001110001 .......... U U U U 4 4 2 2
  662. not 8 . d 0100011000000... .......... U U U U 4 4 2 2
  663. not 8 . . 0100011000...... A+-DXWL... U U U U 8 8 4 4
  664. not 16 . d 0100011001000... .......... U U U U 4 4 2 2
  665. not 16 . . 0100011001...... A+-DXWL... U U U U 8 8 4 4
  666. not 32 . d 0100011010000... .......... U U U U 6 6 2 2
  667. not 32 . . 0100011010...... A+-DXWL... U U U U 12 12 4 4
  668. or 8 er d 1000...000000... .......... U U U U 4 4 2 2
  669. or 8 er . 1000...000...... A+-DXWLdxI U U U U 4 4 2 2
  670. or 16 er d 1000...001000... .......... U U U U 4 4 2 2
  671. or 16 er . 1000...001...... A+-DXWLdxI U U U U 4 4 2 2
  672. or 32 er d 1000...010000... .......... U U U U 6 6 2 2
  673. or 32 er . 1000...010...... A+-DXWLdxI U U U U 6 6 2 2
  674. or 8 re . 1000...100...... A+-DXWL... U U U U 8 8 4 4
  675. or 16 re . 1000...101...... A+-DXWL... U U U U 8 8 4 4
  676. or 32 re . 1000...110...... A+-DXWL... U U U U 12 12 4 4
  677. ori 16 toc . 0000000000111100 .......... U U U U 20 16 12 12
  678. ori 16 tos . 0000000001111100 .......... S S S S 20 16 12 12
  679. ori 8 . d 0000000000000... .......... U U U U 8 8 2 2
  680. ori 8 . . 0000000000...... A+-DXWL... U U U U 12 12 4 4
  681. ori 16 . d 0000000001000... .......... U U U U 8 8 2 2
  682. ori 16 . . 0000000001...... A+-DXWL... U U U U 12 12 4 4
  683. ori 32 . d 0000000010000... .......... U U U U 16 14 2 2
  684. ori 32 . . 0000000010...... A+-DXWL... U U U U 20 20 4 4
  685. pack 16 rr . 1000...101000... .......... . . U U . . 6 6
  686. pack 16 mm ax7 1000111101001... .......... . . U U . . 13 13
  687. pack 16 mm ay7 1000...101001111 .......... . . U U . . 13 13
  688. pack 16 mm axy7 1000111101001111 .......... . . U U . . 13 13
  689. pack 16 mm . 1000...101001... .......... . . U U . . 13 13
  690. pea 32 . . 0100100001...... A..DXWLdx. U U U U 6 6 5 5
  691. pflush 32 . . 1111010100011000 .......... . . . S . . . 4 TODO: correct timing
  692. reset 0 . . 0100111001110000 .......... S S S S 0 0 0 0
  693. ror 8 s . 1110...000011... .......... U U U U 6 6 8 8
  694. ror 16 s . 1110...001011... .......... U U U U 6 6 8 8
  695. ror 32 s . 1110...010011... .......... U U U U 8 8 8 8
  696. ror 8 r . 1110...000111... .......... U U U U 6 6 8 8
  697. ror 16 r . 1110...001111... .......... U U U U 6 6 8 8
  698. ror 32 r . 1110...010111... .......... U U U U 8 8 8 8
  699. ror 16 . . 1110011011...... A+-DXWL... U U U U 8 8 7 7
  700. rol 8 s . 1110...100011... .......... U U U U 6 6 8 8
  701. rol 16 s . 1110...101011... .......... U U U U 6 6 8 8
  702. rol 32 s . 1110...110011... .......... U U U U 8 8 8 8
  703. rol 8 r . 1110...100111... .......... U U U U 6 6 8 8
  704. rol 16 r . 1110...101111... .......... U U U U 6 6 8 8
  705. rol 32 r . 1110...110111... .......... U U U U 8 8 8 8
  706. rol 16 . . 1110011111...... A+-DXWL... U U U U 8 8 7 7
  707. roxr 8 s . 1110...000010... .......... U U U U 6 6 12 12
  708. roxr 16 s . 1110...001010... .......... U U U U 6 6 12 12
  709. roxr 32 s . 1110...010010... .......... U U U U 8 8 12 12
  710. roxr 8 r . 1110...000110... .......... U U U U 6 6 12 12
  711. roxr 16 r . 1110...001110... .......... U U U U 6 6 12 12
  712. roxr 32 r . 1110...010110... .......... U U U U 8 8 12 12
  713. roxr 16 . . 1110010011...... A+-DXWL... U U U U 8 8 5 5
  714. roxl 8 s . 1110...100010... .......... U U U U 6 6 12 12
  715. roxl 16 s . 1110...101010... .......... U U U U 6 6 12 12
  716. roxl 32 s . 1110...110010... .......... U U U U 8 8 12 12
  717. roxl 8 r . 1110...100110... .......... U U U U 6 6 12 12
  718. roxl 16 r . 1110...101110... .......... U U U U 6 6 12 12
  719. roxl 32 r . 1110...110110... .......... U U U U 8 8 12 12
  720. roxl 16 . . 1110010111...... A+-DXWL... U U U U 8 8 5 5
  721. rtd 32 . . 0100111001110100 .......... . U U U . 16 10 10
  722. rte 32 . . 0100111001110011 .......... S S S S 20 24 20 20 bus fault not emulated
  723. rtm 32 . . 000001101100.... .......... . . U U . . 19 19 not properly emulated
  724. rtr 32 . . 0100111001110111 .......... U U U U 20 20 14 14
  725. rts 32 . . 0100111001110101 .......... U U U U 16 16 10 10
  726. sbcd 8 rr . 1000...100000... .......... U U U U 6 6 4 4
  727. sbcd 8 mm ax7 1000111100001... .......... U U U U 18 18 16 16
  728. sbcd 8 mm ay7 1000...100001111 .......... U U U U 18 18 16 16
  729. sbcd 8 mm axy7 1000111100001111 .......... U U U U 18 18 16 16
  730. sbcd 8 mm . 1000...100001... .......... U U U U 18 18 16 16
  731. st 8 . d 0101000011000... .......... U U U U 6 4 4 4
  732. st 8 . . 0101000011...... A+-DXWL... U U U U 8 8 6 6
  733. sf 8 . d 0101000111000... .......... U U U U 4 4 4 4
  734. sf 8 . . 0101000111...... A+-DXWL... U U U U 8 8 6 6
  735. scc 8 . d 0101....11000... .......... U U U U 4 4 4 4
  736. scc 8 . . 0101....11...... A+-DXWL... U U U U 8 8 6 6
  737. stop 0 . . 0100111001110010 .......... S S S S 4 4 8 8
  738. sub 8 er d 1001...000000... .......... U U U U 4 4 2 2
  739. sub 8 er . 1001...000...... A+-DXWLdxI U U U U 4 4 2 2
  740. sub 16 er d 1001...001000... .......... U U U U 4 4 2 2
  741. sub 16 er a 1001...001001... .......... U U U U 4 4 2 2
  742. sub 16 er . 1001...001...... A+-DXWLdxI U U U U 4 4 2 2
  743. sub 32 er d 1001...010000... .......... U U U U 6 6 2 2
  744. sub 32 er a 1001...010001... .......... U U U U 6 6 2 2
  745. sub 32 er . 1001...010...... A+-DXWLdxI U U U U 6 6 2 2
  746. sub 8 re . 1001...100...... A+-DXWL... U U U U 8 8 4 4
  747. sub 16 re . 1001...101...... A+-DXWL... U U U U 8 8 4 4
  748. sub 32 re . 1001...110...... A+-DXWL... U U U U 12 12 4 4
  749. suba 16 . d 1001...011000... .......... U U U U 8 8 2 2
  750. suba 16 . a 1001...011001... .......... U U U U 8 8 2 2
  751. suba 16 . . 1001...011...... A+-DXWLdxI U U U U 8 8 2 2
  752. suba 32 . d 1001...111000... .......... U U U U 6 6 2 2
  753. suba 32 . a 1001...111001... .......... U U U U 6 6 2 2
  754. suba 32 . . 1001...111...... A+-DXWLdxI U U U U 6 6 2 2
  755. subi 8 . d 0000010000000... .......... U U U U 8 8 2 2
  756. subi 8 . . 0000010000...... A+-DXWL... U U U U 12 12 4 4
  757. subi 16 . d 0000010001000... .......... U U U U 8 8 2 2
  758. subi 16 . . 0000010001...... A+-DXWL... U U U U 12 12 4 4
  759. subi 32 . d 0000010010000... .......... U U U U 16 14 2 2
  760. subi 32 . . 0000010010...... A+-DXWL... U U U U 20 20 4 4
  761. subq 8 . d 0101...100000... .......... U U U U 4 4 2 2
  762. subq 8 . . 0101...100...... A+-DXWL... U U U U 8 8 4 4
  763. subq 16 . d 0101...101000... .......... U U U U 4 4 2 2
  764. subq 16 . a 0101...101001... .......... U U U U 8 4 2 2
  765. subq 16 . . 0101...101...... A+-DXWL... U U U U 8 8 4 4
  766. subq 32 . d 0101...110000... .......... U U U U 8 8 2 2
  767. subq 32 . a 0101...110001... .......... U U U U 8 8 2 2
  768. subq 32 . . 0101...110...... A+-DXWL... U U U U 12 12 4 4
  769. subx 8 rr . 1001...100000... .......... U U U U 4 4 2 2
  770. subx 16 rr . 1001...101000... .......... U U U U 4 4 2 2
  771. subx 32 rr . 1001...110000... .......... U U U U 8 6 2 2
  772. subx 8 mm ax7 1001111100001... .......... U U U U 18 18 12 12
  773. subx 8 mm ay7 1001...100001111 .......... U U U U 18 18 12 12
  774. subx 8 mm axy7 1001111100001111 .......... U U U U 18 18 12 12
  775. subx 8 mm . 1001...100001... .......... U U U U 18 18 12 12
  776. subx 16 mm . 1001...101001... .......... U U U U 18 18 12 12
  777. subx 32 mm . 1001...110001... .......... U U U U 30 30 12 12
  778. swap 32 . . 0100100001000... .......... U U U U 4 4 4 4
  779. tas 8 . d 0100101011000... .......... U U U U 4 4 4 4
  780. tas 8 . . 0100101011...... A+-DXWL... U U U U 14 14 12 12
  781. trap 0 . . 010011100100.... .......... U U U U 4 4 4 4
  782. trapt 0 . . 0101000011111100 .......... . . U U . . 4 4
  783. trapt 16 . . 0101000011111010 .......... . . U U . . 6 6
  784. trapt 32 . . 0101000011111011 .......... . . U U . . 8 8
  785. trapf 0 . . 0101000111111100 .......... . . U U . . 4 4
  786. trapf 16 . . 0101000111111010 .......... . . U U . . 6 6
  787. trapf 32 . . 0101000111111011 .......... . . U U . . 8 8
  788. trapcc 0 . . 0101....11111100 .......... . . U U . . 4 4
  789. trapcc 16 . . 0101....11111010 .......... . . U U . . 6 6
  790. trapcc 32 . . 0101....11111011 .......... . . U U . . 8 8
  791. trapv 0 . . 0100111001110110 .......... U U U U 4 4 4 4
  792. tst 8 . d 0100101000000... .......... U U U U 4 4 2 2
  793. tst 8 . . 0100101000...... A+-DXWL... U U U U 4 4 2 2
  794. tst 8 . pcdi 0100101000111010 .......... . . U U . . 7 7
  795. tst 8 . pcix 0100101000111011 .......... . . U U . . 9 9
  796. tst 8 . i 0100101000111100 .......... . . U U . . 6 6
  797. tst 16 . d 0100101001000... .......... U U U U 4 4 2 2
  798. tst 16 . a 0100101001001... .......... . . U U . . 2 2
  799. tst 16 . . 0100101001...... A+-DXWL... U U U U 4 4 2 2
  800. tst 16 . pcdi 0100101001111010 .......... . . U U . . 7 7
  801. tst 16 . pcix 0100101001111011 .......... . . U U . . 9 9
  802. tst 16 . i 0100101001111100 .......... . . U U . . 6 6
  803. tst 32 . d 0100101010000... .......... U U U U 4 4 2 2
  804. tst 32 . a 0100101010001... .......... . . U U . . 2 2
  805. tst 32 . . 0100101010...... A+-DXWL... U U U U 4 4 2 2
  806. tst 32 . pcdi 0100101010111010 .......... . . U U . . 7 7
  807. tst 32 . pcix 0100101010111011 .......... . . U U . . 9 9
  808. tst 32 . i 0100101010111100 .......... . . U U . . 6 6
  809. unlk 32 . a7 0100111001011111 .......... U U U U 12 12 6 6
  810. unlk 32 . . 0100111001011... .......... U U U U 12 12 6 6
  811. unpk 16 rr . 1000...110000... .......... . . U U . . 8 8
  812. unpk 16 mm ax7 1000111110001... .......... . . U U . . 13 13
  813. unpk 16 mm ay7 1000...110001111 .......... . . U U . . 13 13
  814. unpk 16 mm axy7 1000111110001111 .......... . . U U . . 13 13
  815. unpk 16 mm . 1000...110001... .......... . . U U . . 13 13
  816. XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  817. M68KMAKE_OPCODE_HANDLER_BODY
  818. M68KMAKE_OP(1010, 0, ., .)
  819. {
  820. m68ki_exception_1010();
  821. }
  822. M68KMAKE_OP(1111, 0, ., .)
  823. {
  824. m68ki_exception_1111();
  825. }
  826. M68KMAKE_OP(040fpu0, 32, ., .)
  827. {
  828. if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  829. {
  830. m68040_fpu_op0();
  831. return;
  832. }
  833. m68ki_exception_1111();
  834. }
  835. M68KMAKE_OP(040fpu1, 32, ., .)
  836. {
  837. if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  838. {
  839. m68040_fpu_op1();
  840. return;
  841. }
  842. m68ki_exception_1111();
  843. }
  844. M68KMAKE_OP(abcd, 8, rr, .)
  845. {
  846. uint* r_dst = &DX;
  847. uint src = DY;
  848. uint dst = *r_dst;
  849. uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
  850. FLAG_V = ~res; /* Undefined V behavior */
  851. if(res > 9)
  852. res += 6;
  853. res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
  854. FLAG_X = FLAG_C = (res > 0x99) << 8;
  855. if(FLAG_C)
  856. res -= 0xa0;
  857. FLAG_V &= res; /* Undefined V behavior part II */
  858. FLAG_N = NFLAG_8(res); /* Undefined N behavior */
  859. res = MASK_OUT_ABOVE_8(res);
  860. FLAG_Z |= res;
  861. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  862. }
  863. M68KMAKE_OP(abcd, 8, mm, ax7)
  864. {
  865. uint src = OPER_AY_PD_8();
  866. uint ea = EA_A7_PD_8();
  867. uint dst = m68ki_read_8(ea);
  868. uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
  869. FLAG_V = ~res; /* Undefined V behavior */
  870. if(res > 9)
  871. res += 6;
  872. res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
  873. FLAG_X = FLAG_C = (res > 0x99) << 8;
  874. if(FLAG_C)
  875. res -= 0xa0;
  876. FLAG_V &= res; /* Undefined V behavior part II */
  877. FLAG_N = NFLAG_8(res); /* Undefined N behavior */
  878. res = MASK_OUT_ABOVE_8(res);
  879. FLAG_Z |= res;
  880. m68ki_write_8(ea, res);
  881. }
  882. M68KMAKE_OP(abcd, 8, mm, ay7)
  883. {
  884. uint src = OPER_A7_PD_8();
  885. uint ea = EA_AX_PD_8();
  886. uint dst = m68ki_read_8(ea);
  887. uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
  888. FLAG_V = ~res; /* Undefined V behavior */
  889. if(res > 9)
  890. res += 6;
  891. res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
  892. FLAG_X = FLAG_C = (res > 0x99) << 8;
  893. if(FLAG_C)
  894. res -= 0xa0;
  895. FLAG_V &= res; /* Undefined V behavior part II */
  896. FLAG_N = NFLAG_8(res); /* Undefined N behavior */
  897. res = MASK_OUT_ABOVE_8(res);
  898. FLAG_Z |= res;
  899. m68ki_write_8(ea, res);
  900. }
  901. M68KMAKE_OP(abcd, 8, mm, axy7)
  902. {
  903. uint src = OPER_A7_PD_8();
  904. uint ea = EA_A7_PD_8();
  905. uint dst = m68ki_read_8(ea);
  906. uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
  907. FLAG_V = ~res; /* Undefined V behavior */
  908. if(res > 9)
  909. res += 6;
  910. res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
  911. FLAG_X = FLAG_C = (res > 0x99) << 8;
  912. if(FLAG_C)
  913. res -= 0xa0;
  914. FLAG_V &= res; /* Undefined V behavior part II */
  915. FLAG_N = NFLAG_8(res); /* Undefined N behavior */
  916. res = MASK_OUT_ABOVE_8(res);
  917. FLAG_Z |= res;
  918. m68ki_write_8(ea, res);
  919. }
  920. M68KMAKE_OP(abcd, 8, mm, .)
  921. {
  922. uint src = OPER_AY_PD_8();
  923. uint ea = EA_AX_PD_8();
  924. uint dst = m68ki_read_8(ea);
  925. uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
  926. FLAG_V = ~res; /* Undefined V behavior */
  927. if(res > 9)
  928. res += 6;
  929. res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
  930. FLAG_X = FLAG_C = (res > 0x99) << 8;
  931. if(FLAG_C)
  932. res -= 0xa0;
  933. FLAG_V &= res; /* Undefined V behavior part II */
  934. FLAG_N = NFLAG_8(res); /* Undefined N behavior */
  935. res = MASK_OUT_ABOVE_8(res);
  936. FLAG_Z |= res;
  937. m68ki_write_8(ea, res);
  938. }
  939. M68KMAKE_OP(add, 8, er, d)
  940. {
  941. uint* r_dst = &DX;
  942. uint src = MASK_OUT_ABOVE_8(DY);
  943. uint dst = MASK_OUT_ABOVE_8(*r_dst);
  944. uint res = src + dst;
  945. FLAG_N = NFLAG_8(res);
  946. FLAG_V = VFLAG_ADD_8(src, dst, res);
  947. FLAG_X = FLAG_C = CFLAG_8(res);
  948. FLAG_Z = MASK_OUT_ABOVE_8(res);
  949. *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
  950. }
  951. M68KMAKE_OP(add, 8, er, .)
  952. {
  953. uint* r_dst = &DX;
  954. uint src = M68KMAKE_GET_OPER_AY_8;
  955. uint dst = MASK_OUT_ABOVE_8(*r_dst);
  956. uint res = src + dst;
  957. FLAG_N = NFLAG_8(res);
  958. FLAG_V = VFLAG_ADD_8(src, dst, res);
  959. FLAG_X = FLAG_C = CFLAG_8(res);
  960. FLAG_Z = MASK_OUT_ABOVE_8(res);
  961. *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
  962. }
  963. M68KMAKE_OP(add, 16, er, d)
  964. {
  965. uint* r_dst = &DX;
  966. uint src = MASK_OUT_ABOVE_16(DY);
  967. uint dst = MASK_OUT_ABOVE_16(*r_dst);
  968. uint res = src + dst;
  969. FLAG_N = NFLAG_16(res);
  970. FLAG_V = VFLAG_ADD_16(src, dst, res);
  971. FLAG_X = FLAG_C = CFLAG_16(res);
  972. FLAG_Z = MASK_OUT_ABOVE_16(res);
  973. *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
  974. }
  975. M68KMAKE_OP(add, 16, er, a)
  976. {
  977. uint* r_dst = &DX;
  978. uint src = MASK_OUT_ABOVE_16(AY);
  979. uint dst = MASK_OUT_ABOVE_16(*r_dst);
  980. uint res = src + dst;
  981. FLAG_N = NFLAG_16(res);
  982. FLAG_V = VFLAG_ADD_16(src, dst, res);
  983. FLAG_X = FLAG_C = CFLAG_16(res);
  984. FLAG_Z = MASK_OUT_ABOVE_16(res);
  985. *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
  986. }
  987. M68KMAKE_OP(add, 16, er, .)
  988. {
  989. uint* r_dst = &DX;
  990. uint src = M68KMAKE_GET_OPER_AY_16;
  991. uint dst = MASK_OUT_ABOVE_16(*r_dst);
  992. uint res = src + dst;
  993. FLAG_N = NFLAG_16(res);
  994. FLAG_V = VFLAG_ADD_16(src, dst, res);
  995. FLAG_X = FLAG_C = CFLAG_16(res);
  996. FLAG_Z = MASK_OUT_ABOVE_16(res);
  997. *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
  998. }
  999. M68KMAKE_OP(add, 32, er, d)
  1000. {
  1001. uint* r_dst = &DX;
  1002. uint src = DY;
  1003. uint dst = *r_dst;
  1004. uint res = src + dst;
  1005. FLAG_N = NFLAG_32(res);
  1006. FLAG_V = VFLAG_ADD_32(src, dst, res);
  1007. FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
  1008. FLAG_Z = MASK_OUT_ABOVE_32(res);
  1009. *r_dst = FLAG_Z;
  1010. }
  1011. M68KMAKE_OP(add, 32, er, a)
  1012. {
  1013. uint* r_dst = &DX;
  1014. uint src = AY;
  1015. uint dst = *r_dst;
  1016. uint res = src + dst;
  1017. FLAG_N = NFLAG_32(res);
  1018. FLAG_V = VFLAG_ADD_32(src, dst, res);
  1019. FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
  1020. FLAG_Z = MASK_OUT_ABOVE_32(res);
  1021. *r_dst = FLAG_Z;
  1022. }
  1023. M68KMAKE_OP(add, 32, er, .)
  1024. {
  1025. uint* r_dst = &DX;
  1026. uint src = M68KMAKE_GET_OPER_AY_32;
  1027. uint dst = *r_dst;
  1028. uint res = src + dst;
  1029. FLAG_N = NFLAG_32(res);
  1030. FLAG_V = VFLAG_ADD_32(src, dst, res);
  1031. FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
  1032. FLAG_Z = MASK_OUT_ABOVE_32(res);
  1033. *r_dst = FLAG_Z;
  1034. }
  1035. M68KMAKE_OP(add, 8, re, .)
  1036. {
  1037. uint ea = M68KMAKE_GET_EA_AY_8;
  1038. uint src = MASK_OUT_ABOVE_8(DX);
  1039. uint dst = m68ki_read_8(ea);
  1040. uint res = src + dst;
  1041. FLAG_N = NFLAG_8(res);
  1042. FLAG_V = VFLAG_ADD_8(src, dst, res);
  1043. FLAG_X = FLAG_C = CFLAG_8(res);
  1044. FLAG_Z = MASK_OUT_ABOVE_8(res);
  1045. m68ki_write_8(ea, FLAG_Z);
  1046. }
  1047. M68KMAKE_OP(add, 16, re, .)
  1048. {
  1049. uint ea = M68KMAKE_GET_EA_AY_16;
  1050. uint src = MASK_OUT_ABOVE_16(DX);
  1051. uint dst = m68ki_read_16(ea);
  1052. uint res = src + dst;
  1053. FLAG_N = NFLAG_16(res);
  1054. FLAG_V = VFLAG_ADD_16(src, dst, res);
  1055. FLAG_X = FLAG_C = CFLAG_16(res);
  1056. FLAG_Z = MASK_OUT_ABOVE_16(res);
  1057. m68ki_write_16(ea, FLAG_Z);
  1058. }
  1059. M68KMAKE_OP(add, 32, re, .)
  1060. {
  1061. uint ea = M68KMAKE_GET_EA_AY_32;
  1062. uint src = DX;
  1063. uint dst = m68ki_read_32(ea);
  1064. uint res = src + dst;
  1065. FLAG_N = NFLAG_32(res);
  1066. FLAG_V = VFLAG_ADD_32(src, dst, res);
  1067. FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
  1068. FLAG_Z = MASK_OUT_ABOVE_32(res);
  1069. m68ki_write_32(ea, FLAG_Z);
  1070. }
  1071. M68KMAKE_OP(adda, 16, ., d)
  1072. {
  1073. uint* r_dst = &AX;
  1074. *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY));
  1075. }
  1076. M68KMAKE_OP(adda, 16, ., a)
  1077. {
  1078. uint* r_dst = &AX;
  1079. *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY));
  1080. }
  1081. M68KMAKE_OP(adda, 16, ., .)
  1082. {
  1083. uint* r_dst = &AX;
  1084. uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
  1085. *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
  1086. }
  1087. M68KMAKE_OP(adda, 32, ., d)
  1088. {
  1089. uint* r_dst = &AX;
  1090. *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY);
  1091. }
  1092. M68KMAKE_OP(adda, 32, ., a)
  1093. {
  1094. uint* r_dst = &AX;
  1095. *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY);
  1096. }
  1097. M68KMAKE_OP(adda, 32, ., .)
  1098. {
  1099. uint* r_dst = &AX;
  1100. *r_dst = MASK_OUT_ABOVE_32(*r_dst + M68KMAKE_GET_OPER_AY_32);
  1101. }
  1102. M68KMAKE_OP(addi, 8, ., d)
  1103. {
  1104. uint* r_dst = &DY;
  1105. uint src = OPER_I_8();
  1106. uint dst = MASK_OUT_ABOVE_8(*r_dst);
  1107. uint res = src + dst;
  1108. FLAG_N = NFLAG_8(res);
  1109. FLAG_V = VFLAG_ADD_8(src, dst, res);
  1110. FLAG_X = FLAG_C = CFLAG_8(res);
  1111. FLAG_Z = MASK_OUT_ABOVE_8(res);
  1112. *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
  1113. }
  1114. M68KMAKE_OP(addi, 8, ., .)
  1115. {
  1116. uint src = OPER_I_8();
  1117. uint ea = M68KMAKE_GET_EA_AY_8;
  1118. uint dst = m68ki_read_8(ea);
  1119. uint res = src + dst;
  1120. FLAG_N = NFLAG_8(res);
  1121. FLAG_V = VFLAG_ADD_8(src, dst, res);
  1122. FLAG_X = FLAG_C = CFLAG_8(res);
  1123. FLAG_Z = MASK_OUT_ABOVE_8(res);
  1124. m68ki_write_8(ea, FLAG_Z);
  1125. }
  1126. M68KMAKE_OP(addi, 16, ., d)
  1127. {
  1128. uint* r_dst = &DY;
  1129. uint src = OPER_I_16();
  1130. uint dst = MASK_OUT_ABOVE_16(*r_dst);
  1131. uint res = src + dst;
  1132. FLAG_N = NFLAG_16(res);
  1133. FLAG_V = VFLAG_ADD_16(src, dst, res);
  1134. FLAG_X = FLAG_C = CFLAG_16(res);
  1135. FLAG_Z = MASK_OUT_ABOVE_16(res);
  1136. *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
  1137. }
  1138. M68KMAKE_OP(addi, 16, ., .)
  1139. {
  1140. uint src = OPER_I_16();
  1141. uint ea = M68KMAKE_GET_EA_AY_16;
  1142. uint dst = m68ki_read_16(ea);
  1143. uint res = src + dst;
  1144. FLAG_N = NFLAG_16(res);
  1145. FLAG_V = VFLAG_ADD_16(src, dst, res);
  1146. FLAG_X = FLAG_C = CFLAG_16(res);
  1147. FLAG_Z = MASK_OUT_ABOVE_16(res);
  1148. m68ki_write_16(ea, FLAG_Z);
  1149. }
  1150. M68KMAKE_OP(addi, 32, ., d)
  1151. {
  1152. uint* r_dst = &DY;
  1153. uint src = OPER_I_32();
  1154. uint dst = *r_dst;
  1155. uint res = src + dst;
  1156. FLAG_N = NFLAG_32(res);
  1157. FLAG_V = VFLAG_ADD_32(src, dst, res);
  1158. FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
  1159. FLAG_Z = MASK_OUT_ABOVE_32(res);
  1160. *r_dst = FLAG_Z;
  1161. }
  1162. M68KMAKE_OP(addi, 32, ., .)
  1163. {
  1164. uint src = OPER_I_32();
  1165. uint ea = M68KMAKE_GET_EA_AY_32;
  1166. uint dst = m68ki_read_32(ea);
  1167. uint res = src + dst;
  1168. FLAG_N = NFLAG_32(res);
  1169. FLAG_V = VFLAG_ADD_32(src, dst, res);
  1170. FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
  1171. FLAG_Z = MASK_OUT_ABOVE_32(res);
  1172. m68ki_write_32(ea, FLAG_Z);
  1173. }
  1174. M68KMAKE_OP(addq, 8, ., d)
  1175. {
  1176. uint* r_dst = &DY;
  1177. uint src = (((REG_IR >> 9) - 1) & 7) + 1;
  1178. uint dst = MASK_OUT_ABOVE_8(*r_dst);
  1179. uint res = src + dst;
  1180. FLAG_N = NFLAG_8(res);
  1181. FLAG_V = VFLAG_ADD_8(src, dst, res);
  1182. FLAG_X = FLAG_C = CFLAG_8(res);
  1183. FLAG_Z = MASK_OUT_ABOVE_8(res);
  1184. *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
  1185. }
  1186. M68KMAKE_OP(addq, 8, ., .)
  1187. {
  1188. uint src = (((REG_IR >> 9) - 1) & 7) + 1;
  1189. uint ea = M68KMAKE_GET_EA_AY_8;
  1190. uint dst = m68ki_read_8(ea);
  1191. uint res = src + dst;
  1192. FLAG_N = NFLAG_8(res);
  1193. FLAG_V = VFLAG_ADD_8(src, dst, res);
  1194. FLAG_X = FLAG_C = CFLAG_8(res);
  1195. FLAG_Z = MASK_OUT_ABOVE_8(res);
  1196. m68ki_write_8(ea, FLAG_Z);
  1197. }
  1198. M68KMAKE_OP(addq, 16, ., d)
  1199. {
  1200. uint* r_dst = &DY;
  1201. uint src = (((REG_IR >> 9) - 1) & 7) + 1;
  1202. uint dst = MASK_OUT_ABOVE_16(*r_dst);
  1203. uint res = src + dst;
  1204. FLAG_N = NFLAG_16(res);
  1205. FLAG_V = VFLAG_ADD_16(src, dst, res);
  1206. FLAG_X = FLAG_C = CFLAG_16(res);
  1207. FLAG_Z = MASK_OUT_ABOVE_16(res);
  1208. *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
  1209. }
  1210. M68KMAKE_OP(addq, 16, ., a)
  1211. {
  1212. uint* r_dst = &AY;
  1213. *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
  1214. }
  1215. M68KMAKE_OP(addq, 16, ., .)
  1216. {
  1217. uint src = (((REG_IR >> 9) - 1) & 7) + 1;
  1218. uint ea = M68KMAKE_GET_EA_AY_16;
  1219. uint dst = m68ki_read_16(ea);
  1220. uint res = src + dst;
  1221. FLAG_N = NFLAG_16(res);
  1222. FLAG_V = VFLAG_ADD_16(src, dst, res);
  1223. FLAG_X = FLAG_C = CFLAG_16(res);
  1224. FLAG_Z = MASK_OUT_ABOVE_16(res);
  1225. m68ki_write_16(ea, FLAG_Z);
  1226. }
  1227. M68KMAKE_OP(addq, 32, ., d)
  1228. {
  1229. uint* r_dst = &DY;
  1230. uint src = (((REG_IR >> 9) - 1) & 7) + 1;
  1231. uint dst = *r_dst;
  1232. uint res = src + dst;
  1233. FLAG_N = NFLAG_32(res);
  1234. FLAG_V = VFLAG_ADD_32(src, dst, res);
  1235. FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
  1236. FLAG_Z = MASK_OUT_ABOVE_32(res);
  1237. *r_dst = FLAG_Z;
  1238. }
  1239. M68KMAKE_OP(addq, 32, ., a)
  1240. {
  1241. uint* r_dst = &AY;
  1242. *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
  1243. }
  1244. M68KMAKE_OP(addq, 32, ., .)
  1245. {
  1246. uint src = (((REG_IR >> 9) - 1) & 7) + 1;
  1247. uint ea = M68KMAKE_GET_EA_AY_32;
  1248. uint dst = m68ki_read_32(ea);
  1249. uint res = src + dst;
  1250. FLAG_N = NFLAG_32(res);
  1251. FLAG_V = VFLAG_ADD_32(src, dst, res);
  1252. FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
  1253. FLAG_Z = MASK_OUT_ABOVE_32(res);
  1254. m68ki_write_32(ea, FLAG_Z);
  1255. }
  1256. M68KMAKE_OP(addx, 8, rr, .)
  1257. {
  1258. uint* r_dst = &DX;
  1259. uint src = MASK_OUT_ABOVE_8(DY);
  1260. uint dst = MASK_OUT_ABOVE_8(*r_dst);
  1261. uint res = src + dst + XFLAG_AS_1();
  1262. FLAG_N = NFLAG_8(res);
  1263. FLAG_V = VFLAG_ADD_8(src, dst, res);
  1264. FLAG_X = FLAG_C = CFLAG_8(res);
  1265. res = MASK_OUT_ABOVE_8(res);
  1266. FLAG_Z |= res;
  1267. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  1268. }
  1269. M68KMAKE_OP(addx, 16, rr, .)
  1270. {
  1271. uint* r_dst = &DX;
  1272. uint src = MASK_OUT_ABOVE_16(DY);
  1273. uint dst = MASK_OUT_ABOVE_16(*r_dst);
  1274. uint res = src + dst + XFLAG_AS_1();
  1275. FLAG_N = NFLAG_16(res);
  1276. FLAG_V = VFLAG_ADD_16(src, dst, res);
  1277. FLAG_X = FLAG_C = CFLAG_16(res);
  1278. res = MASK_OUT_ABOVE_16(res);
  1279. FLAG_Z |= res;
  1280. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  1281. }
  1282. M68KMAKE_OP(addx, 32, rr, .)
  1283. {
  1284. uint* r_dst = &DX;
  1285. uint src = DY;
  1286. uint dst = *r_dst;
  1287. uint res = src + dst + XFLAG_AS_1();
  1288. FLAG_N = NFLAG_32(res);
  1289. FLAG_V = VFLAG_ADD_32(src, dst, res);
  1290. FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
  1291. res = MASK_OUT_ABOVE_32(res);
  1292. FLAG_Z |= res;
  1293. *r_dst = res;
  1294. }
  1295. M68KMAKE_OP(addx, 8, mm, ax7)
  1296. {
  1297. uint src = OPER_AY_PD_8();
  1298. uint ea = EA_A7_PD_8();
  1299. uint dst = m68ki_read_8(ea);
  1300. uint res = src + dst + XFLAG_AS_1();
  1301. FLAG_N = NFLAG_8(res);
  1302. FLAG_V = VFLAG_ADD_8(src, dst, res);
  1303. FLAG_X = FLAG_C = CFLAG_8(res);
  1304. res = MASK_OUT_ABOVE_8(res);
  1305. FLAG_Z |= res;
  1306. m68ki_write_8(ea, res);
  1307. }
  1308. M68KMAKE_OP(addx, 8, mm, ay7)
  1309. {
  1310. uint src = OPER_A7_PD_8();
  1311. uint ea = EA_AX_PD_8();
  1312. uint dst = m68ki_read_8(ea);
  1313. uint res = src + dst + XFLAG_AS_1();
  1314. FLAG_N = NFLAG_8(res);
  1315. FLAG_V = VFLAG_ADD_8(src, dst, res);
  1316. FLAG_X = FLAG_C = CFLAG_8(res);
  1317. res = MASK_OUT_ABOVE_8(res);
  1318. FLAG_Z |= res;
  1319. m68ki_write_8(ea, res);
  1320. }
  1321. M68KMAKE_OP(addx, 8, mm, axy7)
  1322. {
  1323. uint src = OPER_A7_PD_8();
  1324. uint ea = EA_A7_PD_8();
  1325. uint dst = m68ki_read_8(ea);
  1326. uint res = src + dst + XFLAG_AS_1();
  1327. FLAG_N = NFLAG_8(res);
  1328. FLAG_V = VFLAG_ADD_8(src, dst, res);
  1329. FLAG_X = FLAG_C = CFLAG_8(res);
  1330. res = MASK_OUT_ABOVE_8(res);
  1331. FLAG_Z |= res;
  1332. m68ki_write_8(ea, res);
  1333. }
  1334. M68KMAKE_OP(addx, 8, mm, .)
  1335. {
  1336. uint src = OPER_AY_PD_8();
  1337. uint ea = EA_AX_PD_8();
  1338. uint dst = m68ki_read_8(ea);
  1339. uint res = src + dst + XFLAG_AS_1();
  1340. FLAG_N = NFLAG_8(res);
  1341. FLAG_V = VFLAG_ADD_8(src, dst, res);
  1342. FLAG_X = FLAG_C = CFLAG_8(res);
  1343. res = MASK_OUT_ABOVE_8(res);
  1344. FLAG_Z |= res;
  1345. m68ki_write_8(ea, res);
  1346. }
  1347. M68KMAKE_OP(addx, 16, mm, .)
  1348. {
  1349. uint src = OPER_AY_PD_16();
  1350. uint ea = EA_AX_PD_16();
  1351. uint dst = m68ki_read_16(ea);
  1352. uint res = src + dst + XFLAG_AS_1();
  1353. FLAG_N = NFLAG_16(res);
  1354. FLAG_V = VFLAG_ADD_16(src, dst, res);
  1355. FLAG_X = FLAG_C = CFLAG_16(res);
  1356. res = MASK_OUT_ABOVE_16(res);
  1357. FLAG_Z |= res;
  1358. m68ki_write_16(ea, res);
  1359. }
  1360. M68KMAKE_OP(addx, 32, mm, .)
  1361. {
  1362. uint src = OPER_AY_PD_32();
  1363. uint ea = EA_AX_PD_32();
  1364. uint dst = m68ki_read_32(ea);
  1365. uint res = src + dst + XFLAG_AS_1();
  1366. FLAG_N = NFLAG_32(res);
  1367. FLAG_V = VFLAG_ADD_32(src, dst, res);
  1368. FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
  1369. res = MASK_OUT_ABOVE_32(res);
  1370. FLAG_Z |= res;
  1371. m68ki_write_32(ea, res);
  1372. }
  1373. M68KMAKE_OP(and, 8, er, d)
  1374. {
  1375. FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00));
  1376. FLAG_N = NFLAG_8(FLAG_Z);
  1377. FLAG_C = CFLAG_CLEAR;
  1378. FLAG_V = VFLAG_CLEAR;
  1379. }
  1380. M68KMAKE_OP(and, 8, er, .)
  1381. {
  1382. FLAG_Z = MASK_OUT_ABOVE_8(DX &= (M68KMAKE_GET_OPER_AY_8 | 0xffffff00));
  1383. FLAG_N = NFLAG_8(FLAG_Z);
  1384. FLAG_C = CFLAG_CLEAR;
  1385. FLAG_V = VFLAG_CLEAR;
  1386. }
  1387. M68KMAKE_OP(and, 16, er, d)
  1388. {
  1389. FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000));
  1390. FLAG_N = NFLAG_16(FLAG_Z);
  1391. FLAG_C = CFLAG_CLEAR;
  1392. FLAG_V = VFLAG_CLEAR;
  1393. }
  1394. M68KMAKE_OP(and, 16, er, .)
  1395. {
  1396. FLAG_Z = MASK_OUT_ABOVE_16(DX &= (M68KMAKE_GET_OPER_AY_16 | 0xffff0000));
  1397. FLAG_N = NFLAG_16(FLAG_Z);
  1398. FLAG_C = CFLAG_CLEAR;
  1399. FLAG_V = VFLAG_CLEAR;
  1400. }
  1401. M68KMAKE_OP(and, 32, er, d)
  1402. {
  1403. FLAG_Z = DX &= DY;
  1404. FLAG_N = NFLAG_32(FLAG_Z);
  1405. FLAG_C = CFLAG_CLEAR;
  1406. FLAG_V = VFLAG_CLEAR;
  1407. }
  1408. M68KMAKE_OP(and, 32, er, .)
  1409. {
  1410. FLAG_Z = DX &= M68KMAKE_GET_OPER_AY_32;
  1411. FLAG_N = NFLAG_32(FLAG_Z);
  1412. FLAG_C = CFLAG_CLEAR;
  1413. FLAG_V = VFLAG_CLEAR;
  1414. }
  1415. M68KMAKE_OP(and, 8, re, .)
  1416. {
  1417. uint ea = M68KMAKE_GET_EA_AY_8;
  1418. uint res = DX & m68ki_read_8(ea);
  1419. FLAG_N = NFLAG_8(res);
  1420. FLAG_C = CFLAG_CLEAR;
  1421. FLAG_V = VFLAG_CLEAR;
  1422. FLAG_Z = MASK_OUT_ABOVE_8(res);
  1423. m68ki_write_8(ea, FLAG_Z);
  1424. }
  1425. M68KMAKE_OP(and, 16, re, .)
  1426. {
  1427. uint ea = M68KMAKE_GET_EA_AY_16;
  1428. uint res = DX & m68ki_read_16(ea);
  1429. FLAG_N = NFLAG_16(res);
  1430. FLAG_C = CFLAG_CLEAR;
  1431. FLAG_V = VFLAG_CLEAR;
  1432. FLAG_Z = MASK_OUT_ABOVE_16(res);
  1433. m68ki_write_16(ea, FLAG_Z);
  1434. }
  1435. M68KMAKE_OP(and, 32, re, .)
  1436. {
  1437. uint ea = M68KMAKE_GET_EA_AY_32;
  1438. uint res = DX & m68ki_read_32(ea);
  1439. FLAG_N = NFLAG_32(res);
  1440. FLAG_Z = res;
  1441. FLAG_C = CFLAG_CLEAR;
  1442. FLAG_V = VFLAG_CLEAR;
  1443. m68ki_write_32(ea, res);
  1444. }
  1445. M68KMAKE_OP(andi, 8, ., d)
  1446. {
  1447. FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00));
  1448. FLAG_N = NFLAG_8(FLAG_Z);
  1449. FLAG_C = CFLAG_CLEAR;
  1450. FLAG_V = VFLAG_CLEAR;
  1451. }
  1452. M68KMAKE_OP(andi, 8, ., .)
  1453. {
  1454. uint src = OPER_I_8();
  1455. uint ea = M68KMAKE_GET_EA_AY_8;
  1456. uint res = src & m68ki_read_8(ea);
  1457. FLAG_N = NFLAG_8(res);
  1458. FLAG_Z = res;
  1459. FLAG_C = CFLAG_CLEAR;
  1460. FLAG_V = VFLAG_CLEAR;
  1461. m68ki_write_8(ea, res);
  1462. }
  1463. M68KMAKE_OP(andi, 16, ., d)
  1464. {
  1465. FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000));
  1466. FLAG_N = NFLAG_16(FLAG_Z);
  1467. FLAG_C = CFLAG_CLEAR;
  1468. FLAG_V = VFLAG_CLEAR;
  1469. }
  1470. M68KMAKE_OP(andi, 16, ., .)
  1471. {
  1472. uint src = OPER_I_16();
  1473. uint ea = M68KMAKE_GET_EA_AY_16;
  1474. uint res = src & m68ki_read_16(ea);
  1475. FLAG_N = NFLAG_16(res);
  1476. FLAG_Z = res;
  1477. FLAG_C = CFLAG_CLEAR;
  1478. FLAG_V = VFLAG_CLEAR;
  1479. m68ki_write_16(ea, res);
  1480. }
  1481. M68KMAKE_OP(andi, 32, ., d)
  1482. {
  1483. FLAG_Z = DY &= (OPER_I_32());
  1484. FLAG_N = NFLAG_32(FLAG_Z);
  1485. FLAG_C = CFLAG_CLEAR;
  1486. FLAG_V = VFLAG_CLEAR;
  1487. }
  1488. M68KMAKE_OP(andi, 32, ., .)
  1489. {
  1490. uint src = OPER_I_32();
  1491. uint ea = M68KMAKE_GET_EA_AY_32;
  1492. uint res = src & m68ki_read_32(ea);
  1493. FLAG_N = NFLAG_32(res);
  1494. FLAG_Z = res;
  1495. FLAG_C = CFLAG_CLEAR;
  1496. FLAG_V = VFLAG_CLEAR;
  1497. m68ki_write_32(ea, res);
  1498. }
  1499. M68KMAKE_OP(andi, 16, toc, .)
  1500. {
  1501. m68ki_set_ccr(m68ki_get_ccr() & OPER_I_16());
  1502. }
  1503. M68KMAKE_OP(andi, 16, tos, .)
  1504. {
  1505. if(FLAG_S)
  1506. {
  1507. uint src = OPER_I_16();
  1508. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  1509. m68ki_set_sr(m68ki_get_sr() & src);
  1510. return;
  1511. }
  1512. m68ki_exception_privilege_violation();
  1513. }
  1514. M68KMAKE_OP(asr, 8, s, .)
  1515. {
  1516. uint* r_dst = &DY;
  1517. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  1518. uint src = MASK_OUT_ABOVE_8(*r_dst);
  1519. uint res = src >> shift;
  1520. if(shift != 0)
  1521. USE_CYCLES(shift<<CYC_SHIFT);
  1522. if(GET_MSB_8(src))
  1523. res |= m68ki_shift_8_table[shift];
  1524. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  1525. FLAG_N = NFLAG_8(res);
  1526. FLAG_Z = res;
  1527. FLAG_V = VFLAG_CLEAR;
  1528. FLAG_X = FLAG_C = src << (9-shift);
  1529. }
  1530. M68KMAKE_OP(asr, 16, s, .)
  1531. {
  1532. uint* r_dst = &DY;
  1533. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  1534. uint src = MASK_OUT_ABOVE_16(*r_dst);
  1535. uint res = src >> shift;
  1536. if(shift != 0)
  1537. USE_CYCLES(shift<<CYC_SHIFT);
  1538. if(GET_MSB_16(src))
  1539. res |= m68ki_shift_16_table[shift];
  1540. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  1541. FLAG_N = NFLAG_16(res);
  1542. FLAG_Z = res;
  1543. FLAG_V = VFLAG_CLEAR;
  1544. FLAG_X = FLAG_C = src << (9-shift);
  1545. }
  1546. M68KMAKE_OP(asr, 32, s, .)
  1547. {
  1548. uint* r_dst = &DY;
  1549. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  1550. uint src = *r_dst;
  1551. uint res = src >> shift;
  1552. if(shift != 0)
  1553. USE_CYCLES(shift<<CYC_SHIFT);
  1554. if(GET_MSB_32(src))
  1555. res |= m68ki_shift_32_table[shift];
  1556. *r_dst = res;
  1557. FLAG_N = NFLAG_32(res);
  1558. FLAG_Z = res;
  1559. FLAG_V = VFLAG_CLEAR;
  1560. FLAG_X = FLAG_C = src << (9-shift);
  1561. }
  1562. M68KMAKE_OP(asr, 8, r, .)
  1563. {
  1564. uint* r_dst = &DY;
  1565. uint shift = DX & 0x3f;
  1566. uint src = MASK_OUT_ABOVE_8(*r_dst);
  1567. uint res = src >> shift;
  1568. if(shift != 0)
  1569. {
  1570. USE_CYCLES(shift<<CYC_SHIFT);
  1571. if(shift < 8)
  1572. {
  1573. if(GET_MSB_8(src))
  1574. res |= m68ki_shift_8_table[shift];
  1575. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  1576. FLAG_X = FLAG_C = src << (9-shift);
  1577. FLAG_N = NFLAG_8(res);
  1578. FLAG_Z = res;
  1579. FLAG_V = VFLAG_CLEAR;
  1580. return;
  1581. }
  1582. if(GET_MSB_8(src))
  1583. {
  1584. *r_dst |= 0xff;
  1585. FLAG_C = CFLAG_SET;
  1586. FLAG_X = XFLAG_SET;
  1587. FLAG_N = NFLAG_SET;
  1588. FLAG_Z = ZFLAG_CLEAR;
  1589. FLAG_V = VFLAG_CLEAR;
  1590. return;
  1591. }
  1592. *r_dst &= 0xffffff00;
  1593. FLAG_C = CFLAG_CLEAR;
  1594. FLAG_X = XFLAG_CLEAR;
  1595. FLAG_N = NFLAG_CLEAR;
  1596. FLAG_Z = ZFLAG_SET;
  1597. FLAG_V = VFLAG_CLEAR;
  1598. return;
  1599. }
  1600. FLAG_C = CFLAG_CLEAR;
  1601. FLAG_N = NFLAG_8(src);
  1602. FLAG_Z = src;
  1603. FLAG_V = VFLAG_CLEAR;
  1604. }
  1605. M68KMAKE_OP(asr, 16, r, .)
  1606. {
  1607. uint* r_dst = &DY;
  1608. uint shift = DX & 0x3f;
  1609. uint src = MASK_OUT_ABOVE_16(*r_dst);
  1610. uint res = src >> shift;
  1611. if(shift != 0)
  1612. {
  1613. USE_CYCLES(shift<<CYC_SHIFT);
  1614. if(shift < 16)
  1615. {
  1616. if(GET_MSB_16(src))
  1617. res |= m68ki_shift_16_table[shift];
  1618. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  1619. FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
  1620. FLAG_N = NFLAG_16(res);
  1621. FLAG_Z = res;
  1622. FLAG_V = VFLAG_CLEAR;
  1623. return;
  1624. }
  1625. if(GET_MSB_16(src))
  1626. {
  1627. *r_dst |= 0xffff;
  1628. FLAG_C = CFLAG_SET;
  1629. FLAG_X = XFLAG_SET;
  1630. FLAG_N = NFLAG_SET;
  1631. FLAG_Z = ZFLAG_CLEAR;
  1632. FLAG_V = VFLAG_CLEAR;
  1633. return;
  1634. }
  1635. *r_dst &= 0xffff0000;
  1636. FLAG_C = CFLAG_CLEAR;
  1637. FLAG_X = XFLAG_CLEAR;
  1638. FLAG_N = NFLAG_CLEAR;
  1639. FLAG_Z = ZFLAG_SET;
  1640. FLAG_V = VFLAG_CLEAR;
  1641. return;
  1642. }
  1643. FLAG_C = CFLAG_CLEAR;
  1644. FLAG_N = NFLAG_16(src);
  1645. FLAG_Z = src;
  1646. FLAG_V = VFLAG_CLEAR;
  1647. }
  1648. M68KMAKE_OP(asr, 32, r, .)
  1649. {
  1650. uint* r_dst = &DY;
  1651. uint shift = DX & 0x3f;
  1652. uint src = *r_dst;
  1653. uint res = src >> shift;
  1654. if(shift != 0)
  1655. {
  1656. USE_CYCLES(shift<<CYC_SHIFT);
  1657. if(shift < 32)
  1658. {
  1659. if(GET_MSB_32(src))
  1660. res |= m68ki_shift_32_table[shift];
  1661. *r_dst = res;
  1662. FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
  1663. FLAG_N = NFLAG_32(res);
  1664. FLAG_Z = res;
  1665. FLAG_V = VFLAG_CLEAR;
  1666. return;
  1667. }
  1668. if(GET_MSB_32(src))
  1669. {
  1670. *r_dst = 0xffffffff;
  1671. FLAG_C = CFLAG_SET;
  1672. FLAG_X = XFLAG_SET;
  1673. FLAG_N = NFLAG_SET;
  1674. FLAG_Z = ZFLAG_CLEAR;
  1675. FLAG_V = VFLAG_CLEAR;
  1676. return;
  1677. }
  1678. *r_dst = 0;
  1679. FLAG_C = CFLAG_CLEAR;
  1680. FLAG_X = XFLAG_CLEAR;
  1681. FLAG_N = NFLAG_CLEAR;
  1682. FLAG_Z = ZFLAG_SET;
  1683. FLAG_V = VFLAG_CLEAR;
  1684. return;
  1685. }
  1686. FLAG_C = CFLAG_CLEAR;
  1687. FLAG_N = NFLAG_32(src);
  1688. FLAG_Z = src;
  1689. FLAG_V = VFLAG_CLEAR;
  1690. }
  1691. M68KMAKE_OP(asr, 16, ., .)
  1692. {
  1693. uint ea = M68KMAKE_GET_EA_AY_16;
  1694. uint src = m68ki_read_16(ea);
  1695. uint res = src >> 1;
  1696. if(GET_MSB_16(src))
  1697. res |= 0x8000;
  1698. m68ki_write_16(ea, res);
  1699. FLAG_N = NFLAG_16(res);
  1700. FLAG_Z = res;
  1701. FLAG_V = VFLAG_CLEAR;
  1702. FLAG_C = FLAG_X = src << 8;
  1703. }
  1704. M68KMAKE_OP(asl, 8, s, .)
  1705. {
  1706. uint* r_dst = &DY;
  1707. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  1708. uint src = MASK_OUT_ABOVE_8(*r_dst);
  1709. uint res = MASK_OUT_ABOVE_8(src << shift);
  1710. if(shift != 0)
  1711. USE_CYCLES(shift<<CYC_SHIFT);
  1712. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  1713. FLAG_X = FLAG_C = src << shift;
  1714. FLAG_N = NFLAG_8(res);
  1715. FLAG_Z = res;
  1716. src &= m68ki_shift_8_table[shift + 1];
  1717. FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7;
  1718. }
  1719. M68KMAKE_OP(asl, 16, s, .)
  1720. {
  1721. uint* r_dst = &DY;
  1722. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  1723. uint src = MASK_OUT_ABOVE_16(*r_dst);
  1724. uint res = MASK_OUT_ABOVE_16(src << shift);
  1725. if(shift != 0)
  1726. USE_CYCLES(shift<<CYC_SHIFT);
  1727. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  1728. FLAG_N = NFLAG_16(res);
  1729. FLAG_Z = res;
  1730. FLAG_X = FLAG_C = src >> (8-shift);
  1731. src &= m68ki_shift_16_table[shift + 1];
  1732. FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
  1733. }
  1734. M68KMAKE_OP(asl, 32, s, .)
  1735. {
  1736. uint* r_dst = &DY;
  1737. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  1738. uint src = *r_dst;
  1739. uint res = MASK_OUT_ABOVE_32(src << shift);
  1740. if(shift != 0)
  1741. USE_CYCLES(shift<<CYC_SHIFT);
  1742. *r_dst = res;
  1743. FLAG_N = NFLAG_32(res);
  1744. FLAG_Z = res;
  1745. FLAG_X = FLAG_C = src >> (24-shift);
  1746. src &= m68ki_shift_32_table[shift + 1];
  1747. FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
  1748. }
  1749. M68KMAKE_OP(asl, 8, r, .)
  1750. {
  1751. uint* r_dst = &DY;
  1752. uint shift = DX & 0x3f;
  1753. uint src = MASK_OUT_ABOVE_8(*r_dst);
  1754. uint res = MASK_OUT_ABOVE_8(src << shift);
  1755. if(shift != 0)
  1756. {
  1757. USE_CYCLES(shift<<CYC_SHIFT);
  1758. if(shift < 8)
  1759. {
  1760. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  1761. FLAG_X = FLAG_C = src << shift;
  1762. FLAG_N = NFLAG_8(res);
  1763. FLAG_Z = res;
  1764. src &= m68ki_shift_8_table[shift + 1];
  1765. FLAG_V = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7;
  1766. return;
  1767. }
  1768. *r_dst &= 0xffffff00;
  1769. FLAG_X = FLAG_C = ((shift == 8 ? src & 1 : 0))<<8;
  1770. FLAG_N = NFLAG_CLEAR;
  1771. FLAG_Z = ZFLAG_SET;
  1772. FLAG_V = (!(src == 0))<<7;
  1773. return;
  1774. }
  1775. FLAG_C = CFLAG_CLEAR;
  1776. FLAG_N = NFLAG_8(src);
  1777. FLAG_Z = src;
  1778. FLAG_V = VFLAG_CLEAR;
  1779. }
  1780. M68KMAKE_OP(asl, 16, r, .)
  1781. {
  1782. uint* r_dst = &DY;
  1783. uint shift = DX & 0x3f;
  1784. uint src = MASK_OUT_ABOVE_16(*r_dst);
  1785. uint res = MASK_OUT_ABOVE_16(src << shift);
  1786. if(shift != 0)
  1787. {
  1788. USE_CYCLES(shift<<CYC_SHIFT);
  1789. if(shift < 16)
  1790. {
  1791. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  1792. FLAG_X = FLAG_C = (src << shift) >> 8;
  1793. FLAG_N = NFLAG_16(res);
  1794. FLAG_Z = res;
  1795. src &= m68ki_shift_16_table[shift + 1];
  1796. FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
  1797. return;
  1798. }
  1799. *r_dst &= 0xffff0000;
  1800. FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8;
  1801. FLAG_N = NFLAG_CLEAR;
  1802. FLAG_Z = ZFLAG_SET;
  1803. FLAG_V = (!(src == 0))<<7;
  1804. return;
  1805. }
  1806. FLAG_C = CFLAG_CLEAR;
  1807. FLAG_N = NFLAG_16(src);
  1808. FLAG_Z = src;
  1809. FLAG_V = VFLAG_CLEAR;
  1810. }
  1811. M68KMAKE_OP(asl, 32, r, .)
  1812. {
  1813. uint* r_dst = &DY;
  1814. uint shift = DX & 0x3f;
  1815. uint src = *r_dst;
  1816. uint res = MASK_OUT_ABOVE_32(src << shift);
  1817. if(shift != 0)
  1818. {
  1819. USE_CYCLES(shift<<CYC_SHIFT);
  1820. if(shift < 32)
  1821. {
  1822. *r_dst = res;
  1823. FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
  1824. FLAG_N = NFLAG_32(res);
  1825. FLAG_Z = res;
  1826. src &= m68ki_shift_32_table[shift + 1];
  1827. FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
  1828. return;
  1829. }
  1830. *r_dst = 0;
  1831. FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
  1832. FLAG_N = NFLAG_CLEAR;
  1833. FLAG_Z = ZFLAG_SET;
  1834. FLAG_V = (!(src == 0))<<7;
  1835. return;
  1836. }
  1837. FLAG_C = CFLAG_CLEAR;
  1838. FLAG_N = NFLAG_32(src);
  1839. FLAG_Z = src;
  1840. FLAG_V = VFLAG_CLEAR;
  1841. }
  1842. M68KMAKE_OP(asl, 16, ., .)
  1843. {
  1844. uint ea = M68KMAKE_GET_EA_AY_16;
  1845. uint src = m68ki_read_16(ea);
  1846. uint res = MASK_OUT_ABOVE_16(src << 1);
  1847. m68ki_write_16(ea, res);
  1848. FLAG_N = NFLAG_16(res);
  1849. FLAG_Z = res;
  1850. FLAG_X = FLAG_C = src >> 7;
  1851. src &= 0xc000;
  1852. FLAG_V = (!(src == 0 || src == 0xc000))<<7;
  1853. }
  1854. M68KMAKE_OP(bcc, 8, ., .)
  1855. {
  1856. if(M68KMAKE_CC)
  1857. {
  1858. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  1859. m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
  1860. return;
  1861. }
  1862. USE_CYCLES(CYC_BCC_NOTAKE_B);
  1863. }
  1864. M68KMAKE_OP(bcc, 16, ., .)
  1865. {
  1866. if(M68KMAKE_CC)
  1867. {
  1868. uint offset = OPER_I_16();
  1869. REG_PC -= 2;
  1870. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  1871. m68ki_branch_16(offset);
  1872. return;
  1873. }
  1874. REG_PC += 2;
  1875. USE_CYCLES(CYC_BCC_NOTAKE_W);
  1876. }
  1877. M68KMAKE_OP(bcc, 32, ., .)
  1878. {
  1879. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  1880. {
  1881. if(M68KMAKE_CC)
  1882. {
  1883. uint offset = OPER_I_32();
  1884. REG_PC -= 4;
  1885. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  1886. m68ki_branch_32(offset);
  1887. return;
  1888. }
  1889. REG_PC += 4;
  1890. return;
  1891. }
  1892. else
  1893. {
  1894. if(M68KMAKE_CC)
  1895. {
  1896. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  1897. m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
  1898. return;
  1899. }
  1900. USE_CYCLES(CYC_BCC_NOTAKE_B);
  1901. }
  1902. }
  1903. M68KMAKE_OP(bchg, 32, r, d)
  1904. {
  1905. uint* r_dst = &DY;
  1906. uint mask = 1 << (DX & 0x1f);
  1907. FLAG_Z = *r_dst & mask;
  1908. *r_dst ^= mask;
  1909. }
  1910. M68KMAKE_OP(bchg, 8, r, .)
  1911. {
  1912. uint ea = M68KMAKE_GET_EA_AY_8;
  1913. uint src = m68ki_read_8(ea);
  1914. uint mask = 1 << (DX & 7);
  1915. FLAG_Z = src & mask;
  1916. m68ki_write_8(ea, src ^ mask);
  1917. }
  1918. M68KMAKE_OP(bchg, 32, s, d)
  1919. {
  1920. uint* r_dst = &DY;
  1921. uint mask = 1 << (OPER_I_8() & 0x1f);
  1922. FLAG_Z = *r_dst & mask;
  1923. *r_dst ^= mask;
  1924. }
  1925. M68KMAKE_OP(bchg, 8, s, .)
  1926. {
  1927. uint mask = 1 << (OPER_I_8() & 7);
  1928. uint ea = M68KMAKE_GET_EA_AY_8;
  1929. uint src = m68ki_read_8(ea);
  1930. FLAG_Z = src & mask;
  1931. m68ki_write_8(ea, src ^ mask);
  1932. }
  1933. M68KMAKE_OP(bclr, 32, r, d)
  1934. {
  1935. uint* r_dst = &DY;
  1936. uint mask = 1 << (DX & 0x1f);
  1937. FLAG_Z = *r_dst & mask;
  1938. *r_dst &= ~mask;
  1939. }
  1940. M68KMAKE_OP(bclr, 8, r, .)
  1941. {
  1942. uint ea = M68KMAKE_GET_EA_AY_8;
  1943. uint src = m68ki_read_8(ea);
  1944. uint mask = 1 << (DX & 7);
  1945. FLAG_Z = src & mask;
  1946. m68ki_write_8(ea, src & ~mask);
  1947. }
  1948. M68KMAKE_OP(bclr, 32, s, d)
  1949. {
  1950. uint* r_dst = &DY;
  1951. uint mask = 1 << (OPER_I_8() & 0x1f);
  1952. FLAG_Z = *r_dst & mask;
  1953. *r_dst &= ~mask;
  1954. }
  1955. M68KMAKE_OP(bclr, 8, s, .)
  1956. {
  1957. uint mask = 1 << (OPER_I_8() & 7);
  1958. uint ea = M68KMAKE_GET_EA_AY_8;
  1959. uint src = m68ki_read_8(ea);
  1960. FLAG_Z = src & mask;
  1961. m68ki_write_8(ea, src & ~mask);
  1962. }
  1963. M68KMAKE_OP(bfchg, 32, ., d)
  1964. {
  1965. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  1966. {
  1967. uint word2 = OPER_I_16();
  1968. uint offset = (word2>>6)&31;
  1969. uint width = word2;
  1970. uint* data = &DY;
  1971. uint64 mask;
  1972. if(BIT_B(word2))
  1973. offset = REG_D[offset&7];
  1974. if(BIT_5(word2))
  1975. width = REG_D[width&7];
  1976. offset &= 31;
  1977. width = ((width-1) & 31) + 1;
  1978. mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
  1979. mask = ROR_32(mask, offset);
  1980. FLAG_N = NFLAG_32(*data<<offset);
  1981. FLAG_Z = *data & mask;
  1982. FLAG_V = VFLAG_CLEAR;
  1983. FLAG_C = CFLAG_CLEAR;
  1984. *data ^= mask;
  1985. return;
  1986. }
  1987. m68ki_exception_illegal();
  1988. }
  1989. M68KMAKE_OP(bfchg, 32, ., .)
  1990. {
  1991. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  1992. {
  1993. uint word2 = OPER_I_16();
  1994. sint offset = (word2>>6)&31;
  1995. uint width = word2;
  1996. uint mask_base;
  1997. uint data_long;
  1998. uint mask_long;
  1999. uint data_byte = 0;
  2000. uint mask_byte = 0;
  2001. uint ea = M68KMAKE_GET_EA_AY_8;
  2002. if(BIT_B(word2))
  2003. offset = MAKE_INT_32(REG_D[offset&7]);
  2004. if(BIT_5(word2))
  2005. width = REG_D[width&7];
  2006. /* Offset is signed so we have to use ugly math =( */
  2007. ea += offset / 8;
  2008. offset %= 8;
  2009. if(offset < 0)
  2010. {
  2011. offset += 8;
  2012. ea--;
  2013. }
  2014. width = ((width-1) & 31) + 1;
  2015. mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
  2016. mask_long = mask_base >> offset;
  2017. data_long = m68ki_read_32(ea);
  2018. FLAG_N = NFLAG_32(data_long << offset);
  2019. FLAG_Z = data_long & mask_long;
  2020. FLAG_V = VFLAG_CLEAR;
  2021. FLAG_C = CFLAG_CLEAR;
  2022. m68ki_write_32(ea, data_long ^ mask_long);
  2023. if((width + offset) > 32)
  2024. {
  2025. mask_byte = MASK_OUT_ABOVE_8(mask_base);
  2026. data_byte = m68ki_read_8(ea+4);
  2027. FLAG_Z |= (data_byte & mask_byte);
  2028. m68ki_write_8(ea+4, data_byte ^ mask_byte);
  2029. }
  2030. return;
  2031. }
  2032. m68ki_exception_illegal();
  2033. }
  2034. M68KMAKE_OP(bfclr, 32, ., d)
  2035. {
  2036. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2037. {
  2038. uint word2 = OPER_I_16();
  2039. uint offset = (word2>>6)&31;
  2040. uint width = word2;
  2041. uint* data = &DY;
  2042. uint64 mask;
  2043. if(BIT_B(word2))
  2044. offset = REG_D[offset&7];
  2045. if(BIT_5(word2))
  2046. width = REG_D[width&7];
  2047. offset &= 31;
  2048. width = ((width-1) & 31) + 1;
  2049. mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
  2050. mask = ROR_32(mask, offset);
  2051. FLAG_N = NFLAG_32(*data<<offset);
  2052. FLAG_Z = *data & mask;
  2053. FLAG_V = VFLAG_CLEAR;
  2054. FLAG_C = CFLAG_CLEAR;
  2055. *data &= ~mask;
  2056. return;
  2057. }
  2058. m68ki_exception_illegal();
  2059. }
  2060. M68KMAKE_OP(bfclr, 32, ., .)
  2061. {
  2062. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2063. {
  2064. uint word2 = OPER_I_16();
  2065. sint offset = (word2>>6)&31;
  2066. uint width = word2;
  2067. uint mask_base;
  2068. uint data_long;
  2069. uint mask_long;
  2070. uint data_byte = 0;
  2071. uint mask_byte = 0;
  2072. uint ea = M68KMAKE_GET_EA_AY_8;
  2073. if(BIT_B(word2))
  2074. offset = MAKE_INT_32(REG_D[offset&7]);
  2075. if(BIT_5(word2))
  2076. width = REG_D[width&7];
  2077. /* Offset is signed so we have to use ugly math =( */
  2078. ea += offset / 8;
  2079. offset %= 8;
  2080. if(offset < 0)
  2081. {
  2082. offset += 8;
  2083. ea--;
  2084. }
  2085. width = ((width-1) & 31) + 1;
  2086. mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
  2087. mask_long = mask_base >> offset;
  2088. data_long = m68ki_read_32(ea);
  2089. FLAG_N = NFLAG_32(data_long << offset);
  2090. FLAG_Z = data_long & mask_long;
  2091. FLAG_V = VFLAG_CLEAR;
  2092. FLAG_C = CFLAG_CLEAR;
  2093. m68ki_write_32(ea, data_long & ~mask_long);
  2094. if((width + offset) > 32)
  2095. {
  2096. mask_byte = MASK_OUT_ABOVE_8(mask_base);
  2097. data_byte = m68ki_read_8(ea+4);
  2098. FLAG_Z |= (data_byte & mask_byte);
  2099. m68ki_write_8(ea+4, data_byte & ~mask_byte);
  2100. }
  2101. return;
  2102. }
  2103. m68ki_exception_illegal();
  2104. }
  2105. M68KMAKE_OP(bfexts, 32, ., d)
  2106. {
  2107. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2108. {
  2109. uint word2 = OPER_I_16();
  2110. uint offset = (word2>>6)&31;
  2111. uint width = word2;
  2112. uint64 data = DY;
  2113. if(BIT_B(word2))
  2114. offset = REG_D[offset&7];
  2115. if(BIT_5(word2))
  2116. width = REG_D[width&7];
  2117. offset &= 31;
  2118. width = ((width-1) & 31) + 1;
  2119. data = ROL_32(data, offset);
  2120. FLAG_N = NFLAG_32(data);
  2121. data = MAKE_INT_32(data) >> (32 - width);
  2122. FLAG_Z = data;
  2123. FLAG_V = VFLAG_CLEAR;
  2124. FLAG_C = CFLAG_CLEAR;
  2125. REG_D[(word2>>12)&7] = data;
  2126. return;
  2127. }
  2128. m68ki_exception_illegal();
  2129. }
  2130. M68KMAKE_OP(bfexts, 32, ., .)
  2131. {
  2132. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2133. {
  2134. uint word2 = OPER_I_16();
  2135. sint offset = (word2>>6)&31;
  2136. uint width = word2;
  2137. uint data;
  2138. uint ea = M68KMAKE_GET_EA_AY_8;
  2139. if(BIT_B(word2))
  2140. offset = MAKE_INT_32(REG_D[offset&7]);
  2141. if(BIT_5(word2))
  2142. width = REG_D[width&7];
  2143. /* Offset is signed so we have to use ugly math =( */
  2144. ea += offset / 8;
  2145. offset %= 8;
  2146. if(offset < 0)
  2147. {
  2148. offset += 8;
  2149. ea--;
  2150. }
  2151. width = ((width-1) & 31) + 1;
  2152. data = m68ki_read_32(ea);
  2153. data = MASK_OUT_ABOVE_32(data<<offset);
  2154. if((offset+width) > 32)
  2155. data |= (m68ki_read_8(ea+4) << offset) >> 8;
  2156. FLAG_N = NFLAG_32(data);
  2157. data = MAKE_INT_32(data) >> (32 - width);
  2158. FLAG_Z = data;
  2159. FLAG_V = VFLAG_CLEAR;
  2160. FLAG_C = CFLAG_CLEAR;
  2161. REG_D[(word2 >> 12) & 7] = data;
  2162. return;
  2163. }
  2164. m68ki_exception_illegal();
  2165. }
  2166. M68KMAKE_OP(bfextu, 32, ., d)
  2167. {
  2168. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2169. {
  2170. uint word2 = OPER_I_16();
  2171. uint offset = (word2>>6)&31;
  2172. uint width = word2;
  2173. uint64 data = DY;
  2174. if(BIT_B(word2))
  2175. offset = REG_D[offset&7];
  2176. if(BIT_5(word2))
  2177. width = REG_D[width&7];
  2178. offset &= 31;
  2179. width = ((width-1) & 31) + 1;
  2180. data = ROL_32(data, offset);
  2181. FLAG_N = NFLAG_32(data);
  2182. data >>= 32 - width;
  2183. FLAG_Z = data;
  2184. FLAG_V = VFLAG_CLEAR;
  2185. FLAG_C = CFLAG_CLEAR;
  2186. REG_D[(word2>>12)&7] = data;
  2187. return;
  2188. }
  2189. m68ki_exception_illegal();
  2190. }
  2191. M68KMAKE_OP(bfextu, 32, ., .)
  2192. {
  2193. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2194. {
  2195. uint word2 = OPER_I_16();
  2196. sint offset = (word2>>6)&31;
  2197. uint width = word2;
  2198. uint data;
  2199. uint ea = M68KMAKE_GET_EA_AY_8;
  2200. if(BIT_B(word2))
  2201. offset = MAKE_INT_32(REG_D[offset&7]);
  2202. if(BIT_5(word2))
  2203. width = REG_D[width&7];
  2204. /* Offset is signed so we have to use ugly math =( */
  2205. ea += offset / 8;
  2206. offset %= 8;
  2207. if(offset < 0)
  2208. {
  2209. offset += 8;
  2210. ea--;
  2211. }
  2212. width = ((width-1) & 31) + 1;
  2213. data = m68ki_read_32(ea);
  2214. data = MASK_OUT_ABOVE_32(data<<offset);
  2215. if((offset+width) > 32)
  2216. data |= (m68ki_read_8(ea+4) << offset) >> 8;
  2217. FLAG_N = NFLAG_32(data);
  2218. data >>= (32 - width);
  2219. FLAG_Z = data;
  2220. FLAG_V = VFLAG_CLEAR;
  2221. FLAG_C = CFLAG_CLEAR;
  2222. REG_D[(word2 >> 12) & 7] = data;
  2223. return;
  2224. }
  2225. m68ki_exception_illegal();
  2226. }
  2227. M68KMAKE_OP(bfffo, 32, ., d)
  2228. {
  2229. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2230. {
  2231. uint word2 = OPER_I_16();
  2232. uint offset = (word2>>6)&31;
  2233. uint width = word2;
  2234. uint64 data = DY;
  2235. uint bit;
  2236. if(BIT_B(word2))
  2237. offset = REG_D[offset&7];
  2238. if(BIT_5(word2))
  2239. width = REG_D[width&7];
  2240. offset &= 31;
  2241. width = ((width-1) & 31) + 1;
  2242. data = ROL_32(data, offset);
  2243. FLAG_N = NFLAG_32(data);
  2244. data >>= 32 - width;
  2245. FLAG_Z = data;
  2246. FLAG_V = VFLAG_CLEAR;
  2247. FLAG_C = CFLAG_CLEAR;
  2248. for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
  2249. offset++;
  2250. REG_D[(word2>>12)&7] = offset;
  2251. return;
  2252. }
  2253. m68ki_exception_illegal();
  2254. }
  2255. M68KMAKE_OP(bfffo, 32, ., .)
  2256. {
  2257. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2258. {
  2259. uint word2 = OPER_I_16();
  2260. sint offset = (word2>>6)&31;
  2261. sint local_offset;
  2262. uint width = word2;
  2263. uint data;
  2264. uint bit;
  2265. uint ea = M68KMAKE_GET_EA_AY_8;
  2266. if(BIT_B(word2))
  2267. offset = MAKE_INT_32(REG_D[offset&7]);
  2268. if(BIT_5(word2))
  2269. width = REG_D[width&7];
  2270. /* Offset is signed so we have to use ugly math =( */
  2271. ea += offset / 8;
  2272. local_offset = offset % 8;
  2273. if(local_offset < 0)
  2274. {
  2275. local_offset += 8;
  2276. ea--;
  2277. }
  2278. width = ((width-1) & 31) + 1;
  2279. data = m68ki_read_32(ea);
  2280. data = MASK_OUT_ABOVE_32(data<<local_offset);
  2281. if((local_offset+width) > 32)
  2282. data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
  2283. FLAG_N = NFLAG_32(data);
  2284. data >>= (32 - width);
  2285. FLAG_Z = data;
  2286. FLAG_V = VFLAG_CLEAR;
  2287. FLAG_C = CFLAG_CLEAR;
  2288. for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
  2289. offset++;
  2290. REG_D[(word2>>12)&7] = offset;
  2291. return;
  2292. }
  2293. m68ki_exception_illegal();
  2294. }
  2295. M68KMAKE_OP(bfins, 32, ., d)
  2296. {
  2297. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2298. {
  2299. uint word2 = OPER_I_16();
  2300. uint offset = (word2>>6)&31;
  2301. uint width = word2;
  2302. uint* data = &DY;
  2303. uint64 mask;
  2304. uint64 insert = REG_D[(word2>>12)&7];
  2305. if(BIT_B(word2))
  2306. offset = REG_D[offset&7];
  2307. if(BIT_5(word2))
  2308. width = REG_D[width&7];
  2309. offset &= 31;
  2310. width = ((width-1) & 31) + 1;
  2311. mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
  2312. mask = ROR_32(mask, offset);
  2313. insert = MASK_OUT_ABOVE_32(insert << (32 - width));
  2314. FLAG_N = NFLAG_32(insert);
  2315. FLAG_Z = insert;
  2316. insert = ROR_32(insert, offset);
  2317. FLAG_V = VFLAG_CLEAR;
  2318. FLAG_C = CFLAG_CLEAR;
  2319. *data &= ~mask;
  2320. *data |= insert;
  2321. return;
  2322. }
  2323. m68ki_exception_illegal();
  2324. }
  2325. M68KMAKE_OP(bfins, 32, ., .)
  2326. {
  2327. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2328. {
  2329. uint word2 = OPER_I_16();
  2330. sint offset = (word2>>6)&31;
  2331. uint width = word2;
  2332. uint insert_base = REG_D[(word2>>12)&7];
  2333. uint insert_long;
  2334. uint insert_byte;
  2335. uint mask_base;
  2336. uint data_long;
  2337. uint mask_long;
  2338. uint data_byte = 0;
  2339. uint mask_byte = 0;
  2340. uint ea = M68KMAKE_GET_EA_AY_8;
  2341. if(BIT_B(word2))
  2342. offset = MAKE_INT_32(REG_D[offset&7]);
  2343. if(BIT_5(word2))
  2344. width = REG_D[width&7];
  2345. /* Offset is signed so we have to use ugly math =( */
  2346. ea += offset / 8;
  2347. offset %= 8;
  2348. if(offset < 0)
  2349. {
  2350. offset += 8;
  2351. ea--;
  2352. }
  2353. width = ((width-1) & 31) + 1;
  2354. mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
  2355. mask_long = mask_base >> offset;
  2356. insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));
  2357. FLAG_N = NFLAG_32(insert_base);
  2358. FLAG_Z = insert_base;
  2359. insert_long = insert_base >> offset;
  2360. data_long = m68ki_read_32(ea);
  2361. FLAG_V = VFLAG_CLEAR;
  2362. FLAG_C = CFLAG_CLEAR;
  2363. m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);
  2364. if((width + offset) > 32)
  2365. {
  2366. mask_byte = MASK_OUT_ABOVE_8(mask_base);
  2367. insert_byte = MASK_OUT_ABOVE_8(insert_base);
  2368. data_byte = m68ki_read_8(ea+4);
  2369. FLAG_Z |= (data_byte & mask_byte);
  2370. m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);
  2371. }
  2372. return;
  2373. }
  2374. m68ki_exception_illegal();
  2375. }
  2376. M68KMAKE_OP(bfset, 32, ., d)
  2377. {
  2378. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2379. {
  2380. uint word2 = OPER_I_16();
  2381. uint offset = (word2>>6)&31;
  2382. uint width = word2;
  2383. uint* data = &DY;
  2384. uint64 mask;
  2385. if(BIT_B(word2))
  2386. offset = REG_D[offset&7];
  2387. if(BIT_5(word2))
  2388. width = REG_D[width&7];
  2389. offset &= 31;
  2390. width = ((width-1) & 31) + 1;
  2391. mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
  2392. mask = ROR_32(mask, offset);
  2393. FLAG_N = NFLAG_32(*data<<offset);
  2394. FLAG_Z = *data & mask;
  2395. FLAG_V = VFLAG_CLEAR;
  2396. FLAG_C = CFLAG_CLEAR;
  2397. *data |= mask;
  2398. return;
  2399. }
  2400. m68ki_exception_illegal();
  2401. }
  2402. M68KMAKE_OP(bfset, 32, ., .)
  2403. {
  2404. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2405. {
  2406. uint word2 = OPER_I_16();
  2407. sint offset = (word2>>6)&31;
  2408. uint width = word2;
  2409. uint mask_base;
  2410. uint data_long;
  2411. uint mask_long;
  2412. uint data_byte = 0;
  2413. uint mask_byte = 0;
  2414. uint ea = M68KMAKE_GET_EA_AY_8;
  2415. if(BIT_B(word2))
  2416. offset = MAKE_INT_32(REG_D[offset&7]);
  2417. if(BIT_5(word2))
  2418. width = REG_D[width&7];
  2419. /* Offset is signed so we have to use ugly math =( */
  2420. ea += offset / 8;
  2421. offset %= 8;
  2422. if(offset < 0)
  2423. {
  2424. offset += 8;
  2425. ea--;
  2426. }
  2427. width = ((width-1) & 31) + 1;
  2428. mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
  2429. mask_long = mask_base >> offset;
  2430. data_long = m68ki_read_32(ea);
  2431. FLAG_N = NFLAG_32(data_long << offset);
  2432. FLAG_Z = data_long & mask_long;
  2433. FLAG_V = VFLAG_CLEAR;
  2434. FLAG_C = CFLAG_CLEAR;
  2435. m68ki_write_32(ea, data_long | mask_long);
  2436. if((width + offset) > 32)
  2437. {
  2438. mask_byte = MASK_OUT_ABOVE_8(mask_base);
  2439. data_byte = m68ki_read_8(ea+4);
  2440. FLAG_Z |= (data_byte & mask_byte);
  2441. m68ki_write_8(ea+4, data_byte | mask_byte);
  2442. }
  2443. return;
  2444. }
  2445. m68ki_exception_illegal();
  2446. }
  2447. M68KMAKE_OP(bftst, 32, ., d)
  2448. {
  2449. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2450. {
  2451. uint word2 = OPER_I_16();
  2452. uint offset = (word2>>6)&31;
  2453. uint width = word2;
  2454. uint* data = &DY;
  2455. uint64 mask;
  2456. if(BIT_B(word2))
  2457. offset = REG_D[offset&7];
  2458. if(BIT_5(word2))
  2459. width = REG_D[width&7];
  2460. offset &= 31;
  2461. width = ((width-1) & 31) + 1;
  2462. mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
  2463. mask = ROR_32(mask, offset);
  2464. FLAG_N = NFLAG_32(*data<<offset);
  2465. FLAG_Z = *data & mask;
  2466. FLAG_V = VFLAG_CLEAR;
  2467. FLAG_C = CFLAG_CLEAR;
  2468. return;
  2469. }
  2470. m68ki_exception_illegal();
  2471. }
  2472. M68KMAKE_OP(bftst, 32, ., .)
  2473. {
  2474. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2475. {
  2476. uint word2 = OPER_I_16();
  2477. sint offset = (word2>>6)&31;
  2478. uint width = word2;
  2479. uint mask_base;
  2480. uint data_long;
  2481. uint mask_long;
  2482. uint data_byte = 0;
  2483. uint mask_byte = 0;
  2484. uint ea = M68KMAKE_GET_EA_AY_8;
  2485. if(BIT_B(word2))
  2486. offset = MAKE_INT_32(REG_D[offset&7]);
  2487. if(BIT_5(word2))
  2488. width = REG_D[width&7];
  2489. /* Offset is signed so we have to use ugly math =( */
  2490. ea += offset / 8;
  2491. offset %= 8;
  2492. if(offset < 0)
  2493. {
  2494. offset += 8;
  2495. ea--;
  2496. }
  2497. width = ((width-1) & 31) + 1;
  2498. mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
  2499. mask_long = mask_base >> offset;
  2500. data_long = m68ki_read_32(ea);
  2501. FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
  2502. FLAG_Z = data_long & mask_long;
  2503. FLAG_V = VFLAG_CLEAR;
  2504. FLAG_C = CFLAG_CLEAR;
  2505. if((width + offset) > 32)
  2506. {
  2507. mask_byte = MASK_OUT_ABOVE_8(mask_base);
  2508. data_byte = m68ki_read_8(ea+4);
  2509. FLAG_Z |= (data_byte & mask_byte);
  2510. }
  2511. return;
  2512. }
  2513. m68ki_exception_illegal();
  2514. }
  2515. M68KMAKE_OP(bkpt, 0, ., .)
  2516. {
  2517. if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
  2518. {
  2519. m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0); /* auto-disable (see m68kcpu.h) */
  2520. }
  2521. m68ki_exception_illegal();
  2522. }
  2523. M68KMAKE_OP(bra, 8, ., .)
  2524. {
  2525. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  2526. m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
  2527. if(REG_PC == REG_PPC)
  2528. USE_ALL_CYCLES();
  2529. }
  2530. M68KMAKE_OP(bra, 16, ., .)
  2531. {
  2532. uint offset = OPER_I_16();
  2533. REG_PC -= 2;
  2534. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  2535. m68ki_branch_16(offset);
  2536. if(REG_PC == REG_PPC)
  2537. USE_ALL_CYCLES();
  2538. }
  2539. M68KMAKE_OP(bra, 32, ., .)
  2540. {
  2541. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2542. {
  2543. uint offset = OPER_I_32();
  2544. REG_PC -= 4;
  2545. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  2546. m68ki_branch_32(offset);
  2547. if(REG_PC == REG_PPC)
  2548. USE_ALL_CYCLES();
  2549. return;
  2550. }
  2551. else
  2552. {
  2553. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  2554. m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
  2555. if(REG_PC == REG_PPC)
  2556. USE_ALL_CYCLES();
  2557. }
  2558. }
  2559. M68KMAKE_OP(bset, 32, r, d)
  2560. {
  2561. uint* r_dst = &DY;
  2562. uint mask = 1 << (DX & 0x1f);
  2563. FLAG_Z = *r_dst & mask;
  2564. *r_dst |= mask;
  2565. }
  2566. M68KMAKE_OP(bset, 8, r, .)
  2567. {
  2568. uint ea = M68KMAKE_GET_EA_AY_8;
  2569. uint src = m68ki_read_8(ea);
  2570. uint mask = 1 << (DX & 7);
  2571. FLAG_Z = src & mask;
  2572. m68ki_write_8(ea, src | mask);
  2573. }
  2574. M68KMAKE_OP(bset, 32, s, d)
  2575. {
  2576. uint* r_dst = &DY;
  2577. uint mask = 1 << (OPER_I_8() & 0x1f);
  2578. FLAG_Z = *r_dst & mask;
  2579. *r_dst |= mask;
  2580. }
  2581. M68KMAKE_OP(bset, 8, s, .)
  2582. {
  2583. uint mask = 1 << (OPER_I_8() & 7);
  2584. uint ea = M68KMAKE_GET_EA_AY_8;
  2585. uint src = m68ki_read_8(ea);
  2586. FLAG_Z = src & mask;
  2587. m68ki_write_8(ea, src | mask);
  2588. }
  2589. M68KMAKE_OP(bsr, 8, ., .)
  2590. {
  2591. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  2592. m68ki_push_32(REG_PC);
  2593. m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
  2594. }
  2595. M68KMAKE_OP(bsr, 16, ., .)
  2596. {
  2597. uint offset = OPER_I_16();
  2598. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  2599. m68ki_push_32(REG_PC);
  2600. REG_PC -= 2;
  2601. m68ki_branch_16(offset);
  2602. }
  2603. M68KMAKE_OP(bsr, 32, ., .)
  2604. {
  2605. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2606. {
  2607. uint offset = OPER_I_32();
  2608. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  2609. m68ki_push_32(REG_PC);
  2610. REG_PC -= 4;
  2611. m68ki_branch_32(offset);
  2612. return;
  2613. }
  2614. else
  2615. {
  2616. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  2617. m68ki_push_32(REG_PC);
  2618. m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
  2619. }
  2620. }
  2621. M68KMAKE_OP(btst, 32, r, d)
  2622. {
  2623. FLAG_Z = DY & (1 << (DX & 0x1f));
  2624. }
  2625. M68KMAKE_OP(btst, 8, r, .)
  2626. {
  2627. FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << (DX & 7));
  2628. }
  2629. M68KMAKE_OP(btst, 32, s, d)
  2630. {
  2631. FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f));
  2632. }
  2633. M68KMAKE_OP(btst, 8, s, .)
  2634. {
  2635. uint bit = OPER_I_8() & 7;
  2636. FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << bit);
  2637. }
  2638. M68KMAKE_OP(callm, 32, ., .)
  2639. {
  2640. /* note: watch out for pcrelative modes */
  2641. if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
  2642. {
  2643. uint ea = M68KMAKE_GET_EA_AY_32;
  2644. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  2645. REG_PC += 2;
  2646. (void)ea; /* just to avoid an 'unused variable' warning */
  2647. M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
  2648. m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
  2649. m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
  2650. return;
  2651. }
  2652. m68ki_exception_illegal();
  2653. }
  2654. M68KMAKE_OP(cas, 8, ., .)
  2655. {
  2656. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2657. {
  2658. uint word2 = OPER_I_16();
  2659. uint ea = M68KMAKE_GET_EA_AY_8;
  2660. uint dest = m68ki_read_8(ea);
  2661. uint* compare = &REG_D[word2 & 7];
  2662. uint res = dest - MASK_OUT_ABOVE_8(*compare);
  2663. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  2664. FLAG_N = NFLAG_8(res);
  2665. FLAG_Z = MASK_OUT_ABOVE_8(res);
  2666. FLAG_V = VFLAG_SUB_8(*compare, dest, res);
  2667. FLAG_C = CFLAG_8(res);
  2668. if(COND_NE())
  2669. *compare = MASK_OUT_BELOW_8(*compare) | dest;
  2670. else
  2671. {
  2672. USE_CYCLES(3);
  2673. m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
  2674. }
  2675. return;
  2676. }
  2677. m68ki_exception_illegal();
  2678. }
  2679. M68KMAKE_OP(cas, 16, ., .)
  2680. {
  2681. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2682. {
  2683. uint word2 = OPER_I_16();
  2684. uint ea = M68KMAKE_GET_EA_AY_16;
  2685. uint dest = m68ki_read_16(ea);
  2686. uint* compare = &REG_D[word2 & 7];
  2687. uint res = dest - MASK_OUT_ABOVE_16(*compare);
  2688. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  2689. FLAG_N = NFLAG_16(res);
  2690. FLAG_Z = MASK_OUT_ABOVE_16(res);
  2691. FLAG_V = VFLAG_SUB_16(*compare, dest, res);
  2692. FLAG_C = CFLAG_16(res);
  2693. if(COND_NE())
  2694. *compare = MASK_OUT_BELOW_16(*compare) | dest;
  2695. else
  2696. {
  2697. USE_CYCLES(3);
  2698. m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
  2699. }
  2700. return;
  2701. }
  2702. m68ki_exception_illegal();
  2703. }
  2704. M68KMAKE_OP(cas, 32, ., .)
  2705. {
  2706. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2707. {
  2708. uint word2 = OPER_I_16();
  2709. uint ea = M68KMAKE_GET_EA_AY_32;
  2710. uint dest = m68ki_read_32(ea);
  2711. uint* compare = &REG_D[word2 & 7];
  2712. uint res = dest - *compare;
  2713. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  2714. FLAG_N = NFLAG_32(res);
  2715. FLAG_Z = MASK_OUT_ABOVE_32(res);
  2716. FLAG_V = VFLAG_SUB_32(*compare, dest, res);
  2717. FLAG_C = CFLAG_SUB_32(*compare, dest, res);
  2718. if(COND_NE())
  2719. *compare = dest;
  2720. else
  2721. {
  2722. USE_CYCLES(3);
  2723. m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
  2724. }
  2725. return;
  2726. }
  2727. m68ki_exception_illegal();
  2728. }
  2729. M68KMAKE_OP(cas2, 16, ., .)
  2730. {
  2731. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2732. {
  2733. uint word2 = OPER_I_32();
  2734. uint* compare1 = &REG_D[(word2 >> 16) & 7];
  2735. uint ea1 = REG_DA[(word2 >> 28) & 15];
  2736. uint dest1 = m68ki_read_16(ea1);
  2737. uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1);
  2738. uint* compare2 = &REG_D[word2 & 7];
  2739. uint ea2 = REG_DA[(word2 >> 12) & 15];
  2740. uint dest2 = m68ki_read_16(ea2);
  2741. uint res2;
  2742. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  2743. FLAG_N = NFLAG_16(res1);
  2744. FLAG_Z = MASK_OUT_ABOVE_16(res1);
  2745. FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1);
  2746. FLAG_C = CFLAG_16(res1);
  2747. if(COND_EQ())
  2748. {
  2749. res2 = dest2 - MASK_OUT_ABOVE_16(*compare2);
  2750. FLAG_N = NFLAG_16(res2);
  2751. FLAG_Z = MASK_OUT_ABOVE_16(res2);
  2752. FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2);
  2753. FLAG_C = CFLAG_16(res2);
  2754. if(COND_EQ())
  2755. {
  2756. USE_CYCLES(3);
  2757. m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]);
  2758. m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]);
  2759. return;
  2760. }
  2761. }
  2762. *compare1 = BIT_1F(word2) ? MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1;
  2763. *compare2 = BIT_F(word2) ? MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2;
  2764. return;
  2765. }
  2766. m68ki_exception_illegal();
  2767. }
  2768. M68KMAKE_OP(cas2, 32, ., .)
  2769. {
  2770. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2771. {
  2772. uint word2 = OPER_I_32();
  2773. uint* compare1 = &REG_D[(word2 >> 16) & 7];
  2774. uint ea1 = REG_DA[(word2 >> 28) & 15];
  2775. uint dest1 = m68ki_read_32(ea1);
  2776. uint res1 = dest1 - *compare1;
  2777. uint* compare2 = &REG_D[word2 & 7];
  2778. uint ea2 = REG_DA[(word2 >> 12) & 15];
  2779. uint dest2 = m68ki_read_32(ea2);
  2780. uint res2;
  2781. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  2782. FLAG_N = NFLAG_32(res1);
  2783. FLAG_Z = MASK_OUT_ABOVE_32(res1);
  2784. FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1);
  2785. FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1);
  2786. if(COND_EQ())
  2787. {
  2788. res2 = dest2 - *compare2;
  2789. FLAG_N = NFLAG_32(res2);
  2790. FLAG_Z = MASK_OUT_ABOVE_32(res2);
  2791. FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2);
  2792. FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2);
  2793. if(COND_EQ())
  2794. {
  2795. USE_CYCLES(3);
  2796. m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]);
  2797. m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]);
  2798. return;
  2799. }
  2800. }
  2801. *compare1 = dest1;
  2802. *compare2 = dest2;
  2803. return;
  2804. }
  2805. m68ki_exception_illegal();
  2806. }
  2807. M68KMAKE_OP(chk, 16, ., d)
  2808. {
  2809. sint src = MAKE_INT_16(DX);
  2810. sint bound = MAKE_INT_16(DY);
  2811. FLAG_Z = ZFLAG_16(src); /* Undocumented */
  2812. FLAG_V = VFLAG_CLEAR; /* Undocumented */
  2813. FLAG_C = CFLAG_CLEAR; /* Undocumented */
  2814. if(src >= 0 && src <= bound)
  2815. {
  2816. return;
  2817. }
  2818. FLAG_N = (src < 0)<<7;
  2819. m68ki_exception_trap(EXCEPTION_CHK);
  2820. }
  2821. M68KMAKE_OP(chk, 16, ., .)
  2822. {
  2823. sint src = MAKE_INT_16(DX);
  2824. sint bound = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
  2825. FLAG_Z = ZFLAG_16(src); /* Undocumented */
  2826. FLAG_V = VFLAG_CLEAR; /* Undocumented */
  2827. FLAG_C = CFLAG_CLEAR; /* Undocumented */
  2828. if(src >= 0 && src <= bound)
  2829. {
  2830. return;
  2831. }
  2832. FLAG_N = (src < 0)<<7;
  2833. m68ki_exception_trap(EXCEPTION_CHK);
  2834. }
  2835. M68KMAKE_OP(chk, 32, ., d)
  2836. {
  2837. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2838. {
  2839. sint src = MAKE_INT_32(DX);
  2840. sint bound = MAKE_INT_32(DY);
  2841. FLAG_Z = ZFLAG_32(src); /* Undocumented */
  2842. FLAG_V = VFLAG_CLEAR; /* Undocumented */
  2843. FLAG_C = CFLAG_CLEAR; /* Undocumented */
  2844. if(src >= 0 && src <= bound)
  2845. {
  2846. return;
  2847. }
  2848. FLAG_N = (src < 0)<<7;
  2849. m68ki_exception_trap(EXCEPTION_CHK);
  2850. return;
  2851. }
  2852. m68ki_exception_illegal();
  2853. }
  2854. M68KMAKE_OP(chk, 32, ., .)
  2855. {
  2856. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2857. {
  2858. sint src = MAKE_INT_32(DX);
  2859. sint bound = MAKE_INT_32(M68KMAKE_GET_OPER_AY_32);
  2860. FLAG_Z = ZFLAG_32(src); /* Undocumented */
  2861. FLAG_V = VFLAG_CLEAR; /* Undocumented */
  2862. FLAG_C = CFLAG_CLEAR; /* Undocumented */
  2863. if(src >= 0 && src <= bound)
  2864. {
  2865. return;
  2866. }
  2867. FLAG_N = (src < 0)<<7;
  2868. m68ki_exception_trap(EXCEPTION_CHK);
  2869. return;
  2870. }
  2871. m68ki_exception_illegal();
  2872. }
  2873. M68KMAKE_OP(chk2cmp2, 8, ., pcdi)
  2874. {
  2875. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2876. {
  2877. uint word2 = OPER_I_16();
  2878. uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
  2879. uint ea = EA_PCDI_8();
  2880. uint lower_bound = m68ki_read_pcrel_8(ea);
  2881. uint upper_bound = m68ki_read_pcrel_8(ea + 1);
  2882. if(!BIT_F(word2))
  2883. FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
  2884. else
  2885. FLAG_C = compare - lower_bound;
  2886. FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
  2887. if(COND_CS())
  2888. {
  2889. if(BIT_B(word2))
  2890. m68ki_exception_trap(EXCEPTION_CHK);
  2891. return;
  2892. }
  2893. FLAG_C = upper_bound - compare;
  2894. if(COND_CS() && BIT_B(word2))
  2895. m68ki_exception_trap(EXCEPTION_CHK);
  2896. return;
  2897. }
  2898. m68ki_exception_illegal();
  2899. }
  2900. M68KMAKE_OP(chk2cmp2, 8, ., pcix)
  2901. {
  2902. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2903. {
  2904. uint word2 = OPER_I_16();
  2905. uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
  2906. uint ea = EA_PCIX_8();
  2907. uint lower_bound = m68ki_read_pcrel_8(ea);
  2908. uint upper_bound = m68ki_read_pcrel_8(ea + 1);
  2909. if(!BIT_F(word2))
  2910. FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
  2911. else
  2912. FLAG_C = compare - lower_bound;
  2913. FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
  2914. if(COND_CS())
  2915. {
  2916. if(BIT_B(word2))
  2917. m68ki_exception_trap(EXCEPTION_CHK);
  2918. return;
  2919. }
  2920. FLAG_C = upper_bound - compare;
  2921. if(COND_CS() && BIT_B(word2))
  2922. m68ki_exception_trap(EXCEPTION_CHK);
  2923. return;
  2924. }
  2925. m68ki_exception_illegal();
  2926. }
  2927. M68KMAKE_OP(chk2cmp2, 8, ., .)
  2928. {
  2929. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2930. {
  2931. uint word2 = OPER_I_16();
  2932. uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
  2933. uint ea = M68KMAKE_GET_EA_AY_8;
  2934. uint lower_bound = m68ki_read_8(ea);
  2935. uint upper_bound = m68ki_read_8(ea + 1);
  2936. if(!BIT_F(word2))
  2937. FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
  2938. else
  2939. FLAG_C = compare - lower_bound;
  2940. FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
  2941. if(COND_CS())
  2942. {
  2943. if(BIT_B(word2))
  2944. m68ki_exception_trap(EXCEPTION_CHK);
  2945. return;
  2946. }
  2947. FLAG_C = upper_bound - compare;
  2948. if(COND_CS() && BIT_B(word2))
  2949. m68ki_exception_trap(EXCEPTION_CHK);
  2950. return;
  2951. }
  2952. m68ki_exception_illegal();
  2953. }
  2954. M68KMAKE_OP(chk2cmp2, 16, ., pcdi)
  2955. {
  2956. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2957. {
  2958. uint word2 = OPER_I_16();
  2959. uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
  2960. uint ea = EA_PCDI_16();
  2961. uint lower_bound = m68ki_read_pcrel_16(ea);
  2962. uint upper_bound = m68ki_read_pcrel_16(ea + 2);
  2963. if(!BIT_F(word2))
  2964. FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
  2965. else
  2966. FLAG_C = compare - lower_bound;
  2967. FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
  2968. FLAG_C = CFLAG_16(FLAG_C);
  2969. if(COND_CS())
  2970. {
  2971. if(BIT_B(word2))
  2972. m68ki_exception_trap(EXCEPTION_CHK);
  2973. return;
  2974. }
  2975. if(!BIT_F(word2))
  2976. FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
  2977. else
  2978. FLAG_C = upper_bound - compare;
  2979. FLAG_C = CFLAG_16(FLAG_C);
  2980. if(COND_CS() && BIT_B(word2))
  2981. m68ki_exception_trap(EXCEPTION_CHK);
  2982. return;
  2983. }
  2984. m68ki_exception_illegal();
  2985. }
  2986. M68KMAKE_OP(chk2cmp2, 16, ., pcix)
  2987. {
  2988. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  2989. {
  2990. uint word2 = OPER_I_16();
  2991. uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
  2992. uint ea = EA_PCIX_16();
  2993. uint lower_bound = m68ki_read_pcrel_16(ea);
  2994. uint upper_bound = m68ki_read_pcrel_16(ea + 2);
  2995. if(!BIT_F(word2))
  2996. FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
  2997. else
  2998. FLAG_C = compare - lower_bound;
  2999. FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
  3000. FLAG_C = CFLAG_16(FLAG_C);
  3001. if(COND_CS())
  3002. {
  3003. if(BIT_B(word2))
  3004. m68ki_exception_trap(EXCEPTION_CHK);
  3005. return;
  3006. }
  3007. if(!BIT_F(word2))
  3008. FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
  3009. else
  3010. FLAG_C = upper_bound - compare;
  3011. FLAG_C = CFLAG_16(FLAG_C);
  3012. if(COND_CS() && BIT_B(word2))
  3013. m68ki_exception_trap(EXCEPTION_CHK);
  3014. return;
  3015. }
  3016. m68ki_exception_illegal();
  3017. }
  3018. M68KMAKE_OP(chk2cmp2, 16, ., .)
  3019. {
  3020. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3021. {
  3022. uint word2 = OPER_I_16();
  3023. uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
  3024. uint ea = M68KMAKE_GET_EA_AY_16;
  3025. uint lower_bound = m68ki_read_16(ea);
  3026. uint upper_bound = m68ki_read_16(ea + 2);
  3027. if(!BIT_F(word2))
  3028. FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
  3029. else
  3030. FLAG_C = compare - lower_bound;
  3031. FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
  3032. FLAG_C = CFLAG_16(FLAG_C);
  3033. if(COND_CS())
  3034. {
  3035. if(BIT_B(word2))
  3036. m68ki_exception_trap(EXCEPTION_CHK);
  3037. return;
  3038. }
  3039. if(!BIT_F(word2))
  3040. FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
  3041. else
  3042. FLAG_C = upper_bound - compare;
  3043. FLAG_C = CFLAG_16(FLAG_C);
  3044. if(COND_CS() && BIT_B(word2))
  3045. m68ki_exception_trap(EXCEPTION_CHK);
  3046. return;
  3047. }
  3048. m68ki_exception_illegal();
  3049. }
  3050. M68KMAKE_OP(chk2cmp2, 32, ., pcdi)
  3051. {
  3052. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3053. {
  3054. uint word2 = OPER_I_16();
  3055. uint compare = REG_DA[(word2 >> 12) & 15];
  3056. uint ea = EA_PCDI_32();
  3057. uint lower_bound = m68ki_read_pcrel_32(ea);
  3058. uint upper_bound = m68ki_read_pcrel_32(ea + 4);
  3059. FLAG_C = compare - lower_bound;
  3060. FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
  3061. FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
  3062. if(COND_CS())
  3063. {
  3064. if(BIT_B(word2))
  3065. m68ki_exception_trap(EXCEPTION_CHK);
  3066. return;
  3067. }
  3068. FLAG_C = upper_bound - compare;
  3069. FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
  3070. if(COND_CS() && BIT_B(word2))
  3071. m68ki_exception_trap(EXCEPTION_CHK);
  3072. return;
  3073. }
  3074. m68ki_exception_illegal();
  3075. }
  3076. M68KMAKE_OP(chk2cmp2, 32, ., pcix)
  3077. {
  3078. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3079. {
  3080. uint word2 = OPER_I_16();
  3081. uint compare = REG_DA[(word2 >> 12) & 15];
  3082. uint ea = EA_PCIX_32();
  3083. uint lower_bound = m68ki_read_pcrel_32(ea);
  3084. uint upper_bound = m68ki_read_pcrel_32(ea + 4);
  3085. FLAG_C = compare - lower_bound;
  3086. FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
  3087. FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
  3088. if(COND_CS())
  3089. {
  3090. if(BIT_B(word2))
  3091. m68ki_exception_trap(EXCEPTION_CHK);
  3092. return;
  3093. }
  3094. FLAG_C = upper_bound - compare;
  3095. FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
  3096. if(COND_CS() && BIT_B(word2))
  3097. m68ki_exception_trap(EXCEPTION_CHK);
  3098. return;
  3099. }
  3100. m68ki_exception_illegal();
  3101. }
  3102. M68KMAKE_OP(chk2cmp2, 32, ., .)
  3103. {
  3104. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3105. {
  3106. uint word2 = OPER_I_16();
  3107. uint compare = REG_DA[(word2 >> 12) & 15];
  3108. uint ea = M68KMAKE_GET_EA_AY_32;
  3109. uint lower_bound = m68ki_read_32(ea);
  3110. uint upper_bound = m68ki_read_32(ea + 4);
  3111. FLAG_C = compare - lower_bound;
  3112. FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
  3113. FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
  3114. if(COND_CS())
  3115. {
  3116. if(BIT_B(word2))
  3117. m68ki_exception_trap(EXCEPTION_CHK);
  3118. return;
  3119. }
  3120. FLAG_C = upper_bound - compare;
  3121. FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
  3122. if(COND_CS() && BIT_B(word2))
  3123. m68ki_exception_trap(EXCEPTION_CHK);
  3124. return;
  3125. }
  3126. m68ki_exception_illegal();
  3127. }
  3128. M68KMAKE_OP(clr, 8, ., d)
  3129. {
  3130. DY &= 0xffffff00;
  3131. FLAG_N = NFLAG_CLEAR;
  3132. FLAG_V = VFLAG_CLEAR;
  3133. FLAG_C = CFLAG_CLEAR;
  3134. FLAG_Z = ZFLAG_SET;
  3135. }
  3136. M68KMAKE_OP(clr, 8, ., .)
  3137. {
  3138. m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
  3139. FLAG_N = NFLAG_CLEAR;
  3140. FLAG_V = VFLAG_CLEAR;
  3141. FLAG_C = CFLAG_CLEAR;
  3142. FLAG_Z = ZFLAG_SET;
  3143. }
  3144. M68KMAKE_OP(clr, 16, ., d)
  3145. {
  3146. DY &= 0xffff0000;
  3147. FLAG_N = NFLAG_CLEAR;
  3148. FLAG_V = VFLAG_CLEAR;
  3149. FLAG_C = CFLAG_CLEAR;
  3150. FLAG_Z = ZFLAG_SET;
  3151. }
  3152. M68KMAKE_OP(clr, 16, ., .)
  3153. {
  3154. m68ki_write_16(M68KMAKE_GET_EA_AY_16, 0);
  3155. FLAG_N = NFLAG_CLEAR;
  3156. FLAG_V = VFLAG_CLEAR;
  3157. FLAG_C = CFLAG_CLEAR;
  3158. FLAG_Z = ZFLAG_SET;
  3159. }
  3160. M68KMAKE_OP(clr, 32, ., d)
  3161. {
  3162. DY = 0;
  3163. FLAG_N = NFLAG_CLEAR;
  3164. FLAG_V = VFLAG_CLEAR;
  3165. FLAG_C = CFLAG_CLEAR;
  3166. FLAG_Z = ZFLAG_SET;
  3167. }
  3168. M68KMAKE_OP(clr, 32, ., .)
  3169. {
  3170. m68ki_write_32(M68KMAKE_GET_EA_AY_32, 0);
  3171. FLAG_N = NFLAG_CLEAR;
  3172. FLAG_V = VFLAG_CLEAR;
  3173. FLAG_C = CFLAG_CLEAR;
  3174. FLAG_Z = ZFLAG_SET;
  3175. }
  3176. M68KMAKE_OP(cmp, 8, ., d)
  3177. {
  3178. uint src = MASK_OUT_ABOVE_8(DY);
  3179. uint dst = MASK_OUT_ABOVE_8(DX);
  3180. uint res = dst - src;
  3181. FLAG_N = NFLAG_8(res);
  3182. FLAG_Z = MASK_OUT_ABOVE_8(res);
  3183. FLAG_V = VFLAG_SUB_8(src, dst, res);
  3184. FLAG_C = CFLAG_8(res);
  3185. }
  3186. M68KMAKE_OP(cmp, 8, ., .)
  3187. {
  3188. uint src = M68KMAKE_GET_OPER_AY_8;
  3189. uint dst = MASK_OUT_ABOVE_8(DX);
  3190. uint res = dst - src;
  3191. FLAG_N = NFLAG_8(res);
  3192. FLAG_Z = MASK_OUT_ABOVE_8(res);
  3193. FLAG_V = VFLAG_SUB_8(src, dst, res);
  3194. FLAG_C = CFLAG_8(res);
  3195. }
  3196. M68KMAKE_OP(cmp, 16, ., d)
  3197. {
  3198. uint src = MASK_OUT_ABOVE_16(DY);
  3199. uint dst = MASK_OUT_ABOVE_16(DX);
  3200. uint res = dst - src;
  3201. FLAG_N = NFLAG_16(res);
  3202. FLAG_Z = MASK_OUT_ABOVE_16(res);
  3203. FLAG_V = VFLAG_SUB_16(src, dst, res);
  3204. FLAG_C = CFLAG_16(res);
  3205. }
  3206. M68KMAKE_OP(cmp, 16, ., a)
  3207. {
  3208. uint src = MASK_OUT_ABOVE_16(AY);
  3209. uint dst = MASK_OUT_ABOVE_16(DX);
  3210. uint res = dst - src;
  3211. FLAG_N = NFLAG_16(res);
  3212. FLAG_Z = MASK_OUT_ABOVE_16(res);
  3213. FLAG_V = VFLAG_SUB_16(src, dst, res);
  3214. FLAG_C = CFLAG_16(res);
  3215. }
  3216. M68KMAKE_OP(cmp, 16, ., .)
  3217. {
  3218. uint src = M68KMAKE_GET_OPER_AY_16;
  3219. uint dst = MASK_OUT_ABOVE_16(DX);
  3220. uint res = dst - src;
  3221. FLAG_N = NFLAG_16(res);
  3222. FLAG_Z = MASK_OUT_ABOVE_16(res);
  3223. FLAG_V = VFLAG_SUB_16(src, dst, res);
  3224. FLAG_C = CFLAG_16(res);
  3225. }
  3226. M68KMAKE_OP(cmp, 32, ., d)
  3227. {
  3228. uint src = DY;
  3229. uint dst = DX;
  3230. uint res = dst - src;
  3231. FLAG_N = NFLAG_32(res);
  3232. FLAG_Z = MASK_OUT_ABOVE_32(res);
  3233. FLAG_V = VFLAG_SUB_32(src, dst, res);
  3234. FLAG_C = CFLAG_SUB_32(src, dst, res);
  3235. }
  3236. M68KMAKE_OP(cmp, 32, ., a)
  3237. {
  3238. uint src = AY;
  3239. uint dst = DX;
  3240. uint res = dst - src;
  3241. FLAG_N = NFLAG_32(res);
  3242. FLAG_Z = MASK_OUT_ABOVE_32(res);
  3243. FLAG_V = VFLAG_SUB_32(src, dst, res);
  3244. FLAG_C = CFLAG_SUB_32(src, dst, res);
  3245. }
  3246. M68KMAKE_OP(cmp, 32, ., .)
  3247. {
  3248. uint src = M68KMAKE_GET_OPER_AY_32;
  3249. uint dst = DX;
  3250. uint res = dst - src;
  3251. FLAG_N = NFLAG_32(res);
  3252. FLAG_Z = MASK_OUT_ABOVE_32(res);
  3253. FLAG_V = VFLAG_SUB_32(src, dst, res);
  3254. FLAG_C = CFLAG_SUB_32(src, dst, res);
  3255. }
  3256. M68KMAKE_OP(cmpa, 16, ., d)
  3257. {
  3258. uint src = MAKE_INT_16(DY);
  3259. uint dst = AX;
  3260. uint res = dst - src;
  3261. FLAG_N = NFLAG_32(res);
  3262. FLAG_Z = MASK_OUT_ABOVE_32(res);
  3263. FLAG_V = VFLAG_SUB_32(src, dst, res);
  3264. FLAG_C = CFLAG_SUB_32(src, dst, res);
  3265. }
  3266. M68KMAKE_OP(cmpa, 16, ., a)
  3267. {
  3268. uint src = MAKE_INT_16(AY);
  3269. uint dst = AX;
  3270. uint res = dst - src;
  3271. FLAG_N = NFLAG_32(res);
  3272. FLAG_Z = MASK_OUT_ABOVE_32(res);
  3273. FLAG_V = VFLAG_SUB_32(src, dst, res);
  3274. FLAG_C = CFLAG_SUB_32(src, dst, res);
  3275. }
  3276. M68KMAKE_OP(cmpa, 16, ., .)
  3277. {
  3278. uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
  3279. uint dst = AX;
  3280. uint res = dst - src;
  3281. FLAG_N = NFLAG_32(res);
  3282. FLAG_Z = MASK_OUT_ABOVE_32(res);
  3283. FLAG_V = VFLAG_SUB_32(src, dst, res);
  3284. FLAG_C = CFLAG_SUB_32(src, dst, res);
  3285. }
  3286. M68KMAKE_OP(cmpa, 32, ., d)
  3287. {
  3288. uint src = DY;
  3289. uint dst = AX;
  3290. uint res = dst - src;
  3291. FLAG_N = NFLAG_32(res);
  3292. FLAG_Z = MASK_OUT_ABOVE_32(res);
  3293. FLAG_V = VFLAG_SUB_32(src, dst, res);
  3294. FLAG_C = CFLAG_SUB_32(src, dst, res);
  3295. }
  3296. M68KMAKE_OP(cmpa, 32, ., a)
  3297. {
  3298. uint src = AY;
  3299. uint dst = AX;
  3300. uint res = dst - src;
  3301. FLAG_N = NFLAG_32(res);
  3302. FLAG_Z = MASK_OUT_ABOVE_32(res);
  3303. FLAG_V = VFLAG_SUB_32(src, dst, res);
  3304. FLAG_C = CFLAG_SUB_32(src, dst, res);
  3305. }
  3306. M68KMAKE_OP(cmpa, 32, ., .)
  3307. {
  3308. uint src = M68KMAKE_GET_OPER_AY_32;
  3309. uint dst = AX;
  3310. uint res = dst - src;
  3311. FLAG_N = NFLAG_32(res);
  3312. FLAG_Z = MASK_OUT_ABOVE_32(res);
  3313. FLAG_V = VFLAG_SUB_32(src, dst, res);
  3314. FLAG_C = CFLAG_SUB_32(src, dst, res);
  3315. }
  3316. M68KMAKE_OP(cmpi, 8, ., d)
  3317. {
  3318. uint src = OPER_I_8();
  3319. uint dst = MASK_OUT_ABOVE_8(DY);
  3320. uint res = dst - src;
  3321. FLAG_N = NFLAG_8(res);
  3322. FLAG_Z = MASK_OUT_ABOVE_8(res);
  3323. FLAG_V = VFLAG_SUB_8(src, dst, res);
  3324. FLAG_C = CFLAG_8(res);
  3325. }
  3326. M68KMAKE_OP(cmpi, 8, ., .)
  3327. {
  3328. uint src = OPER_I_8();
  3329. uint dst = M68KMAKE_GET_OPER_AY_8;
  3330. uint res = dst - src;
  3331. FLAG_N = NFLAG_8(res);
  3332. FLAG_Z = MASK_OUT_ABOVE_8(res);
  3333. FLAG_V = VFLAG_SUB_8(src, dst, res);
  3334. FLAG_C = CFLAG_8(res);
  3335. }
  3336. M68KMAKE_OP(cmpi, 8, ., pcdi)
  3337. {
  3338. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3339. {
  3340. uint src = OPER_I_8();
  3341. uint dst = OPER_PCDI_8();
  3342. uint res = dst - src;
  3343. FLAG_N = NFLAG_8(res);
  3344. FLAG_Z = MASK_OUT_ABOVE_8(res);
  3345. FLAG_V = VFLAG_SUB_8(src, dst, res);
  3346. FLAG_C = CFLAG_8(res);
  3347. return;
  3348. }
  3349. m68ki_exception_illegal();
  3350. }
  3351. M68KMAKE_OP(cmpi, 8, ., pcix)
  3352. {
  3353. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3354. {
  3355. uint src = OPER_I_8();
  3356. uint dst = OPER_PCIX_8();
  3357. uint res = dst - src;
  3358. FLAG_N = NFLAG_8(res);
  3359. FLAG_Z = MASK_OUT_ABOVE_8(res);
  3360. FLAG_V = VFLAG_SUB_8(src, dst, res);
  3361. FLAG_C = CFLAG_8(res);
  3362. return;
  3363. }
  3364. m68ki_exception_illegal();
  3365. }
  3366. M68KMAKE_OP(cmpi, 16, ., d)
  3367. {
  3368. uint src = OPER_I_16();
  3369. uint dst = MASK_OUT_ABOVE_16(DY);
  3370. uint res = dst - src;
  3371. FLAG_N = NFLAG_16(res);
  3372. FLAG_Z = MASK_OUT_ABOVE_16(res);
  3373. FLAG_V = VFLAG_SUB_16(src, dst, res);
  3374. FLAG_C = CFLAG_16(res);
  3375. }
  3376. M68KMAKE_OP(cmpi, 16, ., .)
  3377. {
  3378. uint src = OPER_I_16();
  3379. uint dst = M68KMAKE_GET_OPER_AY_16;
  3380. uint res = dst - src;
  3381. FLAG_N = NFLAG_16(res);
  3382. FLAG_Z = MASK_OUT_ABOVE_16(res);
  3383. FLAG_V = VFLAG_SUB_16(src, dst, res);
  3384. FLAG_C = CFLAG_16(res);
  3385. }
  3386. M68KMAKE_OP(cmpi, 16, ., pcdi)
  3387. {
  3388. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3389. {
  3390. uint src = OPER_I_16();
  3391. uint dst = OPER_PCDI_16();
  3392. uint res = dst - src;
  3393. FLAG_N = NFLAG_16(res);
  3394. FLAG_Z = MASK_OUT_ABOVE_16(res);
  3395. FLAG_V = VFLAG_SUB_16(src, dst, res);
  3396. FLAG_C = CFLAG_16(res);
  3397. return;
  3398. }
  3399. m68ki_exception_illegal();
  3400. }
  3401. M68KMAKE_OP(cmpi, 16, ., pcix)
  3402. {
  3403. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3404. {
  3405. uint src = OPER_I_16();
  3406. uint dst = OPER_PCIX_16();
  3407. uint res = dst - src;
  3408. FLAG_N = NFLAG_16(res);
  3409. FLAG_Z = MASK_OUT_ABOVE_16(res);
  3410. FLAG_V = VFLAG_SUB_16(src, dst, res);
  3411. FLAG_C = CFLAG_16(res);
  3412. return;
  3413. }
  3414. m68ki_exception_illegal();
  3415. }
  3416. M68KMAKE_OP(cmpi, 32, ., d)
  3417. {
  3418. uint src = OPER_I_32();
  3419. uint dst = DY;
  3420. uint res = dst - src;
  3421. m68ki_cmpild_callback(src, REG_IR & 7); /* auto-disable (see m68kcpu.h) */
  3422. FLAG_N = NFLAG_32(res);
  3423. FLAG_Z = MASK_OUT_ABOVE_32(res);
  3424. FLAG_V = VFLAG_SUB_32(src, dst, res);
  3425. FLAG_C = CFLAG_SUB_32(src, dst, res);
  3426. }
  3427. M68KMAKE_OP(cmpi, 32, ., .)
  3428. {
  3429. uint src = OPER_I_32();
  3430. uint dst = M68KMAKE_GET_OPER_AY_32;
  3431. uint res = dst - src;
  3432. FLAG_N = NFLAG_32(res);
  3433. FLAG_Z = MASK_OUT_ABOVE_32(res);
  3434. FLAG_V = VFLAG_SUB_32(src, dst, res);
  3435. FLAG_C = CFLAG_SUB_32(src, dst, res);
  3436. }
  3437. M68KMAKE_OP(cmpi, 32, ., pcdi)
  3438. {
  3439. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3440. {
  3441. uint src = OPER_I_32();
  3442. uint dst = OPER_PCDI_32();
  3443. uint res = dst - src;
  3444. FLAG_N = NFLAG_32(res);
  3445. FLAG_Z = MASK_OUT_ABOVE_32(res);
  3446. FLAG_V = VFLAG_SUB_32(src, dst, res);
  3447. FLAG_C = CFLAG_SUB_32(src, dst, res);
  3448. return;
  3449. }
  3450. m68ki_exception_illegal();
  3451. }
  3452. M68KMAKE_OP(cmpi, 32, ., pcix)
  3453. {
  3454. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3455. {
  3456. uint src = OPER_I_32();
  3457. uint dst = OPER_PCIX_32();
  3458. uint res = dst - src;
  3459. FLAG_N = NFLAG_32(res);
  3460. FLAG_Z = MASK_OUT_ABOVE_32(res);
  3461. FLAG_V = VFLAG_SUB_32(src, dst, res);
  3462. FLAG_C = CFLAG_SUB_32(src, dst, res);
  3463. return;
  3464. }
  3465. m68ki_exception_illegal();
  3466. }
  3467. M68KMAKE_OP(cmpm, 8, ., ax7)
  3468. {
  3469. uint src = OPER_AY_PI_8();
  3470. uint dst = OPER_A7_PI_8();
  3471. uint res = dst - src;
  3472. FLAG_N = NFLAG_8(res);
  3473. FLAG_Z = MASK_OUT_ABOVE_8(res);
  3474. FLAG_V = VFLAG_SUB_8(src, dst, res);
  3475. FLAG_C = CFLAG_8(res);
  3476. }
  3477. M68KMAKE_OP(cmpm, 8, ., ay7)
  3478. {
  3479. uint src = OPER_A7_PI_8();
  3480. uint dst = OPER_AX_PI_8();
  3481. uint res = dst - src;
  3482. FLAG_N = NFLAG_8(res);
  3483. FLAG_Z = MASK_OUT_ABOVE_8(res);
  3484. FLAG_V = VFLAG_SUB_8(src, dst, res);
  3485. FLAG_C = CFLAG_8(res);
  3486. }
  3487. M68KMAKE_OP(cmpm, 8, ., axy7)
  3488. {
  3489. uint src = OPER_A7_PI_8();
  3490. uint dst = OPER_A7_PI_8();
  3491. uint res = dst - src;
  3492. FLAG_N = NFLAG_8(res);
  3493. FLAG_Z = MASK_OUT_ABOVE_8(res);
  3494. FLAG_V = VFLAG_SUB_8(src, dst, res);
  3495. FLAG_C = CFLAG_8(res);
  3496. }
  3497. M68KMAKE_OP(cmpm, 8, ., .)
  3498. {
  3499. uint src = OPER_AY_PI_8();
  3500. uint dst = OPER_AX_PI_8();
  3501. uint res = dst - src;
  3502. FLAG_N = NFLAG_8(res);
  3503. FLAG_Z = MASK_OUT_ABOVE_8(res);
  3504. FLAG_V = VFLAG_SUB_8(src, dst, res);
  3505. FLAG_C = CFLAG_8(res);
  3506. }
  3507. M68KMAKE_OP(cmpm, 16, ., .)
  3508. {
  3509. uint src = OPER_AY_PI_16();
  3510. uint dst = OPER_AX_PI_16();
  3511. uint res = dst - src;
  3512. FLAG_N = NFLAG_16(res);
  3513. FLAG_Z = MASK_OUT_ABOVE_16(res);
  3514. FLAG_V = VFLAG_SUB_16(src, dst, res);
  3515. FLAG_C = CFLAG_16(res);
  3516. }
  3517. M68KMAKE_OP(cmpm, 32, ., .)
  3518. {
  3519. uint src = OPER_AY_PI_32();
  3520. uint dst = OPER_AX_PI_32();
  3521. uint res = dst - src;
  3522. FLAG_N = NFLAG_32(res);
  3523. FLAG_Z = MASK_OUT_ABOVE_32(res);
  3524. FLAG_V = VFLAG_SUB_32(src, dst, res);
  3525. FLAG_C = CFLAG_SUB_32(src, dst, res);
  3526. }
  3527. M68KMAKE_OP(cpbcc, 32, ., .)
  3528. {
  3529. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3530. {
  3531. M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
  3532. m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
  3533. m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
  3534. return;
  3535. }
  3536. m68ki_exception_1111();
  3537. }
  3538. M68KMAKE_OP(cpdbcc, 32, ., .)
  3539. {
  3540. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3541. {
  3542. M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
  3543. m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
  3544. m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
  3545. return;
  3546. }
  3547. m68ki_exception_1111();
  3548. }
  3549. M68KMAKE_OP(cpgen, 32, ., .)
  3550. {
  3551. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3552. {
  3553. M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
  3554. m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
  3555. m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
  3556. return;
  3557. }
  3558. m68ki_exception_1111();
  3559. }
  3560. M68KMAKE_OP(cpscc, 32, ., .)
  3561. {
  3562. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3563. {
  3564. M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
  3565. m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
  3566. m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
  3567. return;
  3568. }
  3569. m68ki_exception_1111();
  3570. }
  3571. M68KMAKE_OP(cptrapcc, 32, ., .)
  3572. {
  3573. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3574. {
  3575. M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
  3576. m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
  3577. m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
  3578. return;
  3579. }
  3580. m68ki_exception_1111();
  3581. }
  3582. M68KMAKE_OP(dbt, 16, ., .)
  3583. {
  3584. REG_PC += 2;
  3585. }
  3586. M68KMAKE_OP(dbf, 16, ., .)
  3587. {
  3588. uint* r_dst = &DY;
  3589. uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
  3590. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  3591. if(res != 0xffff)
  3592. {
  3593. uint offset = OPER_I_16();
  3594. REG_PC -= 2;
  3595. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  3596. m68ki_branch_16(offset);
  3597. USE_CYCLES(CYC_DBCC_F_NOEXP);
  3598. return;
  3599. }
  3600. REG_PC += 2;
  3601. USE_CYCLES(CYC_DBCC_F_EXP);
  3602. }
  3603. M68KMAKE_OP(dbcc, 16, ., .)
  3604. {
  3605. if(M68KMAKE_NOT_CC)
  3606. {
  3607. uint* r_dst = &DY;
  3608. uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
  3609. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  3610. if(res != 0xffff)
  3611. {
  3612. uint offset = OPER_I_16();
  3613. REG_PC -= 2;
  3614. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  3615. m68ki_branch_16(offset);
  3616. USE_CYCLES(CYC_DBCC_F_NOEXP);
  3617. return;
  3618. }
  3619. REG_PC += 2;
  3620. USE_CYCLES(CYC_DBCC_F_EXP);
  3621. return;
  3622. }
  3623. REG_PC += 2;
  3624. }
  3625. M68KMAKE_OP(divs, 16, ., d)
  3626. {
  3627. uint* r_dst = &DX;
  3628. sint src = MAKE_INT_16(DY);
  3629. sint quotient;
  3630. sint remainder;
  3631. if(src != 0)
  3632. {
  3633. if((uint32)*r_dst == 0x80000000 && src == -1)
  3634. {
  3635. FLAG_Z = 0;
  3636. FLAG_N = NFLAG_CLEAR;
  3637. FLAG_V = VFLAG_CLEAR;
  3638. FLAG_C = CFLAG_CLEAR;
  3639. *r_dst = 0;
  3640. return;
  3641. }
  3642. quotient = MAKE_INT_32(*r_dst) / src;
  3643. remainder = MAKE_INT_32(*r_dst) % src;
  3644. if(quotient == MAKE_INT_16(quotient))
  3645. {
  3646. FLAG_Z = quotient;
  3647. FLAG_N = NFLAG_16(quotient);
  3648. FLAG_V = VFLAG_CLEAR;
  3649. FLAG_C = CFLAG_CLEAR;
  3650. *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
  3651. return;
  3652. }
  3653. FLAG_V = VFLAG_SET;
  3654. return;
  3655. }
  3656. m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
  3657. }
  3658. M68KMAKE_OP(divs, 16, ., .)
  3659. {
  3660. uint* r_dst = &DX;
  3661. sint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
  3662. sint quotient;
  3663. sint remainder;
  3664. if(src != 0)
  3665. {
  3666. if((uint32)*r_dst == 0x80000000 && src == -1)
  3667. {
  3668. FLAG_Z = 0;
  3669. FLAG_N = NFLAG_CLEAR;
  3670. FLAG_V = VFLAG_CLEAR;
  3671. FLAG_C = CFLAG_CLEAR;
  3672. *r_dst = 0;
  3673. return;
  3674. }
  3675. quotient = MAKE_INT_32(*r_dst) / src;
  3676. remainder = MAKE_INT_32(*r_dst) % src;
  3677. if(quotient == MAKE_INT_16(quotient))
  3678. {
  3679. FLAG_Z = quotient;
  3680. FLAG_N = NFLAG_16(quotient);
  3681. FLAG_V = VFLAG_CLEAR;
  3682. FLAG_C = CFLAG_CLEAR;
  3683. *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
  3684. return;
  3685. }
  3686. FLAG_V = VFLAG_SET;
  3687. return;
  3688. }
  3689. m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
  3690. }
  3691. M68KMAKE_OP(divu, 16, ., d)
  3692. {
  3693. uint* r_dst = &DX;
  3694. uint src = MASK_OUT_ABOVE_16(DY);
  3695. if(src != 0)
  3696. {
  3697. uint quotient = *r_dst / src;
  3698. uint remainder = *r_dst % src;
  3699. if(quotient < 0x10000)
  3700. {
  3701. FLAG_Z = quotient;
  3702. FLAG_N = NFLAG_16(quotient);
  3703. FLAG_V = VFLAG_CLEAR;
  3704. FLAG_C = CFLAG_CLEAR;
  3705. *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
  3706. return;
  3707. }
  3708. FLAG_V = VFLAG_SET;
  3709. return;
  3710. }
  3711. m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
  3712. }
  3713. M68KMAKE_OP(divu, 16, ., .)
  3714. {
  3715. uint* r_dst = &DX;
  3716. uint src = M68KMAKE_GET_OPER_AY_16;
  3717. if(src != 0)
  3718. {
  3719. uint quotient = *r_dst / src;
  3720. uint remainder = *r_dst % src;
  3721. if(quotient < 0x10000)
  3722. {
  3723. FLAG_Z = quotient;
  3724. FLAG_N = NFLAG_16(quotient);
  3725. FLAG_V = VFLAG_CLEAR;
  3726. FLAG_C = CFLAG_CLEAR;
  3727. *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
  3728. return;
  3729. }
  3730. FLAG_V = VFLAG_SET;
  3731. return;
  3732. }
  3733. m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
  3734. }
  3735. M68KMAKE_OP(divl, 32, ., d)
  3736. {
  3737. #if M68K_USE_64_BIT
  3738. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3739. {
  3740. uint word2 = OPER_I_16();
  3741. uint64 divisor = DY;
  3742. uint64 dividend = 0;
  3743. uint64 quotient = 0;
  3744. uint64 remainder = 0;
  3745. if(divisor != 0)
  3746. {
  3747. if(BIT_A(word2)) /* 64 bit */
  3748. {
  3749. dividend = REG_D[word2 & 7];
  3750. dividend <<= 32;
  3751. dividend |= REG_D[(word2 >> 12) & 7];
  3752. if(BIT_B(word2)) /* signed */
  3753. {
  3754. quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
  3755. remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
  3756. if((sint64)quotient != (sint64)((sint32)quotient))
  3757. {
  3758. FLAG_V = VFLAG_SET;
  3759. return;
  3760. }
  3761. }
  3762. else /* unsigned */
  3763. {
  3764. quotient = dividend / divisor;
  3765. if(quotient > 0xffffffff)
  3766. {
  3767. FLAG_V = VFLAG_SET;
  3768. return;
  3769. }
  3770. remainder = dividend % divisor;
  3771. }
  3772. }
  3773. else /* 32 bit */
  3774. {
  3775. dividend = REG_D[(word2 >> 12) & 7];
  3776. if(BIT_B(word2)) /* signed */
  3777. {
  3778. quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
  3779. remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
  3780. }
  3781. else /* unsigned */
  3782. {
  3783. quotient = dividend / divisor;
  3784. remainder = dividend % divisor;
  3785. }
  3786. }
  3787. REG_D[word2 & 7] = remainder;
  3788. REG_D[(word2 >> 12) & 7] = quotient;
  3789. FLAG_N = NFLAG_32(quotient);
  3790. FLAG_Z = quotient;
  3791. FLAG_V = VFLAG_CLEAR;
  3792. FLAG_C = CFLAG_CLEAR;
  3793. return;
  3794. }
  3795. m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
  3796. return;
  3797. }
  3798. m68ki_exception_illegal();
  3799. #else
  3800. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3801. {
  3802. uint word2 = OPER_I_16();
  3803. uint divisor = DY;
  3804. uint dividend_hi = REG_D[word2 & 7];
  3805. uint dividend_lo = REG_D[(word2 >> 12) & 7];
  3806. uint quotient = 0;
  3807. uint remainder = 0;
  3808. uint dividend_neg = 0;
  3809. uint divisor_neg = 0;
  3810. sint i;
  3811. uint overflow;
  3812. if(divisor != 0)
  3813. {
  3814. /* quad / long : long quotient, long remainder */
  3815. if(BIT_A(word2))
  3816. {
  3817. if(BIT_B(word2)) /* signed */
  3818. {
  3819. /* special case in signed divide */
  3820. if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
  3821. {
  3822. REG_D[word2 & 7] = 0;
  3823. REG_D[(word2 >> 12) & 7] = 0x80000000;
  3824. FLAG_N = NFLAG_SET;
  3825. FLAG_Z = ZFLAG_CLEAR;
  3826. FLAG_V = VFLAG_CLEAR;
  3827. FLAG_C = CFLAG_CLEAR;
  3828. return;
  3829. }
  3830. if(GET_MSB_32(dividend_hi))
  3831. {
  3832. dividend_neg = 1;
  3833. dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
  3834. dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
  3835. }
  3836. if(GET_MSB_32(divisor))
  3837. {
  3838. divisor_neg = 1;
  3839. divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
  3840. }
  3841. }
  3842. /* if the upper long is greater than the divisor, we're overflowing. */
  3843. if(dividend_hi >= divisor)
  3844. {
  3845. FLAG_V = VFLAG_SET;
  3846. return;
  3847. }
  3848. for(i = 31; i >= 0; i--)
  3849. {
  3850. quotient <<= 1;
  3851. remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
  3852. if(remainder >= divisor)
  3853. {
  3854. remainder -= divisor;
  3855. quotient++;
  3856. }
  3857. }
  3858. for(i = 31; i >= 0; i--)
  3859. {
  3860. quotient <<= 1;
  3861. overflow = GET_MSB_32(remainder);
  3862. remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
  3863. if(remainder >= divisor || overflow)
  3864. {
  3865. remainder -= divisor;
  3866. quotient++;
  3867. }
  3868. }
  3869. if(BIT_B(word2)) /* signed */
  3870. {
  3871. if(quotient > 0x7fffffff)
  3872. {
  3873. FLAG_V = VFLAG_SET;
  3874. return;
  3875. }
  3876. if(dividend_neg)
  3877. {
  3878. remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
  3879. quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
  3880. }
  3881. if(divisor_neg)
  3882. quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
  3883. }
  3884. REG_D[word2 & 7] = remainder;
  3885. REG_D[(word2 >> 12) & 7] = quotient;
  3886. FLAG_N = NFLAG_32(quotient);
  3887. FLAG_Z = quotient;
  3888. FLAG_V = VFLAG_CLEAR;
  3889. FLAG_C = CFLAG_CLEAR;
  3890. return;
  3891. }
  3892. /* long / long: long quotient, maybe long remainder */
  3893. if(BIT_B(word2)) /* signed */
  3894. {
  3895. /* Special case in divide */
  3896. if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
  3897. {
  3898. FLAG_N = NFLAG_SET;
  3899. FLAG_Z = ZFLAG_CLEAR;
  3900. FLAG_V = VFLAG_CLEAR;
  3901. FLAG_C = CFLAG_CLEAR;
  3902. REG_D[(word2 >> 12) & 7] = 0x80000000;
  3903. REG_D[word2 & 7] = 0;
  3904. return;
  3905. }
  3906. REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
  3907. quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
  3908. }
  3909. else
  3910. {
  3911. REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
  3912. quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
  3913. }
  3914. FLAG_N = NFLAG_32(quotient);
  3915. FLAG_Z = quotient;
  3916. FLAG_V = VFLAG_CLEAR;
  3917. FLAG_C = CFLAG_CLEAR;
  3918. return;
  3919. }
  3920. m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
  3921. return;
  3922. }
  3923. m68ki_exception_illegal();
  3924. #endif
  3925. }
  3926. M68KMAKE_OP(divl, 32, ., .)
  3927. {
  3928. #if M68K_USE_64_BIT
  3929. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3930. {
  3931. uint word2 = OPER_I_16();
  3932. uint64 divisor = M68KMAKE_GET_OPER_AY_32;
  3933. uint64 dividend = 0;
  3934. uint64 quotient = 0;
  3935. uint64 remainder = 0;
  3936. if(divisor != 0)
  3937. {
  3938. if(BIT_A(word2)) /* 64 bit */
  3939. {
  3940. dividend = REG_D[word2 & 7];
  3941. dividend <<= 32;
  3942. dividend |= REG_D[(word2 >> 12) & 7];
  3943. if(BIT_B(word2)) /* signed */
  3944. {
  3945. quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
  3946. remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
  3947. if((sint64)quotient != (sint64)((sint32)quotient))
  3948. {
  3949. FLAG_V = VFLAG_SET;
  3950. return;
  3951. }
  3952. }
  3953. else /* unsigned */
  3954. {
  3955. quotient = dividend / divisor;
  3956. if(quotient > 0xffffffff)
  3957. {
  3958. FLAG_V = VFLAG_SET;
  3959. return;
  3960. }
  3961. remainder = dividend % divisor;
  3962. }
  3963. }
  3964. else /* 32 bit */
  3965. {
  3966. dividend = REG_D[(word2 >> 12) & 7];
  3967. if(BIT_B(word2)) /* signed */
  3968. {
  3969. quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
  3970. remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
  3971. }
  3972. else /* unsigned */
  3973. {
  3974. quotient = dividend / divisor;
  3975. remainder = dividend % divisor;
  3976. }
  3977. }
  3978. REG_D[word2 & 7] = remainder;
  3979. REG_D[(word2 >> 12) & 7] = quotient;
  3980. FLAG_N = NFLAG_32(quotient);
  3981. FLAG_Z = quotient;
  3982. FLAG_V = VFLAG_CLEAR;
  3983. FLAG_C = CFLAG_CLEAR;
  3984. return;
  3985. }
  3986. m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
  3987. return;
  3988. }
  3989. m68ki_exception_illegal();
  3990. #else
  3991. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  3992. {
  3993. uint word2 = OPER_I_16();
  3994. uint divisor = M68KMAKE_GET_OPER_AY_32;
  3995. uint dividend_hi = REG_D[word2 & 7];
  3996. uint dividend_lo = REG_D[(word2 >> 12) & 7];
  3997. uint quotient = 0;
  3998. uint remainder = 0;
  3999. uint dividend_neg = 0;
  4000. uint divisor_neg = 0;
  4001. sint i;
  4002. uint overflow;
  4003. if(divisor != 0)
  4004. {
  4005. /* quad / long : long quotient, long remainder */
  4006. if(BIT_A(word2))
  4007. {
  4008. if(BIT_B(word2)) /* signed */
  4009. {
  4010. /* special case in signed divide */
  4011. if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
  4012. {
  4013. REG_D[word2 & 7] = 0;
  4014. REG_D[(word2 >> 12) & 7] = 0x80000000;
  4015. FLAG_N = NFLAG_SET;
  4016. FLAG_Z = ZFLAG_CLEAR;
  4017. FLAG_V = VFLAG_CLEAR;
  4018. FLAG_C = CFLAG_CLEAR;
  4019. return;
  4020. }
  4021. if(GET_MSB_32(dividend_hi))
  4022. {
  4023. dividend_neg = 1;
  4024. dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
  4025. dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
  4026. }
  4027. if(GET_MSB_32(divisor))
  4028. {
  4029. divisor_neg = 1;
  4030. divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
  4031. }
  4032. }
  4033. /* if the upper long is greater than the divisor, we're overflowing. */
  4034. if(dividend_hi >= divisor)
  4035. {
  4036. FLAG_V = VFLAG_SET;
  4037. return;
  4038. }
  4039. for(i = 31; i >= 0; i--)
  4040. {
  4041. quotient <<= 1;
  4042. remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
  4043. if(remainder >= divisor)
  4044. {
  4045. remainder -= divisor;
  4046. quotient++;
  4047. }
  4048. }
  4049. for(i = 31; i >= 0; i--)
  4050. {
  4051. quotient <<= 1;
  4052. overflow = GET_MSB_32(remainder);
  4053. remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
  4054. if(remainder >= divisor || overflow)
  4055. {
  4056. remainder -= divisor;
  4057. quotient++;
  4058. }
  4059. }
  4060. if(BIT_B(word2)) /* signed */
  4061. {
  4062. if(quotient > 0x7fffffff)
  4063. {
  4064. FLAG_V = VFLAG_SET;
  4065. return;
  4066. }
  4067. if(dividend_neg)
  4068. {
  4069. remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
  4070. quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
  4071. }
  4072. if(divisor_neg)
  4073. quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
  4074. }
  4075. REG_D[word2 & 7] = remainder;
  4076. REG_D[(word2 >> 12) & 7] = quotient;
  4077. FLAG_N = NFLAG_32(quotient);
  4078. FLAG_Z = quotient;
  4079. FLAG_V = VFLAG_CLEAR;
  4080. FLAG_C = CFLAG_CLEAR;
  4081. return;
  4082. }
  4083. /* long / long: long quotient, maybe long remainder */
  4084. if(BIT_B(word2)) /* signed */
  4085. {
  4086. /* Special case in divide */
  4087. if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
  4088. {
  4089. FLAG_N = NFLAG_SET;
  4090. FLAG_Z = ZFLAG_CLEAR;
  4091. FLAG_V = VFLAG_CLEAR;
  4092. FLAG_C = CFLAG_CLEAR;
  4093. REG_D[(word2 >> 12) & 7] = 0x80000000;
  4094. REG_D[word2 & 7] = 0;
  4095. return;
  4096. }
  4097. REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
  4098. quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
  4099. }
  4100. else
  4101. {
  4102. REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
  4103. quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
  4104. }
  4105. FLAG_N = NFLAG_32(quotient);
  4106. FLAG_Z = quotient;
  4107. FLAG_V = VFLAG_CLEAR;
  4108. FLAG_C = CFLAG_CLEAR;
  4109. return;
  4110. }
  4111. m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
  4112. return;
  4113. }
  4114. m68ki_exception_illegal();
  4115. #endif
  4116. }
  4117. M68KMAKE_OP(eor, 8, ., d)
  4118. {
  4119. uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX));
  4120. FLAG_N = NFLAG_8(res);
  4121. FLAG_Z = res;
  4122. FLAG_C = CFLAG_CLEAR;
  4123. FLAG_V = VFLAG_CLEAR;
  4124. }
  4125. M68KMAKE_OP(eor, 8, ., .)
  4126. {
  4127. uint ea = M68KMAKE_GET_EA_AY_8;
  4128. uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
  4129. m68ki_write_8(ea, res);
  4130. FLAG_N = NFLAG_8(res);
  4131. FLAG_Z = res;
  4132. FLAG_C = CFLAG_CLEAR;
  4133. FLAG_V = VFLAG_CLEAR;
  4134. }
  4135. M68KMAKE_OP(eor, 16, ., d)
  4136. {
  4137. uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX));
  4138. FLAG_N = NFLAG_16(res);
  4139. FLAG_Z = res;
  4140. FLAG_C = CFLAG_CLEAR;
  4141. FLAG_V = VFLAG_CLEAR;
  4142. }
  4143. M68KMAKE_OP(eor, 16, ., .)
  4144. {
  4145. uint ea = M68KMAKE_GET_EA_AY_16;
  4146. uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
  4147. m68ki_write_16(ea, res);
  4148. FLAG_N = NFLAG_16(res);
  4149. FLAG_Z = res;
  4150. FLAG_C = CFLAG_CLEAR;
  4151. FLAG_V = VFLAG_CLEAR;
  4152. }
  4153. M68KMAKE_OP(eor, 32, ., d)
  4154. {
  4155. uint res = DY ^= DX;
  4156. FLAG_N = NFLAG_32(res);
  4157. FLAG_Z = res;
  4158. FLAG_C = CFLAG_CLEAR;
  4159. FLAG_V = VFLAG_CLEAR;
  4160. }
  4161. M68KMAKE_OP(eor, 32, ., .)
  4162. {
  4163. uint ea = M68KMAKE_GET_EA_AY_32;
  4164. uint res = DX ^ m68ki_read_32(ea);
  4165. m68ki_write_32(ea, res);
  4166. FLAG_N = NFLAG_32(res);
  4167. FLAG_Z = res;
  4168. FLAG_C = CFLAG_CLEAR;
  4169. FLAG_V = VFLAG_CLEAR;
  4170. }
  4171. M68KMAKE_OP(eori, 8, ., d)
  4172. {
  4173. uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8());
  4174. FLAG_N = NFLAG_8(res);
  4175. FLAG_Z = res;
  4176. FLAG_C = CFLAG_CLEAR;
  4177. FLAG_V = VFLAG_CLEAR;
  4178. }
  4179. M68KMAKE_OP(eori, 8, ., .)
  4180. {
  4181. uint src = OPER_I_8();
  4182. uint ea = M68KMAKE_GET_EA_AY_8;
  4183. uint res = src ^ m68ki_read_8(ea);
  4184. m68ki_write_8(ea, res);
  4185. FLAG_N = NFLAG_8(res);
  4186. FLAG_Z = res;
  4187. FLAG_C = CFLAG_CLEAR;
  4188. FLAG_V = VFLAG_CLEAR;
  4189. }
  4190. M68KMAKE_OP(eori, 16, ., d)
  4191. {
  4192. uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16());
  4193. FLAG_N = NFLAG_16(res);
  4194. FLAG_Z = res;
  4195. FLAG_C = CFLAG_CLEAR;
  4196. FLAG_V = VFLAG_CLEAR;
  4197. }
  4198. M68KMAKE_OP(eori, 16, ., .)
  4199. {
  4200. uint src = OPER_I_16();
  4201. uint ea = M68KMAKE_GET_EA_AY_16;
  4202. uint res = src ^ m68ki_read_16(ea);
  4203. m68ki_write_16(ea, res);
  4204. FLAG_N = NFLAG_16(res);
  4205. FLAG_Z = res;
  4206. FLAG_C = CFLAG_CLEAR;
  4207. FLAG_V = VFLAG_CLEAR;
  4208. }
  4209. M68KMAKE_OP(eori, 32, ., d)
  4210. {
  4211. uint res = DY ^= OPER_I_32();
  4212. FLAG_N = NFLAG_32(res);
  4213. FLAG_Z = res;
  4214. FLAG_C = CFLAG_CLEAR;
  4215. FLAG_V = VFLAG_CLEAR;
  4216. }
  4217. M68KMAKE_OP(eori, 32, ., .)
  4218. {
  4219. uint src = OPER_I_32();
  4220. uint ea = M68KMAKE_GET_EA_AY_32;
  4221. uint res = src ^ m68ki_read_32(ea);
  4222. m68ki_write_32(ea, res);
  4223. FLAG_N = NFLAG_32(res);
  4224. FLAG_Z = res;
  4225. FLAG_C = CFLAG_CLEAR;
  4226. FLAG_V = VFLAG_CLEAR;
  4227. }
  4228. M68KMAKE_OP(eori, 16, toc, .)
  4229. {
  4230. m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_16());
  4231. }
  4232. M68KMAKE_OP(eori, 16, tos, .)
  4233. {
  4234. if(FLAG_S)
  4235. {
  4236. uint src = OPER_I_16();
  4237. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  4238. m68ki_set_sr(m68ki_get_sr() ^ src);
  4239. return;
  4240. }
  4241. m68ki_exception_privilege_violation();
  4242. }
  4243. M68KMAKE_OP(exg, 32, dd, .)
  4244. {
  4245. uint* reg_a = &DX;
  4246. uint* reg_b = &DY;
  4247. uint tmp = *reg_a;
  4248. *reg_a = *reg_b;
  4249. *reg_b = tmp;
  4250. }
  4251. M68KMAKE_OP(exg, 32, aa, .)
  4252. {
  4253. uint* reg_a = &AX;
  4254. uint* reg_b = &AY;
  4255. uint tmp = *reg_a;
  4256. *reg_a = *reg_b;
  4257. *reg_b = tmp;
  4258. }
  4259. M68KMAKE_OP(exg, 32, da, .)
  4260. {
  4261. uint* reg_a = &DX;
  4262. uint* reg_b = &AY;
  4263. uint tmp = *reg_a;
  4264. *reg_a = *reg_b;
  4265. *reg_b = tmp;
  4266. }
  4267. M68KMAKE_OP(ext, 16, ., .)
  4268. {
  4269. uint* r_dst = &DY;
  4270. *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0);
  4271. FLAG_N = NFLAG_16(*r_dst);
  4272. FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
  4273. FLAG_V = VFLAG_CLEAR;
  4274. FLAG_C = CFLAG_CLEAR;
  4275. }
  4276. M68KMAKE_OP(ext, 32, ., .)
  4277. {
  4278. uint* r_dst = &DY;
  4279. *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0);
  4280. FLAG_N = NFLAG_32(*r_dst);
  4281. FLAG_Z = *r_dst;
  4282. FLAG_V = VFLAG_CLEAR;
  4283. FLAG_C = CFLAG_CLEAR;
  4284. }
  4285. M68KMAKE_OP(extb, 32, ., .)
  4286. {
  4287. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  4288. {
  4289. uint* r_dst = &DY;
  4290. *r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0);
  4291. FLAG_N = NFLAG_32(*r_dst);
  4292. FLAG_Z = *r_dst;
  4293. FLAG_V = VFLAG_CLEAR;
  4294. FLAG_C = CFLAG_CLEAR;
  4295. return;
  4296. }
  4297. m68ki_exception_illegal();
  4298. }
  4299. M68KMAKE_OP(illegal, 0, ., .)
  4300. {
  4301. m68ki_exception_illegal();
  4302. }
  4303. M68KMAKE_OP(jmp, 32, ., .)
  4304. {
  4305. m68ki_jump(M68KMAKE_GET_EA_AY_32);
  4306. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  4307. if(REG_PC == REG_PPC)
  4308. USE_ALL_CYCLES();
  4309. }
  4310. M68KMAKE_OP(jsr, 32, ., .)
  4311. {
  4312. uint ea = M68KMAKE_GET_EA_AY_32;
  4313. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  4314. m68ki_push_32(REG_PC);
  4315. m68ki_jump(ea);
  4316. }
  4317. M68KMAKE_OP(lea, 32, ., .)
  4318. {
  4319. AX = M68KMAKE_GET_EA_AY_32;
  4320. }
  4321. M68KMAKE_OP(link, 16, ., a7)
  4322. {
  4323. REG_A[7] -= 4;
  4324. m68ki_write_32(REG_A[7], REG_A[7]);
  4325. REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
  4326. }
  4327. M68KMAKE_OP(link, 16, ., .)
  4328. {
  4329. uint* r_dst = &AY;
  4330. m68ki_push_32(*r_dst);
  4331. *r_dst = REG_A[7];
  4332. REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
  4333. }
  4334. M68KMAKE_OP(link, 32, ., a7)
  4335. {
  4336. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  4337. {
  4338. REG_A[7] -= 4;
  4339. m68ki_write_32(REG_A[7], REG_A[7]);
  4340. REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
  4341. return;
  4342. }
  4343. m68ki_exception_illegal();
  4344. }
  4345. M68KMAKE_OP(link, 32, ., .)
  4346. {
  4347. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  4348. {
  4349. uint* r_dst = &AY;
  4350. m68ki_push_32(*r_dst);
  4351. *r_dst = REG_A[7];
  4352. REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
  4353. return;
  4354. }
  4355. m68ki_exception_illegal();
  4356. }
  4357. M68KMAKE_OP(lsr, 8, s, .)
  4358. {
  4359. uint* r_dst = &DY;
  4360. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  4361. uint src = MASK_OUT_ABOVE_8(*r_dst);
  4362. uint res = src >> shift;
  4363. if(shift != 0)
  4364. USE_CYCLES(shift<<CYC_SHIFT);
  4365. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  4366. FLAG_N = NFLAG_CLEAR;
  4367. FLAG_Z = res;
  4368. FLAG_X = FLAG_C = src << (9-shift);
  4369. FLAG_V = VFLAG_CLEAR;
  4370. }
  4371. M68KMAKE_OP(lsr, 16, s, .)
  4372. {
  4373. uint* r_dst = &DY;
  4374. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  4375. uint src = MASK_OUT_ABOVE_16(*r_dst);
  4376. uint res = src >> shift;
  4377. if(shift != 0)
  4378. USE_CYCLES(shift<<CYC_SHIFT);
  4379. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  4380. FLAG_N = NFLAG_CLEAR;
  4381. FLAG_Z = res;
  4382. FLAG_X = FLAG_C = src << (9-shift);
  4383. FLAG_V = VFLAG_CLEAR;
  4384. }
  4385. M68KMAKE_OP(lsr, 32, s, .)
  4386. {
  4387. uint* r_dst = &DY;
  4388. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  4389. uint src = *r_dst;
  4390. uint res = src >> shift;
  4391. if(shift != 0)
  4392. USE_CYCLES(shift<<CYC_SHIFT);
  4393. *r_dst = res;
  4394. FLAG_N = NFLAG_CLEAR;
  4395. FLAG_Z = res;
  4396. FLAG_X = FLAG_C = src << (9-shift);
  4397. FLAG_V = VFLAG_CLEAR;
  4398. }
  4399. M68KMAKE_OP(lsr, 8, r, .)
  4400. {
  4401. uint* r_dst = &DY;
  4402. uint shift = DX & 0x3f;
  4403. uint src = MASK_OUT_ABOVE_8(*r_dst);
  4404. uint res = src >> shift;
  4405. if(shift != 0)
  4406. {
  4407. USE_CYCLES(shift<<CYC_SHIFT);
  4408. if(shift <= 8)
  4409. {
  4410. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  4411. FLAG_X = FLAG_C = src << (9-shift);
  4412. FLAG_N = NFLAG_CLEAR;
  4413. FLAG_Z = res;
  4414. FLAG_V = VFLAG_CLEAR;
  4415. return;
  4416. }
  4417. *r_dst &= 0xffffff00;
  4418. FLAG_X = XFLAG_CLEAR;
  4419. FLAG_C = CFLAG_CLEAR;
  4420. FLAG_N = NFLAG_CLEAR;
  4421. FLAG_Z = ZFLAG_SET;
  4422. FLAG_V = VFLAG_CLEAR;
  4423. return;
  4424. }
  4425. FLAG_C = CFLAG_CLEAR;
  4426. FLAG_N = NFLAG_8(src);
  4427. FLAG_Z = src;
  4428. FLAG_V = VFLAG_CLEAR;
  4429. }
  4430. M68KMAKE_OP(lsr, 16, r, .)
  4431. {
  4432. uint* r_dst = &DY;
  4433. uint shift = DX & 0x3f;
  4434. uint src = MASK_OUT_ABOVE_16(*r_dst);
  4435. uint res = src >> shift;
  4436. if(shift != 0)
  4437. {
  4438. USE_CYCLES(shift<<CYC_SHIFT);
  4439. if(shift <= 16)
  4440. {
  4441. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  4442. FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
  4443. FLAG_N = NFLAG_CLEAR;
  4444. FLAG_Z = res;
  4445. FLAG_V = VFLAG_CLEAR;
  4446. return;
  4447. }
  4448. *r_dst &= 0xffff0000;
  4449. FLAG_X = XFLAG_CLEAR;
  4450. FLAG_C = CFLAG_CLEAR;
  4451. FLAG_N = NFLAG_CLEAR;
  4452. FLAG_Z = ZFLAG_SET;
  4453. FLAG_V = VFLAG_CLEAR;
  4454. return;
  4455. }
  4456. FLAG_C = CFLAG_CLEAR;
  4457. FLAG_N = NFLAG_16(src);
  4458. FLAG_Z = src;
  4459. FLAG_V = VFLAG_CLEAR;
  4460. }
  4461. M68KMAKE_OP(lsr, 32, r, .)
  4462. {
  4463. uint* r_dst = &DY;
  4464. uint shift = DX & 0x3f;
  4465. uint src = *r_dst;
  4466. uint res = src >> shift;
  4467. if(shift != 0)
  4468. {
  4469. USE_CYCLES(shift<<CYC_SHIFT);
  4470. if(shift < 32)
  4471. {
  4472. *r_dst = res;
  4473. FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
  4474. FLAG_N = NFLAG_CLEAR;
  4475. FLAG_Z = res;
  4476. FLAG_V = VFLAG_CLEAR;
  4477. return;
  4478. }
  4479. *r_dst = 0;
  4480. FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0);
  4481. FLAG_N = NFLAG_CLEAR;
  4482. FLAG_Z = ZFLAG_SET;
  4483. FLAG_V = VFLAG_CLEAR;
  4484. return;
  4485. }
  4486. FLAG_C = CFLAG_CLEAR;
  4487. FLAG_N = NFLAG_32(src);
  4488. FLAG_Z = src;
  4489. FLAG_V = VFLAG_CLEAR;
  4490. }
  4491. M68KMAKE_OP(lsr, 16, ., .)
  4492. {
  4493. uint ea = M68KMAKE_GET_EA_AY_16;
  4494. uint src = m68ki_read_16(ea);
  4495. uint res = src >> 1;
  4496. m68ki_write_16(ea, res);
  4497. FLAG_N = NFLAG_CLEAR;
  4498. FLAG_Z = res;
  4499. FLAG_C = FLAG_X = src << 8;
  4500. FLAG_V = VFLAG_CLEAR;
  4501. }
  4502. M68KMAKE_OP(lsl, 8, s, .)
  4503. {
  4504. uint* r_dst = &DY;
  4505. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  4506. uint src = MASK_OUT_ABOVE_8(*r_dst);
  4507. uint res = MASK_OUT_ABOVE_8(src << shift);
  4508. if(shift != 0)
  4509. USE_CYCLES(shift<<CYC_SHIFT);
  4510. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  4511. FLAG_N = NFLAG_8(res);
  4512. FLAG_Z = res;
  4513. FLAG_X = FLAG_C = src << shift;
  4514. FLAG_V = VFLAG_CLEAR;
  4515. }
  4516. M68KMAKE_OP(lsl, 16, s, .)
  4517. {
  4518. uint* r_dst = &DY;
  4519. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  4520. uint src = MASK_OUT_ABOVE_16(*r_dst);
  4521. uint res = MASK_OUT_ABOVE_16(src << shift);
  4522. if(shift != 0)
  4523. USE_CYCLES(shift<<CYC_SHIFT);
  4524. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  4525. FLAG_N = NFLAG_16(res);
  4526. FLAG_Z = res;
  4527. FLAG_X = FLAG_C = src >> (8-shift);
  4528. FLAG_V = VFLAG_CLEAR;
  4529. }
  4530. M68KMAKE_OP(lsl, 32, s, .)
  4531. {
  4532. uint* r_dst = &DY;
  4533. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  4534. uint src = *r_dst;
  4535. uint res = MASK_OUT_ABOVE_32(src << shift);
  4536. if(shift != 0)
  4537. USE_CYCLES(shift<<CYC_SHIFT);
  4538. *r_dst = res;
  4539. FLAG_N = NFLAG_32(res);
  4540. FLAG_Z = res;
  4541. FLAG_X = FLAG_C = src >> (24-shift);
  4542. FLAG_V = VFLAG_CLEAR;
  4543. }
  4544. M68KMAKE_OP(lsl, 8, r, .)
  4545. {
  4546. uint* r_dst = &DY;
  4547. uint shift = DX & 0x3f;
  4548. uint src = MASK_OUT_ABOVE_8(*r_dst);
  4549. uint res = MASK_OUT_ABOVE_8(src << shift);
  4550. if(shift != 0)
  4551. {
  4552. USE_CYCLES(shift<<CYC_SHIFT);
  4553. if(shift <= 8)
  4554. {
  4555. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  4556. FLAG_X = FLAG_C = src << shift;
  4557. FLAG_N = NFLAG_8(res);
  4558. FLAG_Z = res;
  4559. FLAG_V = VFLAG_CLEAR;
  4560. return;
  4561. }
  4562. *r_dst &= 0xffffff00;
  4563. FLAG_X = XFLAG_CLEAR;
  4564. FLAG_C = CFLAG_CLEAR;
  4565. FLAG_N = NFLAG_CLEAR;
  4566. FLAG_Z = ZFLAG_SET;
  4567. FLAG_V = VFLAG_CLEAR;
  4568. return;
  4569. }
  4570. FLAG_C = CFLAG_CLEAR;
  4571. FLAG_N = NFLAG_8(src);
  4572. FLAG_Z = src;
  4573. FLAG_V = VFLAG_CLEAR;
  4574. }
  4575. M68KMAKE_OP(lsl, 16, r, .)
  4576. {
  4577. uint* r_dst = &DY;
  4578. uint shift = DX & 0x3f;
  4579. uint src = MASK_OUT_ABOVE_16(*r_dst);
  4580. uint res = MASK_OUT_ABOVE_16(src << shift);
  4581. if(shift != 0)
  4582. {
  4583. USE_CYCLES(shift<<CYC_SHIFT);
  4584. if(shift <= 16)
  4585. {
  4586. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  4587. FLAG_X = FLAG_C = (src << shift) >> 8;
  4588. FLAG_N = NFLAG_16(res);
  4589. FLAG_Z = res;
  4590. FLAG_V = VFLAG_CLEAR;
  4591. return;
  4592. }
  4593. *r_dst &= 0xffff0000;
  4594. FLAG_X = XFLAG_CLEAR;
  4595. FLAG_C = CFLAG_CLEAR;
  4596. FLAG_N = NFLAG_CLEAR;
  4597. FLAG_Z = ZFLAG_SET;
  4598. FLAG_V = VFLAG_CLEAR;
  4599. return;
  4600. }
  4601. FLAG_C = CFLAG_CLEAR;
  4602. FLAG_N = NFLAG_16(src);
  4603. FLAG_Z = src;
  4604. FLAG_V = VFLAG_CLEAR;
  4605. }
  4606. M68KMAKE_OP(lsl, 32, r, .)
  4607. {
  4608. uint* r_dst = &DY;
  4609. uint shift = DX & 0x3f;
  4610. uint src = *r_dst;
  4611. uint res = MASK_OUT_ABOVE_32(src << shift);
  4612. if(shift != 0)
  4613. {
  4614. USE_CYCLES(shift<<CYC_SHIFT);
  4615. if(shift < 32)
  4616. {
  4617. *r_dst = res;
  4618. FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
  4619. FLAG_N = NFLAG_32(res);
  4620. FLAG_Z = res;
  4621. FLAG_V = VFLAG_CLEAR;
  4622. return;
  4623. }
  4624. *r_dst = 0;
  4625. FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
  4626. FLAG_N = NFLAG_CLEAR;
  4627. FLAG_Z = ZFLAG_SET;
  4628. FLAG_V = VFLAG_CLEAR;
  4629. return;
  4630. }
  4631. FLAG_C = CFLAG_CLEAR;
  4632. FLAG_N = NFLAG_32(src);
  4633. FLAG_Z = src;
  4634. FLAG_V = VFLAG_CLEAR;
  4635. }
  4636. M68KMAKE_OP(lsl, 16, ., .)
  4637. {
  4638. uint ea = M68KMAKE_GET_EA_AY_16;
  4639. uint src = m68ki_read_16(ea);
  4640. uint res = MASK_OUT_ABOVE_16(src << 1);
  4641. m68ki_write_16(ea, res);
  4642. FLAG_N = NFLAG_16(res);
  4643. FLAG_Z = res;
  4644. FLAG_X = FLAG_C = src >> 7;
  4645. FLAG_V = VFLAG_CLEAR;
  4646. }
  4647. M68KMAKE_OP(move, 8, d, d)
  4648. {
  4649. uint res = MASK_OUT_ABOVE_8(DY);
  4650. uint* r_dst = &DX;
  4651. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  4652. FLAG_N = NFLAG_8(res);
  4653. FLAG_Z = res;
  4654. FLAG_V = VFLAG_CLEAR;
  4655. FLAG_C = CFLAG_CLEAR;
  4656. }
  4657. M68KMAKE_OP(move, 8, d, .)
  4658. {
  4659. uint res = M68KMAKE_GET_OPER_AY_8;
  4660. uint* r_dst = &DX;
  4661. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  4662. FLAG_N = NFLAG_8(res);
  4663. FLAG_Z = res;
  4664. FLAG_V = VFLAG_CLEAR;
  4665. FLAG_C = CFLAG_CLEAR;
  4666. }
  4667. M68KMAKE_OP(move, 8, ai, d)
  4668. {
  4669. uint res = MASK_OUT_ABOVE_8(DY);
  4670. uint ea = EA_AX_AI_8();
  4671. m68ki_write_8(ea, res);
  4672. FLAG_N = NFLAG_8(res);
  4673. FLAG_Z = res;
  4674. FLAG_V = VFLAG_CLEAR;
  4675. FLAG_C = CFLAG_CLEAR;
  4676. }
  4677. M68KMAKE_OP(move, 8, ai, .)
  4678. {
  4679. uint res = M68KMAKE_GET_OPER_AY_8;
  4680. uint ea = EA_AX_AI_8();
  4681. m68ki_write_8(ea, res);
  4682. FLAG_N = NFLAG_8(res);
  4683. FLAG_Z = res;
  4684. FLAG_V = VFLAG_CLEAR;
  4685. FLAG_C = CFLAG_CLEAR;
  4686. }
  4687. M68KMAKE_OP(move, 8, pi7, d)
  4688. {
  4689. uint res = MASK_OUT_ABOVE_8(DY);
  4690. uint ea = EA_A7_PI_8();
  4691. m68ki_write_8(ea, res);
  4692. FLAG_N = NFLAG_8(res);
  4693. FLAG_Z = res;
  4694. FLAG_V = VFLAG_CLEAR;
  4695. FLAG_C = CFLAG_CLEAR;
  4696. }
  4697. M68KMAKE_OP(move, 8, pi, d)
  4698. {
  4699. uint res = MASK_OUT_ABOVE_8(DY);
  4700. uint ea = EA_AX_PI_8();
  4701. m68ki_write_8(ea, res);
  4702. FLAG_N = NFLAG_8(res);
  4703. FLAG_Z = res;
  4704. FLAG_V = VFLAG_CLEAR;
  4705. FLAG_C = CFLAG_CLEAR;
  4706. }
  4707. M68KMAKE_OP(move, 8, pi7, .)
  4708. {
  4709. uint res = M68KMAKE_GET_OPER_AY_8;
  4710. uint ea = EA_A7_PI_8();
  4711. m68ki_write_8(ea, res);
  4712. FLAG_N = NFLAG_8(res);
  4713. FLAG_Z = res;
  4714. FLAG_V = VFLAG_CLEAR;
  4715. FLAG_C = CFLAG_CLEAR;
  4716. }
  4717. M68KMAKE_OP(move, 8, pi, .)
  4718. {
  4719. uint res = M68KMAKE_GET_OPER_AY_8;
  4720. uint ea = EA_AX_PI_8();
  4721. m68ki_write_8(ea, res);
  4722. FLAG_N = NFLAG_8(res);
  4723. FLAG_Z = res;
  4724. FLAG_V = VFLAG_CLEAR;
  4725. FLAG_C = CFLAG_CLEAR;
  4726. }
  4727. M68KMAKE_OP(move, 8, pd7, d)
  4728. {
  4729. uint res = MASK_OUT_ABOVE_8(DY);
  4730. uint ea = EA_A7_PD_8();
  4731. m68ki_write_8(ea, res);
  4732. FLAG_N = NFLAG_8(res);
  4733. FLAG_Z = res;
  4734. FLAG_V = VFLAG_CLEAR;
  4735. FLAG_C = CFLAG_CLEAR;
  4736. }
  4737. M68KMAKE_OP(move, 8, pd, d)
  4738. {
  4739. uint res = MASK_OUT_ABOVE_8(DY);
  4740. uint ea = EA_AX_PD_8();
  4741. m68ki_write_8(ea, res);
  4742. FLAG_N = NFLAG_8(res);
  4743. FLAG_Z = res;
  4744. FLAG_V = VFLAG_CLEAR;
  4745. FLAG_C = CFLAG_CLEAR;
  4746. }
  4747. M68KMAKE_OP(move, 8, pd7, .)
  4748. {
  4749. uint res = M68KMAKE_GET_OPER_AY_8;
  4750. uint ea = EA_A7_PD_8();
  4751. m68ki_write_8(ea, res);
  4752. FLAG_N = NFLAG_8(res);
  4753. FLAG_Z = res;
  4754. FLAG_V = VFLAG_CLEAR;
  4755. FLAG_C = CFLAG_CLEAR;
  4756. }
  4757. M68KMAKE_OP(move, 8, pd, .)
  4758. {
  4759. uint res = M68KMAKE_GET_OPER_AY_8;
  4760. uint ea = EA_AX_PD_8();
  4761. m68ki_write_8(ea, res);
  4762. FLAG_N = NFLAG_8(res);
  4763. FLAG_Z = res;
  4764. FLAG_V = VFLAG_CLEAR;
  4765. FLAG_C = CFLAG_CLEAR;
  4766. }
  4767. M68KMAKE_OP(move, 8, di, d)
  4768. {
  4769. uint res = MASK_OUT_ABOVE_8(DY);
  4770. uint ea = EA_AX_DI_8();
  4771. m68ki_write_8(ea, res);
  4772. FLAG_N = NFLAG_8(res);
  4773. FLAG_Z = res;
  4774. FLAG_V = VFLAG_CLEAR;
  4775. FLAG_C = CFLAG_CLEAR;
  4776. }
  4777. M68KMAKE_OP(move, 8, di, .)
  4778. {
  4779. uint res = M68KMAKE_GET_OPER_AY_8;
  4780. uint ea = EA_AX_DI_8();
  4781. m68ki_write_8(ea, res);
  4782. FLAG_N = NFLAG_8(res);
  4783. FLAG_Z = res;
  4784. FLAG_V = VFLAG_CLEAR;
  4785. FLAG_C = CFLAG_CLEAR;
  4786. }
  4787. M68KMAKE_OP(move, 8, ix, d)
  4788. {
  4789. uint res = MASK_OUT_ABOVE_8(DY);
  4790. uint ea = EA_AX_IX_8();
  4791. m68ki_write_8(ea, res);
  4792. FLAG_N = NFLAG_8(res);
  4793. FLAG_Z = res;
  4794. FLAG_V = VFLAG_CLEAR;
  4795. FLAG_C = CFLAG_CLEAR;
  4796. }
  4797. M68KMAKE_OP(move, 8, ix, .)
  4798. {
  4799. uint res = M68KMAKE_GET_OPER_AY_8;
  4800. uint ea = EA_AX_IX_8();
  4801. m68ki_write_8(ea, res);
  4802. FLAG_N = NFLAG_8(res);
  4803. FLAG_Z = res;
  4804. FLAG_V = VFLAG_CLEAR;
  4805. FLAG_C = CFLAG_CLEAR;
  4806. }
  4807. M68KMAKE_OP(move, 8, aw, d)
  4808. {
  4809. uint res = MASK_OUT_ABOVE_8(DY);
  4810. uint ea = EA_AW_8();
  4811. m68ki_write_8(ea, res);
  4812. FLAG_N = NFLAG_8(res);
  4813. FLAG_Z = res;
  4814. FLAG_V = VFLAG_CLEAR;
  4815. FLAG_C = CFLAG_CLEAR;
  4816. }
  4817. M68KMAKE_OP(move, 8, aw, .)
  4818. {
  4819. uint res = M68KMAKE_GET_OPER_AY_8;
  4820. uint ea = EA_AW_8();
  4821. m68ki_write_8(ea, res);
  4822. FLAG_N = NFLAG_8(res);
  4823. FLAG_Z = res;
  4824. FLAG_V = VFLAG_CLEAR;
  4825. FLAG_C = CFLAG_CLEAR;
  4826. }
  4827. M68KMAKE_OP(move, 8, al, d)
  4828. {
  4829. uint res = MASK_OUT_ABOVE_8(DY);
  4830. uint ea = EA_AL_8();
  4831. m68ki_write_8(ea, res);
  4832. FLAG_N = NFLAG_8(res);
  4833. FLAG_Z = res;
  4834. FLAG_V = VFLAG_CLEAR;
  4835. FLAG_C = CFLAG_CLEAR;
  4836. }
  4837. M68KMAKE_OP(move, 8, al, .)
  4838. {
  4839. uint res = M68KMAKE_GET_OPER_AY_8;
  4840. uint ea = EA_AL_8();
  4841. m68ki_write_8(ea, res);
  4842. FLAG_N = NFLAG_8(res);
  4843. FLAG_Z = res;
  4844. FLAG_V = VFLAG_CLEAR;
  4845. FLAG_C = CFLAG_CLEAR;
  4846. }
  4847. M68KMAKE_OP(move, 16, d, d)
  4848. {
  4849. uint res = MASK_OUT_ABOVE_16(DY);
  4850. uint* r_dst = &DX;
  4851. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  4852. FLAG_N = NFLAG_16(res);
  4853. FLAG_Z = res;
  4854. FLAG_V = VFLAG_CLEAR;
  4855. FLAG_C = CFLAG_CLEAR;
  4856. }
  4857. M68KMAKE_OP(move, 16, d, a)
  4858. {
  4859. uint res = MASK_OUT_ABOVE_16(AY);
  4860. uint* r_dst = &DX;
  4861. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  4862. FLAG_N = NFLAG_16(res);
  4863. FLAG_Z = res;
  4864. FLAG_V = VFLAG_CLEAR;
  4865. FLAG_C = CFLAG_CLEAR;
  4866. }
  4867. M68KMAKE_OP(move, 16, d, .)
  4868. {
  4869. uint res = M68KMAKE_GET_OPER_AY_16;
  4870. uint* r_dst = &DX;
  4871. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  4872. FLAG_N = NFLAG_16(res);
  4873. FLAG_Z = res;
  4874. FLAG_V = VFLAG_CLEAR;
  4875. FLAG_C = CFLAG_CLEAR;
  4876. }
  4877. M68KMAKE_OP(move, 16, ai, d)
  4878. {
  4879. uint res = MASK_OUT_ABOVE_16(DY);
  4880. uint ea = EA_AX_AI_16();
  4881. m68ki_write_16(ea, res);
  4882. FLAG_N = NFLAG_16(res);
  4883. FLAG_Z = res;
  4884. FLAG_V = VFLAG_CLEAR;
  4885. FLAG_C = CFLAG_CLEAR;
  4886. }
  4887. M68KMAKE_OP(move, 16, ai, a)
  4888. {
  4889. uint res = MASK_OUT_ABOVE_16(AY);
  4890. uint ea = EA_AX_AI_16();
  4891. m68ki_write_16(ea, res);
  4892. FLAG_N = NFLAG_16(res);
  4893. FLAG_Z = res;
  4894. FLAG_V = VFLAG_CLEAR;
  4895. FLAG_C = CFLAG_CLEAR;
  4896. }
  4897. M68KMAKE_OP(move, 16, ai, .)
  4898. {
  4899. uint res = M68KMAKE_GET_OPER_AY_16;
  4900. uint ea = EA_AX_AI_16();
  4901. m68ki_write_16(ea, res);
  4902. FLAG_N = NFLAG_16(res);
  4903. FLAG_Z = res;
  4904. FLAG_V = VFLAG_CLEAR;
  4905. FLAG_C = CFLAG_CLEAR;
  4906. }
  4907. M68KMAKE_OP(move, 16, pi, d)
  4908. {
  4909. uint res = MASK_OUT_ABOVE_16(DY);
  4910. uint ea = EA_AX_PI_16();
  4911. m68ki_write_16(ea, res);
  4912. FLAG_N = NFLAG_16(res);
  4913. FLAG_Z = res;
  4914. FLAG_V = VFLAG_CLEAR;
  4915. FLAG_C = CFLAG_CLEAR;
  4916. }
  4917. M68KMAKE_OP(move, 16, pi, a)
  4918. {
  4919. uint res = MASK_OUT_ABOVE_16(AY);
  4920. uint ea = EA_AX_PI_16();
  4921. m68ki_write_16(ea, res);
  4922. FLAG_N = NFLAG_16(res);
  4923. FLAG_Z = res;
  4924. FLAG_V = VFLAG_CLEAR;
  4925. FLAG_C = CFLAG_CLEAR;
  4926. }
  4927. M68KMAKE_OP(move, 16, pi, .)
  4928. {
  4929. uint res = M68KMAKE_GET_OPER_AY_16;
  4930. uint ea = EA_AX_PI_16();
  4931. m68ki_write_16(ea, res);
  4932. FLAG_N = NFLAG_16(res);
  4933. FLAG_Z = res;
  4934. FLAG_V = VFLAG_CLEAR;
  4935. FLAG_C = CFLAG_CLEAR;
  4936. }
  4937. M68KMAKE_OP(move, 16, pd, d)
  4938. {
  4939. uint res = MASK_OUT_ABOVE_16(DY);
  4940. uint ea = EA_AX_PD_16();
  4941. m68ki_write_16(ea, res);
  4942. FLAG_N = NFLAG_16(res);
  4943. FLAG_Z = res;
  4944. FLAG_V = VFLAG_CLEAR;
  4945. FLAG_C = CFLAG_CLEAR;
  4946. }
  4947. M68KMAKE_OP(move, 16, pd, a)
  4948. {
  4949. uint res = MASK_OUT_ABOVE_16(AY);
  4950. uint ea = EA_AX_PD_16();
  4951. m68ki_write_16(ea, res);
  4952. FLAG_N = NFLAG_16(res);
  4953. FLAG_Z = res;
  4954. FLAG_V = VFLAG_CLEAR;
  4955. FLAG_C = CFLAG_CLEAR;
  4956. }
  4957. M68KMAKE_OP(move, 16, pd, .)
  4958. {
  4959. uint res = M68KMAKE_GET_OPER_AY_16;
  4960. uint ea = EA_AX_PD_16();
  4961. m68ki_write_16(ea, res);
  4962. FLAG_N = NFLAG_16(res);
  4963. FLAG_Z = res;
  4964. FLAG_V = VFLAG_CLEAR;
  4965. FLAG_C = CFLAG_CLEAR;
  4966. }
  4967. M68KMAKE_OP(move, 16, di, d)
  4968. {
  4969. uint res = MASK_OUT_ABOVE_16(DY);
  4970. uint ea = EA_AX_DI_16();
  4971. m68ki_write_16(ea, res);
  4972. FLAG_N = NFLAG_16(res);
  4973. FLAG_Z = res;
  4974. FLAG_V = VFLAG_CLEAR;
  4975. FLAG_C = CFLAG_CLEAR;
  4976. }
  4977. M68KMAKE_OP(move, 16, di, a)
  4978. {
  4979. uint res = MASK_OUT_ABOVE_16(AY);
  4980. uint ea = EA_AX_DI_16();
  4981. m68ki_write_16(ea, res);
  4982. FLAG_N = NFLAG_16(res);
  4983. FLAG_Z = res;
  4984. FLAG_V = VFLAG_CLEAR;
  4985. FLAG_C = CFLAG_CLEAR;
  4986. }
  4987. M68KMAKE_OP(move, 16, di, .)
  4988. {
  4989. uint res = M68KMAKE_GET_OPER_AY_16;
  4990. uint ea = EA_AX_DI_16();
  4991. m68ki_write_16(ea, res);
  4992. FLAG_N = NFLAG_16(res);
  4993. FLAG_Z = res;
  4994. FLAG_V = VFLAG_CLEAR;
  4995. FLAG_C = CFLAG_CLEAR;
  4996. }
  4997. M68KMAKE_OP(move, 16, ix, d)
  4998. {
  4999. uint res = MASK_OUT_ABOVE_16(DY);
  5000. uint ea = EA_AX_IX_16();
  5001. m68ki_write_16(ea, res);
  5002. FLAG_N = NFLAG_16(res);
  5003. FLAG_Z = res;
  5004. FLAG_V = VFLAG_CLEAR;
  5005. FLAG_C = CFLAG_CLEAR;
  5006. }
  5007. M68KMAKE_OP(move, 16, ix, a)
  5008. {
  5009. uint res = MASK_OUT_ABOVE_16(AY);
  5010. uint ea = EA_AX_IX_16();
  5011. m68ki_write_16(ea, res);
  5012. FLAG_N = NFLAG_16(res);
  5013. FLAG_Z = res;
  5014. FLAG_V = VFLAG_CLEAR;
  5015. FLAG_C = CFLAG_CLEAR;
  5016. }
  5017. M68KMAKE_OP(move, 16, ix, .)
  5018. {
  5019. uint res = M68KMAKE_GET_OPER_AY_16;
  5020. uint ea = EA_AX_IX_16();
  5021. m68ki_write_16(ea, res);
  5022. FLAG_N = NFLAG_16(res);
  5023. FLAG_Z = res;
  5024. FLAG_V = VFLAG_CLEAR;
  5025. FLAG_C = CFLAG_CLEAR;
  5026. }
  5027. M68KMAKE_OP(move, 16, aw, d)
  5028. {
  5029. uint res = MASK_OUT_ABOVE_16(DY);
  5030. uint ea = EA_AW_16();
  5031. m68ki_write_16(ea, res);
  5032. FLAG_N = NFLAG_16(res);
  5033. FLAG_Z = res;
  5034. FLAG_V = VFLAG_CLEAR;
  5035. FLAG_C = CFLAG_CLEAR;
  5036. }
  5037. M68KMAKE_OP(move, 16, aw, a)
  5038. {
  5039. uint res = MASK_OUT_ABOVE_16(AY);
  5040. uint ea = EA_AW_16();
  5041. m68ki_write_16(ea, res);
  5042. FLAG_N = NFLAG_16(res);
  5043. FLAG_Z = res;
  5044. FLAG_V = VFLAG_CLEAR;
  5045. FLAG_C = CFLAG_CLEAR;
  5046. }
  5047. M68KMAKE_OP(move, 16, aw, .)
  5048. {
  5049. uint res = M68KMAKE_GET_OPER_AY_16;
  5050. uint ea = EA_AW_16();
  5051. m68ki_write_16(ea, res);
  5052. FLAG_N = NFLAG_16(res);
  5053. FLAG_Z = res;
  5054. FLAG_V = VFLAG_CLEAR;
  5055. FLAG_C = CFLAG_CLEAR;
  5056. }
  5057. M68KMAKE_OP(move, 16, al, d)
  5058. {
  5059. uint res = MASK_OUT_ABOVE_16(DY);
  5060. uint ea = EA_AL_16();
  5061. m68ki_write_16(ea, res);
  5062. FLAG_N = NFLAG_16(res);
  5063. FLAG_Z = res;
  5064. FLAG_V = VFLAG_CLEAR;
  5065. FLAG_C = CFLAG_CLEAR;
  5066. }
  5067. M68KMAKE_OP(move, 16, al, a)
  5068. {
  5069. uint res = MASK_OUT_ABOVE_16(AY);
  5070. uint ea = EA_AL_16();
  5071. m68ki_write_16(ea, res);
  5072. FLAG_N = NFLAG_16(res);
  5073. FLAG_Z = res;
  5074. FLAG_V = VFLAG_CLEAR;
  5075. FLAG_C = CFLAG_CLEAR;
  5076. }
  5077. M68KMAKE_OP(move, 16, al, .)
  5078. {
  5079. uint res = M68KMAKE_GET_OPER_AY_16;
  5080. uint ea = EA_AL_16();
  5081. m68ki_write_16(ea, res);
  5082. FLAG_N = NFLAG_16(res);
  5083. FLAG_Z = res;
  5084. FLAG_V = VFLAG_CLEAR;
  5085. FLAG_C = CFLAG_CLEAR;
  5086. }
  5087. M68KMAKE_OP(move, 32, d, d)
  5088. {
  5089. uint res = DY;
  5090. uint* r_dst = &DX;
  5091. *r_dst = res;
  5092. FLAG_N = NFLAG_32(res);
  5093. FLAG_Z = res;
  5094. FLAG_V = VFLAG_CLEAR;
  5095. FLAG_C = CFLAG_CLEAR;
  5096. }
  5097. M68KMAKE_OP(move, 32, d, a)
  5098. {
  5099. uint res = AY;
  5100. uint* r_dst = &DX;
  5101. *r_dst = res;
  5102. FLAG_N = NFLAG_32(res);
  5103. FLAG_Z = res;
  5104. FLAG_V = VFLAG_CLEAR;
  5105. FLAG_C = CFLAG_CLEAR;
  5106. }
  5107. M68KMAKE_OP(move, 32, d, .)
  5108. {
  5109. uint res = M68KMAKE_GET_OPER_AY_32;
  5110. uint* r_dst = &DX;
  5111. *r_dst = res;
  5112. FLAG_N = NFLAG_32(res);
  5113. FLAG_Z = res;
  5114. FLAG_V = VFLAG_CLEAR;
  5115. FLAG_C = CFLAG_CLEAR;
  5116. }
  5117. M68KMAKE_OP(move, 32, ai, d)
  5118. {
  5119. uint res = DY;
  5120. uint ea = EA_AX_AI_32();
  5121. m68ki_write_32(ea, res);
  5122. FLAG_N = NFLAG_32(res);
  5123. FLAG_Z = res;
  5124. FLAG_V = VFLAG_CLEAR;
  5125. FLAG_C = CFLAG_CLEAR;
  5126. }
  5127. M68KMAKE_OP(move, 32, ai, a)
  5128. {
  5129. uint res = AY;
  5130. uint ea = EA_AX_AI_32();
  5131. m68ki_write_32(ea, res);
  5132. FLAG_N = NFLAG_32(res);
  5133. FLAG_Z = res;
  5134. FLAG_V = VFLAG_CLEAR;
  5135. FLAG_C = CFLAG_CLEAR;
  5136. }
  5137. M68KMAKE_OP(move, 32, ai, .)
  5138. {
  5139. uint res = M68KMAKE_GET_OPER_AY_32;
  5140. uint ea = EA_AX_AI_32();
  5141. m68ki_write_32(ea, res);
  5142. FLAG_N = NFLAG_32(res);
  5143. FLAG_Z = res;
  5144. FLAG_V = VFLAG_CLEAR;
  5145. FLAG_C = CFLAG_CLEAR;
  5146. }
  5147. M68KMAKE_OP(move, 32, pi, d)
  5148. {
  5149. uint res = DY;
  5150. uint ea = EA_AX_PI_32();
  5151. m68ki_write_32(ea, res);
  5152. FLAG_N = NFLAG_32(res);
  5153. FLAG_Z = res;
  5154. FLAG_V = VFLAG_CLEAR;
  5155. FLAG_C = CFLAG_CLEAR;
  5156. }
  5157. M68KMAKE_OP(move, 32, pi, a)
  5158. {
  5159. uint res = AY;
  5160. uint ea = EA_AX_PI_32();
  5161. m68ki_write_32(ea, res);
  5162. FLAG_N = NFLAG_32(res);
  5163. FLAG_Z = res;
  5164. FLAG_V = VFLAG_CLEAR;
  5165. FLAG_C = CFLAG_CLEAR;
  5166. }
  5167. M68KMAKE_OP(move, 32, pi, .)
  5168. {
  5169. uint res = M68KMAKE_GET_OPER_AY_32;
  5170. uint ea = EA_AX_PI_32();
  5171. m68ki_write_32(ea, res);
  5172. FLAG_N = NFLAG_32(res);
  5173. FLAG_Z = res;
  5174. FLAG_V = VFLAG_CLEAR;
  5175. FLAG_C = CFLAG_CLEAR;
  5176. }
  5177. M68KMAKE_OP(move, 32, pd, d)
  5178. {
  5179. uint res = DY;
  5180. uint ea = EA_AX_PD_32();
  5181. m68ki_write_16(ea+2, res & 0xFFFF );
  5182. m68ki_write_16(ea, (res >> 16) & 0xFFFF );
  5183. FLAG_N = NFLAG_32(res);
  5184. FLAG_Z = res;
  5185. FLAG_V = VFLAG_CLEAR;
  5186. FLAG_C = CFLAG_CLEAR;
  5187. }
  5188. M68KMAKE_OP(move, 32, pd, a)
  5189. {
  5190. uint res = AY;
  5191. uint ea = EA_AX_PD_32();
  5192. m68ki_write_16(ea+2, res & 0xFFFF );
  5193. m68ki_write_16(ea, (res >> 16) & 0xFFFF );
  5194. FLAG_N = NFLAG_32(res);
  5195. FLAG_Z = res;
  5196. FLAG_V = VFLAG_CLEAR;
  5197. FLAG_C = CFLAG_CLEAR;
  5198. }
  5199. M68KMAKE_OP(move, 32, pd, .)
  5200. {
  5201. uint res = M68KMAKE_GET_OPER_AY_32;
  5202. uint ea = EA_AX_PD_32();
  5203. m68ki_write_16(ea+2, res & 0xFFFF );
  5204. m68ki_write_16(ea, (res >> 16) & 0xFFFF );
  5205. FLAG_N = NFLAG_32(res);
  5206. FLAG_Z = res;
  5207. FLAG_V = VFLAG_CLEAR;
  5208. FLAG_C = CFLAG_CLEAR;
  5209. }
  5210. M68KMAKE_OP(move, 32, di, d)
  5211. {
  5212. uint res = DY;
  5213. uint ea = EA_AX_DI_32();
  5214. m68ki_write_32(ea, res);
  5215. FLAG_N = NFLAG_32(res);
  5216. FLAG_Z = res;
  5217. FLAG_V = VFLAG_CLEAR;
  5218. FLAG_C = CFLAG_CLEAR;
  5219. }
  5220. M68KMAKE_OP(move, 32, di, a)
  5221. {
  5222. uint res = AY;
  5223. uint ea = EA_AX_DI_32();
  5224. m68ki_write_32(ea, res);
  5225. FLAG_N = NFLAG_32(res);
  5226. FLAG_Z = res;
  5227. FLAG_V = VFLAG_CLEAR;
  5228. FLAG_C = CFLAG_CLEAR;
  5229. }
  5230. M68KMAKE_OP(move, 32, di, .)
  5231. {
  5232. uint res = M68KMAKE_GET_OPER_AY_32;
  5233. uint ea = EA_AX_DI_32();
  5234. m68ki_write_32(ea, res);
  5235. FLAG_N = NFLAG_32(res);
  5236. FLAG_Z = res;
  5237. FLAG_V = VFLAG_CLEAR;
  5238. FLAG_C = CFLAG_CLEAR;
  5239. }
  5240. M68KMAKE_OP(move, 32, ix, d)
  5241. {
  5242. uint res = DY;
  5243. uint ea = EA_AX_IX_32();
  5244. m68ki_write_32(ea, res);
  5245. FLAG_N = NFLAG_32(res);
  5246. FLAG_Z = res;
  5247. FLAG_V = VFLAG_CLEAR;
  5248. FLAG_C = CFLAG_CLEAR;
  5249. }
  5250. M68KMAKE_OP(move, 32, ix, a)
  5251. {
  5252. uint res = AY;
  5253. uint ea = EA_AX_IX_32();
  5254. m68ki_write_32(ea, res);
  5255. FLAG_N = NFLAG_32(res);
  5256. FLAG_Z = res;
  5257. FLAG_V = VFLAG_CLEAR;
  5258. FLAG_C = CFLAG_CLEAR;
  5259. }
  5260. M68KMAKE_OP(move, 32, ix, .)
  5261. {
  5262. uint res = M68KMAKE_GET_OPER_AY_32;
  5263. uint ea = EA_AX_IX_32();
  5264. m68ki_write_32(ea, res);
  5265. FLAG_N = NFLAG_32(res);
  5266. FLAG_Z = res;
  5267. FLAG_V = VFLAG_CLEAR;
  5268. FLAG_C = CFLAG_CLEAR;
  5269. }
  5270. M68KMAKE_OP(move, 32, aw, d)
  5271. {
  5272. uint res = DY;
  5273. uint ea = EA_AW_32();
  5274. m68ki_write_32(ea, res);
  5275. FLAG_N = NFLAG_32(res);
  5276. FLAG_Z = res;
  5277. FLAG_V = VFLAG_CLEAR;
  5278. FLAG_C = CFLAG_CLEAR;
  5279. }
  5280. M68KMAKE_OP(move, 32, aw, a)
  5281. {
  5282. uint res = AY;
  5283. uint ea = EA_AW_32();
  5284. m68ki_write_32(ea, res);
  5285. FLAG_N = NFLAG_32(res);
  5286. FLAG_Z = res;
  5287. FLAG_V = VFLAG_CLEAR;
  5288. FLAG_C = CFLAG_CLEAR;
  5289. }
  5290. M68KMAKE_OP(move, 32, aw, .)
  5291. {
  5292. uint res = M68KMAKE_GET_OPER_AY_32;
  5293. uint ea = EA_AW_32();
  5294. m68ki_write_32(ea, res);
  5295. FLAG_N = NFLAG_32(res);
  5296. FLAG_Z = res;
  5297. FLAG_V = VFLAG_CLEAR;
  5298. FLAG_C = CFLAG_CLEAR;
  5299. }
  5300. M68KMAKE_OP(move, 32, al, d)
  5301. {
  5302. uint res = DY;
  5303. uint ea = EA_AL_32();
  5304. m68ki_write_32(ea, res);
  5305. FLAG_N = NFLAG_32(res);
  5306. FLAG_Z = res;
  5307. FLAG_V = VFLAG_CLEAR;
  5308. FLAG_C = CFLAG_CLEAR;
  5309. }
  5310. M68KMAKE_OP(move, 32, al, a)
  5311. {
  5312. uint res = AY;
  5313. uint ea = EA_AL_32();
  5314. m68ki_write_32(ea, res);
  5315. FLAG_N = NFLAG_32(res);
  5316. FLAG_Z = res;
  5317. FLAG_V = VFLAG_CLEAR;
  5318. FLAG_C = CFLAG_CLEAR;
  5319. }
  5320. M68KMAKE_OP(move, 32, al, .)
  5321. {
  5322. uint res = M68KMAKE_GET_OPER_AY_32;
  5323. uint ea = EA_AL_32();
  5324. m68ki_write_32(ea, res);
  5325. FLAG_N = NFLAG_32(res);
  5326. FLAG_Z = res;
  5327. FLAG_V = VFLAG_CLEAR;
  5328. FLAG_C = CFLAG_CLEAR;
  5329. }
  5330. M68KMAKE_OP(movea, 16, ., d)
  5331. {
  5332. AX = MAKE_INT_16(DY);
  5333. }
  5334. M68KMAKE_OP(movea, 16, ., a)
  5335. {
  5336. AX = MAKE_INT_16(AY);
  5337. }
  5338. M68KMAKE_OP(movea, 16, ., .)
  5339. {
  5340. AX = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
  5341. }
  5342. M68KMAKE_OP(movea, 32, ., d)
  5343. {
  5344. AX = DY;
  5345. }
  5346. M68KMAKE_OP(movea, 32, ., a)
  5347. {
  5348. AX = AY;
  5349. }
  5350. M68KMAKE_OP(movea, 32, ., .)
  5351. {
  5352. AX = M68KMAKE_GET_OPER_AY_32;
  5353. }
  5354. M68KMAKE_OP(move, 16, frc, d)
  5355. {
  5356. if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
  5357. {
  5358. DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr();
  5359. return;
  5360. }
  5361. m68ki_exception_illegal();
  5362. }
  5363. M68KMAKE_OP(move, 16, frc, .)
  5364. {
  5365. if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
  5366. {
  5367. m68ki_write_16(M68KMAKE_GET_EA_AY_16, m68ki_get_ccr());
  5368. return;
  5369. }
  5370. m68ki_exception_illegal();
  5371. }
  5372. M68KMAKE_OP(move, 16, toc, d)
  5373. {
  5374. m68ki_set_ccr(DY);
  5375. }
  5376. M68KMAKE_OP(move, 16, toc, .)
  5377. {
  5378. m68ki_set_ccr(M68KMAKE_GET_OPER_AY_16);
  5379. }
  5380. M68KMAKE_OP(move, 16, frs, d)
  5381. {
  5382. if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
  5383. {
  5384. DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr();
  5385. return;
  5386. }
  5387. m68ki_exception_privilege_violation();
  5388. }
  5389. M68KMAKE_OP(move, 16, frs, .)
  5390. {
  5391. if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
  5392. {
  5393. uint ea = M68KMAKE_GET_EA_AY_16;
  5394. m68ki_write_16(ea, m68ki_get_sr());
  5395. return;
  5396. }
  5397. m68ki_exception_privilege_violation();
  5398. }
  5399. M68KMAKE_OP(move, 16, tos, d)
  5400. {
  5401. if(FLAG_S)
  5402. {
  5403. m68ki_set_sr(DY);
  5404. return;
  5405. }
  5406. m68ki_exception_privilege_violation();
  5407. }
  5408. M68KMAKE_OP(move, 16, tos, .)
  5409. {
  5410. if(FLAG_S)
  5411. {
  5412. uint new_sr = M68KMAKE_GET_OPER_AY_16;
  5413. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  5414. m68ki_set_sr(new_sr);
  5415. return;
  5416. }
  5417. m68ki_exception_privilege_violation();
  5418. }
  5419. M68KMAKE_OP(move, 32, fru, .)
  5420. {
  5421. if(FLAG_S)
  5422. {
  5423. AY = REG_USP;
  5424. return;
  5425. }
  5426. m68ki_exception_privilege_violation();
  5427. }
  5428. M68KMAKE_OP(move, 32, tou, .)
  5429. {
  5430. if(FLAG_S)
  5431. {
  5432. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  5433. REG_USP = AY;
  5434. return;
  5435. }
  5436. m68ki_exception_privilege_violation();
  5437. }
  5438. M68KMAKE_OP(movec, 32, cr, .)
  5439. {
  5440. if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
  5441. {
  5442. if(FLAG_S)
  5443. {
  5444. uint word2 = OPER_I_16();
  5445. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  5446. switch (word2 & 0xfff)
  5447. {
  5448. case 0x000: /* SFC */
  5449. REG_DA[(word2 >> 12) & 15] = REG_SFC;
  5450. return;
  5451. case 0x001: /* DFC */
  5452. REG_DA[(word2 >> 12) & 15] = REG_DFC;
  5453. return;
  5454. case 0x002: /* CACR */
  5455. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  5456. {
  5457. REG_DA[(word2 >> 12) & 15] = REG_CACR;
  5458. return;
  5459. }
  5460. return;
  5461. case 0x800: /* USP */
  5462. REG_DA[(word2 >> 12) & 15] = REG_USP;
  5463. return;
  5464. case 0x801: /* VBR */
  5465. REG_DA[(word2 >> 12) & 15] = REG_VBR;
  5466. return;
  5467. case 0x802: /* CAAR */
  5468. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  5469. {
  5470. REG_DA[(word2 >> 12) & 15] = REG_CAAR;
  5471. return;
  5472. }
  5473. m68ki_exception_illegal();
  5474. break;
  5475. case 0x803: /* MSP */
  5476. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  5477. {
  5478. REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_SP : REG_MSP;
  5479. return;
  5480. }
  5481. m68ki_exception_illegal();
  5482. return;
  5483. case 0x804: /* ISP */
  5484. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  5485. {
  5486. REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_ISP : REG_SP;
  5487. return;
  5488. }
  5489. m68ki_exception_illegal();
  5490. return;
  5491. case 0x003: /* TC */
  5492. if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5493. {
  5494. /* TODO */
  5495. return;
  5496. }
  5497. m68ki_exception_illegal();
  5498. return;
  5499. case 0x004: /* ITT0 */
  5500. if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5501. {
  5502. /* TODO */
  5503. return;
  5504. }
  5505. m68ki_exception_illegal();
  5506. return;
  5507. case 0x005: /* ITT1 */
  5508. if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5509. {
  5510. /* TODO */
  5511. return;
  5512. }
  5513. m68ki_exception_illegal();
  5514. return;
  5515. case 0x006: /* DTT0 */
  5516. if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5517. {
  5518. /* TODO */
  5519. return;
  5520. }
  5521. m68ki_exception_illegal();
  5522. return;
  5523. case 0x007: /* DTT1 */
  5524. if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5525. {
  5526. /* TODO */
  5527. return;
  5528. }
  5529. m68ki_exception_illegal();
  5530. return;
  5531. case 0x805: /* MMUSR */
  5532. if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5533. {
  5534. /* TODO */
  5535. return;
  5536. }
  5537. m68ki_exception_illegal();
  5538. return;
  5539. case 0x806: /* URP */
  5540. if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5541. {
  5542. /* TODO */
  5543. return;
  5544. }
  5545. m68ki_exception_illegal();
  5546. return;
  5547. case 0x807: /* SRP */
  5548. if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5549. {
  5550. /* TODO */
  5551. return;
  5552. }
  5553. m68ki_exception_illegal();
  5554. return;
  5555. default:
  5556. m68ki_exception_illegal();
  5557. return;
  5558. }
  5559. }
  5560. m68ki_exception_privilege_violation();
  5561. return;
  5562. }
  5563. m68ki_exception_illegal();
  5564. }
  5565. M68KMAKE_OP(movec, 32, rc, .)
  5566. {
  5567. if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
  5568. {
  5569. if(FLAG_S)
  5570. {
  5571. uint word2 = OPER_I_16();
  5572. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  5573. switch (word2 & 0xfff)
  5574. {
  5575. case 0x000: /* SFC */
  5576. REG_SFC = REG_DA[(word2 >> 12) & 15] & 7;
  5577. return;
  5578. case 0x001: /* DFC */
  5579. REG_DFC = REG_DA[(word2 >> 12) & 15] & 7;
  5580. return;
  5581. case 0x002: /* CACR */
  5582. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  5583. {
  5584. if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5585. {
  5586. REG_CACR = REG_DA[(word2 >> 12) & 15];
  5587. }
  5588. else
  5589. {
  5590. /* non 68040 can only set the lower 4 bits (C,CE,F,E) */
  5591. REG_CACR = REG_DA[(word2 >> 12) & 15] & 0x0f;
  5592. }
  5593. return;
  5594. }
  5595. m68ki_exception_illegal();
  5596. return;
  5597. case 0x800: /* USP */
  5598. REG_USP = REG_DA[(word2 >> 12) & 15];
  5599. return;
  5600. case 0x801: /* VBR */
  5601. REG_VBR = REG_DA[(word2 >> 12) & 15];
  5602. return;
  5603. case 0x802: /* CAAR */
  5604. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  5605. {
  5606. REG_CAAR = REG_DA[(word2 >> 12) & 15];
  5607. return;
  5608. }
  5609. m68ki_exception_illegal();
  5610. return;
  5611. case 0x803: /* MSP */
  5612. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  5613. {
  5614. /* we are in supervisor mode so just check for M flag */
  5615. if(!FLAG_M)
  5616. {
  5617. REG_MSP = REG_DA[(word2 >> 12) & 15];
  5618. return;
  5619. }
  5620. REG_SP = REG_DA[(word2 >> 12) & 15];
  5621. return;
  5622. }
  5623. m68ki_exception_illegal();
  5624. return;
  5625. case 0x804: /* ISP */
  5626. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  5627. {
  5628. if(!FLAG_M)
  5629. {
  5630. REG_SP = REG_DA[(word2 >> 12) & 15];
  5631. return;
  5632. }
  5633. REG_ISP = REG_DA[(word2 >> 12) & 15];
  5634. return;
  5635. }
  5636. m68ki_exception_illegal();
  5637. return;
  5638. case 0x003: /* TC */
  5639. if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5640. {
  5641. /* TODO */
  5642. return;
  5643. }
  5644. m68ki_exception_illegal();
  5645. return;
  5646. case 0x004: /* ITT0 */
  5647. if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5648. {
  5649. /* TODO */
  5650. return;
  5651. }
  5652. m68ki_exception_illegal();
  5653. return;
  5654. case 0x005: /* ITT1 */
  5655. if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5656. {
  5657. /* TODO */
  5658. return;
  5659. }
  5660. m68ki_exception_illegal();
  5661. return;
  5662. case 0x006: /* DTT0 */
  5663. if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5664. {
  5665. /* TODO */
  5666. return;
  5667. }
  5668. m68ki_exception_illegal();
  5669. return;
  5670. case 0x007: /* DTT1 */
  5671. if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5672. {
  5673. /* TODO */
  5674. return;
  5675. }
  5676. m68ki_exception_illegal();
  5677. return;
  5678. case 0x805: /* MMUSR */
  5679. if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5680. {
  5681. /* TODO */
  5682. return;
  5683. }
  5684. m68ki_exception_illegal();
  5685. return;
  5686. case 0x806: /* URP */
  5687. if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5688. {
  5689. /* TODO */
  5690. return;
  5691. }
  5692. m68ki_exception_illegal();
  5693. return;
  5694. case 0x807: /* SRP */
  5695. if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  5696. {
  5697. /* TODO */
  5698. return;
  5699. }
  5700. m68ki_exception_illegal();
  5701. return;
  5702. default:
  5703. m68ki_exception_illegal();
  5704. return;
  5705. }
  5706. }
  5707. m68ki_exception_privilege_violation();
  5708. return;
  5709. }
  5710. m68ki_exception_illegal();
  5711. }
  5712. M68KMAKE_OP(movem, 16, re, pd)
  5713. {
  5714. uint i = 0;
  5715. uint register_list = OPER_I_16();
  5716. uint ea = AY;
  5717. uint count = 0;
  5718. for(; i < 16; i++)
  5719. if(register_list & (1 << i))
  5720. {
  5721. ea -= 2;
  5722. m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i]));
  5723. count++;
  5724. }
  5725. AY = ea;
  5726. USE_CYCLES(count<<CYC_MOVEM_W);
  5727. }
  5728. M68KMAKE_OP(movem, 16, re, .)
  5729. {
  5730. uint i = 0;
  5731. uint register_list = OPER_I_16();
  5732. uint ea = M68KMAKE_GET_EA_AY_16;
  5733. uint count = 0;
  5734. for(; i < 16; i++)
  5735. if(register_list & (1 << i))
  5736. {
  5737. m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
  5738. ea += 2;
  5739. count++;
  5740. }
  5741. USE_CYCLES(count<<CYC_MOVEM_W);
  5742. }
  5743. M68KMAKE_OP(movem, 32, re, pd)
  5744. {
  5745. uint i = 0;
  5746. uint register_list = OPER_I_16();
  5747. uint ea = AY;
  5748. uint count = 0;
  5749. for(; i < 16; i++)
  5750. if(register_list & (1 << i))
  5751. {
  5752. ea -= 4;
  5753. m68ki_write_16(ea+2, REG_DA[15-i] & 0xFFFF );
  5754. m68ki_write_16(ea, (REG_DA[15-i] >> 16) & 0xFFFF );
  5755. count++;
  5756. }
  5757. AY = ea;
  5758. USE_CYCLES(count<<CYC_MOVEM_L);
  5759. }
  5760. M68KMAKE_OP(movem, 32, re, .)
  5761. {
  5762. uint i = 0;
  5763. uint register_list = OPER_I_16();
  5764. uint ea = M68KMAKE_GET_EA_AY_32;
  5765. uint count = 0;
  5766. for(; i < 16; i++)
  5767. if(register_list & (1 << i))
  5768. {
  5769. m68ki_write_32(ea, REG_DA[i]);
  5770. ea += 4;
  5771. count++;
  5772. }
  5773. USE_CYCLES(count<<CYC_MOVEM_L);
  5774. }
  5775. M68KMAKE_OP(movem, 16, er, pi)
  5776. {
  5777. uint i = 0;
  5778. uint register_list = OPER_I_16();
  5779. uint ea = AY;
  5780. uint count = 0;
  5781. for(; i < 16; i++)
  5782. if(register_list & (1 << i))
  5783. {
  5784. REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
  5785. ea += 2;
  5786. count++;
  5787. }
  5788. AY = ea;
  5789. USE_CYCLES(count<<CYC_MOVEM_W);
  5790. }
  5791. M68KMAKE_OP(movem, 16, er, pcdi)
  5792. {
  5793. uint i = 0;
  5794. uint register_list = OPER_I_16();
  5795. uint ea = EA_PCDI_16();
  5796. uint count = 0;
  5797. for(; i < 16; i++)
  5798. if(register_list & (1 << i))
  5799. {
  5800. REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
  5801. ea += 2;
  5802. count++;
  5803. }
  5804. USE_CYCLES(count<<CYC_MOVEM_W);
  5805. }
  5806. M68KMAKE_OP(movem, 16, er, pcix)
  5807. {
  5808. uint i = 0;
  5809. uint register_list = OPER_I_16();
  5810. uint ea = EA_PCIX_16();
  5811. uint count = 0;
  5812. for(; i < 16; i++)
  5813. if(register_list & (1 << i))
  5814. {
  5815. REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
  5816. ea += 2;
  5817. count++;
  5818. }
  5819. USE_CYCLES(count<<CYC_MOVEM_W);
  5820. }
  5821. M68KMAKE_OP(movem, 16, er, .)
  5822. {
  5823. uint i = 0;
  5824. uint register_list = OPER_I_16();
  5825. uint ea = M68KMAKE_GET_EA_AY_16;
  5826. uint count = 0;
  5827. for(; i < 16; i++)
  5828. if(register_list & (1 << i))
  5829. {
  5830. REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
  5831. ea += 2;
  5832. count++;
  5833. }
  5834. USE_CYCLES(count<<CYC_MOVEM_W);
  5835. }
  5836. M68KMAKE_OP(movem, 32, er, pi)
  5837. {
  5838. uint i = 0;
  5839. uint register_list = OPER_I_16();
  5840. uint ea = AY;
  5841. uint count = 0;
  5842. for(; i < 16; i++)
  5843. if(register_list & (1 << i))
  5844. {
  5845. REG_DA[i] = m68ki_read_32(ea);
  5846. ea += 4;
  5847. count++;
  5848. }
  5849. AY = ea;
  5850. USE_CYCLES(count<<CYC_MOVEM_L);
  5851. }
  5852. M68KMAKE_OP(movem, 32, er, pcdi)
  5853. {
  5854. uint i = 0;
  5855. uint register_list = OPER_I_16();
  5856. uint ea = EA_PCDI_32();
  5857. uint count = 0;
  5858. for(; i < 16; i++)
  5859. if(register_list & (1 << i))
  5860. {
  5861. REG_DA[i] = m68ki_read_pcrel_32(ea);
  5862. ea += 4;
  5863. count++;
  5864. }
  5865. USE_CYCLES(count<<CYC_MOVEM_L);
  5866. }
  5867. M68KMAKE_OP(movem, 32, er, pcix)
  5868. {
  5869. uint i = 0;
  5870. uint register_list = OPER_I_16();
  5871. uint ea = EA_PCIX_32();
  5872. uint count = 0;
  5873. for(; i < 16; i++)
  5874. if(register_list & (1 << i))
  5875. {
  5876. REG_DA[i] = m68ki_read_pcrel_32(ea);
  5877. ea += 4;
  5878. count++;
  5879. }
  5880. USE_CYCLES(count<<CYC_MOVEM_L);
  5881. }
  5882. M68KMAKE_OP(movem, 32, er, .)
  5883. {
  5884. uint i = 0;
  5885. uint register_list = OPER_I_16();
  5886. uint ea = M68KMAKE_GET_EA_AY_32;
  5887. uint count = 0;
  5888. for(; i < 16; i++)
  5889. if(register_list & (1 << i))
  5890. {
  5891. REG_DA[i] = m68ki_read_32(ea);
  5892. ea += 4;
  5893. count++;
  5894. }
  5895. USE_CYCLES(count<<CYC_MOVEM_L);
  5896. }
  5897. M68KMAKE_OP(movep, 16, re, .)
  5898. {
  5899. uint ea = EA_AY_DI_16();
  5900. uint src = DX;
  5901. m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 8));
  5902. m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
  5903. }
  5904. M68KMAKE_OP(movep, 32, re, .)
  5905. {
  5906. uint ea = EA_AY_DI_32();
  5907. uint src = DX;
  5908. m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24));
  5909. m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16));
  5910. m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8));
  5911. m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
  5912. }
  5913. M68KMAKE_OP(movep, 16, er, .)
  5914. {
  5915. uint ea = EA_AY_DI_16();
  5916. uint* r_dst = &DX;
  5917. *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2));
  5918. }
  5919. M68KMAKE_OP(movep, 32, er, .)
  5920. {
  5921. uint ea = EA_AY_DI_32();
  5922. DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16)
  5923. + (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6);
  5924. }
  5925. M68KMAKE_OP(moves, 8, ., .)
  5926. {
  5927. if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
  5928. {
  5929. if(FLAG_S)
  5930. {
  5931. uint word2 = OPER_I_16();
  5932. uint ea = M68KMAKE_GET_EA_AY_8;
  5933. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  5934. if(BIT_B(word2)) /* Register to memory */
  5935. {
  5936. m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
  5937. return;
  5938. }
  5939. if(BIT_F(word2)) /* Memory to address register */
  5940. {
  5941. REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
  5942. if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
  5943. USE_CYCLES(2);
  5944. return;
  5945. }
  5946. /* Memory to data register */
  5947. REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
  5948. if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
  5949. USE_CYCLES(2);
  5950. return;
  5951. }
  5952. m68ki_exception_privilege_violation();
  5953. return;
  5954. }
  5955. m68ki_exception_illegal();
  5956. }
  5957. M68KMAKE_OP(moves, 16, ., .)
  5958. {
  5959. if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
  5960. {
  5961. if(FLAG_S)
  5962. {
  5963. uint word2 = OPER_I_16();
  5964. uint ea = M68KMAKE_GET_EA_AY_16;
  5965. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  5966. if(BIT_B(word2)) /* Register to memory */
  5967. {
  5968. m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
  5969. return;
  5970. }
  5971. if(BIT_F(word2)) /* Memory to address register */
  5972. {
  5973. REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
  5974. if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
  5975. USE_CYCLES(2);
  5976. return;
  5977. }
  5978. /* Memory to data register */
  5979. REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
  5980. if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
  5981. USE_CYCLES(2);
  5982. return;
  5983. }
  5984. m68ki_exception_privilege_violation();
  5985. return;
  5986. }
  5987. m68ki_exception_illegal();
  5988. }
  5989. M68KMAKE_OP(moves, 32, ., .)
  5990. {
  5991. if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
  5992. {
  5993. if(FLAG_S)
  5994. {
  5995. uint word2 = OPER_I_16();
  5996. uint ea = M68KMAKE_GET_EA_AY_32;
  5997. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  5998. if(BIT_B(word2)) /* Register to memory */
  5999. {
  6000. m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
  6001. if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
  6002. USE_CYCLES(2);
  6003. return;
  6004. }
  6005. /* Memory to register */
  6006. REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
  6007. if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
  6008. USE_CYCLES(2);
  6009. return;
  6010. }
  6011. m68ki_exception_privilege_violation();
  6012. return;
  6013. }
  6014. m68ki_exception_illegal();
  6015. }
  6016. M68KMAKE_OP(moveq, 32, ., .)
  6017. {
  6018. uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR));
  6019. FLAG_N = NFLAG_32(res);
  6020. FLAG_Z = res;
  6021. FLAG_V = VFLAG_CLEAR;
  6022. FLAG_C = CFLAG_CLEAR;
  6023. }
  6024. M68KMAKE_OP(move16, 32, ., .)
  6025. {
  6026. UINT16 w2 = OPER_I_16();
  6027. int ax = REG_IR & 7;
  6028. int ay = (w2 >> 12) & 7;
  6029. m68ki_write_32(REG_A[ay], m68ki_read_32(REG_A[ax]));
  6030. m68ki_write_32(REG_A[ay]+4, m68ki_read_32(REG_A[ax]+4));
  6031. m68ki_write_32(REG_A[ay]+8, m68ki_read_32(REG_A[ax]+8));
  6032. m68ki_write_32(REG_A[ay]+12, m68ki_read_32(REG_A[ax]+12));
  6033. REG_A[ax] += 16;
  6034. REG_A[ay] += 16;
  6035. }
  6036. M68KMAKE_OP(muls, 16, ., d)
  6037. {
  6038. uint* r_dst = &DX;
  6039. uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(DY) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
  6040. *r_dst = res;
  6041. FLAG_Z = res;
  6042. FLAG_N = NFLAG_32(res);
  6043. FLAG_V = VFLAG_CLEAR;
  6044. FLAG_C = CFLAG_CLEAR;
  6045. }
  6046. M68KMAKE_OP(muls, 16, ., .)
  6047. {
  6048. uint* r_dst = &DX;
  6049. uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(M68KMAKE_GET_OPER_AY_16) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
  6050. *r_dst = res;
  6051. FLAG_Z = res;
  6052. FLAG_N = NFLAG_32(res);
  6053. FLAG_V = VFLAG_CLEAR;
  6054. FLAG_C = CFLAG_CLEAR;
  6055. }
  6056. M68KMAKE_OP(mulu, 16, ., d)
  6057. {
  6058. uint* r_dst = &DX;
  6059. uint res = MASK_OUT_ABOVE_16(DY) * MASK_OUT_ABOVE_16(*r_dst);
  6060. *r_dst = res;
  6061. FLAG_Z = res;
  6062. FLAG_N = NFLAG_32(res);
  6063. FLAG_V = VFLAG_CLEAR;
  6064. FLAG_C = CFLAG_CLEAR;
  6065. }
  6066. M68KMAKE_OP(mulu, 16, ., .)
  6067. {
  6068. uint* r_dst = &DX;
  6069. uint res = M68KMAKE_GET_OPER_AY_16 * MASK_OUT_ABOVE_16(*r_dst);
  6070. *r_dst = res;
  6071. FLAG_Z = res;
  6072. FLAG_N = NFLAG_32(res);
  6073. FLAG_V = VFLAG_CLEAR;
  6074. FLAG_C = CFLAG_CLEAR;
  6075. }
  6076. M68KMAKE_OP(mull, 32, ., d)
  6077. {
  6078. #if M68K_USE_64_BIT
  6079. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  6080. {
  6081. uint word2 = OPER_I_16();
  6082. uint64 src = DY;
  6083. uint64 dst = REG_D[(word2 >> 12) & 7];
  6084. uint64 res;
  6085. FLAG_C = CFLAG_CLEAR;
  6086. if(BIT_B(word2)) /* signed */
  6087. {
  6088. res = (sint64)((sint32)src) * (sint64)((sint32)dst);
  6089. if(!BIT_A(word2))
  6090. {
  6091. FLAG_Z = MASK_OUT_ABOVE_32(res);
  6092. FLAG_N = NFLAG_32(res);
  6093. FLAG_V = ((sint64)res != (sint32)res)<<7;
  6094. REG_D[(word2 >> 12) & 7] = FLAG_Z;
  6095. return;
  6096. }
  6097. FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
  6098. FLAG_N = NFLAG_64(res);
  6099. FLAG_V = VFLAG_CLEAR;
  6100. REG_D[word2 & 7] = (res >> 32);
  6101. REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
  6102. return;
  6103. }
  6104. res = src * dst;
  6105. if(!BIT_A(word2))
  6106. {
  6107. FLAG_Z = MASK_OUT_ABOVE_32(res);
  6108. FLAG_N = NFLAG_32(res);
  6109. FLAG_V = (res > 0xffffffff)<<7;
  6110. REG_D[(word2 >> 12) & 7] = FLAG_Z;
  6111. return;
  6112. }
  6113. FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
  6114. FLAG_N = NFLAG_64(res);
  6115. FLAG_V = VFLAG_CLEAR;
  6116. REG_D[word2 & 7] = (res >> 32);
  6117. REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
  6118. return;
  6119. }
  6120. m68ki_exception_illegal();
  6121. #else
  6122. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  6123. {
  6124. uint word2 = OPER_I_16();
  6125. uint src = DY;
  6126. uint dst = REG_D[(word2 >> 12) & 7];
  6127. uint neg = GET_MSB_32(src ^ dst);
  6128. uint src1;
  6129. uint src2;
  6130. uint dst1;
  6131. uint dst2;
  6132. uint r1;
  6133. uint r2;
  6134. uint r3;
  6135. uint r4;
  6136. uint lo;
  6137. uint hi;
  6138. FLAG_C = CFLAG_CLEAR;
  6139. if(BIT_B(word2)) /* signed */
  6140. {
  6141. if(GET_MSB_32(src))
  6142. src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
  6143. if(GET_MSB_32(dst))
  6144. dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
  6145. }
  6146. src1 = MASK_OUT_ABOVE_16(src);
  6147. src2 = src>>16;
  6148. dst1 = MASK_OUT_ABOVE_16(dst);
  6149. dst2 = dst>>16;
  6150. r1 = src1 * dst1;
  6151. r2 = src1 * dst2;
  6152. r3 = src2 * dst1;
  6153. r4 = src2 * dst2;
  6154. lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
  6155. hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
  6156. if(BIT_B(word2) && neg)
  6157. {
  6158. hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
  6159. lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
  6160. }
  6161. if(BIT_A(word2))
  6162. {
  6163. REG_D[word2 & 7] = hi;
  6164. REG_D[(word2 >> 12) & 7] = lo;
  6165. FLAG_N = NFLAG_32(hi);
  6166. FLAG_Z = hi | lo;
  6167. FLAG_V = VFLAG_CLEAR;
  6168. return;
  6169. }
  6170. REG_D[(word2 >> 12) & 7] = lo;
  6171. FLAG_N = NFLAG_32(lo);
  6172. FLAG_Z = lo;
  6173. if(BIT_B(word2))
  6174. FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
  6175. else
  6176. FLAG_V = (hi != 0) << 7;
  6177. return;
  6178. }
  6179. m68ki_exception_illegal();
  6180. #endif
  6181. }
  6182. M68KMAKE_OP(mull, 32, ., .)
  6183. {
  6184. #if M68K_USE_64_BIT
  6185. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  6186. {
  6187. uint word2 = OPER_I_16();
  6188. uint64 src = M68KMAKE_GET_OPER_AY_32;
  6189. uint64 dst = REG_D[(word2 >> 12) & 7];
  6190. uint64 res;
  6191. FLAG_C = CFLAG_CLEAR;
  6192. if(BIT_B(word2)) /* signed */
  6193. {
  6194. res = (sint64)((sint32)src) * (sint64)((sint32)dst);
  6195. if(!BIT_A(word2))
  6196. {
  6197. FLAG_Z = MASK_OUT_ABOVE_32(res);
  6198. FLAG_N = NFLAG_32(res);
  6199. FLAG_V = ((sint64)res != (sint32)res)<<7;
  6200. REG_D[(word2 >> 12) & 7] = FLAG_Z;
  6201. return;
  6202. }
  6203. FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
  6204. FLAG_N = NFLAG_64(res);
  6205. FLAG_V = VFLAG_CLEAR;
  6206. REG_D[word2 & 7] = (res >> 32);
  6207. REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
  6208. return;
  6209. }
  6210. res = src * dst;
  6211. if(!BIT_A(word2))
  6212. {
  6213. FLAG_Z = MASK_OUT_ABOVE_32(res);
  6214. FLAG_N = NFLAG_32(res);
  6215. FLAG_V = (res > 0xffffffff)<<7;
  6216. REG_D[(word2 >> 12) & 7] = FLAG_Z;
  6217. return;
  6218. }
  6219. FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
  6220. FLAG_N = NFLAG_64(res);
  6221. FLAG_V = VFLAG_CLEAR;
  6222. REG_D[word2 & 7] = (res >> 32);
  6223. REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
  6224. return;
  6225. }
  6226. m68ki_exception_illegal();
  6227. #else
  6228. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  6229. {
  6230. uint word2 = OPER_I_16();
  6231. uint src = M68KMAKE_GET_OPER_AY_32;
  6232. uint dst = REG_D[(word2 >> 12) & 7];
  6233. uint neg = GET_MSB_32(src ^ dst);
  6234. uint src1;
  6235. uint src2;
  6236. uint dst1;
  6237. uint dst2;
  6238. uint r1;
  6239. uint r2;
  6240. uint r3;
  6241. uint r4;
  6242. uint lo;
  6243. uint hi;
  6244. FLAG_C = CFLAG_CLEAR;
  6245. if(BIT_B(word2)) /* signed */
  6246. {
  6247. if(GET_MSB_32(src))
  6248. src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
  6249. if(GET_MSB_32(dst))
  6250. dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
  6251. }
  6252. src1 = MASK_OUT_ABOVE_16(src);
  6253. src2 = src>>16;
  6254. dst1 = MASK_OUT_ABOVE_16(dst);
  6255. dst2 = dst>>16;
  6256. r1 = src1 * dst1;
  6257. r2 = src1 * dst2;
  6258. r3 = src2 * dst1;
  6259. r4 = src2 * dst2;
  6260. lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
  6261. hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
  6262. if(BIT_B(word2) && neg)
  6263. {
  6264. hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
  6265. lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
  6266. }
  6267. if(BIT_A(word2))
  6268. {
  6269. REG_D[word2 & 7] = hi;
  6270. REG_D[(word2 >> 12) & 7] = lo;
  6271. FLAG_N = NFLAG_32(hi);
  6272. FLAG_Z = hi | lo;
  6273. FLAG_V = VFLAG_CLEAR;
  6274. return;
  6275. }
  6276. REG_D[(word2 >> 12) & 7] = lo;
  6277. FLAG_N = NFLAG_32(lo);
  6278. FLAG_Z = lo;
  6279. if(BIT_B(word2))
  6280. FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
  6281. else
  6282. FLAG_V = (hi != 0) << 7;
  6283. return;
  6284. }
  6285. m68ki_exception_illegal();
  6286. #endif
  6287. }
  6288. M68KMAKE_OP(nbcd, 8, ., d)
  6289. {
  6290. uint* r_dst = &DY;
  6291. uint dst = *r_dst;
  6292. uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
  6293. if(res != 0x9a)
  6294. {
  6295. FLAG_V = ~res; /* Undefined V behavior */
  6296. if((res & 0x0f) == 0xa)
  6297. res = (res & 0xf0) + 0x10;
  6298. res = MASK_OUT_ABOVE_8(res);
  6299. FLAG_V &= res; /* Undefined V behavior part II */
  6300. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  6301. FLAG_Z |= res;
  6302. FLAG_C = CFLAG_SET;
  6303. FLAG_X = XFLAG_SET;
  6304. }
  6305. else
  6306. {
  6307. FLAG_V = VFLAG_CLEAR;
  6308. FLAG_C = CFLAG_CLEAR;
  6309. FLAG_X = XFLAG_CLEAR;
  6310. }
  6311. FLAG_N = NFLAG_8(res); /* Undefined N behavior */
  6312. }
  6313. M68KMAKE_OP(nbcd, 8, ., .)
  6314. {
  6315. uint ea = M68KMAKE_GET_EA_AY_8;
  6316. uint dst = m68ki_read_8(ea);
  6317. uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
  6318. if(res != 0x9a)
  6319. {
  6320. FLAG_V = ~res; /* Undefined V behavior */
  6321. if((res & 0x0f) == 0xa)
  6322. res = (res & 0xf0) + 0x10;
  6323. res = MASK_OUT_ABOVE_8(res);
  6324. FLAG_V &= res; /* Undefined V behavior part II */
  6325. m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
  6326. FLAG_Z |= res;
  6327. FLAG_C = CFLAG_SET;
  6328. FLAG_X = XFLAG_SET;
  6329. }
  6330. else
  6331. {
  6332. FLAG_V = VFLAG_CLEAR;
  6333. FLAG_C = CFLAG_CLEAR;
  6334. FLAG_X = XFLAG_CLEAR;
  6335. }
  6336. FLAG_N = NFLAG_8(res); /* Undefined N behavior */
  6337. }
  6338. M68KMAKE_OP(neg, 8, ., d)
  6339. {
  6340. uint* r_dst = &DY;
  6341. uint res = 0 - MASK_OUT_ABOVE_8(*r_dst);
  6342. FLAG_N = NFLAG_8(res);
  6343. FLAG_C = FLAG_X = CFLAG_8(res);
  6344. FLAG_V = *r_dst & res;
  6345. FLAG_Z = MASK_OUT_ABOVE_8(res);
  6346. *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
  6347. }
  6348. M68KMAKE_OP(neg, 8, ., .)
  6349. {
  6350. uint ea = M68KMAKE_GET_EA_AY_8;
  6351. uint src = m68ki_read_8(ea);
  6352. uint res = 0 - src;
  6353. FLAG_N = NFLAG_8(res);
  6354. FLAG_C = FLAG_X = CFLAG_8(res);
  6355. FLAG_V = src & res;
  6356. FLAG_Z = MASK_OUT_ABOVE_8(res);
  6357. m68ki_write_8(ea, FLAG_Z);
  6358. }
  6359. M68KMAKE_OP(neg, 16, ., d)
  6360. {
  6361. uint* r_dst = &DY;
  6362. uint res = 0 - MASK_OUT_ABOVE_16(*r_dst);
  6363. FLAG_N = NFLAG_16(res);
  6364. FLAG_C = FLAG_X = CFLAG_16(res);
  6365. FLAG_V = (*r_dst & res)>>8;
  6366. FLAG_Z = MASK_OUT_ABOVE_16(res);
  6367. *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
  6368. }
  6369. M68KMAKE_OP(neg, 16, ., .)
  6370. {
  6371. uint ea = M68KMAKE_GET_EA_AY_16;
  6372. uint src = m68ki_read_16(ea);
  6373. uint res = 0 - src;
  6374. FLAG_N = NFLAG_16(res);
  6375. FLAG_C = FLAG_X = CFLAG_16(res);
  6376. FLAG_V = (src & res)>>8;
  6377. FLAG_Z = MASK_OUT_ABOVE_16(res);
  6378. m68ki_write_16(ea, FLAG_Z);
  6379. }
  6380. M68KMAKE_OP(neg, 32, ., d)
  6381. {
  6382. uint* r_dst = &DY;
  6383. uint res = 0 - *r_dst;
  6384. FLAG_N = NFLAG_32(res);
  6385. FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res);
  6386. FLAG_V = (*r_dst & res)>>24;
  6387. FLAG_Z = MASK_OUT_ABOVE_32(res);
  6388. *r_dst = FLAG_Z;
  6389. }
  6390. M68KMAKE_OP(neg, 32, ., .)
  6391. {
  6392. uint ea = M68KMAKE_GET_EA_AY_32;
  6393. uint src = m68ki_read_32(ea);
  6394. uint res = 0 - src;
  6395. FLAG_N = NFLAG_32(res);
  6396. FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
  6397. FLAG_V = (src & res)>>24;
  6398. FLAG_Z = MASK_OUT_ABOVE_32(res);
  6399. m68ki_write_32(ea, FLAG_Z);
  6400. }
  6401. M68KMAKE_OP(negx, 8, ., d)
  6402. {
  6403. uint* r_dst = &DY;
  6404. uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1();
  6405. FLAG_N = NFLAG_8(res);
  6406. FLAG_X = FLAG_C = CFLAG_8(res);
  6407. FLAG_V = *r_dst & res;
  6408. res = MASK_OUT_ABOVE_8(res);
  6409. FLAG_Z |= res;
  6410. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  6411. }
  6412. M68KMAKE_OP(negx, 8, ., .)
  6413. {
  6414. uint ea = M68KMAKE_GET_EA_AY_8;
  6415. uint src = m68ki_read_8(ea);
  6416. uint res = 0 - src - XFLAG_AS_1();
  6417. FLAG_N = NFLAG_8(res);
  6418. FLAG_X = FLAG_C = CFLAG_8(res);
  6419. FLAG_V = src & res;
  6420. res = MASK_OUT_ABOVE_8(res);
  6421. FLAG_Z |= res;
  6422. m68ki_write_8(ea, res);
  6423. }
  6424. M68KMAKE_OP(negx, 16, ., d)
  6425. {
  6426. uint* r_dst = &DY;
  6427. uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1();
  6428. FLAG_N = NFLAG_16(res);
  6429. FLAG_X = FLAG_C = CFLAG_16(res);
  6430. FLAG_V = (*r_dst & res)>>8;
  6431. res = MASK_OUT_ABOVE_16(res);
  6432. FLAG_Z |= res;
  6433. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  6434. }
  6435. M68KMAKE_OP(negx, 16, ., .)
  6436. {
  6437. uint ea = M68KMAKE_GET_EA_AY_16;
  6438. uint src = m68ki_read_16(ea);
  6439. uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
  6440. FLAG_N = NFLAG_16(res);
  6441. FLAG_X = FLAG_C = CFLAG_16(res);
  6442. FLAG_V = (src & res)>>8;
  6443. res = MASK_OUT_ABOVE_16(res);
  6444. FLAG_Z |= res;
  6445. m68ki_write_16(ea, res);
  6446. }
  6447. M68KMAKE_OP(negx, 32, ., d)
  6448. {
  6449. uint* r_dst = &DY;
  6450. uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1();
  6451. FLAG_N = NFLAG_32(res);
  6452. FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res);
  6453. FLAG_V = (*r_dst & res)>>24;
  6454. res = MASK_OUT_ABOVE_32(res);
  6455. FLAG_Z |= res;
  6456. *r_dst = res;
  6457. }
  6458. M68KMAKE_OP(negx, 32, ., .)
  6459. {
  6460. uint ea = M68KMAKE_GET_EA_AY_32;
  6461. uint src = m68ki_read_32(ea);
  6462. uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
  6463. FLAG_N = NFLAG_32(res);
  6464. FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
  6465. FLAG_V = (src & res)>>24;
  6466. res = MASK_OUT_ABOVE_32(res);
  6467. FLAG_Z |= res;
  6468. m68ki_write_32(ea, res);
  6469. }
  6470. M68KMAKE_OP(nop, 0, ., .)
  6471. {
  6472. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  6473. }
  6474. M68KMAKE_OP(not, 8, ., d)
  6475. {
  6476. uint* r_dst = &DY;
  6477. uint res = MASK_OUT_ABOVE_8(~*r_dst);
  6478. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  6479. FLAG_N = NFLAG_8(res);
  6480. FLAG_Z = res;
  6481. FLAG_C = CFLAG_CLEAR;
  6482. FLAG_V = VFLAG_CLEAR;
  6483. }
  6484. M68KMAKE_OP(not, 8, ., .)
  6485. {
  6486. uint ea = M68KMAKE_GET_EA_AY_8;
  6487. uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
  6488. m68ki_write_8(ea, res);
  6489. FLAG_N = NFLAG_8(res);
  6490. FLAG_Z = res;
  6491. FLAG_C = CFLAG_CLEAR;
  6492. FLAG_V = VFLAG_CLEAR;
  6493. }
  6494. M68KMAKE_OP(not, 16, ., d)
  6495. {
  6496. uint* r_dst = &DY;
  6497. uint res = MASK_OUT_ABOVE_16(~*r_dst);
  6498. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  6499. FLAG_N = NFLAG_16(res);
  6500. FLAG_Z = res;
  6501. FLAG_C = CFLAG_CLEAR;
  6502. FLAG_V = VFLAG_CLEAR;
  6503. }
  6504. M68KMAKE_OP(not, 16, ., .)
  6505. {
  6506. uint ea = M68KMAKE_GET_EA_AY_16;
  6507. uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
  6508. m68ki_write_16(ea, res);
  6509. FLAG_N = NFLAG_16(res);
  6510. FLAG_Z = res;
  6511. FLAG_C = CFLAG_CLEAR;
  6512. FLAG_V = VFLAG_CLEAR;
  6513. }
  6514. M68KMAKE_OP(not, 32, ., d)
  6515. {
  6516. uint* r_dst = &DY;
  6517. uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst);
  6518. FLAG_N = NFLAG_32(res);
  6519. FLAG_Z = res;
  6520. FLAG_C = CFLAG_CLEAR;
  6521. FLAG_V = VFLAG_CLEAR;
  6522. }
  6523. M68KMAKE_OP(not, 32, ., .)
  6524. {
  6525. uint ea = M68KMAKE_GET_EA_AY_32;
  6526. uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
  6527. m68ki_write_32(ea, res);
  6528. FLAG_N = NFLAG_32(res);
  6529. FLAG_Z = res;
  6530. FLAG_C = CFLAG_CLEAR;
  6531. FLAG_V = VFLAG_CLEAR;
  6532. }
  6533. M68KMAKE_OP(or, 8, er, d)
  6534. {
  6535. uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY)));
  6536. FLAG_N = NFLAG_8(res);
  6537. FLAG_Z = res;
  6538. FLAG_C = CFLAG_CLEAR;
  6539. FLAG_V = VFLAG_CLEAR;
  6540. }
  6541. M68KMAKE_OP(or, 8, er, .)
  6542. {
  6543. uint res = MASK_OUT_ABOVE_8((DX |= M68KMAKE_GET_OPER_AY_8));
  6544. FLAG_N = NFLAG_8(res);
  6545. FLAG_Z = res;
  6546. FLAG_C = CFLAG_CLEAR;
  6547. FLAG_V = VFLAG_CLEAR;
  6548. }
  6549. M68KMAKE_OP(or, 16, er, d)
  6550. {
  6551. uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY)));
  6552. FLAG_N = NFLAG_16(res);
  6553. FLAG_Z = res;
  6554. FLAG_C = CFLAG_CLEAR;
  6555. FLAG_V = VFLAG_CLEAR;
  6556. }
  6557. M68KMAKE_OP(or, 16, er, .)
  6558. {
  6559. uint res = MASK_OUT_ABOVE_16((DX |= M68KMAKE_GET_OPER_AY_16));
  6560. FLAG_N = NFLAG_16(res);
  6561. FLAG_Z = res;
  6562. FLAG_C = CFLAG_CLEAR;
  6563. FLAG_V = VFLAG_CLEAR;
  6564. }
  6565. M68KMAKE_OP(or, 32, er, d)
  6566. {
  6567. uint res = DX |= DY;
  6568. FLAG_N = NFLAG_32(res);
  6569. FLAG_Z = res;
  6570. FLAG_C = CFLAG_CLEAR;
  6571. FLAG_V = VFLAG_CLEAR;
  6572. }
  6573. M68KMAKE_OP(or, 32, er, .)
  6574. {
  6575. uint res = DX |= M68KMAKE_GET_OPER_AY_32;
  6576. FLAG_N = NFLAG_32(res);
  6577. FLAG_Z = res;
  6578. FLAG_C = CFLAG_CLEAR;
  6579. FLAG_V = VFLAG_CLEAR;
  6580. }
  6581. M68KMAKE_OP(or, 8, re, .)
  6582. {
  6583. uint ea = M68KMAKE_GET_EA_AY_8;
  6584. uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
  6585. m68ki_write_8(ea, res);
  6586. FLAG_N = NFLAG_8(res);
  6587. FLAG_Z = res;
  6588. FLAG_C = CFLAG_CLEAR;
  6589. FLAG_V = VFLAG_CLEAR;
  6590. }
  6591. M68KMAKE_OP(or, 16, re, .)
  6592. {
  6593. uint ea = M68KMAKE_GET_EA_AY_16;
  6594. uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
  6595. m68ki_write_16(ea, res);
  6596. FLAG_N = NFLAG_16(res);
  6597. FLAG_Z = res;
  6598. FLAG_C = CFLAG_CLEAR;
  6599. FLAG_V = VFLAG_CLEAR;
  6600. }
  6601. M68KMAKE_OP(or, 32, re, .)
  6602. {
  6603. uint ea = M68KMAKE_GET_EA_AY_32;
  6604. uint res = DX | m68ki_read_32(ea);
  6605. m68ki_write_32(ea, res);
  6606. FLAG_N = NFLAG_32(res);
  6607. FLAG_Z = res;
  6608. FLAG_C = CFLAG_CLEAR;
  6609. FLAG_V = VFLAG_CLEAR;
  6610. }
  6611. M68KMAKE_OP(ori, 8, ., d)
  6612. {
  6613. uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8()));
  6614. FLAG_N = NFLAG_8(res);
  6615. FLAG_Z = res;
  6616. FLAG_C = CFLAG_CLEAR;
  6617. FLAG_V = VFLAG_CLEAR;
  6618. }
  6619. M68KMAKE_OP(ori, 8, ., .)
  6620. {
  6621. uint src = OPER_I_8();
  6622. uint ea = M68KMAKE_GET_EA_AY_8;
  6623. uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
  6624. m68ki_write_8(ea, res);
  6625. FLAG_N = NFLAG_8(res);
  6626. FLAG_Z = res;
  6627. FLAG_C = CFLAG_CLEAR;
  6628. FLAG_V = VFLAG_CLEAR;
  6629. }
  6630. M68KMAKE_OP(ori, 16, ., d)
  6631. {
  6632. uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16());
  6633. FLAG_N = NFLAG_16(res);
  6634. FLAG_Z = res;
  6635. FLAG_C = CFLAG_CLEAR;
  6636. FLAG_V = VFLAG_CLEAR;
  6637. }
  6638. M68KMAKE_OP(ori, 16, ., .)
  6639. {
  6640. uint src = OPER_I_16();
  6641. uint ea = M68KMAKE_GET_EA_AY_16;
  6642. uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
  6643. m68ki_write_16(ea, res);
  6644. FLAG_N = NFLAG_16(res);
  6645. FLAG_Z = res;
  6646. FLAG_C = CFLAG_CLEAR;
  6647. FLAG_V = VFLAG_CLEAR;
  6648. }
  6649. M68KMAKE_OP(ori, 32, ., d)
  6650. {
  6651. uint res = DY |= OPER_I_32();
  6652. FLAG_N = NFLAG_32(res);
  6653. FLAG_Z = res;
  6654. FLAG_C = CFLAG_CLEAR;
  6655. FLAG_V = VFLAG_CLEAR;
  6656. }
  6657. M68KMAKE_OP(ori, 32, ., .)
  6658. {
  6659. uint src = OPER_I_32();
  6660. uint ea = M68KMAKE_GET_EA_AY_32;
  6661. uint res = src | m68ki_read_32(ea);
  6662. m68ki_write_32(ea, res);
  6663. FLAG_N = NFLAG_32(res);
  6664. FLAG_Z = res;
  6665. FLAG_C = CFLAG_CLEAR;
  6666. FLAG_V = VFLAG_CLEAR;
  6667. }
  6668. M68KMAKE_OP(ori, 16, toc, .)
  6669. {
  6670. m68ki_set_ccr(m68ki_get_ccr() | OPER_I_16());
  6671. }
  6672. M68KMAKE_OP(ori, 16, tos, .)
  6673. {
  6674. if(FLAG_S)
  6675. {
  6676. uint src = OPER_I_16();
  6677. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  6678. m68ki_set_sr(m68ki_get_sr() | src);
  6679. return;
  6680. }
  6681. m68ki_exception_privilege_violation();
  6682. }
  6683. M68KMAKE_OP(pack, 16, rr, .)
  6684. {
  6685. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  6686. {
  6687. /* Note: DX and DY are reversed in Motorola's docs */
  6688. uint src = DY + OPER_I_16();
  6689. uint* r_dst = &DX;
  6690. *r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f);
  6691. return;
  6692. }
  6693. m68ki_exception_illegal();
  6694. }
  6695. M68KMAKE_OP(pack, 16, mm, ax7)
  6696. {
  6697. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  6698. {
  6699. /* Note: AX and AY are reversed in Motorola's docs */
  6700. uint ea_src = EA_AY_PD_8();
  6701. uint src = m68ki_read_8(ea_src);
  6702. ea_src = EA_AY_PD_8();
  6703. src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
  6704. m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
  6705. return;
  6706. }
  6707. m68ki_exception_illegal();
  6708. }
  6709. M68KMAKE_OP(pack, 16, mm, ay7)
  6710. {
  6711. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  6712. {
  6713. /* Note: AX and AY are reversed in Motorola's docs */
  6714. uint ea_src = EA_A7_PD_8();
  6715. uint src = m68ki_read_8(ea_src);
  6716. ea_src = EA_A7_PD_8();
  6717. src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
  6718. m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
  6719. return;
  6720. }
  6721. m68ki_exception_illegal();
  6722. }
  6723. M68KMAKE_OP(pack, 16, mm, axy7)
  6724. {
  6725. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  6726. {
  6727. uint ea_src = EA_A7_PD_8();
  6728. uint src = m68ki_read_8(ea_src);
  6729. ea_src = EA_A7_PD_8();
  6730. src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
  6731. m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
  6732. return;
  6733. }
  6734. m68ki_exception_illegal();
  6735. }
  6736. M68KMAKE_OP(pack, 16, mm, .)
  6737. {
  6738. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  6739. {
  6740. /* Note: AX and AY are reversed in Motorola's docs */
  6741. uint ea_src = EA_AY_PD_8();
  6742. uint src = m68ki_read_8(ea_src);
  6743. ea_src = EA_AY_PD_8();
  6744. src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
  6745. m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
  6746. return;
  6747. }
  6748. m68ki_exception_illegal();
  6749. }
  6750. M68KMAKE_OP(pea, 32, ., .)
  6751. {
  6752. uint ea = M68KMAKE_GET_EA_AY_32;
  6753. m68ki_push_32(ea);
  6754. }
  6755. M68KMAKE_OP(pflush, 32, ., .)
  6756. {
  6757. if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
  6758. {
  6759. // Nothing to do, unless address translation cache is emulated
  6760. return;
  6761. }
  6762. m68ki_exception_illegal();
  6763. }
  6764. M68KMAKE_OP(reset, 0, ., .)
  6765. {
  6766. if(FLAG_S)
  6767. {
  6768. m68ki_output_reset(); /* auto-disable (see m68kcpu.h) */
  6769. USE_CYCLES(CYC_RESET);
  6770. return;
  6771. }
  6772. m68ki_exception_privilege_violation();
  6773. }
  6774. M68KMAKE_OP(ror, 8, s, .)
  6775. {
  6776. uint* r_dst = &DY;
  6777. uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
  6778. uint shift = orig_shift & 7;
  6779. uint src = MASK_OUT_ABOVE_8(*r_dst);
  6780. uint res = ROR_8(src, shift);
  6781. if(orig_shift != 0)
  6782. USE_CYCLES(orig_shift<<CYC_SHIFT);
  6783. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  6784. FLAG_N = NFLAG_8(res);
  6785. FLAG_Z = res;
  6786. FLAG_C = src << (9-orig_shift);
  6787. FLAG_V = VFLAG_CLEAR;
  6788. }
  6789. M68KMAKE_OP(ror, 16, s, .)
  6790. {
  6791. uint* r_dst = &DY;
  6792. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  6793. uint src = MASK_OUT_ABOVE_16(*r_dst);
  6794. uint res = ROR_16(src, shift);
  6795. if(shift != 0)
  6796. USE_CYCLES(shift<<CYC_SHIFT);
  6797. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  6798. FLAG_N = NFLAG_16(res);
  6799. FLAG_Z = res;
  6800. FLAG_C = src << (9-shift);
  6801. FLAG_V = VFLAG_CLEAR;
  6802. }
  6803. M68KMAKE_OP(ror, 32, s, .)
  6804. {
  6805. uint* r_dst = &DY;
  6806. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  6807. uint64 src = *r_dst;
  6808. uint res = ROR_32(src, shift);
  6809. if(shift != 0)
  6810. USE_CYCLES(shift<<CYC_SHIFT);
  6811. *r_dst = res;
  6812. FLAG_N = NFLAG_32(res);
  6813. FLAG_Z = res;
  6814. FLAG_C = src << (9-shift);
  6815. FLAG_V = VFLAG_CLEAR;
  6816. }
  6817. M68KMAKE_OP(ror, 8, r, .)
  6818. {
  6819. uint* r_dst = &DY;
  6820. uint orig_shift = DX & 0x3f;
  6821. uint shift = orig_shift & 7;
  6822. uint src = MASK_OUT_ABOVE_8(*r_dst);
  6823. uint res = ROR_8(src, shift);
  6824. if(orig_shift != 0)
  6825. {
  6826. USE_CYCLES(orig_shift<<CYC_SHIFT);
  6827. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  6828. FLAG_C = src << (8-((shift-1)&7));
  6829. FLAG_N = NFLAG_8(res);
  6830. FLAG_Z = res;
  6831. FLAG_V = VFLAG_CLEAR;
  6832. return;
  6833. }
  6834. FLAG_C = CFLAG_CLEAR;
  6835. FLAG_N = NFLAG_8(src);
  6836. FLAG_Z = src;
  6837. FLAG_V = VFLAG_CLEAR;
  6838. }
  6839. M68KMAKE_OP(ror, 16, r, .)
  6840. {
  6841. uint* r_dst = &DY;
  6842. uint orig_shift = DX & 0x3f;
  6843. uint shift = orig_shift & 15;
  6844. uint src = MASK_OUT_ABOVE_16(*r_dst);
  6845. uint res = ROR_16(src, shift);
  6846. if(orig_shift != 0)
  6847. {
  6848. USE_CYCLES(orig_shift<<CYC_SHIFT);
  6849. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  6850. FLAG_C = (src >> ((shift - 1) & 15)) << 8;
  6851. FLAG_N = NFLAG_16(res);
  6852. FLAG_Z = res;
  6853. FLAG_V = VFLAG_CLEAR;
  6854. return;
  6855. }
  6856. FLAG_C = CFLAG_CLEAR;
  6857. FLAG_N = NFLAG_16(src);
  6858. FLAG_Z = src;
  6859. FLAG_V = VFLAG_CLEAR;
  6860. }
  6861. M68KMAKE_OP(ror, 32, r, .)
  6862. {
  6863. uint* r_dst = &DY;
  6864. uint orig_shift = DX & 0x3f;
  6865. uint shift = orig_shift & 31;
  6866. uint64 src = *r_dst;
  6867. uint res = ROR_32(src, shift);
  6868. if(orig_shift != 0)
  6869. {
  6870. USE_CYCLES(orig_shift<<CYC_SHIFT);
  6871. *r_dst = res;
  6872. FLAG_C = (src >> ((shift - 1) & 31)) << 8;
  6873. FLAG_N = NFLAG_32(res);
  6874. FLAG_Z = res;
  6875. FLAG_V = VFLAG_CLEAR;
  6876. return;
  6877. }
  6878. FLAG_C = CFLAG_CLEAR;
  6879. FLAG_N = NFLAG_32(src);
  6880. FLAG_Z = src;
  6881. FLAG_V = VFLAG_CLEAR;
  6882. }
  6883. M68KMAKE_OP(ror, 16, ., .)
  6884. {
  6885. uint ea = M68KMAKE_GET_EA_AY_16;
  6886. uint src = m68ki_read_16(ea);
  6887. uint res = ROR_16(src, 1);
  6888. m68ki_write_16(ea, res);
  6889. FLAG_N = NFLAG_16(res);
  6890. FLAG_Z = res;
  6891. FLAG_C = src << 8;
  6892. FLAG_V = VFLAG_CLEAR;
  6893. }
  6894. M68KMAKE_OP(rol, 8, s, .)
  6895. {
  6896. uint* r_dst = &DY;
  6897. uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
  6898. uint shift = orig_shift & 7;
  6899. uint src = MASK_OUT_ABOVE_8(*r_dst);
  6900. uint res = ROL_8(src, shift);
  6901. if(orig_shift != 0)
  6902. USE_CYCLES(orig_shift<<CYC_SHIFT);
  6903. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  6904. FLAG_N = NFLAG_8(res);
  6905. FLAG_Z = res;
  6906. FLAG_C = src << orig_shift;
  6907. FLAG_V = VFLAG_CLEAR;
  6908. }
  6909. M68KMAKE_OP(rol, 16, s, .)
  6910. {
  6911. uint* r_dst = &DY;
  6912. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  6913. uint src = MASK_OUT_ABOVE_16(*r_dst);
  6914. uint res = ROL_16(src, shift);
  6915. if(shift != 0)
  6916. USE_CYCLES(shift<<CYC_SHIFT);
  6917. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  6918. FLAG_N = NFLAG_16(res);
  6919. FLAG_Z = res;
  6920. FLAG_C = src >> (8-shift);
  6921. FLAG_V = VFLAG_CLEAR;
  6922. }
  6923. M68KMAKE_OP(rol, 32, s, .)
  6924. {
  6925. uint* r_dst = &DY;
  6926. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  6927. uint64 src = *r_dst;
  6928. uint res = ROL_32(src, shift);
  6929. if(shift != 0)
  6930. USE_CYCLES(shift<<CYC_SHIFT);
  6931. *r_dst = res;
  6932. FLAG_N = NFLAG_32(res);
  6933. FLAG_Z = res;
  6934. FLAG_C = src >> (24-shift);
  6935. FLAG_V = VFLAG_CLEAR;
  6936. }
  6937. M68KMAKE_OP(rol, 8, r, .)
  6938. {
  6939. uint* r_dst = &DY;
  6940. uint orig_shift = DX & 0x3f;
  6941. uint shift = orig_shift & 7;
  6942. uint src = MASK_OUT_ABOVE_8(*r_dst);
  6943. uint res = ROL_8(src, shift);
  6944. if(orig_shift != 0)
  6945. {
  6946. USE_CYCLES(orig_shift<<CYC_SHIFT);
  6947. if(shift != 0)
  6948. {
  6949. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  6950. FLAG_C = src << shift;
  6951. FLAG_N = NFLAG_8(res);
  6952. FLAG_Z = res;
  6953. FLAG_V = VFLAG_CLEAR;
  6954. return;
  6955. }
  6956. FLAG_C = (src & 1)<<8;
  6957. FLAG_N = NFLAG_8(src);
  6958. FLAG_Z = src;
  6959. FLAG_V = VFLAG_CLEAR;
  6960. return;
  6961. }
  6962. FLAG_C = CFLAG_CLEAR;
  6963. FLAG_N = NFLAG_8(src);
  6964. FLAG_Z = src;
  6965. FLAG_V = VFLAG_CLEAR;
  6966. }
  6967. M68KMAKE_OP(rol, 16, r, .)
  6968. {
  6969. uint* r_dst = &DY;
  6970. uint orig_shift = DX & 0x3f;
  6971. uint shift = orig_shift & 15;
  6972. uint src = MASK_OUT_ABOVE_16(*r_dst);
  6973. uint res = MASK_OUT_ABOVE_16(ROL_16(src, shift));
  6974. if(orig_shift != 0)
  6975. {
  6976. USE_CYCLES(orig_shift<<CYC_SHIFT);
  6977. if(shift != 0)
  6978. {
  6979. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  6980. FLAG_C = (src << shift) >> 8;
  6981. FLAG_N = NFLAG_16(res);
  6982. FLAG_Z = res;
  6983. FLAG_V = VFLAG_CLEAR;
  6984. return;
  6985. }
  6986. FLAG_C = (src & 1)<<8;
  6987. FLAG_N = NFLAG_16(src);
  6988. FLAG_Z = src;
  6989. FLAG_V = VFLAG_CLEAR;
  6990. return;
  6991. }
  6992. FLAG_C = CFLAG_CLEAR;
  6993. FLAG_N = NFLAG_16(src);
  6994. FLAG_Z = src;
  6995. FLAG_V = VFLAG_CLEAR;
  6996. }
  6997. M68KMAKE_OP(rol, 32, r, .)
  6998. {
  6999. uint* r_dst = &DY;
  7000. uint orig_shift = DX & 0x3f;
  7001. uint shift = orig_shift & 31;
  7002. uint64 src = *r_dst;
  7003. uint res = ROL_32(src, shift);
  7004. if(orig_shift != 0)
  7005. {
  7006. USE_CYCLES(orig_shift<<CYC_SHIFT);
  7007. *r_dst = res;
  7008. FLAG_C = (src >> ((32 - shift) & 0x1f)) << 8;
  7009. FLAG_N = NFLAG_32(res);
  7010. FLAG_Z = res;
  7011. FLAG_V = VFLAG_CLEAR;
  7012. return;
  7013. }
  7014. FLAG_C = CFLAG_CLEAR;
  7015. FLAG_N = NFLAG_32(src);
  7016. FLAG_Z = src;
  7017. FLAG_V = VFLAG_CLEAR;
  7018. }
  7019. M68KMAKE_OP(rol, 16, ., .)
  7020. {
  7021. uint ea = M68KMAKE_GET_EA_AY_16;
  7022. uint src = m68ki_read_16(ea);
  7023. uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
  7024. m68ki_write_16(ea, res);
  7025. FLAG_N = NFLAG_16(res);
  7026. FLAG_Z = res;
  7027. FLAG_C = src >> 7;
  7028. FLAG_V = VFLAG_CLEAR;
  7029. }
  7030. M68KMAKE_OP(roxr, 8, s, .)
  7031. {
  7032. uint* r_dst = &DY;
  7033. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  7034. uint src = MASK_OUT_ABOVE_8(*r_dst);
  7035. uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
  7036. if(shift != 0)
  7037. USE_CYCLES(shift<<CYC_SHIFT);
  7038. FLAG_C = FLAG_X = res;
  7039. res = MASK_OUT_ABOVE_8(res);
  7040. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  7041. FLAG_N = NFLAG_8(res);
  7042. FLAG_Z = res;
  7043. FLAG_V = VFLAG_CLEAR;
  7044. }
  7045. M68KMAKE_OP(roxr, 16, s, .)
  7046. {
  7047. uint* r_dst = &DY;
  7048. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  7049. uint src = MASK_OUT_ABOVE_16(*r_dst);
  7050. uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
  7051. if(shift != 0)
  7052. USE_CYCLES(shift<<CYC_SHIFT);
  7053. FLAG_C = FLAG_X = res >> 8;
  7054. res = MASK_OUT_ABOVE_16(res);
  7055. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  7056. FLAG_N = NFLAG_16(res);
  7057. FLAG_Z = res;
  7058. FLAG_V = VFLAG_CLEAR;
  7059. }
  7060. M68KMAKE_OP(roxr, 32, s, .)
  7061. {
  7062. #if M68K_USE_64_BIT
  7063. uint* r_dst = &DY;
  7064. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  7065. uint64 src = *r_dst;
  7066. uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
  7067. if(shift != 0)
  7068. USE_CYCLES(shift<<CYC_SHIFT);
  7069. res = ROR_33_64(res, shift);
  7070. FLAG_C = FLAG_X = res >> 24;
  7071. res = MASK_OUT_ABOVE_32(res);
  7072. *r_dst = res;
  7073. FLAG_N = NFLAG_32(res);
  7074. FLAG_Z = res;
  7075. FLAG_V = VFLAG_CLEAR;
  7076. #else
  7077. uint* r_dst = &DY;
  7078. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  7079. uint src = *r_dst;
  7080. uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
  7081. uint new_x_flag = src & (1 << (shift - 1));
  7082. if(shift != 0)
  7083. USE_CYCLES(shift<<CYC_SHIFT);
  7084. *r_dst = res;
  7085. FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
  7086. FLAG_N = NFLAG_32(res);
  7087. FLAG_Z = res;
  7088. FLAG_V = VFLAG_CLEAR;
  7089. #endif
  7090. }
  7091. M68KMAKE_OP(roxr, 8, r, .)
  7092. {
  7093. uint* r_dst = &DY;
  7094. uint orig_shift = DX & 0x3f;
  7095. if(orig_shift != 0)
  7096. {
  7097. uint shift = orig_shift % 9;
  7098. uint src = MASK_OUT_ABOVE_8(*r_dst);
  7099. uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
  7100. USE_CYCLES(orig_shift<<CYC_SHIFT);
  7101. FLAG_C = FLAG_X = res;
  7102. res = MASK_OUT_ABOVE_8(res);
  7103. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  7104. FLAG_N = NFLAG_8(res);
  7105. FLAG_Z = res;
  7106. FLAG_V = VFLAG_CLEAR;
  7107. return;
  7108. }
  7109. FLAG_C = FLAG_X;
  7110. FLAG_N = NFLAG_8(*r_dst);
  7111. FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
  7112. FLAG_V = VFLAG_CLEAR;
  7113. }
  7114. M68KMAKE_OP(roxr, 16, r, .)
  7115. {
  7116. uint* r_dst = &DY;
  7117. uint orig_shift = DX & 0x3f;
  7118. if(orig_shift != 0)
  7119. {
  7120. uint shift = orig_shift % 17;
  7121. uint src = MASK_OUT_ABOVE_16(*r_dst);
  7122. uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
  7123. USE_CYCLES(orig_shift<<CYC_SHIFT);
  7124. FLAG_C = FLAG_X = res >> 8;
  7125. res = MASK_OUT_ABOVE_16(res);
  7126. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  7127. FLAG_N = NFLAG_16(res);
  7128. FLAG_Z = res;
  7129. FLAG_V = VFLAG_CLEAR;
  7130. return;
  7131. }
  7132. FLAG_C = FLAG_X;
  7133. FLAG_N = NFLAG_16(*r_dst);
  7134. FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
  7135. FLAG_V = VFLAG_CLEAR;
  7136. }
  7137. M68KMAKE_OP(roxr, 32, r, .)
  7138. {
  7139. #if M68K_USE_64_BIT
  7140. uint* r_dst = &DY;
  7141. uint orig_shift = DX & 0x3f;
  7142. if(orig_shift != 0)
  7143. {
  7144. uint shift = orig_shift % 33;
  7145. uint64 src = *r_dst;
  7146. uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
  7147. res = ROR_33_64(res, shift);
  7148. USE_CYCLES(orig_shift<<CYC_SHIFT);
  7149. FLAG_C = FLAG_X = res >> 24;
  7150. res = MASK_OUT_ABOVE_32(res);
  7151. *r_dst = res;
  7152. FLAG_N = NFLAG_32(res);
  7153. FLAG_Z = res;
  7154. FLAG_V = VFLAG_CLEAR;
  7155. return;
  7156. }
  7157. FLAG_C = FLAG_X;
  7158. FLAG_N = NFLAG_32(*r_dst);
  7159. FLAG_Z = *r_dst;
  7160. FLAG_V = VFLAG_CLEAR;
  7161. #else
  7162. uint* r_dst = &DY;
  7163. uint orig_shift = DX & 0x3f;
  7164. uint shift = orig_shift % 33;
  7165. uint src = *r_dst;
  7166. uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
  7167. uint new_x_flag = src & (1 << (shift - 1));
  7168. if(orig_shift != 0)
  7169. USE_CYCLES(orig_shift<<CYC_SHIFT);
  7170. if(shift != 0)
  7171. {
  7172. *r_dst = res;
  7173. FLAG_X = (new_x_flag != 0)<<8;
  7174. }
  7175. else
  7176. res = src;
  7177. FLAG_C = FLAG_X;
  7178. FLAG_N = NFLAG_32(res);
  7179. FLAG_Z = res;
  7180. FLAG_V = VFLAG_CLEAR;
  7181. #endif
  7182. }
  7183. M68KMAKE_OP(roxr, 16, ., .)
  7184. {
  7185. uint ea = M68KMAKE_GET_EA_AY_16;
  7186. uint src = m68ki_read_16(ea);
  7187. uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
  7188. FLAG_C = FLAG_X = res >> 8;
  7189. res = MASK_OUT_ABOVE_16(res);
  7190. m68ki_write_16(ea, res);
  7191. FLAG_N = NFLAG_16(res);
  7192. FLAG_Z = res;
  7193. FLAG_V = VFLAG_CLEAR;
  7194. }
  7195. M68KMAKE_OP(roxl, 8, s, .)
  7196. {
  7197. uint* r_dst = &DY;
  7198. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  7199. uint src = MASK_OUT_ABOVE_8(*r_dst);
  7200. uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
  7201. if(shift != 0)
  7202. USE_CYCLES(shift<<CYC_SHIFT);
  7203. FLAG_C = FLAG_X = res;
  7204. res = MASK_OUT_ABOVE_8(res);
  7205. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  7206. FLAG_N = NFLAG_8(res);
  7207. FLAG_Z = res;
  7208. FLAG_V = VFLAG_CLEAR;
  7209. }
  7210. M68KMAKE_OP(roxl, 16, s, .)
  7211. {
  7212. uint* r_dst = &DY;
  7213. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  7214. uint src = MASK_OUT_ABOVE_16(*r_dst);
  7215. uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
  7216. if(shift != 0)
  7217. USE_CYCLES(shift<<CYC_SHIFT);
  7218. FLAG_C = FLAG_X = res >> 8;
  7219. res = MASK_OUT_ABOVE_16(res);
  7220. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  7221. FLAG_N = NFLAG_16(res);
  7222. FLAG_Z = res;
  7223. FLAG_V = VFLAG_CLEAR;
  7224. }
  7225. M68KMAKE_OP(roxl, 32, s, .)
  7226. {
  7227. #if M68K_USE_64_BIT
  7228. uint* r_dst = &DY;
  7229. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  7230. uint64 src = *r_dst;
  7231. uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
  7232. if(shift != 0)
  7233. USE_CYCLES(shift<<CYC_SHIFT);
  7234. res = ROL_33_64(res, shift);
  7235. FLAG_C = FLAG_X = res >> 24;
  7236. res = MASK_OUT_ABOVE_32(res);
  7237. *r_dst = res;
  7238. FLAG_N = NFLAG_32(res);
  7239. FLAG_Z = res;
  7240. FLAG_V = VFLAG_CLEAR;
  7241. #else
  7242. uint* r_dst = &DY;
  7243. uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
  7244. uint src = *r_dst;
  7245. uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
  7246. uint new_x_flag = src & (1 << (32 - shift));
  7247. if(shift != 0)
  7248. USE_CYCLES(shift<<CYC_SHIFT);
  7249. *r_dst = res;
  7250. FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
  7251. FLAG_N = NFLAG_32(res);
  7252. FLAG_Z = res;
  7253. FLAG_V = VFLAG_CLEAR;
  7254. #endif
  7255. }
  7256. M68KMAKE_OP(roxl, 8, r, .)
  7257. {
  7258. uint* r_dst = &DY;
  7259. uint orig_shift = DX & 0x3f;
  7260. if(orig_shift != 0)
  7261. {
  7262. uint shift = orig_shift % 9;
  7263. uint src = MASK_OUT_ABOVE_8(*r_dst);
  7264. uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
  7265. USE_CYCLES(orig_shift<<CYC_SHIFT);
  7266. FLAG_C = FLAG_X = res;
  7267. res = MASK_OUT_ABOVE_8(res);
  7268. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  7269. FLAG_N = NFLAG_8(res);
  7270. FLAG_Z = res;
  7271. FLAG_V = VFLAG_CLEAR;
  7272. return;
  7273. }
  7274. FLAG_C = FLAG_X;
  7275. FLAG_N = NFLAG_8(*r_dst);
  7276. FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
  7277. FLAG_V = VFLAG_CLEAR;
  7278. }
  7279. M68KMAKE_OP(roxl, 16, r, .)
  7280. {
  7281. uint* r_dst = &DY;
  7282. uint orig_shift = DX & 0x3f;
  7283. if(orig_shift != 0)
  7284. {
  7285. uint shift = orig_shift % 17;
  7286. uint src = MASK_OUT_ABOVE_16(*r_dst);
  7287. uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
  7288. USE_CYCLES(orig_shift<<CYC_SHIFT);
  7289. FLAG_C = FLAG_X = res >> 8;
  7290. res = MASK_OUT_ABOVE_16(res);
  7291. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  7292. FLAG_N = NFLAG_16(res);
  7293. FLAG_Z = res;
  7294. FLAG_V = VFLAG_CLEAR;
  7295. return;
  7296. }
  7297. FLAG_C = FLAG_X;
  7298. FLAG_N = NFLAG_16(*r_dst);
  7299. FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
  7300. FLAG_V = VFLAG_CLEAR;
  7301. }
  7302. M68KMAKE_OP(roxl, 32, r, .)
  7303. {
  7304. #if M68K_USE_64_BIT
  7305. uint* r_dst = &DY;
  7306. uint orig_shift = DX & 0x3f;
  7307. if(orig_shift != 0)
  7308. {
  7309. uint shift = orig_shift % 33;
  7310. uint64 src = *r_dst;
  7311. uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
  7312. res = ROL_33_64(res, shift);
  7313. USE_CYCLES(orig_shift<<CYC_SHIFT);
  7314. FLAG_C = FLAG_X = res >> 24;
  7315. res = MASK_OUT_ABOVE_32(res);
  7316. *r_dst = res;
  7317. FLAG_N = NFLAG_32(res);
  7318. FLAG_Z = res;
  7319. FLAG_V = VFLAG_CLEAR;
  7320. return;
  7321. }
  7322. FLAG_C = FLAG_X;
  7323. FLAG_N = NFLAG_32(*r_dst);
  7324. FLAG_Z = *r_dst;
  7325. FLAG_V = VFLAG_CLEAR;
  7326. #else
  7327. uint* r_dst = &DY;
  7328. uint orig_shift = DX & 0x3f;
  7329. uint shift = orig_shift % 33;
  7330. uint src = *r_dst;
  7331. uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
  7332. uint new_x_flag = src & (1 << (32 - shift));
  7333. if(orig_shift != 0)
  7334. USE_CYCLES(orig_shift<<CYC_SHIFT);
  7335. if(shift != 0)
  7336. {
  7337. *r_dst = res;
  7338. FLAG_X = (new_x_flag != 0)<<8;
  7339. }
  7340. else
  7341. res = src;
  7342. FLAG_C = FLAG_X;
  7343. FLAG_N = NFLAG_32(res);
  7344. FLAG_Z = res;
  7345. FLAG_V = VFLAG_CLEAR;
  7346. #endif
  7347. }
  7348. M68KMAKE_OP(roxl, 16, ., .)
  7349. {
  7350. uint ea = M68KMAKE_GET_EA_AY_16;
  7351. uint src = m68ki_read_16(ea);
  7352. uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
  7353. FLAG_C = FLAG_X = res >> 8;
  7354. res = MASK_OUT_ABOVE_16(res);
  7355. m68ki_write_16(ea, res);
  7356. FLAG_N = NFLAG_16(res);
  7357. FLAG_Z = res;
  7358. FLAG_V = VFLAG_CLEAR;
  7359. }
  7360. M68KMAKE_OP(rtd, 32, ., .)
  7361. {
  7362. if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
  7363. {
  7364. uint new_pc = m68ki_pull_32();
  7365. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  7366. REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
  7367. m68ki_jump(new_pc);
  7368. return;
  7369. }
  7370. m68ki_exception_illegal();
  7371. }
  7372. M68KMAKE_OP(rte, 32, ., .)
  7373. {
  7374. if(FLAG_S)
  7375. {
  7376. uint new_sr;
  7377. uint new_pc;
  7378. uint format_word;
  7379. m68ki_rte_callback(); /* auto-disable (see m68kcpu.h) */
  7380. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  7381. if(CPU_TYPE_IS_000(CPU_TYPE))
  7382. {
  7383. new_sr = m68ki_pull_16();
  7384. new_pc = m68ki_pull_32();
  7385. m68ki_jump(new_pc);
  7386. m68ki_set_sr(new_sr);
  7387. CPU_INSTR_MODE = INSTRUCTION_YES;
  7388. CPU_RUN_MODE = RUN_MODE_NORMAL;
  7389. return;
  7390. }
  7391. if(CPU_TYPE_IS_010(CPU_TYPE))
  7392. {
  7393. format_word = m68ki_read_16(REG_A[7]+6) >> 12;
  7394. if(format_word == 0)
  7395. {
  7396. new_sr = m68ki_pull_16();
  7397. new_pc = m68ki_pull_32();
  7398. m68ki_fake_pull_16(); /* format word */
  7399. m68ki_jump(new_pc);
  7400. m68ki_set_sr(new_sr);
  7401. CPU_INSTR_MODE = INSTRUCTION_YES;
  7402. CPU_RUN_MODE = RUN_MODE_NORMAL;
  7403. return;
  7404. }
  7405. CPU_INSTR_MODE = INSTRUCTION_YES;
  7406. CPU_RUN_MODE = RUN_MODE_NORMAL;
  7407. /* Not handling bus fault (9) */
  7408. m68ki_exception_format_error();
  7409. return;
  7410. }
  7411. /* Otherwise it's 020 */
  7412. rte_loop:
  7413. format_word = m68ki_read_16(REG_A[7]+6) >> 12;
  7414. switch(format_word)
  7415. {
  7416. case 0: /* Normal */
  7417. new_sr = m68ki_pull_16();
  7418. new_pc = m68ki_pull_32();
  7419. m68ki_fake_pull_16(); /* format word */
  7420. m68ki_jump(new_pc);
  7421. m68ki_set_sr(new_sr);
  7422. CPU_INSTR_MODE = INSTRUCTION_YES;
  7423. CPU_RUN_MODE = RUN_MODE_NORMAL;
  7424. return;
  7425. case 1: /* Throwaway */
  7426. new_sr = m68ki_pull_16();
  7427. m68ki_fake_pull_32(); /* program counter */
  7428. m68ki_fake_pull_16(); /* format word */
  7429. m68ki_set_sr_noint(new_sr);
  7430. goto rte_loop;
  7431. case 2: /* Trap */
  7432. new_sr = m68ki_pull_16();
  7433. new_pc = m68ki_pull_32();
  7434. m68ki_fake_pull_16(); /* format word */
  7435. m68ki_fake_pull_32(); /* address */
  7436. m68ki_jump(new_pc);
  7437. m68ki_set_sr(new_sr);
  7438. CPU_INSTR_MODE = INSTRUCTION_YES;
  7439. CPU_RUN_MODE = RUN_MODE_NORMAL;
  7440. return;
  7441. }
  7442. /* Not handling long or short bus fault */
  7443. CPU_INSTR_MODE = INSTRUCTION_YES;
  7444. CPU_RUN_MODE = RUN_MODE_NORMAL;
  7445. m68ki_exception_format_error();
  7446. return;
  7447. }
  7448. m68ki_exception_privilege_violation();
  7449. }
  7450. M68KMAKE_OP(rtm, 32, ., .)
  7451. {
  7452. if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
  7453. {
  7454. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  7455. M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
  7456. m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
  7457. m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
  7458. return;
  7459. }
  7460. m68ki_exception_illegal();
  7461. }
  7462. M68KMAKE_OP(rtr, 32, ., .)
  7463. {
  7464. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  7465. m68ki_set_ccr(m68ki_pull_16());
  7466. m68ki_jump(m68ki_pull_32());
  7467. }
  7468. M68KMAKE_OP(rts, 32, ., .)
  7469. {
  7470. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  7471. m68ki_jump(m68ki_pull_32());
  7472. }
  7473. M68KMAKE_OP(sbcd, 8, rr, .)
  7474. {
  7475. uint* r_dst = &DX;
  7476. uint src = DY;
  7477. uint dst = *r_dst;
  7478. uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
  7479. // FLAG_V = ~res; /* Undefined V behavior */
  7480. FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to assume cleared. */
  7481. if(res > 9)
  7482. res -= 6;
  7483. res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
  7484. if(res > 0x99)
  7485. {
  7486. res += 0xa0;
  7487. FLAG_X = FLAG_C = CFLAG_SET;
  7488. FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */
  7489. }
  7490. else
  7491. FLAG_N = FLAG_X = FLAG_C = 0;
  7492. res = MASK_OUT_ABOVE_8(res);
  7493. // FLAG_V &= res; /* Undefined V behavior part II */
  7494. // FLAG_N = NFLAG_8(res); /* Undefined N behavior */
  7495. FLAG_Z |= res;
  7496. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  7497. }
  7498. M68KMAKE_OP(sbcd, 8, mm, ax7)
  7499. {
  7500. uint src = OPER_AY_PD_8();
  7501. uint ea = EA_A7_PD_8();
  7502. uint dst = m68ki_read_8(ea);
  7503. uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
  7504. // FLAG_V = ~res; /* Undefined V behavior */
  7505. FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */
  7506. if(res > 9)
  7507. res -= 6;
  7508. res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
  7509. if(res > 0x99)
  7510. {
  7511. res += 0xa0;
  7512. FLAG_X = FLAG_C = CFLAG_SET;
  7513. FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */
  7514. }
  7515. else
  7516. FLAG_N = FLAG_X = FLAG_C = 0;
  7517. res = MASK_OUT_ABOVE_8(res);
  7518. // FLAG_V &= res; /* Undefined V behavior part II */
  7519. // FLAG_N = NFLAG_8(res); /* Undefined N behavior */
  7520. FLAG_Z |= res;
  7521. m68ki_write_8(ea, res);
  7522. }
  7523. M68KMAKE_OP(sbcd, 8, mm, ay7)
  7524. {
  7525. uint src = OPER_A7_PD_8();
  7526. uint ea = EA_AX_PD_8();
  7527. uint dst = m68ki_read_8(ea);
  7528. uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
  7529. // FLAG_V = ~res; /* Undefined V behavior */
  7530. FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */
  7531. if(res > 9)
  7532. res -= 6;
  7533. res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
  7534. if(res > 0x99)
  7535. {
  7536. res += 0xa0;
  7537. FLAG_X = FLAG_C = CFLAG_SET;
  7538. FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */
  7539. }
  7540. else
  7541. FLAG_N = FLAG_X = FLAG_C = 0;
  7542. res = MASK_OUT_ABOVE_8(res);
  7543. // FLAG_V &= res; /* Undefined V behavior part II */
  7544. // FLAG_N = NFLAG_8(res); /* Undefined N behavior */
  7545. FLAG_Z |= res;
  7546. m68ki_write_8(ea, res);
  7547. }
  7548. M68KMAKE_OP(sbcd, 8, mm, axy7)
  7549. {
  7550. uint src = OPER_A7_PD_8();
  7551. uint ea = EA_A7_PD_8();
  7552. uint dst = m68ki_read_8(ea);
  7553. uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
  7554. // FLAG_V = ~res; /* Undefined V behavior */
  7555. FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */
  7556. if(res > 9)
  7557. res -= 6;
  7558. res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
  7559. if(res > 0x99)
  7560. {
  7561. res += 0xa0;
  7562. FLAG_X = FLAG_C = CFLAG_SET;
  7563. FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */
  7564. }
  7565. else
  7566. FLAG_N = FLAG_X = FLAG_C = 0;
  7567. res = MASK_OUT_ABOVE_8(res);
  7568. // FLAG_V &= res; /* Undefined V behavior part II */
  7569. // FLAG_N = NFLAG_8(res); /* Undefined N behavior */
  7570. FLAG_Z |= res;
  7571. m68ki_write_8(ea, res);
  7572. }
  7573. M68KMAKE_OP(sbcd, 8, mm, .)
  7574. {
  7575. uint src = OPER_AY_PD_8();
  7576. uint ea = EA_AX_PD_8();
  7577. uint dst = m68ki_read_8(ea);
  7578. uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
  7579. // FLAG_V = ~res; /* Undefined V behavior */
  7580. FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */
  7581. if(res > 9)
  7582. res -= 6;
  7583. res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
  7584. if(res > 0x99)
  7585. {
  7586. res += 0xa0;
  7587. FLAG_X = FLAG_C = CFLAG_SET;
  7588. FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */
  7589. }
  7590. else
  7591. FLAG_N = FLAG_X = FLAG_C = 0;
  7592. res = MASK_OUT_ABOVE_8(res);
  7593. // FLAG_V &= res; /* Undefined V behavior part II */
  7594. // FLAG_N = NFLAG_8(res); /* Undefined N behavior */
  7595. FLAG_Z |= res;
  7596. m68ki_write_8(ea, res);
  7597. }
  7598. M68KMAKE_OP(st, 8, ., d)
  7599. {
  7600. DY |= 0xff;
  7601. }
  7602. M68KMAKE_OP(st, 8, ., .)
  7603. {
  7604. m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0xff);
  7605. }
  7606. M68KMAKE_OP(sf, 8, ., d)
  7607. {
  7608. DY &= 0xffffff00;
  7609. }
  7610. M68KMAKE_OP(sf, 8, ., .)
  7611. {
  7612. m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
  7613. }
  7614. M68KMAKE_OP(scc, 8, ., d)
  7615. {
  7616. if(M68KMAKE_CC)
  7617. {
  7618. DY |= 0xff;
  7619. USE_CYCLES(CYC_SCC_R_TRUE);
  7620. return;
  7621. }
  7622. DY &= 0xffffff00;
  7623. }
  7624. M68KMAKE_OP(scc, 8, ., .)
  7625. {
  7626. m68ki_write_8(M68KMAKE_GET_EA_AY_8, M68KMAKE_CC ? 0xff : 0);
  7627. }
  7628. M68KMAKE_OP(stop, 0, ., .)
  7629. {
  7630. if(FLAG_S)
  7631. {
  7632. uint new_sr = OPER_I_16();
  7633. m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
  7634. CPU_STOPPED |= STOP_LEVEL_STOP;
  7635. m68ki_set_sr(new_sr);
  7636. m68ki_remaining_cycles = 0;
  7637. return;
  7638. }
  7639. m68ki_exception_privilege_violation();
  7640. }
  7641. M68KMAKE_OP(sub, 8, er, d)
  7642. {
  7643. uint* r_dst = &DX;
  7644. uint src = MASK_OUT_ABOVE_8(DY);
  7645. uint dst = MASK_OUT_ABOVE_8(*r_dst);
  7646. uint res = dst - src;
  7647. FLAG_N = NFLAG_8(res);
  7648. FLAG_X = FLAG_C = CFLAG_8(res);
  7649. FLAG_V = VFLAG_SUB_8(src, dst, res);
  7650. FLAG_Z = MASK_OUT_ABOVE_8(res);
  7651. *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
  7652. }
  7653. M68KMAKE_OP(sub, 8, er, .)
  7654. {
  7655. uint* r_dst = &DX;
  7656. uint src = M68KMAKE_GET_OPER_AY_8;
  7657. uint dst = MASK_OUT_ABOVE_8(*r_dst);
  7658. uint res = dst - src;
  7659. FLAG_N = NFLAG_8(res);
  7660. FLAG_X = FLAG_C = CFLAG_8(res);
  7661. FLAG_V = VFLAG_SUB_8(src, dst, res);
  7662. FLAG_Z = MASK_OUT_ABOVE_8(res);
  7663. *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
  7664. }
  7665. M68KMAKE_OP(sub, 16, er, d)
  7666. {
  7667. uint* r_dst = &DX;
  7668. uint src = MASK_OUT_ABOVE_16(DY);
  7669. uint dst = MASK_OUT_ABOVE_16(*r_dst);
  7670. uint res = dst - src;
  7671. FLAG_N = NFLAG_16(res);
  7672. FLAG_X = FLAG_C = CFLAG_16(res);
  7673. FLAG_V = VFLAG_SUB_16(src, dst, res);
  7674. FLAG_Z = MASK_OUT_ABOVE_16(res);
  7675. *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
  7676. }
  7677. M68KMAKE_OP(sub, 16, er, a)
  7678. {
  7679. uint* r_dst = &DX;
  7680. uint src = MASK_OUT_ABOVE_16(AY);
  7681. uint dst = MASK_OUT_ABOVE_16(*r_dst);
  7682. uint res = dst - src;
  7683. FLAG_N = NFLAG_16(res);
  7684. FLAG_X = FLAG_C = CFLAG_16(res);
  7685. FLAG_V = VFLAG_SUB_16(src, dst, res);
  7686. FLAG_Z = MASK_OUT_ABOVE_16(res);
  7687. *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
  7688. }
  7689. M68KMAKE_OP(sub, 16, er, .)
  7690. {
  7691. uint* r_dst = &DX;
  7692. uint src = M68KMAKE_GET_OPER_AY_16;
  7693. uint dst = MASK_OUT_ABOVE_16(*r_dst);
  7694. uint res = dst - src;
  7695. FLAG_N = NFLAG_16(res);
  7696. FLAG_X = FLAG_C = CFLAG_16(res);
  7697. FLAG_V = VFLAG_SUB_16(src, dst, res);
  7698. FLAG_Z = MASK_OUT_ABOVE_16(res);
  7699. *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
  7700. }
  7701. M68KMAKE_OP(sub, 32, er, d)
  7702. {
  7703. uint* r_dst = &DX;
  7704. uint src = DY;
  7705. uint dst = *r_dst;
  7706. uint res = dst - src;
  7707. FLAG_N = NFLAG_32(res);
  7708. FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
  7709. FLAG_V = VFLAG_SUB_32(src, dst, res);
  7710. FLAG_Z = MASK_OUT_ABOVE_32(res);
  7711. *r_dst = FLAG_Z;
  7712. }
  7713. M68KMAKE_OP(sub, 32, er, a)
  7714. {
  7715. uint* r_dst = &DX;
  7716. uint src = AY;
  7717. uint dst = *r_dst;
  7718. uint res = dst - src;
  7719. FLAG_N = NFLAG_32(res);
  7720. FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
  7721. FLAG_V = VFLAG_SUB_32(src, dst, res);
  7722. FLAG_Z = MASK_OUT_ABOVE_32(res);
  7723. *r_dst = FLAG_Z;
  7724. }
  7725. M68KMAKE_OP(sub, 32, er, .)
  7726. {
  7727. uint* r_dst = &DX;
  7728. uint src = M68KMAKE_GET_OPER_AY_32;
  7729. uint dst = *r_dst;
  7730. uint res = dst - src;
  7731. FLAG_N = NFLAG_32(res);
  7732. FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
  7733. FLAG_V = VFLAG_SUB_32(src, dst, res);
  7734. FLAG_Z = MASK_OUT_ABOVE_32(res);
  7735. *r_dst = FLAG_Z;
  7736. }
  7737. M68KMAKE_OP(sub, 8, re, .)
  7738. {
  7739. uint ea = M68KMAKE_GET_EA_AY_8;
  7740. uint src = MASK_OUT_ABOVE_8(DX);
  7741. uint dst = m68ki_read_8(ea);
  7742. uint res = dst - src;
  7743. FLAG_N = NFLAG_8(res);
  7744. FLAG_Z = MASK_OUT_ABOVE_8(res);
  7745. FLAG_X = FLAG_C = CFLAG_8(res);
  7746. FLAG_V = VFLAG_SUB_8(src, dst, res);
  7747. m68ki_write_8(ea, FLAG_Z);
  7748. }
  7749. M68KMAKE_OP(sub, 16, re, .)
  7750. {
  7751. uint ea = M68KMAKE_GET_EA_AY_16;
  7752. uint src = MASK_OUT_ABOVE_16(DX);
  7753. uint dst = m68ki_read_16(ea);
  7754. uint res = dst - src;
  7755. FLAG_N = NFLAG_16(res);
  7756. FLAG_Z = MASK_OUT_ABOVE_16(res);
  7757. FLAG_X = FLAG_C = CFLAG_16(res);
  7758. FLAG_V = VFLAG_SUB_16(src, dst, res);
  7759. m68ki_write_16(ea, FLAG_Z);
  7760. }
  7761. M68KMAKE_OP(sub, 32, re, .)
  7762. {
  7763. uint ea = M68KMAKE_GET_EA_AY_32;
  7764. uint src = DX;
  7765. uint dst = m68ki_read_32(ea);
  7766. uint res = dst - src;
  7767. FLAG_N = NFLAG_32(res);
  7768. FLAG_Z = MASK_OUT_ABOVE_32(res);
  7769. FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
  7770. FLAG_V = VFLAG_SUB_32(src, dst, res);
  7771. m68ki_write_32(ea, FLAG_Z);
  7772. }
  7773. M68KMAKE_OP(suba, 16, ., d)
  7774. {
  7775. uint* r_dst = &AX;
  7776. *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY));
  7777. }
  7778. M68KMAKE_OP(suba, 16, ., a)
  7779. {
  7780. uint* r_dst = &AX;
  7781. *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY));
  7782. }
  7783. M68KMAKE_OP(suba, 16, ., .)
  7784. {
  7785. uint* r_dst = &AX;
  7786. uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
  7787. *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
  7788. }
  7789. M68KMAKE_OP(suba, 32, ., d)
  7790. {
  7791. uint* r_dst = &AX;
  7792. *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY);
  7793. }
  7794. M68KMAKE_OP(suba, 32, ., a)
  7795. {
  7796. uint* r_dst = &AX;
  7797. *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY);
  7798. }
  7799. M68KMAKE_OP(suba, 32, ., .)
  7800. {
  7801. uint* r_dst = &AX;
  7802. *r_dst = MASK_OUT_ABOVE_32(*r_dst - M68KMAKE_GET_OPER_AY_32);
  7803. }
  7804. M68KMAKE_OP(subi, 8, ., d)
  7805. {
  7806. uint* r_dst = &DY;
  7807. uint src = OPER_I_8();
  7808. uint dst = MASK_OUT_ABOVE_8(*r_dst);
  7809. uint res = dst - src;
  7810. FLAG_N = NFLAG_8(res);
  7811. FLAG_Z = MASK_OUT_ABOVE_8(res);
  7812. FLAG_X = FLAG_C = CFLAG_8(res);
  7813. FLAG_V = VFLAG_SUB_8(src, dst, res);
  7814. *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
  7815. }
  7816. M68KMAKE_OP(subi, 8, ., .)
  7817. {
  7818. uint src = OPER_I_8();
  7819. uint ea = M68KMAKE_GET_EA_AY_8;
  7820. uint dst = m68ki_read_8(ea);
  7821. uint res = dst - src;
  7822. FLAG_N = NFLAG_8(res);
  7823. FLAG_Z = MASK_OUT_ABOVE_8(res);
  7824. FLAG_X = FLAG_C = CFLAG_8(res);
  7825. FLAG_V = VFLAG_SUB_8(src, dst, res);
  7826. m68ki_write_8(ea, FLAG_Z);
  7827. }
  7828. M68KMAKE_OP(subi, 16, ., d)
  7829. {
  7830. uint* r_dst = &DY;
  7831. uint src = OPER_I_16();
  7832. uint dst = MASK_OUT_ABOVE_16(*r_dst);
  7833. uint res = dst - src;
  7834. FLAG_N = NFLAG_16(res);
  7835. FLAG_Z = MASK_OUT_ABOVE_16(res);
  7836. FLAG_X = FLAG_C = CFLAG_16(res);
  7837. FLAG_V = VFLAG_SUB_16(src, dst, res);
  7838. *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
  7839. }
  7840. M68KMAKE_OP(subi, 16, ., .)
  7841. {
  7842. uint src = OPER_I_16();
  7843. uint ea = M68KMAKE_GET_EA_AY_16;
  7844. uint dst = m68ki_read_16(ea);
  7845. uint res = dst - src;
  7846. FLAG_N = NFLAG_16(res);
  7847. FLAG_Z = MASK_OUT_ABOVE_16(res);
  7848. FLAG_X = FLAG_C = CFLAG_16(res);
  7849. FLAG_V = VFLAG_SUB_16(src, dst, res);
  7850. m68ki_write_16(ea, FLAG_Z);
  7851. }
  7852. M68KMAKE_OP(subi, 32, ., d)
  7853. {
  7854. uint* r_dst = &DY;
  7855. uint src = OPER_I_32();
  7856. uint dst = *r_dst;
  7857. uint res = dst - src;
  7858. FLAG_N = NFLAG_32(res);
  7859. FLAG_Z = MASK_OUT_ABOVE_32(res);
  7860. FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
  7861. FLAG_V = VFLAG_SUB_32(src, dst, res);
  7862. *r_dst = FLAG_Z;
  7863. }
  7864. M68KMAKE_OP(subi, 32, ., .)
  7865. {
  7866. uint src = OPER_I_32();
  7867. uint ea = M68KMAKE_GET_EA_AY_32;
  7868. uint dst = m68ki_read_32(ea);
  7869. uint res = dst - src;
  7870. FLAG_N = NFLAG_32(res);
  7871. FLAG_Z = MASK_OUT_ABOVE_32(res);
  7872. FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
  7873. FLAG_V = VFLAG_SUB_32(src, dst, res);
  7874. m68ki_write_32(ea, FLAG_Z);
  7875. }
  7876. M68KMAKE_OP(subq, 8, ., d)
  7877. {
  7878. uint* r_dst = &DY;
  7879. uint src = (((REG_IR >> 9) - 1) & 7) + 1;
  7880. uint dst = MASK_OUT_ABOVE_8(*r_dst);
  7881. uint res = dst - src;
  7882. FLAG_N = NFLAG_8(res);
  7883. FLAG_Z = MASK_OUT_ABOVE_8(res);
  7884. FLAG_X = FLAG_C = CFLAG_8(res);
  7885. FLAG_V = VFLAG_SUB_8(src, dst, res);
  7886. *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
  7887. }
  7888. M68KMAKE_OP(subq, 8, ., .)
  7889. {
  7890. uint src = (((REG_IR >> 9) - 1) & 7) + 1;
  7891. uint ea = M68KMAKE_GET_EA_AY_8;
  7892. uint dst = m68ki_read_8(ea);
  7893. uint res = dst - src;
  7894. FLAG_N = NFLAG_8(res);
  7895. FLAG_Z = MASK_OUT_ABOVE_8(res);
  7896. FLAG_X = FLAG_C = CFLAG_8(res);
  7897. FLAG_V = VFLAG_SUB_8(src, dst, res);
  7898. m68ki_write_8(ea, FLAG_Z);
  7899. }
  7900. M68KMAKE_OP(subq, 16, ., d)
  7901. {
  7902. uint* r_dst = &DY;
  7903. uint src = (((REG_IR >> 9) - 1) & 7) + 1;
  7904. uint dst = MASK_OUT_ABOVE_16(*r_dst);
  7905. uint res = dst - src;
  7906. FLAG_N = NFLAG_16(res);
  7907. FLAG_Z = MASK_OUT_ABOVE_16(res);
  7908. FLAG_X = FLAG_C = CFLAG_16(res);
  7909. FLAG_V = VFLAG_SUB_16(src, dst, res);
  7910. *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
  7911. }
  7912. M68KMAKE_OP(subq, 16, ., a)
  7913. {
  7914. uint* r_dst = &AY;
  7915. *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
  7916. }
  7917. M68KMAKE_OP(subq, 16, ., .)
  7918. {
  7919. uint src = (((REG_IR >> 9) - 1) & 7) + 1;
  7920. uint ea = M68KMAKE_GET_EA_AY_16;
  7921. uint dst = m68ki_read_16(ea);
  7922. uint res = dst - src;
  7923. FLAG_N = NFLAG_16(res);
  7924. FLAG_Z = MASK_OUT_ABOVE_16(res);
  7925. FLAG_X = FLAG_C = CFLAG_16(res);
  7926. FLAG_V = VFLAG_SUB_16(src, dst, res);
  7927. m68ki_write_16(ea, FLAG_Z);
  7928. }
  7929. M68KMAKE_OP(subq, 32, ., d)
  7930. {
  7931. uint* r_dst = &DY;
  7932. uint src = (((REG_IR >> 9) - 1) & 7) + 1;
  7933. uint dst = *r_dst;
  7934. uint res = dst - src;
  7935. FLAG_N = NFLAG_32(res);
  7936. FLAG_Z = MASK_OUT_ABOVE_32(res);
  7937. FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
  7938. FLAG_V = VFLAG_SUB_32(src, dst, res);
  7939. *r_dst = FLAG_Z;
  7940. }
  7941. M68KMAKE_OP(subq, 32, ., a)
  7942. {
  7943. uint* r_dst = &AY;
  7944. *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
  7945. }
  7946. M68KMAKE_OP(subq, 32, ., .)
  7947. {
  7948. uint src = (((REG_IR >> 9) - 1) & 7) + 1;
  7949. uint ea = M68KMAKE_GET_EA_AY_32;
  7950. uint dst = m68ki_read_32(ea);
  7951. uint res = dst - src;
  7952. FLAG_N = NFLAG_32(res);
  7953. FLAG_Z = MASK_OUT_ABOVE_32(res);
  7954. FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
  7955. FLAG_V = VFLAG_SUB_32(src, dst, res);
  7956. m68ki_write_32(ea, FLAG_Z);
  7957. }
  7958. M68KMAKE_OP(subx, 8, rr, .)
  7959. {
  7960. uint* r_dst = &DX;
  7961. uint src = MASK_OUT_ABOVE_8(DY);
  7962. uint dst = MASK_OUT_ABOVE_8(*r_dst);
  7963. uint res = dst - src - XFLAG_AS_1();
  7964. FLAG_N = NFLAG_8(res);
  7965. FLAG_X = FLAG_C = CFLAG_8(res);
  7966. FLAG_V = VFLAG_SUB_8(src, dst, res);
  7967. res = MASK_OUT_ABOVE_8(res);
  7968. FLAG_Z |= res;
  7969. *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
  7970. }
  7971. M68KMAKE_OP(subx, 16, rr, .)
  7972. {
  7973. uint* r_dst = &DX;
  7974. uint src = MASK_OUT_ABOVE_16(DY);
  7975. uint dst = MASK_OUT_ABOVE_16(*r_dst);
  7976. uint res = dst - src - XFLAG_AS_1();
  7977. FLAG_N = NFLAG_16(res);
  7978. FLAG_X = FLAG_C = CFLAG_16(res);
  7979. FLAG_V = VFLAG_SUB_16(src, dst, res);
  7980. res = MASK_OUT_ABOVE_16(res);
  7981. FLAG_Z |= res;
  7982. *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
  7983. }
  7984. M68KMAKE_OP(subx, 32, rr, .)
  7985. {
  7986. uint* r_dst = &DX;
  7987. uint src = DY;
  7988. uint dst = *r_dst;
  7989. uint res = dst - src - XFLAG_AS_1();
  7990. FLAG_N = NFLAG_32(res);
  7991. FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
  7992. FLAG_V = VFLAG_SUB_32(src, dst, res);
  7993. res = MASK_OUT_ABOVE_32(res);
  7994. FLAG_Z |= res;
  7995. *r_dst = res;
  7996. }
  7997. M68KMAKE_OP(subx, 8, mm, ax7)
  7998. {
  7999. uint src = OPER_AY_PD_8();
  8000. uint ea = EA_A7_PD_8();
  8001. uint dst = m68ki_read_8(ea);
  8002. uint res = dst - src - XFLAG_AS_1();
  8003. FLAG_N = NFLAG_8(res);
  8004. FLAG_X = FLAG_C = CFLAG_8(res);
  8005. FLAG_V = VFLAG_SUB_8(src, dst, res);
  8006. res = MASK_OUT_ABOVE_8(res);
  8007. FLAG_Z |= res;
  8008. m68ki_write_8(ea, res);
  8009. }
  8010. M68KMAKE_OP(subx, 8, mm, ay7)
  8011. {
  8012. uint src = OPER_A7_PD_8();
  8013. uint ea = EA_AX_PD_8();
  8014. uint dst = m68ki_read_8(ea);
  8015. uint res = dst - src - XFLAG_AS_1();
  8016. FLAG_N = NFLAG_8(res);
  8017. FLAG_X = FLAG_C = CFLAG_8(res);
  8018. FLAG_V = VFLAG_SUB_8(src, dst, res);
  8019. res = MASK_OUT_ABOVE_8(res);
  8020. FLAG_Z |= res;
  8021. m68ki_write_8(ea, res);
  8022. }
  8023. M68KMAKE_OP(subx, 8, mm, axy7)
  8024. {
  8025. uint src = OPER_A7_PD_8();
  8026. uint ea = EA_A7_PD_8();
  8027. uint dst = m68ki_read_8(ea);
  8028. uint res = dst - src - XFLAG_AS_1();
  8029. FLAG_N = NFLAG_8(res);
  8030. FLAG_X = FLAG_C = CFLAG_8(res);
  8031. FLAG_V = VFLAG_SUB_8(src, dst, res);
  8032. res = MASK_OUT_ABOVE_8(res);
  8033. FLAG_Z |= res;
  8034. m68ki_write_8(ea, res);
  8035. }
  8036. M68KMAKE_OP(subx, 8, mm, .)
  8037. {
  8038. uint src = OPER_AY_PD_8();
  8039. uint ea = EA_AX_PD_8();
  8040. uint dst = m68ki_read_8(ea);
  8041. uint res = dst - src - XFLAG_AS_1();
  8042. FLAG_N = NFLAG_8(res);
  8043. FLAG_X = FLAG_C = CFLAG_8(res);
  8044. FLAG_V = VFLAG_SUB_8(src, dst, res);
  8045. res = MASK_OUT_ABOVE_8(res);
  8046. FLAG_Z |= res;
  8047. m68ki_write_8(ea, res);
  8048. }
  8049. M68KMAKE_OP(subx, 16, mm, .)
  8050. {
  8051. uint src = OPER_AY_PD_16();
  8052. uint ea = EA_AX_PD_16();
  8053. uint dst = m68ki_read_16(ea);
  8054. uint res = dst - src - XFLAG_AS_1();
  8055. FLAG_N = NFLAG_16(res);
  8056. FLAG_X = FLAG_C = CFLAG_16(res);
  8057. FLAG_V = VFLAG_SUB_16(src, dst, res);
  8058. res = MASK_OUT_ABOVE_16(res);
  8059. FLAG_Z |= res;
  8060. m68ki_write_16(ea, res);
  8061. }
  8062. M68KMAKE_OP(subx, 32, mm, .)
  8063. {
  8064. uint src = OPER_AY_PD_32();
  8065. uint ea = EA_AX_PD_32();
  8066. uint dst = m68ki_read_32(ea);
  8067. uint res = dst - src - XFLAG_AS_1();
  8068. FLAG_N = NFLAG_32(res);
  8069. FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
  8070. FLAG_V = VFLAG_SUB_32(src, dst, res);
  8071. res = MASK_OUT_ABOVE_32(res);
  8072. FLAG_Z |= res;
  8073. m68ki_write_32(ea, res);
  8074. }
  8075. M68KMAKE_OP(swap, 32, ., .)
  8076. {
  8077. uint* r_dst = &DY;
  8078. FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16);
  8079. *r_dst = (*r_dst>>16) | FLAG_Z;
  8080. FLAG_Z = *r_dst;
  8081. FLAG_N = NFLAG_32(*r_dst);
  8082. FLAG_C = CFLAG_CLEAR;
  8083. FLAG_V = VFLAG_CLEAR;
  8084. }
  8085. M68KMAKE_OP(tas, 8, ., d)
  8086. {
  8087. uint* r_dst = &DY;
  8088. FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
  8089. FLAG_N = NFLAG_8(*r_dst);
  8090. FLAG_V = VFLAG_CLEAR;
  8091. FLAG_C = CFLAG_CLEAR;
  8092. *r_dst |= 0x80;
  8093. }
  8094. M68KMAKE_OP(tas, 8, ., .)
  8095. {
  8096. uint ea = M68KMAKE_GET_EA_AY_8;
  8097. uint dst = m68ki_read_8(ea);
  8098. uint allow_writeback;
  8099. FLAG_Z = dst;
  8100. FLAG_N = NFLAG_8(dst);
  8101. FLAG_V = VFLAG_CLEAR;
  8102. FLAG_C = CFLAG_CLEAR;
  8103. /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
  8104. disabled in order to function properly. Some Amiga software may also rely
  8105. on this, but only when accessing specific addresses so additional functionality
  8106. will be needed. */
  8107. allow_writeback = m68ki_tas_callback();
  8108. if (allow_writeback==1) m68ki_write_8(ea, dst | 0x80);
  8109. }
  8110. M68KMAKE_OP(trap, 0, ., .)
  8111. {
  8112. /* Trap#n stacks exception frame type 0 */
  8113. m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf)); /* HJB 990403 */
  8114. }
  8115. M68KMAKE_OP(trapt, 0, ., .)
  8116. {
  8117. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8118. {
  8119. m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
  8120. return;
  8121. }
  8122. m68ki_exception_illegal();
  8123. }
  8124. M68KMAKE_OP(trapt, 16, ., .)
  8125. {
  8126. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8127. {
  8128. m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
  8129. return;
  8130. }
  8131. m68ki_exception_illegal();
  8132. }
  8133. M68KMAKE_OP(trapt, 32, ., .)
  8134. {
  8135. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8136. {
  8137. m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
  8138. return;
  8139. }
  8140. m68ki_exception_illegal();
  8141. }
  8142. M68KMAKE_OP(trapf, 0, ., .)
  8143. {
  8144. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8145. {
  8146. return;
  8147. }
  8148. m68ki_exception_illegal();
  8149. }
  8150. M68KMAKE_OP(trapf, 16, ., .)
  8151. {
  8152. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8153. {
  8154. REG_PC += 2;
  8155. return;
  8156. }
  8157. m68ki_exception_illegal();
  8158. }
  8159. M68KMAKE_OP(trapf, 32, ., .)
  8160. {
  8161. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8162. {
  8163. REG_PC += 4;
  8164. return;
  8165. }
  8166. m68ki_exception_illegal();
  8167. }
  8168. M68KMAKE_OP(trapcc, 0, ., .)
  8169. {
  8170. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8171. {
  8172. if(M68KMAKE_CC)
  8173. m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
  8174. return;
  8175. }
  8176. m68ki_exception_illegal();
  8177. }
  8178. M68KMAKE_OP(trapcc, 16, ., .)
  8179. {
  8180. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8181. {
  8182. if(M68KMAKE_CC)
  8183. {
  8184. m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
  8185. return;
  8186. }
  8187. REG_PC += 2;
  8188. return;
  8189. }
  8190. m68ki_exception_illegal();
  8191. }
  8192. M68KMAKE_OP(trapcc, 32, ., .)
  8193. {
  8194. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8195. {
  8196. if(M68KMAKE_CC)
  8197. {
  8198. m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
  8199. return;
  8200. }
  8201. REG_PC += 4;
  8202. return;
  8203. }
  8204. m68ki_exception_illegal();
  8205. }
  8206. M68KMAKE_OP(trapv, 0, ., .)
  8207. {
  8208. if(COND_VC())
  8209. {
  8210. return;
  8211. }
  8212. m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
  8213. }
  8214. M68KMAKE_OP(tst, 8, ., d)
  8215. {
  8216. uint res = MASK_OUT_ABOVE_8(DY);
  8217. FLAG_N = NFLAG_8(res);
  8218. FLAG_Z = res;
  8219. FLAG_V = VFLAG_CLEAR;
  8220. FLAG_C = CFLAG_CLEAR;
  8221. }
  8222. M68KMAKE_OP(tst, 8, ., .)
  8223. {
  8224. uint res = M68KMAKE_GET_OPER_AY_8;
  8225. FLAG_N = NFLAG_8(res);
  8226. FLAG_Z = res;
  8227. FLAG_V = VFLAG_CLEAR;
  8228. FLAG_C = CFLAG_CLEAR;
  8229. }
  8230. M68KMAKE_OP(tst, 8, ., pcdi)
  8231. {
  8232. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8233. {
  8234. uint res = OPER_PCDI_8();
  8235. FLAG_N = NFLAG_8(res);
  8236. FLAG_Z = res;
  8237. FLAG_V = VFLAG_CLEAR;
  8238. FLAG_C = CFLAG_CLEAR;
  8239. return;
  8240. }
  8241. m68ki_exception_illegal();
  8242. }
  8243. M68KMAKE_OP(tst, 8, ., pcix)
  8244. {
  8245. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8246. {
  8247. uint res = OPER_PCIX_8();
  8248. FLAG_N = NFLAG_8(res);
  8249. FLAG_Z = res;
  8250. FLAG_V = VFLAG_CLEAR;
  8251. FLAG_C = CFLAG_CLEAR;
  8252. return;
  8253. }
  8254. m68ki_exception_illegal();
  8255. }
  8256. M68KMAKE_OP(tst, 8, ., i)
  8257. {
  8258. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8259. {
  8260. uint res = OPER_I_8();
  8261. FLAG_N = NFLAG_8(res);
  8262. FLAG_Z = res;
  8263. FLAG_V = VFLAG_CLEAR;
  8264. FLAG_C = CFLAG_CLEAR;
  8265. return;
  8266. }
  8267. m68ki_exception_illegal();
  8268. }
  8269. M68KMAKE_OP(tst, 16, ., d)
  8270. {
  8271. uint res = MASK_OUT_ABOVE_16(DY);
  8272. FLAG_N = NFLAG_16(res);
  8273. FLAG_Z = res;
  8274. FLAG_V = VFLAG_CLEAR;
  8275. FLAG_C = CFLAG_CLEAR;
  8276. }
  8277. M68KMAKE_OP(tst, 16, ., a)
  8278. {
  8279. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8280. {
  8281. uint res = MAKE_INT_16(AY);
  8282. FLAG_N = NFLAG_16(res);
  8283. FLAG_Z = res;
  8284. FLAG_V = VFLAG_CLEAR;
  8285. FLAG_C = CFLAG_CLEAR;
  8286. return;
  8287. }
  8288. m68ki_exception_illegal();
  8289. }
  8290. M68KMAKE_OP(tst, 16, ., .)
  8291. {
  8292. uint res = M68KMAKE_GET_OPER_AY_16;
  8293. FLAG_N = NFLAG_16(res);
  8294. FLAG_Z = res;
  8295. FLAG_V = VFLAG_CLEAR;
  8296. FLAG_C = CFLAG_CLEAR;
  8297. }
  8298. M68KMAKE_OP(tst, 16, ., pcdi)
  8299. {
  8300. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8301. {
  8302. uint res = OPER_PCDI_16();
  8303. FLAG_N = NFLAG_16(res);
  8304. FLAG_Z = res;
  8305. FLAG_V = VFLAG_CLEAR;
  8306. FLAG_C = CFLAG_CLEAR;
  8307. return;
  8308. }
  8309. m68ki_exception_illegal();
  8310. }
  8311. M68KMAKE_OP(tst, 16, ., pcix)
  8312. {
  8313. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8314. {
  8315. uint res = OPER_PCIX_16();
  8316. FLAG_N = NFLAG_16(res);
  8317. FLAG_Z = res;
  8318. FLAG_V = VFLAG_CLEAR;
  8319. FLAG_C = CFLAG_CLEAR;
  8320. return;
  8321. }
  8322. m68ki_exception_illegal();
  8323. }
  8324. M68KMAKE_OP(tst, 16, ., i)
  8325. {
  8326. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8327. {
  8328. uint res = OPER_I_16();
  8329. FLAG_N = NFLAG_16(res);
  8330. FLAG_Z = res;
  8331. FLAG_V = VFLAG_CLEAR;
  8332. FLAG_C = CFLAG_CLEAR;
  8333. return;
  8334. }
  8335. m68ki_exception_illegal();
  8336. }
  8337. M68KMAKE_OP(tst, 32, ., d)
  8338. {
  8339. uint res = DY;
  8340. FLAG_N = NFLAG_32(res);
  8341. FLAG_Z = res;
  8342. FLAG_V = VFLAG_CLEAR;
  8343. FLAG_C = CFLAG_CLEAR;
  8344. }
  8345. M68KMAKE_OP(tst, 32, ., a)
  8346. {
  8347. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8348. {
  8349. uint res = AY;
  8350. FLAG_N = NFLAG_32(res);
  8351. FLAG_Z = res;
  8352. FLAG_V = VFLAG_CLEAR;
  8353. FLAG_C = CFLAG_CLEAR;
  8354. return;
  8355. }
  8356. m68ki_exception_illegal();
  8357. }
  8358. M68KMAKE_OP(tst, 32, ., .)
  8359. {
  8360. uint res = M68KMAKE_GET_OPER_AY_32;
  8361. FLAG_N = NFLAG_32(res);
  8362. FLAG_Z = res;
  8363. FLAG_V = VFLAG_CLEAR;
  8364. FLAG_C = CFLAG_CLEAR;
  8365. }
  8366. M68KMAKE_OP(tst, 32, ., pcdi)
  8367. {
  8368. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8369. {
  8370. uint res = OPER_PCDI_32();
  8371. FLAG_N = NFLAG_32(res);
  8372. FLAG_Z = res;
  8373. FLAG_V = VFLAG_CLEAR;
  8374. FLAG_C = CFLAG_CLEAR;
  8375. return;
  8376. }
  8377. m68ki_exception_illegal();
  8378. }
  8379. M68KMAKE_OP(tst, 32, ., pcix)
  8380. {
  8381. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8382. {
  8383. uint res = OPER_PCIX_32();
  8384. FLAG_N = NFLAG_32(res);
  8385. FLAG_Z = res;
  8386. FLAG_V = VFLAG_CLEAR;
  8387. FLAG_C = CFLAG_CLEAR;
  8388. return;
  8389. }
  8390. m68ki_exception_illegal();
  8391. }
  8392. M68KMAKE_OP(tst, 32, ., i)
  8393. {
  8394. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8395. {
  8396. uint res = OPER_I_32();
  8397. FLAG_N = NFLAG_32(res);
  8398. FLAG_Z = res;
  8399. FLAG_V = VFLAG_CLEAR;
  8400. FLAG_C = CFLAG_CLEAR;
  8401. return;
  8402. }
  8403. m68ki_exception_illegal();
  8404. }
  8405. M68KMAKE_OP(unlk, 32, ., a7)
  8406. {
  8407. REG_A[7] = m68ki_read_32(REG_A[7]);
  8408. }
  8409. M68KMAKE_OP(unlk, 32, ., .)
  8410. {
  8411. uint* r_dst = &AY;
  8412. REG_A[7] = *r_dst;
  8413. *r_dst = m68ki_pull_32();
  8414. }
  8415. M68KMAKE_OP(unpk, 16, rr, .)
  8416. {
  8417. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8418. {
  8419. /* Note: DX and DY are reversed in Motorola's docs */
  8420. uint src = DY;
  8421. uint* r_dst = &DX;
  8422. *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff);
  8423. return;
  8424. }
  8425. m68ki_exception_illegal();
  8426. }
  8427. M68KMAKE_OP(unpk, 16, mm, ax7)
  8428. {
  8429. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8430. {
  8431. /* Note: AX and AY are reversed in Motorola's docs */
  8432. uint src = OPER_AY_PD_8();
  8433. uint ea_dst;
  8434. src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
  8435. ea_dst = EA_A7_PD_8();
  8436. m68ki_write_8(ea_dst, (src >> 8) & 0xff);
  8437. ea_dst = EA_A7_PD_8();
  8438. m68ki_write_8(ea_dst, src & 0xff);
  8439. return;
  8440. }
  8441. m68ki_exception_illegal();
  8442. }
  8443. M68KMAKE_OP(unpk, 16, mm, ay7)
  8444. {
  8445. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8446. {
  8447. /* Note: AX and AY are reversed in Motorola's docs */
  8448. uint src = OPER_A7_PD_8();
  8449. uint ea_dst;
  8450. src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
  8451. ea_dst = EA_AX_PD_8();
  8452. m68ki_write_8(ea_dst, (src >> 8) & 0xff);
  8453. ea_dst = EA_AX_PD_8();
  8454. m68ki_write_8(ea_dst, src & 0xff);
  8455. return;
  8456. }
  8457. m68ki_exception_illegal();
  8458. }
  8459. M68KMAKE_OP(unpk, 16, mm, axy7)
  8460. {
  8461. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8462. {
  8463. uint src = OPER_A7_PD_8();
  8464. uint ea_dst;
  8465. src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
  8466. ea_dst = EA_A7_PD_8();
  8467. m68ki_write_8(ea_dst, (src >> 8) & 0xff);
  8468. ea_dst = EA_A7_PD_8();
  8469. m68ki_write_8(ea_dst, src & 0xff);
  8470. return;
  8471. }
  8472. m68ki_exception_illegal();
  8473. }
  8474. M68KMAKE_OP(unpk, 16, mm, .)
  8475. {
  8476. if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
  8477. {
  8478. /* Note: AX and AY are reversed in Motorola's docs */
  8479. uint src = OPER_AY_PD_8();
  8480. uint ea_dst;
  8481. src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
  8482. ea_dst = EA_AX_PD_8();
  8483. m68ki_write_8(ea_dst, (src >> 8) & 0xff);
  8484. ea_dst = EA_AX_PD_8();
  8485. m68ki_write_8(ea_dst, src & 0xff);
  8486. return;
  8487. }
  8488. m68ki_exception_illegal();
  8489. }
  8490. XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  8491. M68KMAKE_END