compiler.h 2.8 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485
  1. int sh2_drc_init(SH2 *sh2);
  2. void sh2_drc_finish(SH2 *sh2);
  3. void sh2_drc_wcheck_ram(u32 a, unsigned len, SH2 *sh2);
  4. void sh2_drc_wcheck_da(u32 a, unsigned len, SH2 *sh2);
  5. #ifdef DRC_SH2
  6. void sh2_drc_mem_setup(SH2 *sh2);
  7. void sh2_drc_flush_all(void);
  8. #else
  9. #define sh2_drc_mem_setup(x)
  10. #define sh2_drc_flush_all()
  11. #define sh2_drc_frame()
  12. #endif
  13. #define BLOCK_INSN_LIMIT 1024
  14. /* op_flags */
  15. #define OF_DELAY_OP (1 << 0)
  16. #define OF_BTARGET (1 << 1)
  17. #define OF_LOOP (3 << 2) // NONE, IDLE, DELAY, POLL loop
  18. #define OF_B_IN_DS (1 << 4)
  19. #define OF_DELAY_INSN (1 << 5) // DT, (TODO ADD+CMP?)
  20. #define OF_POLL_INSN (1 << 6) // MOV @(...),Rn (no post increment), TST @(...)
  21. #define OF_BASIC_LOOP (1 << 7) // pinnable loop without any branches in it
  22. #define OF_IDLE_LOOP (1 << 2)
  23. #define OF_DELAY_LOOP (2 << 2)
  24. #define OF_POLL_LOOP (3 << 2)
  25. u16 scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc,
  26. u32 *base_literals, u32 *end_literals);
  27. #if defined(DRC_SH2) && defined(__GNUC__) && !defined(__clang__)
  28. // direct access to some host CPU registers used by the DRC if gcc is used.
  29. // XXX MUST match SHR_SR definitions in cpu/drc/emit_*.c; should be moved there
  30. // XXX yuck, there's no portable way to determine register size. Use long long
  31. // if target is 64 bit and data model is ILP32 or LLP64(windows), else long
  32. #if defined(__arm__)
  33. #define DRC_SR_REG "r10"
  34. #define DRC_REG_LL 0 // 32 bit
  35. #elif defined(__aarch64__)
  36. #define DRC_SR_REG "r28"
  37. #define DRC_REG_LL (__ILP32__ || _WIN32)
  38. #elif defined(__mips__)
  39. #define DRC_SR_REG "s6"
  40. #define DRC_REG_LL (_MIPS_SZPTR > _MIPS_SZLONG) // (_MIPS_SIM == _ABIN32)
  41. #elif defined(__riscv__) || defined(__riscv)
  42. #define DRC_SR_REG "s11"
  43. #define DRC_REG_LL 0 // no ABI for (__ILP32__ && __riscv_xlen != 32)
  44. #elif defined(__powerpc__) || defined(__ppc__)
  45. #define DRC_SR_REG "r28"
  46. #define DRC_REG_LL 0 // no ABI for __ILP32__
  47. #elif defined(__i386__)
  48. #define DRC_SR_REG "edi"
  49. #define DRC_REG_LL 0 // 32 bit
  50. #elif defined(__x86_64__)
  51. #define DRC_SR_REG "rbx"
  52. #define DRC_REG_LL (__ILP32__ || _WIN32)
  53. #endif
  54. #endif
  55. #ifdef DRC_SR_REG
  56. // XXX this is more clear but produces too much overhead for slow platforms
  57. extern void REGPARM(1) (*sh2_drc_save_sr)(SH2 *sh2);
  58. extern void REGPARM(1) (*sh2_drc_restore_sr)(SH2 *sh2);
  59. // NB: sh2_sr MUST have register size if optimizing with -O3 (-fif-conversion)
  60. #if DRC_REG_LL
  61. #define DRC_DECLARE_SR register long long _sh2_sr asm(DRC_SR_REG)
  62. #else
  63. #define DRC_DECLARE_SR register long _sh2_sr asm(DRC_SR_REG)
  64. #endif
  65. #define DRC_SAVE_SR(sh2) \
  66. if (likely(sh2->state & SH2_IN_DRC)) \
  67. sh2->sr = (s32)_sh2_sr
  68. // sh2_drc_save_sr(sh2)
  69. #define DRC_RESTORE_SR(sh2) \
  70. if (likely(sh2->state & SH2_IN_DRC)) \
  71. _sh2_sr = (s32)sh2->sr
  72. // sh2_drc_restore_sr(sh2)
  73. #else
  74. #define DRC_DECLARE_SR
  75. #define DRC_SAVE_SR(sh2)
  76. #define DRC_RESTORE_SR(sh2)
  77. #endif