videoport.c 36 KB

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  1. /*
  2. * PicoDrive
  3. * (c) Copyright Dave, 2004
  4. * (C) notaz, 2006-2009
  5. * (C) kub, 2020,2021
  6. *
  7. * This work is licensed under the terms of MAME license.
  8. * See COPYING file in the top-level directory.
  9. */
  10. #include "pico_int.h"
  11. #define NEED_DMA_SOURCE
  12. #include "memory.h"
  13. enum { clkdiv = 2 }; // CPU clock granularity: one of 1,2,4,8
  14. // VDP Slot timing, taken from http://gendev.spritesmind.net/
  15. // forum/viewtopic.php?f=22&t=851&sid=d5701a71396ee7f700c74fb7cd85cb09
  16. // Thank you very much for the great work, Nemesis!
  17. // Slot clock is sysclock/20 for h32 and sysclock/16 for h40.
  18. // One scanline is 63.7us/63.5us (h32/h40) long which is 488.6/487.4 68k cycles.
  19. // Assume 488 for everything.
  20. // 1 slot is 488/171 = 2.8538 68k cycles in h32, and 488/210 = 2.3238 in h40.
  21. enum { slcpu = 488 };
  22. // VDP has a slot counter running from 0x00 to 0xff every scanline, but it has
  23. // a gap depending on the video mode. The slot in which a horizontal interrupt
  24. // is generated also depends on the video mode.
  25. enum { hint32 = 0x85, gapstart32 = 0x94, gapend32 = 0xe9};
  26. enum { hint40 = 0xa5, gapstart40 = 0xb7, gapend40 = 0xe5};
  27. // The horizontal sync period (HBLANK) is 30/37 slots (h32/h40):
  28. // h32: 4 slots front porch (1.49us), 13 HSYNC (4.84us), 13 back porch (4.84us)
  29. // h40: 5 slots front porch (1.49us), 16 HSYNC (4.77us), 16 back porch (4.77us)
  30. // HBLANK starts in slot 0x93/0xb4, according to Nemesis' measurements.
  31. enum { hboff32 = 0x93-hint32, hblen32 = 0xf8-(gapend32-gapstart32)-hint32};//30
  32. enum { hboff40 = 0xb4-hint40, hblen40 = 0xf8-(gapend40-gapstart40)-hint40};//37
  33. // number of slots in a scanline
  34. #define slots32 (0x100-(gapend32-gapstart32)) // 171
  35. #define slots40 (0x100-(gapend40-gapstart40)) // 210
  36. // In blanked display, all slots but the refresh slots are usable for transfers,
  37. // in active display only 16(h32) / 18(h40) slots can be used.
  38. // dma and refresh slots for active display, 16 for H32
  39. static u8 dmaslots32[] =
  40. { 145,243, 2,10,18, 34,42,50, 66,74,82, 98,106,114, 129,130 };
  41. static u8 refslots32[] =
  42. { 250, 26, 58, 90, 122 };
  43. // dma and refresh slots for active display, 18 for H40
  44. static u8 dmaslots40[] =
  45. { 232, 2,10,18, 34,42,50, 66,74,82, 98,106,114, 130,138,146, 161,162 };
  46. static u8 refslots40[] =
  47. { 250, 26, 58, 90, 122, 154 };
  48. // table sizes
  49. enum { cycsz = slcpu/clkdiv };
  50. enum { sl32blsz=slots32-sizeof(refslots32)+1, sl32acsz=sizeof(dmaslots32)+1 };
  51. enum { sl40blsz=slots40-sizeof(refslots40)+1, sl40acsz=sizeof(dmaslots40)+1 };
  52. // Tables must be considerably larger than one scanline, since 68k emulation
  53. // isn't stopping in the middle of an operation. If the last op is a 32 bit
  54. // VDP access 2 slots may need to be taken from the next scanline, which can be
  55. // more than 100 CPU cycles. For safety just cover 2 scanlines.
  56. // table for hvcounter mapping. check: Sonic 3D Blast bonus, Cannon Fodder,
  57. // Chase HQ II, 3 Ninjas kick back, Road Rash 3, Skitchin', Wheel of Fortune
  58. static u8 hcounts_32[2*cycsz], hcounts_40[2*cycsz];
  59. // tables mapping cycles to slots
  60. static u16 vdpcyc2sl_32_bl[2*cycsz],vdpcyc2sl_40_bl[2*cycsz];
  61. static u16 vdpcyc2sl_32_ac[2*cycsz],vdpcyc2sl_40_ac[2*cycsz];
  62. // tables mapping slots to cycles
  63. // NB the sl2cyc tables must cover all slots present in the cyc2sl tables.
  64. static u16 vdpsl2cyc_32_bl[2*sl32blsz],vdpsl2cyc_40_bl[2*sl40blsz];
  65. static u16 vdpsl2cyc_32_ac[2*sl32acsz],vdpsl2cyc_40_ac[2*sl40acsz];
  66. // calculate timing tables for one mode (H32 or H40)
  67. // NB tables aligned to HINT, since the main loop uses HINT as synchronization
  68. #define INITTABLES(s) { \
  69. float factor = (float)slcpu/slots##s; \
  70. int ax, bx, rx, ac, bc; \
  71. int i, n; \
  72. \
  73. /* calculate internal VDP slot numbers */ \
  74. for (i = 0; i < cycsz; i++) { \
  75. n = hint##s + i*clkdiv/factor; \
  76. if (n >= gapstart##s) n += gapend##s-gapstart##s; \
  77. hcounts_##s[i] = n % 256; \
  78. } \
  79. \
  80. ax = bx = ac = bc = rx = 0; \
  81. for (i = 0; i < cycsz; i++) { \
  82. n = hcounts_##s[i]; \
  83. if (i == 0 || n != hcounts_##s[i-1]) { \
  84. /* fill slt <=> cycle tables, active scanline */ \
  85. if (ax < ARRAY_SIZE(dmaslots##s) && dmaslots##s[ax] == n) { \
  86. vdpsl2cyc_##s##_ac[++ax]=i; \
  87. while (ac < i) vdpcyc2sl_##s##_ac[ac++] = ax-1; \
  88. } \
  89. /* fill slt <=> cycle tables, scanline off */ \
  90. if (rx >= ARRAY_SIZE(refslots##s) || refslots##s[rx] != n) { \
  91. vdpsl2cyc_##s##_bl[++bx]=i; \
  92. while (bc < i) vdpcyc2sl_##s##_bl[bc++] = bx-1; \
  93. } else \
  94. ++rx; \
  95. } \
  96. } \
  97. /* fill up cycle to slot mappings for last slot */ \
  98. while (ac < cycsz) \
  99. vdpcyc2sl_##s##_ac[ac] = ARRAY_SIZE(dmaslots##s), ac++; \
  100. while (bc < cycsz) \
  101. vdpcyc2sl_##s##_bl[bc] = slots##s-ARRAY_SIZE(refslots##s), bc++; \
  102. \
  103. /* extend tables for 2nd scanline */ \
  104. memcpy(hcounts_##s+cycsz, hcounts_##s, ARRAY_SIZE(hcounts_##s)-cycsz);\
  105. i = ARRAY_SIZE(dmaslots##s); \
  106. while (ac < ARRAY_SIZE(vdpcyc2sl_##s##_ac)) \
  107. vdpcyc2sl_##s##_ac[ac] = vdpcyc2sl_##s##_ac[ac-cycsz]+i, ac++; \
  108. while (ax < ARRAY_SIZE(vdpsl2cyc_##s##_ac)-1) ax++, \
  109. vdpsl2cyc_##s##_ac[ax] = vdpsl2cyc_##s##_ac[ax-i]+cycsz; \
  110. i = slots##s - ARRAY_SIZE(refslots##s); \
  111. while (bc < ARRAY_SIZE(vdpcyc2sl_##s##_bl)) \
  112. vdpcyc2sl_##s##_bl[bc] = vdpcyc2sl_##s##_bl[bc-cycsz]+i, bc++; \
  113. while (bx < ARRAY_SIZE(vdpsl2cyc_##s##_bl)-1) bx++, \
  114. vdpsl2cyc_##s##_bl[bx] = vdpsl2cyc_##s##_bl[bx-i]+cycsz; \
  115. }
  116. // initialize VDP timing tables
  117. void PicoVideoInit(void)
  118. {
  119. INITTABLES(32);
  120. INITTABLES(40);
  121. }
  122. static int blankline; // display disabled for this line
  123. u32 SATaddr, SATmask; // VRAM addr of sprite attribute table
  124. int (*PicoDmaHook)(u32 source, int len, unsigned short **base, u32 *mask) = NULL;
  125. /* VDP FIFO implementation
  126. *
  127. * fifo_slot: last slot executed in this scanline
  128. * fifo_cnt: #slots remaining for active FIFO write (#writes<<#bytep)
  129. * fifo_total: #total FIFO entries pending
  130. * fifo_data: last values transferred through fifo
  131. * fifo_queue: fifo transfer queue (#writes, flags)
  132. *
  133. * FIFO states: empty total=0
  134. * inuse total>0 && total<4
  135. * full total==4
  136. * wait total>4
  137. * Conditions:
  138. * fifo_slot is normally behind slot2cyc[cycles]. Advancing it beyond cycles
  139. * implies blocking the 68k up to that slot.
  140. *
  141. * A FIFO write goes to the end of the FIFO queue, but DMA running in background
  142. * is always the last queue entry (transfers by CPU intervene and come 1st).
  143. * There can be more pending writes than FIFO slots, but the CPU will be blocked
  144. * until FIFO level (without background DMA) <= 4.
  145. * This is only about correct timing, data xfer must be handled by the caller.
  146. * Blocking the CPU means burning cycles via SekCyclesBurn*(), which is to be
  147. * executed by the caller.
  148. *
  149. * FIFOSync "executes" FIFO write slots up to the given cycle in the current
  150. * scanline. A queue entry completely executed is removed from the queue.
  151. * FIFOWrite pushes writes to the transfer queue. If it's a blocking write, 68k
  152. * is blocked if more than 4 FIFO writes are pending.
  153. * FIFORead executes a 68k read. 68k is blocked until the next transfer slot.
  154. */
  155. // NB code assumes fifo_* arrays have size 2^n
  156. static struct VdpFIFO { // XXX this must go into save file!
  157. // last transferred FIFO data, ...x = index XXX currently only CPU
  158. u16 fifo_data[4], fifo_dx;
  159. // queued FIFO transfers, ...x = index, ...l = queue length
  160. // each entry has 2 values: [n]>>3 = #writes, [n]&7 = flags (FQ_*)
  161. u32 fifo_queue[8], fifo_qx, fifo_ql;
  162. int fifo_total; // total# of pending FIFO entries (w/o BGDMA)
  163. unsigned short fifo_slot; // last executed slot in current scanline
  164. unsigned short fifo_maxslot;// #slots in scanline
  165. const unsigned short *fifo_cyc2sl;
  166. const unsigned short *fifo_sl2cyc;
  167. } VdpFIFO;
  168. enum { FQ_BYTE = 1, FQ_BGDMA = 2, FQ_FGDMA = 4 }; // queue flags, NB: BYTE = 1!
  169. // NB should limit cyc2sl to table size in case 68k overdraws its aim. That can
  170. // happen if the last op is a blocking acess to VDP, or for exceptions (e.g.irq)
  171. #define Cyc2Sl(vf,lc) (vf->fifo_cyc2sl[(lc)/clkdiv])
  172. #define Sl2Cyc(vf,sl) (vf->fifo_sl2cyc[sl]*clkdiv)
  173. // do the FIFO math
  174. static __inline int AdvanceFIFOEntry(struct VdpFIFO *vf, struct PicoVideo *pv, int slots)
  175. {
  176. int l = slots, b = vf->fifo_queue[vf->fifo_qx] & FQ_BYTE;
  177. int cnt = pv->fifo_cnt;
  178. // advance currently active FIFO entry
  179. if (l > cnt)
  180. l = cnt;
  181. if (!(vf->fifo_queue[vf->fifo_qx] & FQ_BGDMA))
  182. vf->fifo_total -= ((cnt & b) + l) >> b;
  183. cnt -= l;
  184. pv->fifo_cnt = cnt;
  185. // if entry has been processed...
  186. if (cnt == 0) {
  187. // remove entry from FIFO
  188. vf->fifo_queue[vf->fifo_qx] = 0;
  189. vf->fifo_qx = (vf->fifo_qx+1) & 7, vf->fifo_ql --;
  190. // start processing for next entry if there is one
  191. if (vf->fifo_ql) {
  192. b = vf->fifo_queue[vf->fifo_qx] & FQ_BYTE;
  193. pv->fifo_cnt = (vf->fifo_queue[vf->fifo_qx] >> 3) << b;
  194. } else { // FIFO empty
  195. pv->status &= ~PVS_FIFORUN;
  196. vf->fifo_total = 0;
  197. }
  198. }
  199. return l;
  200. }
  201. static __inline void SetFIFOState(struct VdpFIFO *vf, struct PicoVideo *pv)
  202. {
  203. u32 st = pv->status, cmd = pv->command;
  204. // release CPU and terminate DMA if FIFO isn't blocking the 68k anymore
  205. if (vf->fifo_total <= 4) {
  206. st &= ~PVS_CPUWR;
  207. if (!(st & (PVS_DMABG|PVS_DMAFILL))) {
  208. st &= ~SR_DMA;
  209. cmd &= ~0x80;
  210. }
  211. }
  212. if (pv->fifo_cnt == 0) {
  213. st &= ~PVS_CPURD;
  214. // terminate DMA if applicable
  215. if (!(st & (PVS_FIFORUN|PVS_DMAFILL))) {
  216. st &= ~(SR_DMA|PVS_DMABG);
  217. cmd &= ~0x80;
  218. }
  219. }
  220. pv->status = st;
  221. pv->command = cmd;
  222. }
  223. // sync FIFO to cycles
  224. void PicoVideoFIFOSync(int cycles)
  225. {
  226. struct VdpFIFO *vf = &VdpFIFO;
  227. struct PicoVideo *pv = &Pico.video;
  228. int slots, done;
  229. // calculate #slots since last executed slot
  230. slots = Cyc2Sl(vf, cycles) - vf->fifo_slot;
  231. // advance FIFO queue by #done slots
  232. done = slots;
  233. while (done > 0 && pv->fifo_cnt) {
  234. int l = AdvanceFIFOEntry(vf, pv, done);
  235. vf->fifo_slot += l;
  236. done -= l;
  237. }
  238. if (done != slots)
  239. SetFIFOState(vf, pv);
  240. }
  241. // drain FIFO, blocking 68k on the way. FIFO must be synced prior to drain.
  242. static int PicoVideoFIFODrain(int level, int cycles, int bgdma)
  243. {
  244. struct VdpFIFO *vf = &VdpFIFO;
  245. struct PicoVideo *pv = &Pico.video;
  246. unsigned ocyc = cycles;
  247. int bd = vf->fifo_queue[vf->fifo_qx] & bgdma;
  248. int burn = 0;
  249. // process FIFO entries until low level is reached
  250. while (vf->fifo_slot < vf->fifo_maxslot &&
  251. vf->fifo_ql && ((vf->fifo_total > level) | bd)) {
  252. int b = vf->fifo_queue[vf->fifo_qx] & FQ_BYTE;
  253. int cnt = bd ? pv->fifo_cnt : ((vf->fifo_total-level)<<b) - (pv->fifo_cnt&b);
  254. int slot = (pv->fifo_cnt<cnt ? pv->fifo_cnt:cnt) + vf->fifo_slot;
  255. if (slot > vf->fifo_maxslot) {
  256. // target slot in later scanline, advance to eol
  257. slot = vf->fifo_maxslot;
  258. }
  259. if (slot > vf->fifo_slot) {
  260. // advance FIFO to target slot and CPU to cycles at that slot
  261. vf->fifo_slot += AdvanceFIFOEntry(vf, pv, slot - vf->fifo_slot);
  262. cycles = Sl2Cyc(vf, vf->fifo_slot);
  263. bd = vf->fifo_queue[vf->fifo_qx] & bgdma;
  264. }
  265. }
  266. if (vf->fifo_ql && ((vf->fifo_total > level) | bd))
  267. cycles = 488; // not completed in this scanline
  268. if (cycles > ocyc)
  269. burn = cycles - ocyc;
  270. SetFIFOState(vf, pv);
  271. return burn;
  272. }
  273. // read VDP data port
  274. static int PicoVideoFIFORead(void)
  275. {
  276. struct VdpFIFO *vf = &VdpFIFO;
  277. struct PicoVideo *pv = &Pico.video;
  278. int lc = SekCyclesDone()-Pico.t.m68c_line_start;
  279. int burn = 0;
  280. if (pv->fifo_cnt) {
  281. PicoVideoFIFOSync(lc);
  282. // advance FIFO and CPU until FIFO is empty
  283. burn = PicoVideoFIFODrain(0, lc, FQ_BGDMA);
  284. lc += burn;
  285. }
  286. if (pv->fifo_cnt)
  287. pv->status |= PVS_CPURD; // target slot is in later scanline
  288. else {
  289. // use next VDP access slot for reading, block 68k until then
  290. vf->fifo_slot = Cyc2Sl(vf, lc) + 1;
  291. burn += Sl2Cyc(vf, vf->fifo_slot) - lc;
  292. }
  293. return burn;
  294. }
  295. // write VDP data port
  296. int PicoVideoFIFOWrite(int count, int flags, unsigned sr_mask,unsigned sr_flags)
  297. {
  298. struct VdpFIFO *vf = &VdpFIFO;
  299. struct PicoVideo *pv = &Pico.video;
  300. int lc = SekCyclesDone()-Pico.t.m68c_line_start;
  301. int burn = 0;
  302. if (pv->fifo_cnt)
  303. PicoVideoFIFOSync(lc);
  304. pv->status = (pv->status & ~sr_mask) | sr_flags;
  305. if (count && vf->fifo_ql < 8) {
  306. // determine queue position for entry
  307. int x = (vf->fifo_qx + vf->fifo_ql - 1) & 7;
  308. if (unlikely(vf->fifo_queue[x] & FQ_BGDMA)) {
  309. // CPU FIFO writes have priority over a background DMA Fill/Copy
  310. // XXX if interrupting a DMA fill, fill data changes
  311. if (x == vf->fifo_qx) { // overtaking to queue head?
  312. int f = vf->fifo_queue[x] & 7;
  313. vf->fifo_queue[x] = (pv->fifo_cnt >> (f & FQ_BYTE) << 3) | f;
  314. pv->status &= ~PVS_FIFORUN;
  315. }
  316. // push background DMA back
  317. vf->fifo_queue[(x+1) & 7] = vf->fifo_queue[x];
  318. x = (x-1) & 7;
  319. }
  320. if ((pv->status & PVS_FIFORUN) && (vf->fifo_queue[x] & 7) == flags) {
  321. // amalgamate entries if of same type
  322. vf->fifo_queue[x] += (count << 3);
  323. if (x == vf->fifo_qx)
  324. pv->fifo_cnt += count << (flags & FQ_BYTE);
  325. } else {
  326. // create new xfer queue entry
  327. vf->fifo_ql ++;
  328. x = (x+1) & 7;
  329. vf->fifo_queue[x] = (count << 3) | flags;
  330. }
  331. // update FIFO state if it was empty
  332. if (!(pv->status & PVS_FIFORUN)) {
  333. vf->fifo_slot = Cyc2Sl(vf, lc+7); // FIFO latency ~3 vdp slots
  334. pv->status |= PVS_FIFORUN;
  335. pv->fifo_cnt = count << (flags & FQ_BYTE);
  336. }
  337. if (!(flags & FQ_BGDMA))
  338. vf->fifo_total += count;
  339. }
  340. // if CPU is waiting for the bus, advance CPU and FIFO until bus is free
  341. if (pv->status & PVS_CPUWR)
  342. burn = PicoVideoFIFODrain(4, lc, 0);
  343. return burn;
  344. }
  345. // at HINT, advance FIFO to new scanline
  346. int PicoVideoFIFOHint(void)
  347. {
  348. struct VdpFIFO *vf = &VdpFIFO;
  349. struct PicoVideo *pv = &Pico.video;
  350. int burn = 0;
  351. // reset slot to start of scanline
  352. vf->fifo_slot = 0;
  353. // if CPU is waiting for the bus, advance CPU and FIFO until bus is free
  354. if (pv->status & PVS_CPUWR)
  355. burn = PicoVideoFIFOWrite(0, 0, 0, 0);
  356. else if (pv->status & PVS_CPURD)
  357. burn = PicoVideoFIFORead();
  358. return burn;
  359. }
  360. // switch FIFO mode between active/inactive display
  361. void PicoVideoFIFOMode(int active, int h40)
  362. {
  363. static const unsigned short *vdpcyc2sl[2][2] =
  364. { {vdpcyc2sl_32_bl, vdpcyc2sl_40_bl},{vdpcyc2sl_32_ac, vdpcyc2sl_40_ac} };
  365. static const unsigned short *vdpsl2cyc[2][2] =
  366. { {vdpsl2cyc_32_bl, vdpsl2cyc_40_bl},{vdpsl2cyc_32_ac, vdpsl2cyc_40_ac} };
  367. struct VdpFIFO *vf = &VdpFIFO;
  368. struct PicoVideo *pv = &Pico.video;
  369. int lc = SekCyclesDone() - Pico.t.m68c_line_start;
  370. active = active && !(pv->status & PVS_VB2);
  371. if (vf->fifo_maxslot)
  372. PicoVideoFIFOSync(lc);
  373. vf->fifo_cyc2sl = vdpcyc2sl[active][h40];
  374. vf->fifo_sl2cyc = vdpsl2cyc[active][h40];
  375. // recalculate FIFO slot for new mode
  376. vf->fifo_slot = Cyc2Sl(vf, lc);
  377. vf->fifo_maxslot = Cyc2Sl(vf, 488);
  378. }
  379. // VDP memory rd/wr
  380. static __inline void AutoIncrement(void)
  381. {
  382. Pico.video.addr=(unsigned short)(Pico.video.addr+Pico.video.reg[0xf]);
  383. if (Pico.video.addr < Pico.video.reg[0xf]) Pico.video.addr_u ^= 1;
  384. }
  385. static NOINLINE void VideoWriteVRAM128(u32 a, u16 d)
  386. {
  387. // nasty
  388. u32 b = ((a & 2) >> 1) | ((a & 0x400) >> 9) | (a & 0x3FC) | ((a & 0x1F800) >> 1);
  389. ((u8 *)PicoMem.vram)[b] = d;
  390. if (!(u16)((b^SATaddr) & SATmask))
  391. Pico.est.rendstatus |= PDRAW_DIRTY_SPRITES;
  392. if (((a^SATaddr) & SATmask) == 0)
  393. UpdateSAT(a, d);
  394. }
  395. static void VideoWrite(u16 d)
  396. {
  397. unsigned int a = Pico.video.addr;
  398. switch (Pico.video.type)
  399. {
  400. case 1: if (a & 1)
  401. d = (u16)((d << 8) | (d >> 8));
  402. a |= Pico.video.addr_u << 16;
  403. VideoWriteVRAM(a, d);
  404. break;
  405. case 3: if (PicoMem.cram [(a >> 1) & 0x3f] != d) Pico.m.dirtyPal = 1;
  406. PicoMem.cram [(a >> 1) & 0x3f] = d & 0xeee; break;
  407. case 5: PicoMem.vsram[(a >> 1) & 0x3f] = d & 0x7ff; break;
  408. case 0x81:
  409. a |= Pico.video.addr_u << 16;
  410. VideoWriteVRAM128(a, d);
  411. break;
  412. //default:elprintf(EL_ANOMALY, "VDP write %04x with bad type %i", d, Pico.video.type); break;
  413. }
  414. AutoIncrement();
  415. }
  416. static unsigned int VideoRead(int is_from_z80)
  417. {
  418. unsigned int a, d = VdpFIFO.fifo_data[(VdpFIFO.fifo_dx+1)&3];
  419. a=Pico.video.addr; a>>=1;
  420. if (!is_from_z80)
  421. SekCyclesBurnRun(PicoVideoFIFORead());
  422. switch (Pico.video.type)
  423. {
  424. case 0: d=PicoMem.vram [a & 0x7fff]; break;
  425. case 8: d=PicoMem.cram [a & 0x003f] | (d & ~0x0eee); break;
  426. case 4: if ((a & 0x3f) >= 0x28) a = 0;
  427. d=PicoMem.vsram [a & 0x003f] | (d & ~0x07ff); break;
  428. case 12:a=PicoMem.vram [a & 0x7fff]; if (Pico.video.addr&1) a >>= 8;
  429. d=(a & 0x00ff) | (d & ~0x00ff); break;
  430. default:elprintf(EL_ANOMALY, "VDP read with bad type %i", Pico.video.type); break;
  431. }
  432. AutoIncrement();
  433. return d;
  434. }
  435. // VDP DMA
  436. static int GetDmaLength(void)
  437. {
  438. struct PicoVideo *pvid=&Pico.video;
  439. int len=0;
  440. // 16-bit words to transfer:
  441. len =pvid->reg[0x13];
  442. len|=pvid->reg[0x14]<<8;
  443. len = ((len - 1) & 0xffff) + 1;
  444. return len;
  445. }
  446. static void DmaSlow(int len, u32 source)
  447. {
  448. u32 inc = Pico.video.reg[0xf];
  449. u32 a = Pico.video.addr | (Pico.video.addr_u << 16);
  450. u16 *r, *base = NULL;
  451. u32 mask = 0x1ffff;
  452. elprintf(EL_VDPDMA, "DmaSlow[%i] %06x->%04x len %i inc=%i blank %i [%u] @ %06x",
  453. Pico.video.type, source, a, len, inc, (Pico.video.status&SR_VB)||!(Pico.video.reg[1]&0x40),
  454. SekCyclesDone(), SekPc);
  455. SekCyclesBurnRun(PicoVideoFIFOWrite(len, FQ_FGDMA | (Pico.video.type == 1),
  456. PVS_DMABG, SR_DMA | PVS_CPUWR));
  457. if ((source & 0xe00000) == 0xe00000) { // Ram
  458. base = (u16 *)PicoMem.ram;
  459. mask = 0xffff;
  460. }
  461. else if (PicoIn.AHW & PAHW_MCD)
  462. {
  463. u8 r3 = Pico_mcd->s68k_regs[3];
  464. elprintf(EL_VDPDMA, "DmaSlow CD, r3=%02x", r3);
  465. if (source < 0x20000) { // Bios area
  466. base = (u16 *)Pico_mcd->bios;
  467. } else if ((source & 0xfc0000) == 0x200000) { // Word Ram
  468. if (!(r3 & 4)) { // 2M mode
  469. base = (u16 *)(Pico_mcd->word_ram2M + (source & 0x20000));
  470. } else {
  471. if (source < 0x220000) { // 1M mode
  472. int bank = r3 & 1;
  473. base = (u16 *)(Pico_mcd->word_ram1M[bank]);
  474. } else {
  475. DmaSlowCell(source - 2, a, len, inc);
  476. return;
  477. }
  478. }
  479. source -= 2;
  480. } else if ((source & 0xfe0000) == 0x020000) { // Prg Ram
  481. base = (u16 *)Pico_mcd->prg_ram_b[r3 >> 6];
  482. source -= 2; // XXX: test
  483. }
  484. }
  485. else
  486. {
  487. // if we have DmaHook, let it handle ROM because of possible DMA delay
  488. u32 source2;
  489. if (PicoDmaHook && (source2 = PicoDmaHook(source, len, &base, &mask)))
  490. source = source2;
  491. else // Rom
  492. base = m68k_dma_source(source);
  493. }
  494. if (!base) {
  495. elprintf(EL_VDPDMA|EL_ANOMALY, "DmaSlow[%i] %06x->%04x: invalid src", Pico.video.type, source, a);
  496. return;
  497. }
  498. // operate in words
  499. source >>= 1;
  500. mask >>= 1;
  501. switch (Pico.video.type)
  502. {
  503. case 1: // vram
  504. r = PicoMem.vram;
  505. if (inc == 2 && !(a & 1) && (a & ~0xffff) == ((a + len*2-1) & ~0xffff) &&
  506. ((a >= SATaddr+0x280) | ((a + len*2-1) < SATaddr)) &&
  507. (source & ~mask) == ((source + len-1) & ~mask))
  508. {
  509. // most used DMA mode
  510. memcpy((char *)r + a, base + (source & mask), len * 2);
  511. a += len * 2;
  512. break;
  513. }
  514. for(; len; len--)
  515. {
  516. u16 d = base[source++ & mask];
  517. if(a & 1) d=(d<<8)|(d>>8);
  518. VideoWriteVRAM(a, d);
  519. // AutoIncrement
  520. a = (a+inc) & ~0x20000;
  521. }
  522. break;
  523. case 3: // cram
  524. Pico.m.dirtyPal = 1;
  525. r = PicoMem.cram;
  526. for (; len; len--)
  527. {
  528. r[(a / 2) & 0x3f] = base[source++ & mask] & 0xeee;
  529. // AutoIncrement
  530. a = (a+inc) & ~0x20000;
  531. }
  532. break;
  533. case 5: // vsram
  534. r = PicoMem.vsram;
  535. for (; len; len--)
  536. {
  537. r[(a / 2) & 0x3f] = base[source++ & mask] & 0x7ff;
  538. // AutoIncrement
  539. a = (a+inc) & ~0x20000;
  540. }
  541. break;
  542. case 0x81: // vram 128k
  543. for(; len; len--)
  544. {
  545. u16 d = base[source++ & mask];
  546. VideoWriteVRAM128(a, d);
  547. // AutoIncrement
  548. a = (a+inc) & ~0x20000;
  549. }
  550. break;
  551. default:
  552. if (Pico.video.type != 0 || (EL_LOGMASK & EL_VDPDMA))
  553. elprintf(EL_VDPDMA|EL_ANOMALY, "DMA with bad type %i", Pico.video.type);
  554. break;
  555. }
  556. // remember addr
  557. Pico.video.addr = a;
  558. Pico.video.addr_u = a >> 16;
  559. }
  560. static void DmaCopy(int len)
  561. {
  562. u32 a = Pico.video.addr | (Pico.video.addr_u << 16);
  563. u8 *vr = (u8 *)PicoMem.vram;
  564. u8 inc = Pico.video.reg[0xf];
  565. int source;
  566. elprintf(EL_VDPDMA, "DmaCopy len %i [%u]", len, SekCyclesDone());
  567. // XXX implement VRAM 128k? Is this even working? xfer/count still FQ_BYTE?
  568. SekCyclesBurnRun(PicoVideoFIFOWrite(len, FQ_BGDMA | FQ_BYTE,
  569. PVS_CPUWR, SR_DMA | PVS_DMABG));
  570. source =Pico.video.reg[0x15];
  571. source|=Pico.video.reg[0x16]<<8;
  572. for (; len; len--)
  573. {
  574. vr[(u16)a] = vr[(u16)(source++)];
  575. if (((a^SATaddr) & SATmask) == 0)
  576. UpdateSAT(a, ((u16 *)vr)[(u16)a >> 1]);
  577. // AutoIncrement
  578. a = (a+inc) & ~0x20000;
  579. }
  580. // remember addr
  581. Pico.video.addr = a;
  582. Pico.video.addr_u = a >> 16;
  583. }
  584. static NOINLINE void DmaFill(int data)
  585. {
  586. u32 a = Pico.video.addr | (Pico.video.addr_u << 16);
  587. u8 *vr = (u8 *)PicoMem.vram;
  588. u8 high = (u8)(data >> 8);
  589. u8 inc = Pico.video.reg[0xf];
  590. int source;
  591. int len, l;
  592. len = GetDmaLength();
  593. elprintf(EL_VDPDMA, "DmaFill len %i inc %i [%u]", len, inc, SekCyclesDone());
  594. SekCyclesBurnRun(PicoVideoFIFOWrite(len, FQ_BGDMA | (Pico.video.type == 1),
  595. PVS_CPUWR | PVS_DMAFILL, SR_DMA | PVS_DMABG));
  596. switch (Pico.video.type)
  597. {
  598. case 1: // vram
  599. if (inc == 1 && (a & ~0xffff) == ((a + len-1) & ~0xffff) &&
  600. ((a >= SATaddr+0x280) | ((a + len-1) < SATaddr)))
  601. {
  602. // most used DMA mode
  603. memset(vr + (u16)a, high, len);
  604. a += len;
  605. break;
  606. }
  607. for (l = len; l; l--) {
  608. // Write upper byte to adjacent address
  609. // (here we are byteswapped, so address is already 'adjacent')
  610. vr[(u16)a] = high;
  611. if (((a^SATaddr) & SATmask) == 0)
  612. UpdateSAT(a, ((u16 *)vr)[(u16)a >> 1]);
  613. // Increment address register
  614. a = (a+inc) & ~0x20000;
  615. }
  616. break;
  617. case 3: // cram
  618. Pico.m.dirtyPal = 1;
  619. data &= 0xeee;
  620. for (l = len; l; l--) {
  621. PicoMem.cram[(a/2) & 0x3f] = data;
  622. // Increment address register
  623. a = (a+inc) & ~0x20000;
  624. }
  625. break;
  626. case 5: { // vsram
  627. data &= 0x7ff;
  628. for (l = len; l; l--) {
  629. PicoMem.vsram[(a/2) & 0x3f] = data;
  630. // Increment address register
  631. a = (a+inc) & ~0x20000;
  632. }
  633. break;
  634. }
  635. case 0x81: // vram 128k
  636. for (l = len; l; l--) {
  637. VideoWriteVRAM128(a, data);
  638. // Increment address register
  639. a = (a+inc) & ~0x20000;
  640. }
  641. break;
  642. default:
  643. a += len * inc;
  644. break;
  645. }
  646. // remember addr
  647. Pico.video.addr = a;
  648. Pico.video.addr_u = a >> 16;
  649. // register update
  650. Pico.video.reg[0x13] = Pico.video.reg[0x14] = 0;
  651. source = Pico.video.reg[0x15];
  652. source |= Pico.video.reg[0x16] << 8;
  653. source += len;
  654. Pico.video.reg[0x15] = source;
  655. Pico.video.reg[0x16] = source >> 8;
  656. }
  657. // VDP command handling
  658. static NOINLINE void CommandDma(void)
  659. {
  660. struct PicoVideo *pvid=&Pico.video;
  661. u32 len, method;
  662. u32 source;
  663. PicoVideoFIFOSync(SekCyclesDone()-Pico.t.m68c_line_start);
  664. if (pvid->status & SR_DMA) {
  665. elprintf(EL_VDPDMA, "Dma overlap, left=%d @ %06x",
  666. VdpFIFO.fifo_total, SekPc);
  667. pvid->fifo_cnt = VdpFIFO.fifo_total = VdpFIFO.fifo_ql = 0;
  668. pvid->status &= ~(PVS_FIFORUN|PVS_DMAFILL);
  669. }
  670. len = GetDmaLength();
  671. source =Pico.video.reg[0x15];
  672. source|=Pico.video.reg[0x16] << 8;
  673. source|=Pico.video.reg[0x17] << 16;
  674. method=pvid->reg[0x17]>>6;
  675. if (method < 2)
  676. DmaSlow(len, source << 1); // 68000 to VDP
  677. else if (method == 3)
  678. DmaCopy(len); // VRAM Copy
  679. else {
  680. pvid->status |= SR_DMA|PVS_DMAFILL;
  681. return;
  682. }
  683. source += len;
  684. Pico.video.reg[0x13] = Pico.video.reg[0x14] = 0;
  685. Pico.video.reg[0x15] = source;
  686. Pico.video.reg[0x16] = source >> 8;
  687. }
  688. static NOINLINE void CommandChange(struct PicoVideo *pvid)
  689. {
  690. unsigned int cmd, addr;
  691. cmd = pvid->command;
  692. // Get type of transfer 0xc0000030 (v/c/vsram read/write)
  693. pvid->type = (u8)(((cmd >> 2) & 0xc) | (cmd >> 30));
  694. if (pvid->type == 1) // vram
  695. pvid->type |= pvid->reg[1] & 0x80; // 128k
  696. // Get address 0x3fff0003
  697. addr = (cmd >> 16) & 0x3fff;
  698. addr |= (cmd << 14) & 0xc000;
  699. pvid->addr = (u16)addr;
  700. pvid->addr_u = (u8)((cmd >> 2) & 1);
  701. }
  702. // VDP interface
  703. static void DrawSync(int skip)
  704. {
  705. int lines = Pico.video.reg[1]&0x08 ? 240 : 224;
  706. int last = Pico.m.scanline - (skip || blankline == Pico.m.scanline);
  707. if (last < lines && !(PicoIn.opt & POPT_ALT_RENDERER) &&
  708. !PicoIn.skipFrame && Pico.est.DrawScanline <= last) {
  709. //elprintf(EL_ANOMALY, "sync");
  710. if (blankline >= 0 && blankline < last) {
  711. PicoDrawSync(blankline, 1);
  712. blankline = -1;
  713. }
  714. PicoDrawSync(last, 0);
  715. }
  716. }
  717. PICO_INTERNAL_ASM void PicoVideoWrite(u32 a,unsigned short d)
  718. {
  719. struct PicoVideo *pvid=&Pico.video;
  720. //elprintf(EL_STATUS, "PicoVideoWrite [%06x] %04x [%u] @ %06x",
  721. // a, d, SekCyclesDone(), SekPc);
  722. a &= 0x1c;
  723. switch (a)
  724. {
  725. case 0x00: // Data port 0 or 2
  726. // try avoiding the sync..
  727. if (Pico.m.scanline < (pvid->reg[1]&0x08 ? 240 : 224) && (pvid->reg[1]&0x40) &&
  728. !(!pvid->pending && ((pvid->command & 0xc00000f0) == 0x40000010 &&
  729. PicoMem.vsram[(pvid->addr>>1) & 0x3f] == (d & 0x7ff)))
  730. )
  731. DrawSync(0); // XXX it's unclear when vscroll data is fetched from vsram?
  732. if (pvid->pending) {
  733. CommandChange(pvid);
  734. pvid->pending=0;
  735. }
  736. if (!(PicoIn.opt&POPT_DIS_VDP_FIFO))
  737. {
  738. VdpFIFO.fifo_data[++VdpFIFO.fifo_dx&3] = d;
  739. SekCyclesBurnRun(PicoVideoFIFOWrite(1, pvid->type == 1, 0, PVS_CPUWR));
  740. elprintf(EL_ASVDP, "VDP data write: [%04x] %04x [%u] {%i} @ %06x",
  741. Pico.video.addr, d, SekCyclesDone(), Pico.video.type, SekPc);
  742. }
  743. VideoWrite(d);
  744. // start DMA fill on write. NB VSRAM and CRAM fills use wrong FIFO data.
  745. if (pvid->status & PVS_DMAFILL)
  746. DmaFill(VdpFIFO.fifo_data[(VdpFIFO.fifo_dx + !!(pvid->type&~0x81))&3]);
  747. break;
  748. case 0x04: // Control (command) port 4 or 6
  749. if (pvid->status & SR_DMA)
  750. SekCyclesBurnRun(PicoVideoFIFORead()); // kludge, flush out running DMA
  751. if (pvid->pending)
  752. {
  753. // Low word of command:
  754. if (!(pvid->reg[1]&0x10))
  755. d = (d&~0x80)|(pvid->command&0x80);
  756. pvid->command &= 0xffff0000;
  757. pvid->command |= d;
  758. pvid->pending = 0;
  759. CommandChange(pvid);
  760. // Check for dma:
  761. if (d & 0x80) {
  762. DrawSync(SekCyclesDone() - Pico.t.m68c_line_start <= 488-390);
  763. CommandDma();
  764. }
  765. }
  766. else
  767. {
  768. if ((d&0xc000)==0x8000)
  769. {
  770. // Register write:
  771. int num=(d>>8)&0x1f;
  772. int dold=pvid->reg[num];
  773. pvid->type=0; // register writes clear command (else no Sega logo in Golden Axe II)
  774. if (num > 0x0a && !(pvid->reg[1]&4)) {
  775. elprintf(EL_ANOMALY, "%02x written to reg %02x in SMS mode @ %06x", d, num, SekPc);
  776. return;
  777. }
  778. if (num == 0 && !(pvid->reg[0]&2) && (d&2))
  779. pvid->hv_latch = PicoVideoRead(0x08);
  780. if (num == 1 && ((pvid->reg[1]^d)&0x40)) {
  781. PicoVideoFIFOMode(d & 0x40, pvid->reg[12]&1);
  782. // handle line blanking before line rendering
  783. if (SekCyclesDone() - Pico.t.m68c_line_start <= 488-390)
  784. blankline = d&0x40 ? -1 : Pico.m.scanline;
  785. }
  786. if (num == 12 && ((pvid->reg[12]^d)&0x01))
  787. PicoVideoFIFOMode(pvid->reg[1]&0x40, d & 1);
  788. DrawSync(SekCyclesDone() - Pico.t.m68c_line_start <= 488-390);
  789. d &= 0xff;
  790. pvid->reg[num]=(unsigned char)d;
  791. switch (num)
  792. {
  793. case 0x00:
  794. elprintf(EL_INTSW, "hint_onoff: %i->%i [%u] pend=%i @ %06x", (dold&0x10)>>4,
  795. (d&0x10)>>4, SekCyclesDone(), (pvid->pending_ints&0x10)>>4, SekPc);
  796. goto update_irq;
  797. case 0x01:
  798. elprintf(EL_INTSW, "vint_onoff: %i->%i [%u] pend=%i @ %06x", (dold&0x20)>>5,
  799. (d&0x20)>>5, SekCyclesDone(), (pvid->pending_ints&0x20)>>5, SekPc);
  800. if (!(pvid->status & PVS_VB2))
  801. pvid->status &= ~SR_VB;
  802. pvid->status |= ((d >> 3) ^ SR_VB) & SR_VB; // forced blanking
  803. goto update_irq;
  804. case 0x05:
  805. case 0x06:
  806. if (d^dold) Pico.est.rendstatus |= PDRAW_SPRITES_MOVED;
  807. break;
  808. case 0x0c:
  809. // renderers should update their palettes if sh/hi mode is changed
  810. if ((d^dold)&8) Pico.m.dirtyPal = 1;
  811. break;
  812. default:
  813. return;
  814. }
  815. SATaddr = ((pvid->reg[5]&0x7f) << 9) | ((pvid->reg[6]&0x20) << 11);
  816. SATmask = ~0x1ff;
  817. if (Pico.video.reg[12]&1)
  818. SATaddr &= ~0x200, SATmask &= ~0x200; // H40, zero lowest SAT bit
  819. //elprintf(EL_STATUS, "spritep moved to %04x", SATaddr);
  820. return;
  821. update_irq:
  822. #ifndef EMU_CORE_DEBUG
  823. // update IRQ level
  824. if (!SekShouldInterrupt()) // hack
  825. {
  826. int lines, pints, irq = 0;
  827. lines = (pvid->reg[1] & 0x20) | (pvid->reg[0] & 0x10);
  828. pints = pvid->pending_ints & lines;
  829. if (pints & 0x20) irq = 6;
  830. else if (pints & 0x10) irq = 4;
  831. SekInterrupt(irq); // update line
  832. // this is broken because cost of current insn isn't known here
  833. if (irq) SekEndRun(21); // make it delayed
  834. }
  835. #endif
  836. }
  837. else
  838. {
  839. // High word of command:
  840. pvid->command&=0x0000ffff;
  841. pvid->command|=d<<16;
  842. pvid->pending=1;
  843. }
  844. }
  845. break;
  846. // case 0x08: // 08 0a - HV counter - lock up
  847. // case 0x0c: // 0c 0e - HV counter - lock up
  848. // case 0x10: // 10 12 - PSG - handled by caller
  849. // case 0x14: // 14 16 - PSG - handled by caller
  850. // case 0x18: // 18 1a - no effect?
  851. case 0x1c: // 1c 1e - debug
  852. pvid->debug = d;
  853. pvid->debug_p = 0;
  854. if (d & (1 << 6)) {
  855. pvid->debug_p |= PVD_KILL_A | PVD_KILL_B;
  856. pvid->debug_p |= PVD_KILL_S_LO | PVD_KILL_S_HI;
  857. }
  858. switch ((d >> 7) & 3) {
  859. case 1:
  860. pvid->debug_p &= ~(PVD_KILL_S_LO | PVD_KILL_S_HI);
  861. pvid->debug_p |= PVD_FORCE_S;
  862. break;
  863. case 2:
  864. pvid->debug_p &= ~PVD_KILL_A;
  865. pvid->debug_p |= PVD_FORCE_A;
  866. break;
  867. case 3:
  868. pvid->debug_p &= ~PVD_KILL_B;
  869. pvid->debug_p |= PVD_FORCE_B;
  870. break;
  871. }
  872. break;
  873. }
  874. }
  875. static u32 VideoSr(const struct PicoVideo *pv)
  876. {
  877. unsigned int hp = pv->reg[12]&1 ? hboff40*488/slots40 : hboff32*488/slots32;
  878. unsigned int hl = pv->reg[12]&1 ? hblen40*488/slots40 : hblen32*488/slots32;
  879. unsigned int c;
  880. u32 d = (u16)pv->status;
  881. c = SekCyclesDone() - Pico.t.m68c_line_start;
  882. if (c - hp < hl)
  883. d |= SR_HB;
  884. PicoVideoFIFOSync(c);
  885. if (VdpFIFO.fifo_total >= 4)
  886. d |= SR_FULL;
  887. else if (!VdpFIFO.fifo_total)
  888. d |= SR_EMPT;
  889. return d;
  890. }
  891. PICO_INTERNAL_ASM u32 PicoVideoRead(u32 a)
  892. {
  893. a &= 0x1c;
  894. if (a == 0x04) // control port
  895. {
  896. struct PicoVideo *pv = &Pico.video;
  897. u32 d = VideoSr(pv);
  898. if (pv->pending) {
  899. CommandChange(pv);
  900. pv->pending = 0;
  901. }
  902. elprintf(EL_SR, "SR read: %04x [%u] @ %06x", d, SekCyclesDone(), SekPc);
  903. return d;
  904. }
  905. if ((a&0x1c)==0x08)
  906. {
  907. unsigned int c;
  908. u32 d;
  909. c = SekCyclesDone() - Pico.t.m68c_line_start;
  910. if (Pico.video.reg[0]&2)
  911. d = Pico.video.hv_latch;
  912. else if (Pico.video.reg[12]&1)
  913. d = hcounts_40[c/clkdiv] | (Pico.video.v_counter << 8);
  914. else d = hcounts_32[c/clkdiv] | (Pico.video.v_counter << 8);
  915. elprintf(EL_HVCNT, "hv: %02x %02x [%u] @ %06x", d, Pico.video.v_counter, SekCyclesDone(), SekPc);
  916. return d;
  917. }
  918. if (a==0x00) // data port
  919. {
  920. return VideoRead(0);
  921. }
  922. return 0;
  923. }
  924. unsigned char PicoVideoRead8DataH(int is_from_z80)
  925. {
  926. return VideoRead(is_from_z80) >> 8;
  927. }
  928. unsigned char PicoVideoRead8DataL(int is_from_z80)
  929. {
  930. return VideoRead(is_from_z80);
  931. }
  932. unsigned char PicoVideoRead8CtlH(int is_from_z80)
  933. {
  934. struct PicoVideo *pv = &Pico.video;
  935. u8 d = VideoSr(pv) >> 8;
  936. if (pv->pending) {
  937. CommandChange(pv);
  938. pv->pending = 0;
  939. }
  940. elprintf(EL_SR, "SR read (h): %02x @ %06x", d, SekPc);
  941. return d;
  942. }
  943. unsigned char PicoVideoRead8CtlL(int is_from_z80)
  944. {
  945. struct PicoVideo *pv = &Pico.video;
  946. u8 d = VideoSr(pv);
  947. if (pv->pending) {
  948. CommandChange(pv);
  949. pv->pending = 0;
  950. }
  951. elprintf(EL_SR, "SR read (l): %02x @ %06x", d, SekPc);
  952. return d;
  953. }
  954. unsigned char PicoVideoRead8HV_H(int is_from_z80)
  955. {
  956. elprintf(EL_HVCNT, "vcounter: %02x [%u] @ %06x", Pico.video.v_counter, SekCyclesDone(), SekPc);
  957. return Pico.video.v_counter;
  958. }
  959. // FIXME: broken
  960. unsigned char PicoVideoRead8HV_L(int is_from_z80)
  961. {
  962. u32 d = SekCyclesDone() - Pico.t.m68c_line_start;
  963. if (Pico.video.reg[0]&2)
  964. d = Pico.video.hv_latch;
  965. else if (Pico.video.reg[12]&1)
  966. d = hcounts_40[d/clkdiv];
  967. else d = hcounts_32[d/clkdiv];
  968. elprintf(EL_HVCNT, "hcounter: %02x [%u] @ %06x", d, SekCyclesDone(), SekPc);
  969. return d;
  970. }
  971. void PicoVideoCacheSAT(void)
  972. {
  973. struct PicoVideo *pv = &Pico.video;
  974. int l;
  975. SATaddr = ((pv->reg[5]&0x7f) << 9) | ((pv->reg[6]&0x20) << 11);
  976. SATmask = ~0x1ff;
  977. if (pv->reg[12]&1)
  978. SATaddr &= ~0x200, SATmask &= ~0x200; // H40, zero lowest SAT bit
  979. // rebuild SAT cache XXX wrong since cache and memory can differ
  980. for (l = 0; l < 80; l++) {
  981. ((u16 *)VdpSATCache)[l*2 ] = PicoMem.vram[(SATaddr>>1) + l*4 ];
  982. ((u16 *)VdpSATCache)[l*2 + 1] = PicoMem.vram[(SATaddr>>1) + l*4 + 1];
  983. }
  984. Pico.est.rendstatus |= PDRAW_SPRITES_MOVED;
  985. }
  986. void PicoVideoSave(void)
  987. {
  988. struct VdpFIFO *vf = &VdpFIFO;
  989. struct PicoVideo *pv = &Pico.video;
  990. int l, x;
  991. // account for all outstanding xfers XXX kludge, entry attr's not saved
  992. for (l = vf->fifo_ql, x = vf->fifo_qx + l-1; l > 1; l--, x--)
  993. pv->fifo_cnt += (vf->fifo_queue[x&7] >> 3) << (vf->fifo_queue[x&7] & FQ_BYTE);
  994. }
  995. void PicoVideoLoad(void)
  996. {
  997. struct VdpFIFO *vf = &VdpFIFO;
  998. struct PicoVideo *pv = &Pico.video;
  999. int b = pv->type == 1;
  1000. // convert former dma_xfers (why was this in PicoMisc anyway?)
  1001. if (Pico.m.dma_xfers) {
  1002. pv->status |= SR_DMA;
  1003. pv->fifo_cnt = Pico.m.dma_xfers << b;
  1004. Pico.m.dma_xfers = 0;
  1005. }
  1006. // make an entry in the FIFO if there are outstanding transfers
  1007. vf->fifo_ql = vf->fifo_total = 0;
  1008. if (pv->fifo_cnt) {
  1009. pv->status |= PVS_FIFORUN|PVS_CPUWR;
  1010. if (!(pv->status & PVS_DMABG))
  1011. vf->fifo_total = (pv->fifo_cnt + b) >> b;
  1012. if ((pv->status & SR_DMA) && !(pv->status & PVS_DMAFILL))
  1013. b |= (pv->status & PVS_DMABG) ? FQ_BGDMA : FQ_FGDMA;
  1014. vf->fifo_queue[vf->fifo_qx] = (vf->fifo_total << 3) | b;
  1015. vf->fifo_ql = 1;
  1016. }
  1017. PicoVideoCacheSAT();
  1018. }
  1019. // vim:shiftwidth=2:ts=2:expandtab