eeprom.c 6.9 KB

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  1. /*
  2. * rarely used EEPROM code
  3. * (C) notaz, 2007-2009
  4. *
  5. * This work is licensed under the terms of MAME license.
  6. * See COPYING file in the top-level directory.
  7. *
  8. * (see Genesis Plus for Wii/GC code and docs for info,
  9. * full game list and better code).
  10. */
  11. #include "pico_int.h"
  12. static unsigned int last_write = 0xffff0000;
  13. // eeprom_status: LA.. s.la (L=pending SCL, A=pending SDA,
  14. // s=started, l=old SCL, a=old SDA)
  15. static void EEPROM_write_do(unsigned int d) // ???? ??la (l=SCL, a=SDA)
  16. {
  17. unsigned int sreg = Pico.m.eeprom_status, saddr = Pico.m.eeprom_addr;
  18. unsigned int scyc = Pico.m.eeprom_cycle, ssa = Pico.m.eeprom_slave;
  19. elprintf(EL_EEPROM, "eeprom: scl/sda: %i/%i -> %i/%i, newtime=%i", (sreg&2)>>1, sreg&1,
  20. (d&2)>>1, d&1, SekCyclesDone() - last_write);
  21. saddr &= 0x1fff;
  22. if(sreg & d & 2) {
  23. // SCL was and is still high..
  24. if((sreg & 1) && !(d&1)) {
  25. // ..and SDA went low, means it's a start command, so clear internal addr reg and clock counter
  26. elprintf(EL_EEPROM, "eeprom: -start-");
  27. //saddr = 0;
  28. scyc = 0;
  29. sreg |= 8;
  30. } else if(!(sreg & 1) && (d&1)) {
  31. // SDA went high == stop command
  32. elprintf(EL_EEPROM, "eeprom: -stop-");
  33. sreg &= ~8;
  34. }
  35. }
  36. else if((sreg & 8) && !(sreg & 2) && (d&2))
  37. {
  38. // we are started and SCL went high - next cycle
  39. scyc++; // pre-increment
  40. if(Pico.sv.eeprom_type) {
  41. // X24C02+
  42. if((ssa&1) && scyc == 18) {
  43. scyc = 9;
  44. saddr++; // next address in read mode
  45. /*if(Pico.sv.eeprom_type==2) saddr&=0xff; else*/ saddr&=0x1fff; // mask
  46. }
  47. else if(Pico.sv.eeprom_type == 2 && scyc == 27) scyc = 18;
  48. else if(scyc == 36) scyc = 27;
  49. } else {
  50. // X24C01
  51. if(scyc == 18) {
  52. scyc = 9; // wrap
  53. if(saddr&1) { saddr+=2; saddr&=0xff; } // next addr in read mode
  54. }
  55. }
  56. elprintf(EL_EEPROM, "eeprom: scyc: %i", scyc);
  57. }
  58. else if((sreg & 8) && (sreg & 2) && !(d&2))
  59. {
  60. // we are started and SCL went low (falling edge)
  61. if(Pico.sv.eeprom_type) {
  62. // X24C02+
  63. if(scyc == 9 || scyc == 18 || scyc == 27); // ACK cycles
  64. else if( (Pico.sv.eeprom_type == 3 && scyc > 27) || (Pico.sv.eeprom_type == 2 && scyc > 18) ) {
  65. if(!(ssa&1)) {
  66. // data write
  67. unsigned char *pm=Pico.sv.data+saddr;
  68. *pm <<= 1; *pm |= d&1;
  69. if(scyc == 26 || scyc == 35) {
  70. saddr=(saddr&~0xf)|((saddr+1)&0xf); // only 4 (?) lowest bits are incremented
  71. elprintf(EL_EEPROM, "eeprom: write done, addr inc to: %x, last byte=%02x", saddr, *pm);
  72. }
  73. Pico.sv.changed = 1;
  74. }
  75. } else if(scyc > 9) {
  76. if(!(ssa&1)) {
  77. // we latch another addr bit
  78. saddr<<=1;
  79. if(Pico.sv.eeprom_type == 2) saddr&=0xff; else saddr&=0x1fff; // mask
  80. saddr|=d&1;
  81. if(scyc==17||scyc==26) {
  82. elprintf(EL_EEPROM, "eeprom: addr reg done: %x", saddr);
  83. if(scyc==17&&Pico.sv.eeprom_type==2) { saddr&=0xff; saddr|=(ssa<<7)&0x700; } // add device bits too
  84. }
  85. }
  86. } else {
  87. // slave address
  88. ssa<<=1; ssa|=d&1;
  89. if(scyc==8) elprintf(EL_EEPROM, "eeprom: slave done: %x", ssa);
  90. }
  91. } else {
  92. // X24C01
  93. if(scyc == 9); // ACK cycle, do nothing
  94. else if(scyc > 9) {
  95. if(!(saddr&1)) {
  96. // data write
  97. unsigned char *pm=Pico.sv.data+(saddr>>1);
  98. *pm <<= 1; *pm |= d&1;
  99. if(scyc == 17) {
  100. saddr=(saddr&0xf9)|((saddr+2)&6); // only 2 lowest bits are incremented
  101. elprintf(EL_EEPROM, "eeprom: write done, addr inc to: %x, last byte=%02x", saddr>>1, *pm);
  102. }
  103. Pico.sv.changed = 1;
  104. }
  105. } else {
  106. // we latch another addr bit
  107. saddr<<=1; saddr|=d&1; saddr&=0xff;
  108. if(scyc==8) elprintf(EL_EEPROM, "eeprom: addr done: %x", saddr>>1);
  109. }
  110. }
  111. }
  112. sreg &= ~3; sreg |= d&3; // remember SCL and SDA
  113. Pico.m.eeprom_status = (unsigned char) sreg;
  114. Pico.m.eeprom_cycle = (unsigned char) scyc;
  115. Pico.m.eeprom_slave = (unsigned char) ssa;
  116. Pico.m.eeprom_addr = (unsigned short)saddr;
  117. }
  118. static void EEPROM_upd_pending(unsigned int d)
  119. {
  120. unsigned int d1, sreg = Pico.m.eeprom_status;
  121. sreg &= ~0xc0;
  122. // SCL
  123. d1 = (d >> Pico.sv.eeprom_bit_cl) & 1;
  124. sreg |= d1 << 7;
  125. // SDA in
  126. d1 = (d >> Pico.sv.eeprom_bit_in) & 1;
  127. sreg |= d1 << 6;
  128. Pico.m.eeprom_status = (unsigned char) sreg;
  129. }
  130. void EEPROM_write16(unsigned int d)
  131. {
  132. // this diff must be at most 16 for NBA Jam to work
  133. if (SekCyclesDone() - last_write < 16) {
  134. // just update pending state
  135. elprintf(EL_EEPROM, "eeprom: skip because cycles=%i",
  136. SekCyclesDone() - last_write);
  137. EEPROM_upd_pending(d);
  138. } else {
  139. int srs = Pico.m.eeprom_status;
  140. EEPROM_write_do(srs >> 6); // execute pending
  141. EEPROM_upd_pending(d);
  142. if ((srs ^ Pico.m.eeprom_status) & 0xc0) // update time only if SDA/SCL changed
  143. last_write = SekCyclesDone();
  144. }
  145. }
  146. void EEPROM_write8(unsigned int a, unsigned int d)
  147. {
  148. unsigned char *wb = Pico.m.eeprom_wb;
  149. wb[a & 1] = d;
  150. EEPROM_write16((wb[0] << 8) | wb[1]);
  151. }
  152. unsigned int EEPROM_read(void)
  153. {
  154. unsigned int shift, d;
  155. unsigned int sreg, saddr, scyc, ssa, interval;
  156. // flush last pending write
  157. EEPROM_write_do(Pico.m.eeprom_status>>6);
  158. sreg = Pico.m.eeprom_status; saddr = Pico.m.eeprom_addr&0x1fff; scyc = Pico.m.eeprom_cycle; ssa = Pico.m.eeprom_slave;
  159. interval = SekCyclesDone() - last_write;
  160. d = (sreg>>6)&1; // use SDA as "open bus"
  161. // NBA Jam is nasty enough to read <before> raising the SCL and starting the new cycle.
  162. // this is probably valid because data changes occur while SCL is low and data can be read
  163. // before it's actual cycle begins.
  164. if (!(sreg&0x80) && interval >= 24) {
  165. elprintf(EL_EEPROM, "eeprom: early read, cycles=%i", interval);
  166. scyc++;
  167. }
  168. if (!(sreg & 8)); // not started, use open bus
  169. else if (scyc == 9 || scyc == 18 || scyc == 27) {
  170. elprintf(EL_EEPROM, "eeprom: r ack");
  171. d = 0;
  172. } else if (scyc > 9 && scyc < 18) {
  173. // started and first command word received
  174. shift = 17-scyc;
  175. if (Pico.sv.eeprom_type) {
  176. // X24C02+
  177. if (ssa&1) {
  178. elprintf(EL_EEPROM, "eeprom: read: addr %02x, cycle %i, reg %02x", saddr, scyc, sreg);
  179. if (shift==0) elprintf(EL_EEPROM, "eeprom: read done, byte %02x", Pico.sv.data[saddr]);
  180. d = (Pico.sv.data[saddr]>>shift)&1;
  181. }
  182. } else {
  183. // X24C01
  184. if (saddr&1) {
  185. elprintf(EL_EEPROM, "eeprom: read: addr %02x, cycle %i, reg %02x", saddr>>1, scyc, sreg);
  186. if (shift==0) elprintf(EL_EEPROM, "eeprom: read done, byte %02x", Pico.sv.data[saddr>>1]);
  187. d = (Pico.sv.data[saddr>>1]>>shift)&1;
  188. }
  189. }
  190. }
  191. return (d << Pico.sv.eeprom_bit_out);
  192. }