cdc.c 20 KB

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  1. /***************************************************************************************
  2. * Genesis Plus
  3. * CD data controller (LC89510 compatible)
  4. *
  5. * Copyright (C) 2012 Eke-Eke (Genesis Plus GX)
  6. *
  7. * Redistribution and use of this code or any derivative works are permitted
  8. * provided that the following conditions are met:
  9. *
  10. * - Redistributions may not be sold, nor may they be used in a commercial
  11. * product or activity.
  12. *
  13. * - Redistributions that are modified from the original source must include the
  14. * complete source code, including the source code for all components used by a
  15. * binary built from the modified sources. However, as a special exception, the
  16. * source code distributed need not include anything that is normally distributed
  17. * (in either source or binary form) with the major components (compiler, kernel,
  18. * and so on) of the operating system on which the executable runs, unless that
  19. * component itself accompanies the executable.
  20. *
  21. * - Redistributions must reproduce the above copyright notice, this list of
  22. * conditions and the following disclaimer in the documentation and/or other
  23. * materials provided with the distribution.
  24. *
  25. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  26. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  27. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  28. * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  29. * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  30. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  31. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  32. * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  33. * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  34. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35. * POSSIBILITY OF SUCH DAMAGE.
  36. *
  37. ****************************************************************************************/
  38. #include "../pico_int.h"
  39. #include "genplus_macros.h"
  40. /* IFSTAT register bitmasks */
  41. #define BIT_DTEI 0x40
  42. #define BIT_DECI 0x20
  43. #define BIT_DTBSY 0x08
  44. #define BIT_DTEN 0x02
  45. /* IFCTRL register bitmasks */
  46. #define BIT_DTEIEN 0x40
  47. #define BIT_DECIEN 0x20
  48. #define BIT_DOUTEN 0x02
  49. /* CTRL0 register bitmasks */
  50. #define BIT_DECEN 0x80
  51. #define BIT_E01RQ 0x20
  52. #define BIT_AUTORQ 0x10
  53. #define BIT_WRRQ 0x04
  54. /* CTRL1 register bitmasks */
  55. #define BIT_MODRQ 0x08
  56. #define BIT_FORMRQ 0x04
  57. #define BIT_SHDREN 0x01
  58. /* CTRL2 register bitmask */
  59. #define BIT_VALST 0x80
  60. /* PicoDrive: doing DMA at once, not using callbacks */
  61. //#define DMA_BYTES_PER_LINE 512
  62. enum dma_type {
  63. word_ram_0_dma_w = 1,
  64. word_ram_1_dma_w = 2,
  65. word_ram_2M_dma_w = 3,
  66. pcm_ram_dma_w = 4,
  67. prg_ram_dma_w = 5,
  68. };
  69. /* CDC hardware */
  70. typedef struct
  71. {
  72. uint8 ifstat;
  73. uint8 ifctrl;
  74. uint16 dbc;
  75. uint16 dac;
  76. uint16 pt;
  77. uint16 wa;
  78. uint8 ctrl[2];
  79. uint8 head[2][4];
  80. uint8 stat[4];
  81. int cycles;
  82. //void (*dma_w)(unsigned int words);
  83. int dma_w;
  84. uint8 ram[0x4000 + 2352]; /* 16K external RAM (with one block overhead to handle buffer overrun) */
  85. } cdc_t;
  86. static cdc_t cdc;
  87. void cdc_init(void)
  88. {
  89. memset(&cdc, 0, sizeof(cdc_t));
  90. }
  91. void cdc_reset(void)
  92. {
  93. /* reset CDC register index */
  94. Pico_mcd->s68k_regs[0x04+1] = 0x00;
  95. /* reset CDC registers */
  96. cdc.ifstat = 0xff;
  97. cdc.ifctrl = 0x00;
  98. cdc.ctrl[0] = 0x00;
  99. cdc.ctrl[1] = 0x00;
  100. cdc.stat[0] = 0x00;
  101. cdc.stat[1] = 0x00;
  102. cdc.stat[2] = 0x00;
  103. cdc.stat[3] = 0x80;
  104. cdc.head[0][0] = 0x00;
  105. cdc.head[0][1] = 0x00;
  106. cdc.head[0][2] = 0x00;
  107. cdc.head[0][3] = 0x01;
  108. cdc.head[1][0] = 0x00;
  109. cdc.head[1][1] = 0x00;
  110. cdc.head[1][2] = 0x00;
  111. cdc.head[1][3] = 0x00;
  112. /* reset CDC cycle counter */
  113. cdc.cycles = 0;
  114. /* DMA transfer disabled */
  115. cdc.dma_w = 0;
  116. }
  117. int cdc_context_save(uint8 *state)
  118. {
  119. uint8 tmp8;
  120. int bufferptr = 0;
  121. if (cdc.dma_w == pcm_ram_dma_w)
  122. {
  123. tmp8 = 1;
  124. }
  125. else if (cdc.dma_w == prg_ram_dma_w)
  126. {
  127. tmp8 = 2;
  128. }
  129. else if (cdc.dma_w == word_ram_0_dma_w)
  130. {
  131. tmp8 = 3;
  132. }
  133. else if (cdc.dma_w == word_ram_1_dma_w)
  134. {
  135. tmp8 = 4;
  136. }
  137. else if (cdc.dma_w == word_ram_2M_dma_w)
  138. {
  139. tmp8 = 5;
  140. }
  141. else
  142. {
  143. tmp8 = 0;
  144. }
  145. save_param(&cdc, sizeof(cdc));
  146. save_param(&tmp8, 1);
  147. return bufferptr;
  148. }
  149. int cdc_context_load(uint8 *state)
  150. {
  151. uint8 tmp8;
  152. int bufferptr = 0;
  153. load_param(&cdc, sizeof(cdc));
  154. load_param(&tmp8, 1);
  155. switch (tmp8)
  156. {
  157. case 1:
  158. cdc.dma_w = pcm_ram_dma_w;
  159. break;
  160. case 2:
  161. cdc.dma_w = prg_ram_dma_w;
  162. break;
  163. case 3:
  164. cdc.dma_w = word_ram_0_dma_w;
  165. break;
  166. case 4:
  167. cdc.dma_w = word_ram_1_dma_w;
  168. break;
  169. case 5:
  170. cdc.dma_w = word_ram_2M_dma_w;
  171. break;
  172. default:
  173. cdc.dma_w = 0;
  174. break;
  175. }
  176. return bufferptr;
  177. }
  178. int cdc_context_load_old(uint8 *state)
  179. {
  180. #define old_load(v, ofs) \
  181. memcpy(&cdc.v, state + ofs, sizeof(cdc.v))
  182. memcpy(cdc.ram, state, 0x4000);
  183. old_load(ifstat, 67892);
  184. old_load(ifctrl, 67924);
  185. old_load(dbc, 67896);
  186. old_load(dac, 67900);
  187. old_load(pt, 67908);
  188. old_load(wa, 67912);
  189. old_load(ctrl, 67928);
  190. old_load(head[0], 67904);
  191. old_load(stat, 67916);
  192. cdc.dma_w = 0;
  193. switch (Pico_mcd->s68k_regs[0x04+0] & 0x07)
  194. {
  195. case 4: /* PCM RAM DMA */
  196. cdc.dma_w = pcm_ram_dma_w;
  197. break;
  198. case 5: /* PRG-RAM DMA */
  199. cdc.dma_w = prg_ram_dma_w;
  200. break;
  201. case 7: /* WORD-RAM DMA */
  202. if (Pico_mcd->s68k_regs[0x02+1] & 0x04)
  203. {
  204. if (Pico_mcd->s68k_regs[0x02+1] & 0x01)
  205. cdc.dma_w = word_ram_0_dma_w;
  206. else
  207. cdc.dma_w = word_ram_1_dma_w;
  208. }
  209. else
  210. {
  211. if (Pico_mcd->s68k_regs[0x02+1] & 0x02)
  212. cdc.dma_w = word_ram_2M_dma_w;
  213. }
  214. break;
  215. }
  216. return 0x10960; // sizeof(old_cdc)
  217. #undef old_load
  218. }
  219. static void do_dma(enum dma_type type, int words_in)
  220. {
  221. int dma_addr = (Pico_mcd->s68k_regs[0x0a] << 8) | Pico_mcd->s68k_regs[0x0b];
  222. int src_addr = cdc.dac & 0x3ffe;
  223. int dst_addr = dma_addr;
  224. int words = words_in;
  225. int dst_limit = 0;
  226. uint8 *dst;
  227. int len;
  228. elprintf(EL_CD, "dma %d %04x->%04x %x",
  229. type, cdc.dac, dst_addr, words_in);
  230. switch (type)
  231. {
  232. case pcm_ram_dma_w:
  233. dst_addr = (dst_addr << 2) & 0xffc;
  234. if (dst_addr + words * 2 > 0x1000) {
  235. elprintf(EL_ANOMALY, "pcm dma oflow: %x %x", dst_addr, words);
  236. words = (0x1000 - dst_addr) / 2;
  237. }
  238. dst = Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank];
  239. dst = dst + dst_addr;
  240. while (words > 0)
  241. {
  242. if (src_addr + words * 2 > 0x4000) {
  243. len = 0x4000 - src_addr;
  244. memcpy(dst, cdc.ram + src_addr, len);
  245. dst += len;
  246. src_addr = 0;
  247. words -= len / 2;
  248. continue;
  249. }
  250. memcpy(dst, cdc.ram + src_addr, words * 2);
  251. break;
  252. }
  253. goto update_dma;
  254. case prg_ram_dma_w:
  255. dst_addr <<= 3;
  256. dst = Pico_mcd->prg_ram + dst_addr;
  257. dst_limit = 0x80000;
  258. break;
  259. case word_ram_0_dma_w:
  260. dst_addr = (dst_addr << 3) & 0x1fffe;
  261. dst = Pico_mcd->word_ram1M[0] + dst_addr;
  262. dst_limit = 0x20000;
  263. break;
  264. case word_ram_1_dma_w:
  265. dst_addr = (dst_addr << 3) & 0x1fffe;
  266. dst = Pico_mcd->word_ram1M[1] + dst_addr;
  267. dst_limit = 0x20000;
  268. break;
  269. case word_ram_2M_dma_w:
  270. dst_addr = (dst_addr << 3) & 0x3fffe;
  271. dst = Pico_mcd->word_ram2M + dst_addr;
  272. dst_limit = 0x40000;
  273. break;
  274. default:
  275. elprintf(EL_ANOMALY, "invalid dma: %d", type);
  276. goto update_dma;
  277. }
  278. if (dst_addr + words * 2 > dst_limit) {
  279. elprintf(EL_ANOMALY, "cd dma %d oflow: %x %x", type, dst_addr, words);
  280. words = (dst_limit - dst_addr) / 2;
  281. }
  282. while (words > 0)
  283. {
  284. if (src_addr + words * 2 > 0x4000) {
  285. len = 0x4000 - src_addr;
  286. memcpy16bswap((void *)dst, cdc.ram + src_addr, len / 2);
  287. dst += len;
  288. src_addr = 0;
  289. words -= len / 2;
  290. continue;
  291. }
  292. memcpy16bswap((void *)dst, cdc.ram + src_addr, words);
  293. break;
  294. }
  295. update_dma:
  296. /* update DMA addresses */
  297. cdc.dac += words_in * 2;
  298. if (type == pcm_ram_dma_w)
  299. dma_addr += words_in >> 1;
  300. else
  301. dma_addr += words_in >> 2;
  302. Pico_mcd->s68k_regs[0x0a] = dma_addr >> 8;
  303. Pico_mcd->s68k_regs[0x0b] = dma_addr;
  304. }
  305. void cdc_dma_update(void)
  306. {
  307. /* end of DMA transfer ? */
  308. //if (cdc.dbc < DMA_BYTES_PER_LINE)
  309. {
  310. /* transfer remaining words using 16-bit DMA */
  311. //cdc.dma_w((cdc.dbc + 1) >> 1);
  312. do_dma(cdc.dma_w, (cdc.dbc + 1) >> 1);
  313. /* reset data byte counter (DBCH bits 4-7 should be set to 1) */
  314. cdc.dbc = 0xf000;
  315. /* clear !DTEN and !DTBSY */
  316. cdc.ifstat |= (BIT_DTBSY | BIT_DTEN);
  317. /* pending Data Transfer End interrupt */
  318. cdc.ifstat &= ~BIT_DTEI;
  319. /* Data Transfer End interrupt enabled ? */
  320. if (cdc.ifctrl & BIT_DTEIEN)
  321. {
  322. /* level 5 interrupt enabled ? */
  323. if (Pico_mcd->s68k_regs[0x32+1] & PCDS_IEN5)
  324. {
  325. /* update IRQ level */
  326. elprintf(EL_INTS, "cdc DTE irq 5");
  327. pcd_irq_s68k(5, 1);
  328. }
  329. }
  330. /* clear DSR bit & set EDT bit (SCD register $04) */
  331. Pico_mcd->s68k_regs[0x04+0] = (Pico_mcd->s68k_regs[0x04+0] & 0x07) | 0x80;
  332. /* disable DMA transfer */
  333. cdc.dma_w = 0;
  334. }
  335. #if 0
  336. else
  337. {
  338. /* transfer all words using 16-bit DMA */
  339. cdc.dma_w(DMA_BYTES_PER_LINE >> 1);
  340. /* decrement data byte counter */
  341. cdc.dbc -= length;
  342. }
  343. #endif
  344. }
  345. int cdc_decoder_update(uint8 header[4])
  346. {
  347. /* data decoding enabled ? */
  348. if (cdc.ctrl[0] & BIT_DECEN)
  349. {
  350. /* update HEAD registers */
  351. memcpy(cdc.head[0], header, sizeof(cdc.head[0]));
  352. /* set !VALST */
  353. cdc.stat[3] = 0x00;
  354. /* pending decoder interrupt */
  355. cdc.ifstat &= ~BIT_DECI;
  356. /* decoder interrupt enabled ? */
  357. if (cdc.ifctrl & BIT_DECIEN)
  358. {
  359. /* level 5 interrupt enabled ? */
  360. if (Pico_mcd->s68k_regs[0x32+1] & PCDS_IEN5)
  361. {
  362. /* update IRQ level */
  363. elprintf(EL_INTS, "cdc DEC irq 5");
  364. pcd_irq_s68k(5, 1);
  365. }
  366. }
  367. /* buffer RAM write enabled ? */
  368. if (cdc.ctrl[0] & BIT_WRRQ)
  369. {
  370. uint16 offset;
  371. /* increment block pointer */
  372. cdc.pt += 2352;
  373. /* increment write address */
  374. cdc.wa += 2352;
  375. /* CDC buffer address */
  376. offset = cdc.pt & 0x3fff;
  377. /* write CDD block header (4 bytes) */
  378. memcpy(cdc.ram + offset, header, 4);
  379. /* write CDD block data (2048 bytes) */
  380. cdd_read_data(cdc.ram + 4 + offset);
  381. /* take care of buffer overrun */
  382. if (offset > (0x4000 - 2048 - 4))
  383. {
  384. /* data should be written at the start of buffer */
  385. memcpy(cdc.ram, cdc.ram + 0x4000, offset + 2048 + 4 - 0x4000);
  386. }
  387. /* read next data block */
  388. return 1;
  389. }
  390. }
  391. /* keep decoding same data block if Buffer Write is disabled */
  392. return 0;
  393. }
  394. void cdc_reg_w(unsigned char data)
  395. {
  396. #ifdef LOG_CDC
  397. elprintf(EL_STATUS, "CDC register %X write 0x%04x", Pico_mcd->s68k_regs[0x04+1] & 0x0F, data);
  398. #endif
  399. switch (Pico_mcd->s68k_regs[0x04+1] & 0x0F)
  400. {
  401. case 0x01: /* IFCTRL */
  402. {
  403. /* pending interrupts ? */
  404. if (((data & BIT_DTEIEN) && !(cdc.ifstat & BIT_DTEI)) ||
  405. ((data & BIT_DECIEN) && !(cdc.ifstat & BIT_DECI)))
  406. {
  407. /* level 5 interrupt enabled ? */
  408. if (Pico_mcd->s68k_regs[0x32+1] & PCDS_IEN5)
  409. {
  410. /* update IRQ level */
  411. elprintf(EL_INTS, "cdc pending irq 5");
  412. pcd_irq_s68k(5, 1);
  413. }
  414. }
  415. else // if (scd.pending & (1 << 5))
  416. {
  417. /* clear pending level 5 interrupts */
  418. pcd_irq_s68k(5, 0);
  419. }
  420. /* abort any data transfer if data output is disabled */
  421. if (!(data & BIT_DOUTEN))
  422. {
  423. /* clear !DTBSY and !DTEN */
  424. cdc.ifstat |= (BIT_DTBSY | BIT_DTEN);
  425. }
  426. cdc.ifctrl = data;
  427. Pico_mcd->s68k_regs[0x04+1] = 0x02;
  428. break;
  429. }
  430. case 0x02: /* DBCL */
  431. cdc.dbc &= 0xff00;
  432. cdc.dbc |= data;
  433. Pico_mcd->s68k_regs[0x04+1] = 0x03;
  434. break;
  435. case 0x03: /* DBCH */
  436. cdc.dbc &= 0x00ff;
  437. cdc.dbc |= data << 8;
  438. Pico_mcd->s68k_regs[0x04+1] = 0x04;
  439. break;
  440. case 0x04: /* DACL */
  441. cdc.dac &= 0xff00;
  442. cdc.dac |= data;
  443. Pico_mcd->s68k_regs[0x04+1] = 0x05;
  444. break;
  445. case 0x05: /* DACH */
  446. cdc.dac &= 0x00ff;
  447. cdc.dac |= data << 8;
  448. Pico_mcd->s68k_regs[0x04+1] = 0x06;
  449. break;
  450. case 0x06: /* DTRG */
  451. {
  452. /* start data transfer if data output is enabled */
  453. if (cdc.ifctrl & BIT_DOUTEN)
  454. {
  455. /* set !DTBSY */
  456. cdc.ifstat &= ~BIT_DTBSY;
  457. /* clear DBCH bits 4-7 */
  458. cdc.dbc &= 0x0fff;
  459. /* clear EDT & DSR bits (SCD register $04) */
  460. Pico_mcd->s68k_regs[0x04+0] &= 0x07;
  461. cdc.dma_w = 0;
  462. /* setup data transfer destination */
  463. switch (Pico_mcd->s68k_regs[0x04+0] & 0x07)
  464. {
  465. case 2: /* MAIN-CPU host read */
  466. case 3: /* SUB-CPU host read */
  467. {
  468. /* set !DTEN */
  469. cdc.ifstat &= ~BIT_DTEN;
  470. /* set DSR bit (register $04) */
  471. Pico_mcd->s68k_regs[0x04+0] |= 0x40;
  472. break;
  473. }
  474. case 4: /* PCM RAM DMA */
  475. {
  476. cdc.dma_w = pcm_ram_dma_w;
  477. break;
  478. }
  479. case 5: /* PRG-RAM DMA */
  480. {
  481. cdc.dma_w = prg_ram_dma_w;
  482. break;
  483. }
  484. case 7: /* WORD-RAM DMA */
  485. {
  486. /* check memory mode */
  487. if (Pico_mcd->s68k_regs[0x02+1] & 0x04)
  488. {
  489. /* 1M mode */
  490. if (Pico_mcd->s68k_regs[0x02+1] & 0x01)
  491. {
  492. /* Word-RAM bank 0 is assigned to SUB-CPU */
  493. cdc.dma_w = word_ram_0_dma_w;
  494. }
  495. else
  496. {
  497. /* Word-RAM bank 1 is assigned to SUB-CPU */
  498. cdc.dma_w = word_ram_1_dma_w;
  499. }
  500. }
  501. else
  502. {
  503. /* 2M mode */
  504. if (Pico_mcd->s68k_regs[0x02+1] & 0x02)
  505. {
  506. /* only process DMA if Word-RAM is assigned to SUB-CPU */
  507. cdc.dma_w = word_ram_2M_dma_w;
  508. }
  509. }
  510. break;
  511. }
  512. default: /* invalid */
  513. {
  514. elprintf(EL_ANOMALY, "invalid CDC tranfer destination (%d)",
  515. Pico_mcd->s68k_regs[0x04+0] & 0x07);
  516. break;
  517. }
  518. }
  519. if (cdc.dma_w)
  520. pcd_event_schedule_s68k(PCD_EVENT_DMA, cdc.dbc / 2);
  521. }
  522. Pico_mcd->s68k_regs[0x04+1] = 0x07;
  523. break;
  524. }
  525. case 0x07: /* DTACK */
  526. {
  527. /* clear pending data transfer end interrupt */
  528. cdc.ifstat |= BIT_DTEI;
  529. /* clear DBCH bits 4-7 */
  530. cdc.dbc &= 0x0fff;
  531. #if 0
  532. /* no pending decoder interrupt ? */
  533. if ((cdc.ifstat | BIT_DECI) || !(cdc.ifctrl & BIT_DECIEN))
  534. {
  535. /* clear pending level 5 interrupt */
  536. pcd_irq_s68k(5, 0);
  537. }
  538. #endif
  539. Pico_mcd->s68k_regs[0x04+1] = 0x08;
  540. break;
  541. }
  542. case 0x08: /* WAL */
  543. cdc.wa &= 0xff00;
  544. cdc.wa |= data;
  545. Pico_mcd->s68k_regs[0x04+1] = 0x09;
  546. break;
  547. case 0x09: /* WAH */
  548. cdc.wa &= 0x00ff;
  549. cdc.wa |= data << 8;
  550. Pico_mcd->s68k_regs[0x04+1] = 0x0a;
  551. break;
  552. case 0x0a: /* CTRL0 */
  553. {
  554. /* set CRCOK bit only if decoding is enabled */
  555. cdc.stat[0] = data & BIT_DECEN;
  556. /* update decoding mode */
  557. if (data & BIT_AUTORQ)
  558. {
  559. /* set MODE bit according to CTRL1 register & clear FORM bit */
  560. cdc.stat[2] = cdc.ctrl[1] & BIT_MODRQ;
  561. }
  562. else
  563. {
  564. /* set MODE & FORM bits according to CTRL1 register */
  565. cdc.stat[2] = cdc.ctrl[1] & (BIT_MODRQ | BIT_FORMRQ);
  566. }
  567. cdc.ctrl[0] = data;
  568. Pico_mcd->s68k_regs[0x04+1] = 0x0b;
  569. break;
  570. }
  571. case 0x0b: /* CTRL1 */
  572. {
  573. /* update decoding mode */
  574. if (cdc.ctrl[0] & BIT_AUTORQ)
  575. {
  576. /* set MODE bit according to CTRL1 register & clear FORM bit */
  577. cdc.stat[2] = data & BIT_MODRQ;
  578. }
  579. else
  580. {
  581. /* set MODE & FORM bits according to CTRL1 register */
  582. cdc.stat[2] = data & (BIT_MODRQ | BIT_FORMRQ);
  583. }
  584. cdc.ctrl[1] = data;
  585. Pico_mcd->s68k_regs[0x04+1] = 0x0c;
  586. break;
  587. }
  588. case 0x0c: /* PTL */
  589. cdc.pt &= 0xff00;
  590. cdc.pt |= data;
  591. Pico_mcd->s68k_regs[0x04+1] = 0x0d;
  592. break;
  593. case 0x0d: /* PTH */
  594. cdc.pt &= 0x00ff;
  595. cdc.pt |= data << 8;
  596. Pico_mcd->s68k_regs[0x04+1] = 0x0e;
  597. break;
  598. case 0x0e: /* CTRL2 (unused) */
  599. Pico_mcd->s68k_regs[0x04+1] = 0x0f;
  600. break;
  601. case 0x0f: /* RESET */
  602. cdc_reset();
  603. break;
  604. default: /* by default, SBOUT is not used */
  605. break;
  606. }
  607. }
  608. unsigned char cdc_reg_r(void)
  609. {
  610. switch (Pico_mcd->s68k_regs[0x04+1] & 0x0F)
  611. {
  612. case 0x01: /* IFSTAT */
  613. Pico_mcd->s68k_regs[0x04+1] = 0x02;
  614. return cdc.ifstat;
  615. case 0x02: /* DBCL */
  616. Pico_mcd->s68k_regs[0x04+1] = 0x03;
  617. return cdc.dbc & 0xff;
  618. case 0x03: /* DBCH */
  619. Pico_mcd->s68k_regs[0x04+1] = 0x04;
  620. return (cdc.dbc >> 8) & 0xff;
  621. case 0x04: /* HEAD0 */
  622. Pico_mcd->s68k_regs[0x04+1] = 0x05;
  623. return cdc.head[cdc.ctrl[1] & BIT_SHDREN][0];
  624. case 0x05: /* HEAD1 */
  625. Pico_mcd->s68k_regs[0x04+1] = 0x06;
  626. return cdc.head[cdc.ctrl[1] & BIT_SHDREN][1];
  627. case 0x06: /* HEAD2 */
  628. Pico_mcd->s68k_regs[0x04+1] = 0x07;
  629. return cdc.head[cdc.ctrl[1] & BIT_SHDREN][2];
  630. case 0x07: /* HEAD3 */
  631. Pico_mcd->s68k_regs[0x04+1] = 0x08;
  632. return cdc.head[cdc.ctrl[1] & BIT_SHDREN][3];
  633. case 0x08: /* PTL */
  634. Pico_mcd->s68k_regs[0x04+1] = 0x09;
  635. return cdc.pt & 0xff;
  636. case 0x09: /* PTH */
  637. Pico_mcd->s68k_regs[0x04+1] = 0x0a;
  638. return (cdc.pt >> 8) & 0xff;
  639. case 0x0a: /* WAL */
  640. Pico_mcd->s68k_regs[0x04+1] = 0x0b;
  641. return cdc.wa & 0xff;
  642. case 0x0b: /* WAH */
  643. Pico_mcd->s68k_regs[0x04+1] = 0x0c;
  644. return (cdc.wa >> 8) & 0xff;
  645. case 0x0c: /* STAT0 */
  646. Pico_mcd->s68k_regs[0x04+1] = 0x0d;
  647. return cdc.stat[0];
  648. case 0x0d: /* STAT1 (always return 0) */
  649. Pico_mcd->s68k_regs[0x04+1] = 0x0e;
  650. return 0x00;
  651. case 0x0e: /* STAT2 */
  652. Pico_mcd->s68k_regs[0x04+1] = 0x0f;
  653. return cdc.stat[2];
  654. case 0x0f: /* STAT3 */
  655. {
  656. uint8 data = cdc.stat[3];
  657. /* clear !VALST (note: this is not 100% correct but BIOS do not seem to care) */
  658. cdc.stat[3] = BIT_VALST;
  659. /* clear pending decoder interrupt */
  660. cdc.ifstat |= BIT_DECI;
  661. #if 0
  662. /* no pending data transfer end interrupt */
  663. if ((cdc.ifstat | BIT_DTEI) || !(cdc.ifctrl & BIT_DTEIEN))
  664. {
  665. /* clear pending level 5 interrupt */
  666. pcd_irq_s68k(5, 0);
  667. }
  668. #endif
  669. Pico_mcd->s68k_regs[0x04+1] = 0x00;
  670. return data;
  671. }
  672. default: /* by default, COMIN is always empty */
  673. return 0xff;
  674. }
  675. }
  676. unsigned short cdc_host_r(void)
  677. {
  678. /* check if data is available */
  679. if (!(cdc.ifstat & BIT_DTEN))
  680. {
  681. /* read data word from CDC RAM buffer */
  682. uint8 *datap = cdc.ram + (cdc.dac & 0x3ffe);
  683. uint16 data = (datap[0] << 8) | datap[1];
  684. #ifdef LOG_CDC
  685. error("CDC host read 0x%04x -> 0x%04x (dbc=0x%x) (%X)\n", cdc.dac, data, cdc.dbc, s68k.pc);
  686. #endif
  687. /* increment data address counter */
  688. cdc.dac += 2;
  689. /* decrement data byte counter */
  690. cdc.dbc -= 2;
  691. /* end of transfer ? */
  692. if ((int16)cdc.dbc <= 0)
  693. {
  694. /* reset data byte counter (DBCH bits 4-7 should be set to 1) */
  695. cdc.dbc = 0xf000;
  696. /* clear !DTEN and !DTBSY */
  697. cdc.ifstat |= (BIT_DTBSY | BIT_DTEN);
  698. /* pending Data Transfer End interrupt */
  699. cdc.ifstat &= ~BIT_DTEI;
  700. /* Data Transfer End interrupt enabled ? */
  701. if (cdc.ifctrl & BIT_DTEIEN)
  702. {
  703. /* level 5 interrupt enabled ? */
  704. if (Pico_mcd->s68k_regs[0x32+1] & PCDS_IEN5)
  705. {
  706. /* update IRQ level */
  707. elprintf(EL_INTS, "cdc DTE irq 5");
  708. pcd_irq_s68k(5, 1);
  709. }
  710. }
  711. /* clear DSR bit & set EDT bit (SCD register $04) */
  712. Pico_mcd->s68k_regs[0x04+0] = (Pico_mcd->s68k_regs[0x04+0] & 0x07) | 0x80;
  713. }
  714. return data;
  715. }
  716. #ifdef LOG_CDC
  717. error("error reading CDC host (data transfer disabled)\n");
  718. #endif
  719. return 0xffff;
  720. }
  721. // vim:shiftwidth=2:ts=2:expandtab