sh2soc.c 16 KB

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  1. /*
  2. * SH2 peripherals/"system on chip"
  3. * (C) notaz, 2013
  4. *
  5. * This work is licensed under the terms of MAME license.
  6. * See COPYING file in the top-level directory.
  7. *
  8. * rough fffffe00-ffffffff map:
  9. * e00-e05 SCI serial communication interface
  10. * e10-e1a FRT free-running timer
  11. * e60-e68 VCRx irq vectors
  12. * e71-e72 DRCR dma selection
  13. * e80-e83 WDT watchdog timer
  14. * e91 SBYCR standby control
  15. * e92 CCR cache control
  16. * ee0 ICR irq control
  17. * ee2 IPRA irq priorities
  18. * ee4 VCRWDT WDT irq vectors
  19. * f00-f17 DIVU
  20. * f40-f7b UBC user break controller
  21. * f80-fb3 DMAC
  22. * fe0-ffb BSC bus state controller
  23. */
  24. #include "../pico_int.h"
  25. #include "../memory.h"
  26. #include <cpu/sh2/compiler.h>
  27. DRC_DECLARE_SR;
  28. // DMAC handling
  29. struct dma_chan {
  30. u32 sar, dar; // src, dst addr
  31. u32 tcr; // transfer count
  32. u32 chcr; // chan ctl
  33. // -- dm dm sm sm ts ts ar am al ds dl tb ta ie te de
  34. // ts - transfer size: 1, 2, 4, 16 bytes
  35. // ar - auto request if 1, else dreq signal
  36. // ie - irq enable
  37. // te - transfer end
  38. // de - dma enable
  39. #define DMA_AR (1 << 9)
  40. #define DMA_IE (1 << 2)
  41. #define DMA_TE (1 << 1)
  42. #define DMA_DE (1 << 0)
  43. };
  44. struct dmac {
  45. struct dma_chan chan[2];
  46. u32 vcrdma0;
  47. u32 unknown0;
  48. u32 vcrdma1;
  49. u32 unknown1;
  50. u32 dmaor;
  51. // -- pr ae nmif dme
  52. // pr - priority: chan0 > chan1 or round-robin
  53. // ae - address error
  54. // nmif - nmi occurred
  55. // dme - DMA master enable
  56. #define DMA_DME (1 << 0)
  57. };
  58. static void dmac_te_irq(SH2 *sh2, struct dma_chan *chan)
  59. {
  60. char *regs = (void *)sh2->peri_regs;
  61. struct dmac *dmac = (void *)(regs + 0x180);
  62. int level = PREG8(regs, 0xe2) & 0x0f; // IPRA
  63. int vector = (chan == &dmac->chan[0]) ?
  64. dmac->vcrdma0 : dmac->vcrdma1;
  65. elprintf(EL_32XP, "dmac irq %d %d", level, vector);
  66. sh2_internal_irq(sh2, level, vector & 0x7f);
  67. }
  68. static void dmac_transfer_complete(SH2 *sh2, struct dma_chan *chan)
  69. {
  70. chan->chcr |= DMA_TE; // DMA has ended normally
  71. p32x_sh2_poll_event(sh2, SH2_STATE_SLEEP, SekCyclesDone());
  72. if (chan->chcr & DMA_IE)
  73. dmac_te_irq(sh2, chan);
  74. }
  75. static void dmac_transfer_one(SH2 *sh2, struct dma_chan *chan)
  76. {
  77. u32 size, d;
  78. size = (chan->chcr >> 10) & 3;
  79. switch (size) {
  80. case 0:
  81. d = p32x_sh2_read8(chan->sar, sh2);
  82. p32x_sh2_write8(chan->dar, d, sh2);
  83. break;
  84. case 1:
  85. d = p32x_sh2_read16(chan->sar, sh2);
  86. p32x_sh2_write16(chan->dar, d, sh2);
  87. break;
  88. case 2:
  89. d = p32x_sh2_read32(chan->sar, sh2);
  90. p32x_sh2_write32(chan->dar, d, sh2);
  91. break;
  92. case 3:
  93. d = p32x_sh2_read32(chan->sar + 0x00, sh2);
  94. p32x_sh2_write32(chan->dar + 0x00, d, sh2);
  95. d = p32x_sh2_read32(chan->sar + 0x04, sh2);
  96. p32x_sh2_write32(chan->dar + 0x04, d, sh2);
  97. d = p32x_sh2_read32(chan->sar + 0x08, sh2);
  98. p32x_sh2_write32(chan->dar + 0x08, d, sh2);
  99. d = p32x_sh2_read32(chan->sar + 0x0c, sh2);
  100. p32x_sh2_write32(chan->dar + 0x0c, d, sh2);
  101. chan->sar += 16; // always?
  102. if (chan->chcr & (1 << 15))
  103. chan->dar -= 16;
  104. if (chan->chcr & (1 << 14))
  105. chan->dar += 16;
  106. chan->tcr -= 4;
  107. return;
  108. }
  109. chan->tcr--;
  110. size = 1 << size;
  111. if (chan->chcr & (1 << 15))
  112. chan->dar -= size;
  113. if (chan->chcr & (1 << 14))
  114. chan->dar += size;
  115. if (chan->chcr & (1 << 13))
  116. chan->sar -= size;
  117. if (chan->chcr & (1 << 12))
  118. chan->sar += size;
  119. }
  120. // optimization for copying around memory with SH2 DMA
  121. static void dmac_memcpy(struct dma_chan *chan, SH2 *sh2)
  122. {
  123. u32 size = (chan->chcr >> 10) & 3, up = chan->chcr & (1 << 14);
  124. int count;
  125. if (!up || chan->tcr < 4)
  126. return;
  127. #if MARS_CHECK_HACK
  128. // XXX Mars Check Program copies 32K longwords (128KB) from a 64KB buffer in
  129. // ROM or DRAM to SDRAM in 4-longword mode, overwriting an SDRAM comm area in
  130. // turn, which crashes the test on emulators without CPU cache emulation.
  131. // This may be a bug in Mars Check. As a kludge limit the transfer to 64KB,
  132. // which is what the check program test uses for checking the result.
  133. // A better way would clearly be to have a mechanism to patch the ROM...
  134. if (size == 3 && chan->tcr == 32768 && chan->dar == 0x06020000) size = 1;
  135. #endif
  136. if (size == 3) size = 2; // 4-word xfer mode still counts in words
  137. // XXX check TCR being a multiple of 4 in 4-word xfer mode?
  138. // XXX check alignment of sar/dar, generating a bus error if unaligned?
  139. count = p32x_sh2_memcpy(chan->dar, chan->sar, chan->tcr, 1 << size, sh2);
  140. chan->sar += count << size;
  141. chan->dar += count << size;
  142. chan->tcr -= count;
  143. }
  144. // DMA trigger by SH2 register write
  145. static void dmac_trigger(SH2 *sh2, struct dma_chan *chan)
  146. {
  147. elprintf_sh2(sh2, EL_32XP, "DMA %08x->%08x, cnt %d, chcr %04x @%06x",
  148. chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc);
  149. chan->tcr &= 0xffffff;
  150. if (chan->chcr & DMA_AR) {
  151. // auto-request transfer
  152. sh2->state |= SH2_STATE_SLEEP;
  153. if ((((chan->chcr >> 12) ^ (chan->chcr >> 14)) & 3) == 0 &&
  154. (((chan->chcr >> 14) ^ (chan->chcr >> 15)) & 1) == 1) {
  155. // SM == DM and either DM0 or DM1 are set. check for mem to mem copy
  156. dmac_memcpy(chan, sh2);
  157. }
  158. while ((int)chan->tcr > 0)
  159. dmac_transfer_one(sh2, chan);
  160. dmac_transfer_complete(sh2, chan);
  161. return;
  162. }
  163. // DREQ0 is only sent after first 4 words are written.
  164. // we do multiple of 4 words to avoid messing up alignment
  165. if ((chan->sar & ~0x20000000) == 0x00004012) {
  166. if (Pico32x.dmac0_fifo_ptr && (Pico32x.dmac0_fifo_ptr & 3) == 0) {
  167. elprintf(EL_32XP, "68k -> sh2 DMA");
  168. p32x_dreq0_trigger();
  169. }
  170. return;
  171. }
  172. // DREQ1
  173. if ((chan->dar & 0xc7fffff0) == 0x00004030)
  174. return;
  175. elprintf(EL_32XP|EL_ANOMALY, "unhandled DMA: "
  176. "%08x->%08x, cnt %d, chcr %04x @%06x",
  177. chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc);
  178. }
  179. // timer state - FIXME
  180. static u32 timer_cycles[2];
  181. static u32 timer_tick_cycles[2];
  182. static u32 timer_tick_factor[2];
  183. // timers
  184. void p32x_timers_recalc(void)
  185. {
  186. int cycles;
  187. int tmp, i;
  188. // SH2 timer step
  189. for (i = 0; i < 2; i++) {
  190. sh2s[i].state &= ~SH2_TIMER_RUN;
  191. if (PREG8(sh2s[i].peri_regs, 0x80) & 0x20) // TME
  192. sh2s[i].state |= SH2_TIMER_RUN;
  193. tmp = PREG8(sh2s[i].peri_regs, 0x80) & 7;
  194. // Sclk cycles per timer tick
  195. if (tmp)
  196. cycles = 0x20 << tmp;
  197. else
  198. cycles = 2;
  199. timer_tick_cycles[i] = cycles;
  200. timer_tick_factor[i] = (1ULL << 32) / cycles;
  201. timer_cycles[i] = 0;
  202. elprintf(EL_32XP, "WDT cycles[%d] = %d", i, cycles);
  203. }
  204. }
  205. NOINLINE void p32x_timer_do(SH2 *sh2, unsigned int m68k_slice)
  206. {
  207. unsigned int cycles = m68k_slice * 3;
  208. void *pregs = sh2->peri_regs;
  209. int cnt; int i = sh2->is_slave;
  210. // WDT timer
  211. timer_cycles[i] += cycles;
  212. if (timer_cycles[i] > timer_tick_cycles[i]) {
  213. // cnt = timer_cycles[i] / timer_tick_cycles[i];
  214. cnt = (1ULL * timer_cycles[i] * timer_tick_factor[i]) >> 32;
  215. timer_cycles[i] -= timer_tick_cycles[i] * cnt;
  216. cnt += PREG8(pregs, 0x81);
  217. if (cnt >= 0x100) {
  218. int level = PREG8(pregs, 0xe3) >> 4;
  219. int vector = PREG8(pregs, 0xe4) & 0x7f;
  220. elprintf(EL_32XP, "%csh2 WDT irq (%d, %d)",
  221. i ? 's' : 'm', level, vector);
  222. sh2_internal_irq(sh2, level, vector);
  223. cnt &= 0xff;
  224. }
  225. PREG8(pregs, 0x81) = cnt;
  226. }
  227. }
  228. void sh2_peripheral_reset(SH2 *sh2)
  229. {
  230. memset(sh2->peri_regs, 0, sizeof(sh2->peri_regs)); // ?
  231. PREG8(sh2->peri_regs, 0x001) = 0xff; // SCI BRR
  232. PREG8(sh2->peri_regs, 0x003) = 0xff; // SCI TDR
  233. PREG8(sh2->peri_regs, 0x004) = 0x84; // SCI SSR
  234. PREG8(sh2->peri_regs, 0x011) = 0x01; // TIER
  235. PREG8(sh2->peri_regs, 0x017) = 0xe0; // TOCR
  236. }
  237. // ------------------------------------------------------------------
  238. // SH2 internal peripheral memhandlers
  239. // we keep them in little endian format
  240. u32 REGPARM(2) sh2_peripheral_read8(u32 a, SH2 *sh2)
  241. {
  242. u8 *r = (void *)sh2->peri_regs;
  243. u32 d;
  244. a &= 0x1ff;
  245. d = PREG8(r, a);
  246. elprintf_sh2(sh2, EL_32XP, "peri r8 [%08x] %02x @%06x",
  247. a | ~0x1ff, d, sh2_pc(sh2));
  248. if ((a & 0x1c0) == 0x140) {
  249. // abused as comm area
  250. DRC_SAVE_SR(sh2);
  251. p32x_sh2_poll_detect(a, sh2, SH2_STATE_CPOLL, 3);
  252. DRC_RESTORE_SR(sh2);
  253. }
  254. return d;
  255. }
  256. u32 REGPARM(2) sh2_peripheral_read16(u32 a, SH2 *sh2)
  257. {
  258. u16 *r = (void *)sh2->peri_regs;
  259. u32 d;
  260. a &= 0x1fe;
  261. d = r[MEM_BE2(a / 2)];
  262. elprintf_sh2(sh2, EL_32XP, "peri r16 [%08x] %04x @%06x",
  263. a | ~0x1ff, d, sh2_pc(sh2));
  264. if ((a & 0x1c0) == 0x140) {
  265. // abused as comm area
  266. DRC_SAVE_SR(sh2);
  267. p32x_sh2_poll_detect(a, sh2, SH2_STATE_CPOLL, 3);
  268. DRC_RESTORE_SR(sh2);
  269. }
  270. return d;
  271. }
  272. u32 REGPARM(2) sh2_peripheral_read32(u32 a, SH2 *sh2)
  273. {
  274. u32 d;
  275. a &= 0x1fc;
  276. d = sh2->peri_regs[a / 4];
  277. elprintf_sh2(sh2, EL_32XP, "peri r32 [%08x] %08x @%06x",
  278. a | ~0x1ff, d, sh2_pc(sh2));
  279. if (a == 0x18c)
  280. // kludge for polling COMM while polling for end of DMA
  281. sh2->poll_cnt = 0;
  282. else if ((a & 0x1c0) == 0x140) {
  283. // abused as comm area
  284. DRC_SAVE_SR(sh2);
  285. p32x_sh2_poll_detect(a, sh2, SH2_STATE_CPOLL, 3);
  286. DRC_RESTORE_SR(sh2);
  287. }
  288. return d;
  289. }
  290. static void sci_trigger(SH2 *sh2, u8 *r)
  291. {
  292. u8 *oregs;
  293. if (!(PREG8(r, 2) & 0x20))
  294. return; // transmitter not enabled
  295. if ((PREG8(r, 4) & 0x80)) // TDRE - TransmitDataR Empty
  296. return;
  297. oregs = (u8 *)sh2->other_sh2->peri_regs;
  298. if (!(PREG8(oregs, 2) & 0x10))
  299. return; // receiver not enabled
  300. PREG8(oregs, 5) = PREG8(r, 3); // other.RDR = this.TDR
  301. PREG8(r, 4) |= 0x80; // TDRE - TDR empty
  302. PREG8(oregs, 4) |= 0x40; // RDRF - RDR Full
  303. // might need to delay these a bit..
  304. if (PREG8(r, 2) & 0x80) { // TIE - tx irq enabled
  305. int level = PREG8(oregs, 0x60) >> 4;
  306. int vector = PREG8(oregs, 0x64) & 0x7f;
  307. elprintf_sh2(sh2, EL_32XP, "SCI tx irq (%d, %d)",
  308. level, vector);
  309. sh2_internal_irq(sh2, level, vector);
  310. }
  311. // TODO: TEIE
  312. if (PREG8(oregs, 2) & 0x40) { // RIE - rx irq enabled
  313. int level = PREG8(oregs, 0x60) >> 4;
  314. int vector = PREG8(oregs, 0x63) & 0x7f;
  315. elprintf_sh2(sh2->other_sh2, EL_32XP, "SCI rx irq (%d, %d)",
  316. level, vector);
  317. sh2_internal_irq(sh2->other_sh2, level, vector);
  318. }
  319. }
  320. void REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, SH2 *sh2)
  321. {
  322. u8 *r = (void *)sh2->peri_regs;
  323. u8 old;
  324. elprintf_sh2(sh2, EL_32XP, "peri w8 [%08x] %02x @%06x",
  325. a, d, sh2_pc(sh2));
  326. a &= 0x1ff;
  327. old = PREG8(r, a);
  328. switch (a) {
  329. case 0x002: // SCR - serial control
  330. if (!(PREG8(r, a) & 0x20) && (d & 0x20)) { // TE being set
  331. PREG8(r, a) = d;
  332. sci_trigger(sh2, r);
  333. }
  334. break;
  335. case 0x003: // TDR - transmit data
  336. break;
  337. case 0x004: // SSR - serial status
  338. d = (old & (d | 0x06)) | (d & 1);
  339. PREG8(r, a) = d;
  340. sci_trigger(sh2, r);
  341. return;
  342. case 0x005: // RDR - receive data
  343. break;
  344. case 0x010: // TIER
  345. if (d & 0x8e)
  346. elprintf(EL_32XP|EL_ANOMALY, "TIER: %02x", d);
  347. d = (d & 0x8e) | 1;
  348. break;
  349. case 0x017: // TOCR
  350. d |= 0xe0;
  351. break;
  352. }
  353. PREG8(r, a) = d;
  354. if ((a & 0x1c0) == 0x140)
  355. p32x_sh2_poll_event(sh2, SH2_STATE_CPOLL, SekCyclesDone());
  356. }
  357. void REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, SH2 *sh2)
  358. {
  359. u16 *r = (void *)sh2->peri_regs;
  360. elprintf_sh2(sh2, EL_32XP, "peri w16 [%08x] %04x @%06x",
  361. a, d, sh2_pc(sh2));
  362. a &= 0x1fe;
  363. // evil WDT
  364. if (a == 0x80) {
  365. if ((d & 0xff00) == 0xa500) { // WTCSR
  366. PREG8(r, 0x80) = d;
  367. p32x_timers_recalc();
  368. }
  369. if ((d & 0xff00) == 0x5a00) // WTCNT
  370. PREG8(r, 0x81) = d;
  371. return;
  372. }
  373. r[MEM_BE2(a / 2)] = d;
  374. if ((a & 0x1c0) == 0x140)
  375. p32x_sh2_poll_event(sh2, SH2_STATE_CPOLL, SekCyclesDone());
  376. }
  377. void REGPARM(3) sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2)
  378. {
  379. u32 *r = sh2->peri_regs;
  380. u32 old;
  381. struct dmac *dmac;
  382. elprintf_sh2(sh2, EL_32XP, "peri w32 [%08x] %08x @%06x",
  383. a, d, sh2_pc(sh2));
  384. a &= 0x1fc;
  385. old = r[a / 4];
  386. r[a / 4] = d;
  387. switch (a) {
  388. // division unit (TODO: verify):
  389. case 0x104: // DVDNT: divident L, starts divide
  390. elprintf_sh2(sh2, EL_32XP, "divide %08x / %08x",
  391. d, r[0x100 / 4]);
  392. if (r[0x100 / 4]) {
  393. signed int divisor = r[0x100 / 4];
  394. r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor;
  395. r[0x104 / 4] = r[0x11c / 4] = r[0x114 / 4] = (signed int)d / divisor;
  396. }
  397. else
  398. r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
  399. break;
  400. case 0x114:
  401. elprintf_sh2(sh2, EL_32XP, "divide %08x%08x / %08x @%08x",
  402. r[0x110 / 4], d, r[0x100 / 4], sh2_pc(sh2));
  403. if (r[0x100 / 4]) {
  404. signed long long divident = (signed long long)r[0x110 / 4] << 32 | d;
  405. signed int divisor = r[0x100 / 4];
  406. // XXX: undocumented mirroring to 0x118,0x11c?
  407. r[0x118 / 4] = r[0x110 / 4] = divident % divisor;
  408. divident /= divisor;
  409. r[0x11c / 4] = r[0x114 / 4] = divident;
  410. divident >>= 31;
  411. if ((unsigned long long)divident + 1 > 1) {
  412. //elprintf_sh2(sh2, EL_32XP, "divide overflow! @%08x", sh2_pc(sh2));
  413. r[0x11c / 4] = r[0x114 / 4] = divident > 0 ? 0x7fffffff : 0x80000000; // overflow
  414. }
  415. }
  416. else
  417. r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
  418. break;
  419. // perhaps starting a DMA?
  420. case 0x18c:
  421. case 0x19c:
  422. case 0x1b0:
  423. dmac = (void *)&sh2->peri_regs[0x180 / 4];
  424. if (a == 0x1b0 && !((old ^ d) & d & DMA_DME))
  425. return;
  426. if (!(dmac->dmaor & DMA_DME))
  427. return;
  428. DRC_SAVE_SR(sh2);
  429. if ((dmac->chan[0].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
  430. dmac_trigger(sh2, &dmac->chan[0]);
  431. if ((dmac->chan[1].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
  432. dmac_trigger(sh2, &dmac->chan[1]);
  433. DRC_RESTORE_SR(sh2);
  434. break;
  435. }
  436. if ((a & 0x1c0) == 0x140)
  437. p32x_sh2_poll_event(sh2, SH2_STATE_CPOLL, SekCyclesDone());
  438. }
  439. /* 32X specific */
  440. static void dreq0_do(SH2 *sh2, struct dma_chan *chan)
  441. {
  442. unsigned short dreqlen = Pico32x.regs[0x10 / 2];
  443. int i;
  444. // debug/sanity checks
  445. if (chan->tcr < dreqlen || chan->tcr > dreqlen + 4)
  446. elprintf(EL_32XP|EL_ANOMALY, "dreq0: tcr0/len inconsistent: %d/%d",
  447. chan->tcr, dreqlen);
  448. // note: DACK is not connected, single addr mode should not be used
  449. if ((chan->chcr & 0x3f08) != 0x0400)
  450. elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad control: %04x", chan->chcr);
  451. if ((chan->sar & ~0x20000000) != 0x00004012)
  452. elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad sar?: %08x", chan->sar);
  453. // HACK: assume bus is busy and SH2 is halted
  454. sh2->state |= SH2_STATE_SLEEP;
  455. for (i = 0; i < Pico32x.dmac0_fifo_ptr && chan->tcr > 0; i++) {
  456. elprintf_sh2(sh2, EL_32XP, "dreq0 [%08x] %04x, dreq_len %d",
  457. chan->dar, Pico32x.dmac_fifo[i], dreqlen);
  458. p32x_sh2_write16(chan->dar, Pico32x.dmac_fifo[i], sh2);
  459. chan->dar += 2;
  460. chan->tcr--;
  461. }
  462. if (Pico32x.dmac0_fifo_ptr != i)
  463. memmove(Pico32x.dmac_fifo, &Pico32x.dmac_fifo[i],
  464. (Pico32x.dmac0_fifo_ptr - i) * 2);
  465. Pico32x.dmac0_fifo_ptr -= i;
  466. Pico32x.regs[6 / 2] &= ~P32XS_FULL;
  467. if (chan->tcr == 0)
  468. dmac_transfer_complete(sh2, chan);
  469. else
  470. sh2_end_run(sh2, 16);
  471. }
  472. static void dreq1_do(SH2 *sh2, struct dma_chan *chan)
  473. {
  474. // debug/sanity checks
  475. if ((chan->chcr & 0xc308) != 0x0000)
  476. elprintf(EL_32XP|EL_ANOMALY, "dreq1: bad control: %04x", chan->chcr);
  477. if ((chan->dar & ~0xf) != 0x20004030)
  478. elprintf(EL_32XP|EL_ANOMALY, "dreq1: bad dar?: %08x\n", chan->dar);
  479. sh2->state |= SH2_STATE_SLEEP;
  480. dmac_transfer_one(sh2, chan);
  481. sh2->state &= ~SH2_STATE_SLEEP;
  482. if (chan->tcr == 0)
  483. dmac_transfer_complete(sh2, chan);
  484. }
  485. void p32x_dreq0_trigger(void)
  486. {
  487. struct dmac *mdmac = (void *)&msh2.peri_regs[0x180 / 4];
  488. struct dmac *sdmac = (void *)&ssh2.peri_regs[0x180 / 4];
  489. elprintf(EL_32XP, "dreq0_trigger");
  490. if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[0].chcr & 3) == DMA_DE) {
  491. dreq0_do(&msh2, &mdmac->chan[0]);
  492. }
  493. if ((sdmac->dmaor & DMA_DME) && (sdmac->chan[0].chcr & 3) == DMA_DE) {
  494. dreq0_do(&ssh2, &sdmac->chan[0]);
  495. }
  496. }
  497. void p32x_dreq1_trigger(void)
  498. {
  499. struct dmac *mdmac = (void *)&msh2.peri_regs[0x180 / 4];
  500. struct dmac *sdmac = (void *)&ssh2.peri_regs[0x180 / 4];
  501. int hit = 0;
  502. elprintf(EL_32XP, "dreq1_trigger");
  503. if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[1].chcr & 3) == DMA_DE) {
  504. dreq1_do(&msh2, &mdmac->chan[1]);
  505. hit = 1;
  506. }
  507. if ((sdmac->dmaor & DMA_DME) && (sdmac->chan[1].chcr & 3) == DMA_DE) {
  508. dreq1_do(&ssh2, &sdmac->chan[1]);
  509. hit = 1;
  510. }
  511. // debug
  512. #if (EL_LOGMASK & (EL_32XP|EL_ANOMALY))
  513. {
  514. static int miss_count;
  515. if (!hit) {
  516. if (++miss_count == 4)
  517. elprintf(EL_32XP|EL_ANOMALY, "dreq1: nobody cared");
  518. }
  519. else
  520. miss_count = 0;
  521. }
  522. #endif
  523. (void)hit;
  524. }
  525. // vim:shiftwidth=2:ts=2:expandtab