sh2.h 4.3 KB

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  1. #ifndef __SH2_H__
  2. #define __SH2_H__
  3. #include <pico/pico_types.h>
  4. #include <pico/pico_port.h>
  5. // registers - matches structure order
  6. typedef enum {
  7. SHR_R0 = 0, SHR_SP = 15,
  8. SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
  9. SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
  10. SH2_REGS, // register set size
  11. SHR_T = 29, SHR_MEM = 30, SHR_TMP = 31, // drc specific pseudo regs
  12. } sh2_reg_e;
  13. #define SHR_R(n) (SHR_R0+(n))
  14. typedef struct SH2_
  15. {
  16. // registers. this MUST correlate with enum sh2_reg_e.
  17. uint32_t r[16] ALIGNED(32);
  18. uint32_t pc; // 40
  19. uint32_t ppc;
  20. uint32_t pr;
  21. uint32_t sr;
  22. uint32_t gbr, vbr; // 50
  23. uint32_t mach, macl; // 58
  24. // common
  25. const void *read8_map;
  26. const void *read16_map;
  27. const void *read32_map;
  28. const void **write8_tab;
  29. const void **write16_tab;
  30. const void **write32_tab;
  31. // drc stuff
  32. int drc_tmp;
  33. int irq_cycles;
  34. void *p_bios; // convenience pointers
  35. void *p_da;
  36. void *p_sdram;
  37. void *p_rom;
  38. void *p_dram;
  39. void *p_drcblk_da;
  40. void *p_drcblk_ram;
  41. unsigned int pdb_io_csum[2];
  42. #define SH2_STATE_RUN (1 << 0) // to prevent recursion
  43. #define SH2_STATE_SLEEP (1 << 1) // temporarily stopped (DMA, IO, ...)
  44. #define SH2_STATE_CPOLL (1 << 2) // polling comm regs
  45. #define SH2_STATE_VPOLL (1 << 3) // polling VDP
  46. #define SH2_STATE_RPOLL (1 << 4) // polling address in SDRAM
  47. #define SH2_TIMER_RUN (1 << 6) // SOC WDT timer is running
  48. #define SH2_IN_DRC (1 << 7) // DRC in use
  49. unsigned int state;
  50. uint32_t poll_addr;
  51. int poll_cycles;
  52. int poll_cnt;
  53. // NB MUST be a bit unused in SH2 SR, see also cpu/sh2/compiler.c!
  54. #define SH2_NO_POLLING (1 << 10) // poll detection control
  55. int no_polling;
  56. // DRC branch cache. size must be 2^n and <=128
  57. int rts_cache_idx;
  58. struct { uint32_t pc; void *code; } rts_cache[16];
  59. struct { uint32_t pc; void *code; } branch_cache[128];
  60. // interpreter stuff
  61. int icount; // cycles left in current timeslice
  62. unsigned int ea;
  63. unsigned int delay;
  64. unsigned int test_irq;
  65. int pending_level; // MAX(pending_irl, pending_int_irq)
  66. int pending_irl;
  67. int pending_int_irq; // internal irq
  68. int pending_int_vector;
  69. int REGPARM(2) (*irq_callback)(struct SH2_ *sh2, int level);
  70. int is_slave;
  71. unsigned int cycles_timeslice;
  72. struct SH2_ *other_sh2;
  73. int (*run)(struct SH2_ *, int);
  74. // we use 68k reference cycles for easier sync
  75. unsigned int m68krcycles_done;
  76. unsigned int mult_m68k_to_sh2;
  77. unsigned int mult_sh2_to_m68k;
  78. uint8_t data_array[0x1000]; // cache (can be used as RAM)
  79. uint32_t peri_regs[0x200/4]; // peripheral regs
  80. } SH2;
  81. #define CYCLE_MULT_SHIFT 10
  82. #define C_M68K_TO_SH2(xsh2, c) \
  83. (int)(((uint64_t)(c) * (xsh2)->mult_m68k_to_sh2) >> CYCLE_MULT_SHIFT)
  84. #define C_SH2_TO_M68K(xsh2, c) \
  85. (int)(((uint64_t)(c+3U) * (xsh2)->mult_sh2_to_m68k) >> CYCLE_MULT_SHIFT)
  86. int sh2_init(SH2 *sh2, int is_slave, SH2 *other_sh2);
  87. void sh2_finish(SH2 *sh2);
  88. void sh2_reset(SH2 *sh2);
  89. int sh2_irl_irq(SH2 *sh2, int level, int nested_call);
  90. void sh2_internal_irq(SH2 *sh2, int level, int vector);
  91. void sh2_do_irq(SH2 *sh2, int level, int vector);
  92. void sh2_pack(const SH2 *sh2, unsigned char *buff);
  93. void sh2_unpack(SH2 *sh2, const unsigned char *buff);
  94. int sh2_execute_drc(SH2 *sh2c, int cycles);
  95. int sh2_execute_interpreter(SH2 *sh2c, int cycles);
  96. static __inline void sh2_execute_prepare(SH2 *sh2, int use_drc)
  97. {
  98. #ifdef DRC_SH2
  99. sh2->run = use_drc ? sh2_execute_drc : sh2_execute_interpreter;
  100. #else
  101. sh2->run = sh2_execute_interpreter;
  102. #endif
  103. }
  104. static __inline int sh2_execute(SH2 *sh2, int cycles)
  105. {
  106. int ret;
  107. sh2->cycles_timeslice = cycles;
  108. ret = sh2->run(sh2, cycles);
  109. return sh2->cycles_timeslice - ret;
  110. }
  111. // regs, pending_int*, cycles, reserved
  112. #define SH2_STATE_SIZE ((24 + 2 + 2 + 12) * 4)
  113. // pico memhandlers
  114. // XXX: move somewhere else
  115. u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2);
  116. u32 REGPARM(2) p32x_sh2_read16(u32 a, SH2 *sh2);
  117. u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2);
  118. void REGPARM(3) p32x_sh2_write8 (u32 a, u32 d, SH2 *sh2);
  119. void REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2);
  120. void REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2);
  121. // debug
  122. #ifdef DRC_CMP
  123. void do_sh2_trace(SH2 *current, int cycles);
  124. void REGPARM(1) do_sh2_cmp(SH2 *current);
  125. #endif
  126. #endif /* __SH2_H__ */