emit_x86.c 39 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434
  1. /*
  2. * Basic macros to emit x86 instructions and some utils
  3. * Copyright (C) 2008,2009,2010 notaz
  4. * Copyright (C) 2019 kub
  5. *
  6. * This work is licensed under the terms of MAME license.
  7. * See COPYING file in the top-level directory.
  8. *
  9. * note:
  10. * temp registers must be eax-edx due to use of SETcc and r/w 8/16.
  11. * note about silly things like emith_eor_r_r_r:
  12. * these are here because the compiler was designed
  13. * for ARM as it's primary target.
  14. */
  15. #include <stdarg.h>
  16. enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI, // x86-64,i386 common
  17. xR8, xR9, xR10, xR11, xR12, xR13, xR14, xR15 }; // x86-64 only
  18. #define CONTEXT_REG xBP
  19. #define RET_REG xAX
  20. #define ICOND_JO 0x00
  21. #define ICOND_JNO 0x01
  22. #define ICOND_JB 0x02
  23. #define ICOND_JAE 0x03
  24. #define ICOND_JE 0x04
  25. #define ICOND_JNE 0x05
  26. #define ICOND_JBE 0x06
  27. #define ICOND_JA 0x07
  28. #define ICOND_JS 0x08
  29. #define ICOND_JNS 0x09
  30. #define ICOND_JL 0x0c
  31. #define ICOND_JGE 0x0d
  32. #define ICOND_JLE 0x0e
  33. #define ICOND_JG 0x0f
  34. #define IOP_JMP 0xeb
  35. // unified conditions (we just use rel8 jump instructions for x86)
  36. #define DCOND_EQ ICOND_JE
  37. #define DCOND_NE ICOND_JNE
  38. #define DCOND_MI ICOND_JS // MInus
  39. #define DCOND_PL ICOND_JNS // PLus or zero
  40. #define DCOND_HI ICOND_JA // higher (unsigned)
  41. #define DCOND_HS ICOND_JAE // higher || same (unsigned)
  42. #define DCOND_LO ICOND_JB // lower (unsigned)
  43. #define DCOND_LS ICOND_JBE // lower || same (unsigned)
  44. #define DCOND_GE ICOND_JGE // greater || equal (signed)
  45. #define DCOND_GT ICOND_JG // greater (signed)
  46. #define DCOND_LE ICOND_JLE // less || equal (signed)
  47. #define DCOND_LT ICOND_JL // less (signed)
  48. #define DCOND_VS ICOND_JO // oVerflow Set
  49. #define DCOND_VC ICOND_JNO // oVerflow Clear
  50. #define DCOND_CS ICOND_JB // carry set
  51. #define DCOND_CC ICOND_JAE // carry clear
  52. #define EMIT_PTR(ptr, val, type) \
  53. *(type *)(ptr) = val
  54. #define EMIT(val, type) do { \
  55. EMIT_PTR(tcache_ptr, val, type); \
  56. tcache_ptr += sizeof(type); \
  57. } while (0)
  58. #define EMIT_OP(op) do { \
  59. COUNT_OP; \
  60. if ((op) > 0xff) EMIT((op) >> 8, u8); \
  61. EMIT((u8)(op), u8); \
  62. } while (0)
  63. #define EMIT_MODRM(mod, r, rm) do { \
  64. assert((mod) < 4u); \
  65. assert((r) < 8u); \
  66. assert((rm) < 8u); \
  67. EMIT(((mod)<<6) | ((r)<<3) | (rm), u8); \
  68. } while (0)
  69. #define EMIT_SIB(scale, index, base) do { \
  70. assert((scale) < 4u); \
  71. assert((index) < 8u); \
  72. assert((base) < 8u); \
  73. EMIT(((scale)<<6) | ((index)<<3) | (base), u8); \
  74. } while (0)
  75. #define EMIT_SIB64(scale, index, base) \
  76. EMIT_SIB(scale, (index) & ~8u, (base) & ~8u)
  77. #define EMIT_REX(w,r,x,b) \
  78. EMIT(0x40 | ((w)<<3) | ((r)<<2) | ((x)<<1) | (b), u8)
  79. #define EMIT_OP_MODRM(op,mod,r,rm) do { \
  80. EMIT_OP(op); \
  81. EMIT_MODRM(mod, (r), rm); \
  82. } while (0)
  83. // 64bit friendly, rm when everything is converted
  84. #define EMIT_OP_MODRM64(op, mod, r, rm) \
  85. EMIT_OP_MODRM(op, mod, (r) & ~8u, (rm) & ~8u)
  86. #define JMP8_POS(ptr) \
  87. ptr = tcache_ptr; \
  88. tcache_ptr += 2
  89. #define JMP8_EMIT(op, ptr) \
  90. EMIT_PTR(ptr, 0x70|(op), u8); \
  91. EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)
  92. #define JMP8_EMIT_NC(ptr) \
  93. EMIT_PTR(ptr, IOP_JMP, u8); \
  94. EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)
  95. // _r_r
  96. #define emith_move_r_r(dst, src) do {\
  97. EMIT_REX_IF(0, dst, src); \
  98. EMIT_OP_MODRM64(0x8b, 3, dst, src); \
  99. } while (0)
  100. #define emith_move_r_r_ptr(dst, src) do { \
  101. EMIT_REX_IF(1, dst, src); \
  102. EMIT_OP_MODRM64(0x8b, 3, dst, src); \
  103. } while (0)
  104. #define emith_add_r_r(d, s) do { \
  105. EMIT_REX_IF(0, s, d); \
  106. EMIT_OP_MODRM64(0x01, 3, s, d); \
  107. } while (0)
  108. #define emith_add_r_r_ptr(d, s) do { \
  109. EMIT_REX_IF(1, s, d); \
  110. EMIT_OP_MODRM64(0x01, 3, s, d); \
  111. } while (0)
  112. #define emith_sub_r_r(d, s) do {\
  113. EMIT_REX_IF(0, s, d); \
  114. EMIT_OP_MODRM64(0x29, 3, s, d); \
  115. } while (0)
  116. #define emith_adc_r_r(d, s) do { \
  117. EMIT_REX_IF(0, s, d); \
  118. EMIT_OP_MODRM64(0x11, 3, s, d); \
  119. } while (0)
  120. #define emith_sbc_r_r(d, s) do { \
  121. EMIT_REX_IF(0, s, d); \
  122. EMIT_OP_MODRM64(0x19, 3, s, d); /* SBB */ \
  123. } while (0)
  124. #define emith_or_r_r(d, s) do { \
  125. EMIT_REX_IF(0, s, d); \
  126. EMIT_OP_MODRM64(0x09, 3, s, d); \
  127. } while (0)
  128. #define emith_and_r_r(d, s) do { \
  129. EMIT_REX_IF(0, s, d); \
  130. EMIT_OP_MODRM64(0x21, 3, s, d); \
  131. } while (0)
  132. #define emith_eor_r_r(d, s) do { \
  133. EMIT_REX_IF(0, s, d); \
  134. EMIT_OP_MODRM64(0x31, 3, s, d); /* XOR */ \
  135. } while (0)
  136. #define emith_tst_r_r(d, s) do { \
  137. EMIT_REX_IF(0, s, d); \
  138. EMIT_OP_MODRM64(0x85, 3, s, d); /* TEST */ \
  139. } while (0)
  140. #define emith_tst_r_r_ptr(d, s) do { \
  141. EMIT_REX_IF(1, s, d); \
  142. EMIT_OP_MODRM64(0x85, 3, s, d); /* TEST */ \
  143. } while (0)
  144. #define emith_cmp_r_r(d, s) do { \
  145. EMIT_REX_IF(0, s, d); \
  146. EMIT_OP_MODRM64(0x39, 3, s, d); \
  147. } while (0)
  148. // fake teq - test equivalence - get_flags(d ^ s)
  149. #define emith_teq_r_r(d, s) do { \
  150. emith_push(d); \
  151. emith_eor_r_r(d, s); \
  152. emith_pop(d); \
  153. } while (0)
  154. #define emith_mvn_r_r(d, s) do { \
  155. if (d != s) \
  156. emith_move_r_r(d, s); \
  157. EMIT_REX_IF(0, 0, d); \
  158. EMIT_OP_MODRM64(0xf7, 3, 2, d); /* NOT d */ \
  159. } while (0)
  160. #define emith_negc_r_r(d, s) do { \
  161. int tmp_ = rcache_get_tmp(); \
  162. emith_move_r_imm(tmp_, 0); \
  163. emith_sbc_r_r(tmp_, s); \
  164. emith_move_r_r(d, tmp_); \
  165. rcache_free_tmp(tmp_); \
  166. } while (0)
  167. #define emith_neg_r_r(d, s) do { \
  168. if (d != s) \
  169. emith_move_r_r(d, s); \
  170. EMIT_REX_IF(0, 0, d); \
  171. EMIT_OP_MODRM64(0xf7, 3, 3, d); /* NEG d */ \
  172. } while (0)
  173. // _r_r_r
  174. #define emith_add_r_r_r(d, s1, s2) do { \
  175. if (d == s1) { \
  176. emith_add_r_r(d, s2); \
  177. } else if (d == s2) { \
  178. emith_add_r_r(d, s1); \
  179. } else { \
  180. emith_move_r_r(d, s1); \
  181. emith_add_r_r(d, s2); \
  182. } \
  183. } while (0)
  184. #define emith_add_r_r_r_ptr(d, s1, s2) do { \
  185. if (d == s1) { \
  186. emith_add_r_r_ptr(d, s2); \
  187. } else if (d == s2) { \
  188. emith_add_r_r_ptr(d, s1); \
  189. } else { \
  190. emith_move_r_r_ptr(d, s1); \
  191. emith_add_r_r_ptr(d, s2); \
  192. } \
  193. } while (0)
  194. #define emith_sub_r_r_r(d, s1, s2) do { \
  195. if (d == s1) { \
  196. emith_sub_r_r(d, s2); \
  197. } else if (d == s2) { \
  198. emith_sub_r_r(d, s1); \
  199. } else { \
  200. emith_move_r_r(d, s1); \
  201. emith_sub_r_r(d, s2); \
  202. } \
  203. } while (0)
  204. #define emith_adc_r_r_r(d, s1, s2) do { \
  205. if (d == s1) { \
  206. emith_adc_r_r(d, s2); \
  207. } else if (d == s2) { \
  208. emith_adc_r_r(d, s1); \
  209. } else { \
  210. emith_move_r_r(d, s1); \
  211. emith_adc_r_r(d, s2); \
  212. } \
  213. } while (0)
  214. #define emith_sbc_r_r_r(d, s1, s2) do { \
  215. if (d == s1) { \
  216. emith_sbc_r_r(d, s2); \
  217. } else if (d == s2) { \
  218. emith_sbc_r_r(d, s1); \
  219. } else { \
  220. emith_move_r_r(d, s1); \
  221. emith_sbc_r_r(d, s2); \
  222. } \
  223. } while (0)
  224. #define emith_and_r_r_r(d, s1, s2) do { \
  225. if (d == s1) { \
  226. emith_and_r_r(d, s2); \
  227. } else if (d == s2) { \
  228. emith_and_r_r(d, s1); \
  229. } else { \
  230. emith_move_r_r(d, s1); \
  231. emith_and_r_r(d, s2); \
  232. } \
  233. } while (0)
  234. #define emith_or_r_r_r(d, s1, s2) do { \
  235. if (d == s1) { \
  236. emith_or_r_r(d, s2); \
  237. } else if (d == s2) { \
  238. emith_or_r_r(d, s1); \
  239. } else { \
  240. emith_move_r_r(d, s1); \
  241. emith_or_r_r(d, s2); \
  242. } \
  243. } while (0)
  244. #define emith_eor_r_r_r(d, s1, s2) do { \
  245. if (d == s1) { \
  246. emith_eor_r_r(d, s2); \
  247. } else if (d == s2) { \
  248. emith_eor_r_r(d, s1); \
  249. } else { \
  250. emith_move_r_r(d, s1); \
  251. emith_eor_r_r(d, s2); \
  252. } \
  253. } while (0)
  254. // _r_r_r_shift
  255. #define emith_add_r_r_r_lsl(d, s1, s2, lslimm) do { \
  256. if (lslimm) { \
  257. int tmp_ = rcache_get_tmp(); \
  258. emith_lsl(tmp_, s2, lslimm); \
  259. emith_add_r_r_r(d, s1, tmp_); \
  260. rcache_free_tmp(tmp_); \
  261. } else emith_add_r_r_r(d, s1, s2); \
  262. } while (0)
  263. #define emith_add_r_r_r_lsl_ptr(d, s1, s2, lslimm) do { \
  264. if (lslimm) { \
  265. int tmp_ = rcache_get_tmp(); \
  266. emith_lsl(tmp_, s2, lslimm); \
  267. emith_add_r_r_r_ptr(d, s1, tmp_); \
  268. rcache_free_tmp(tmp_); \
  269. } else emith_add_r_r_r_ptr(d, s1, s2); \
  270. } while (0)
  271. #define emith_add_r_r_r_lsr(d, s1, s2, lsrimm) do { \
  272. if (lsrimm) { \
  273. int tmp_ = rcache_get_tmp(); \
  274. emith_lsr(tmp_, s2, lsrimm); \
  275. emith_add_r_r_r(d, s1, tmp_); \
  276. rcache_free_tmp(tmp_); \
  277. } else emith_add_r_r_r(d, s1, s2); \
  278. } while (0)
  279. #define emith_sub_r_r_r_lsl(d, s1, s2, lslimm) do { \
  280. if (lslimm) { \
  281. int tmp_ = rcache_get_tmp(); \
  282. emith_lsl(tmp_, s2, lslimm); \
  283. emith_sub_r_r_r(d, s1, tmp_); \
  284. rcache_free_tmp(tmp_); \
  285. } else emith_sub_r_r_r(d, s1, s2); \
  286. } while (0)
  287. #define emith_or_r_r_r_lsl(d, s1, s2, lslimm) do { \
  288. if (lslimm) { \
  289. int tmp_ = rcache_get_tmp(); \
  290. emith_lsl(tmp_, s2, lslimm); \
  291. emith_or_r_r_r(d, s1, tmp_); \
  292. rcache_free_tmp(tmp_); \
  293. } else emith_or_r_r_r(d, s1, s2); \
  294. } while (0)
  295. #define emith_or_r_r_r_lsr(d, s1, s2, lsrimm) do { \
  296. if (lsrimm) { \
  297. int tmp_ = rcache_get_tmp(); \
  298. emith_lsr(tmp_, s2, lsrimm); \
  299. emith_or_r_r_r(d, s1, tmp_); \
  300. rcache_free_tmp(tmp_); \
  301. } else emith_or_r_r_r(d, s1, s2); \
  302. } while (0)
  303. #define emith_eor_r_r_r_lsr(d, s1, s2, lsrimm) do { \
  304. if (lsrimm) { \
  305. int tmp_ = rcache_get_tmp(); \
  306. emith_lsr(tmp_, s2, lsrimm); \
  307. emith_eor_r_r_r(d, s1, tmp_); \
  308. rcache_free_tmp(tmp_); \
  309. } else emith_eor_r_r_r(d, s1, s2); \
  310. } while (0)
  311. // _r_r_shift
  312. #define emith_or_r_r_lsl(d, s, lslimm) \
  313. emith_or_r_r_r_lsl(d, d, s, lslimm)
  314. #define emith_or_r_r_lsr(d, s, lsrimm) \
  315. emith_or_r_r_r_lsr(d, d, s, lsrimm)
  316. #define emith_eor_r_r_lsl(d, s, lslimm) do { \
  317. if (lslimm) { \
  318. int tmp_ = rcache_get_tmp(); \
  319. emith_lsl(tmp_, s, lslimm); \
  320. emith_eor_r_r(d, tmp_); \
  321. rcache_free_tmp(tmp_); \
  322. } else emith_eor_r_r(d, s); \
  323. } while (0)
  324. #define emith_eor_r_r_lsr(d, s, lsrimm) do { \
  325. if (lsrimm) { \
  326. int tmp_ = rcache_get_tmp(); \
  327. emith_lsr(tmp_, s, lsrimm); \
  328. emith_eor_r_r(d, tmp_); \
  329. rcache_free_tmp(tmp_); \
  330. } else emith_eor_r_r(d, s); \
  331. } while (0)
  332. // _r_imm
  333. #define emith_move_r_imm(r, imm) do { \
  334. EMIT_REX_IF(0, 0, r); \
  335. EMIT_OP(0xb8 + ((r)&7)); \
  336. EMIT(imm, u32); \
  337. } while (0)
  338. #define emith_move_r_ptr_imm(r, imm) do { \
  339. if ((uintptr_t)(imm) <= UINT32_MAX) \
  340. emith_move_r_imm(r, (uintptr_t)(imm)); \
  341. else { \
  342. EMIT_REX_IF(1, 0, r); \
  343. EMIT_OP(0xb8 + ((r)&7)); \
  344. EMIT((uintptr_t)(imm), uint64_t); \
  345. } \
  346. } while (0)
  347. #define emith_move_r_imm_s8_patchable(r, imm) do { \
  348. EMIT_REX_IF(0, 0, r); \
  349. EMIT_OP(0xb8 + ((r)&7)); \
  350. EMIT((s8)(imm), u32); \
  351. } while (0)
  352. #define emith_move_r_imm_s8_patch(ptr, imm) do { \
  353. u8 *ptr_ = ptr; \
  354. while ((*ptr_ & 0xf8) != 0xb8) ptr_++; \
  355. EMIT_PTR(ptr_ + 1, (s8)(imm), u32); \
  356. } while (0)
  357. #define emith_arith_r_imm(op, r, imm) do { \
  358. EMIT_REX_IF(0, 0, r); \
  359. EMIT_OP_MODRM64(0x81, 3, op, r); \
  360. EMIT(imm, u32); \
  361. } while (0)
  362. #define emith_add_r_imm(r, imm) \
  363. emith_arith_r_imm(0, r, imm)
  364. #define emith_or_r_imm(r, imm) \
  365. emith_arith_r_imm(1, r, imm)
  366. #define emith_adc_r_imm(r, imm) \
  367. emith_arith_r_imm(2, r, imm)
  368. #define emith_sbc_r_imm(r, imm) \
  369. emith_arith_r_imm(3, r, imm) // sbb
  370. #define emith_and_r_imm(r, imm) \
  371. emith_arith_r_imm(4, r, imm)
  372. #define emith_sub_r_imm(r, imm) \
  373. emith_arith_r_imm(5, r, imm)
  374. #define emith_eor_r_imm(r, imm) \
  375. emith_arith_r_imm(6, r, imm)
  376. #define emith_cmp_r_imm(r, imm) \
  377. emith_arith_r_imm(7, r, imm)
  378. #define emith_eor_r_imm_ptr(r, imm) do { \
  379. EMIT_REX_IF(1, 0, r); \
  380. EMIT_OP_MODRM64(0x81, 3, 6, r); \
  381. EMIT(imm, u32); \
  382. } while (0)
  383. #define emith_tst_r_imm(r, imm) do { \
  384. EMIT_REX_IF(0, 0, r); \
  385. EMIT_OP_MODRM64(0xf7, 3, 0, r); \
  386. EMIT(imm, u32); \
  387. } while (0)
  388. // fake
  389. #define emith_bic_r_imm(r, imm) \
  390. emith_arith_r_imm(4, r, ~(imm))
  391. // fake conditionals (using SJMP instead)
  392. #define emith_move_r_imm_c(cond, r, imm) \
  393. emith_move_r_imm(r, imm)
  394. #define emith_add_r_imm_c(cond, r, imm) \
  395. emith_add_r_imm(r, imm)
  396. #define emith_sub_r_imm_c(cond, r, imm) \
  397. emith_sub_r_imm(r, imm)
  398. #define emith_or_r_imm_c(cond, r, imm) \
  399. emith_or_r_imm(r, imm)
  400. #define emith_eor_r_imm_c(cond, r, imm) \
  401. emith_eor_r_imm(r, imm)
  402. #define emith_eor_r_imm_ptr_c(cond, r, imm) \
  403. emith_eor_r_imm_ptr(r, imm)
  404. #define emith_bic_r_imm_c(cond, r, imm) \
  405. emith_bic_r_imm(r, imm)
  406. #define emith_tst_r_imm_c(cond, r, imm) \
  407. emith_tst_r_imm(r, imm)
  408. #define emith_move_r_r_ptr_c(cond, d, s) \
  409. emith_move_r_r_ptr(d, s)
  410. #define emith_ror_c(cond, d, s, cnt) \
  411. emith_ror(d, s, cnt)
  412. #define emith_and_r_r_c(cond, d, s) \
  413. emith_and_r_r(d, s)
  414. #define emith_add_r_r_imm_c(cond, d, s, imm) \
  415. emith_add_r_r_imm(d, s, imm)
  416. #define emith_sub_r_r_imm_c(cond, d, s, imm) \
  417. emith_sub_r_r_imm(d, s, imm)
  418. #define emith_read8_r_r_r_c(cond, r, rs, rm) \
  419. emith_read8_r_r_r(r, rs, rm)
  420. #define emith_read8s_r_r_r_c(cond, r, rs, rm) \
  421. emith_read8s_r_r_r(r, rs, rm)
  422. #define emith_read16_r_r_r_c(cond, r, rs, rm) \
  423. emith_read16_r_r_r(r, rs, rm)
  424. #define emith_read16s_r_r_r_c(cond, r, rs, rm) \
  425. emith_read16s_r_r_r(r, rs, rm)
  426. #define emith_read_r_r_r_c(cond, r, rs, rm) \
  427. emith_read_r_r_r(r, rs, rm)
  428. #define emith_read_r_r_offs_c(cond, r, rs, offs) \
  429. emith_read_r_r_offs(r, rs, offs)
  430. #define emith_read_r_r_offs_ptr_c(cond, r, rs, offs) \
  431. emith_read_r_r_offs_ptr(r, rs, offs)
  432. #define emith_write_r_r_offs_c(cond, r, rs, offs) \
  433. emith_write_r_r_offs(r, rs, offs)
  434. #define emith_write_r_r_offs_ptr_c(cond, r, rs, offs) \
  435. emith_write_r_r_offs_ptr(r, rs, offs)
  436. #define emith_read8_r_r_offs_c(cond, r, rs, offs) \
  437. emith_read8_r_r_offs(r, rs, offs)
  438. #define emith_write8_r_r_offs_c(cond, r, rs, offs) \
  439. emith_write8_r_r_offs(r, rs, offs)
  440. #define emith_read16_r_r_offs_c(cond, r, rs, offs) \
  441. emith_read16_r_r_offs(r, rs, offs)
  442. #define emith_write16_r_r_offs_c(cond, r, rs, offs) \
  443. emith_write16_r_r_offs(r, rs, offs)
  444. #define emith_jump_reg_c(cond, r) \
  445. emith_jump_reg(r)
  446. #define emith_jump_ctx_c(cond, offs) \
  447. emith_jump_ctx(offs)
  448. #define emith_ret_c(cond) \
  449. emith_ret()
  450. // _r_r_imm - use lea
  451. #define emith_add_r_r_imm(d, s, imm) do { \
  452. EMIT_REX_IF(0, d, s); \
  453. emith_deref_modrm(0x8d, 2, d, s); \
  454. EMIT(imm, s32); \
  455. } while (0)
  456. #define emith_add_r_r_ptr_imm(d, s, imm) do { \
  457. EMIT_REX_IF(1, d, s); \
  458. emith_deref_modrm(0x8d, 2, d, s); \
  459. EMIT(imm, s32); \
  460. } while (0)
  461. #define emith_sub_r_r_imm(d, s, imm) do { \
  462. if (d != s) \
  463. emith_move_r_r(d, s); \
  464. if ((s32)(imm) != 0) \
  465. emith_sub_r_imm(d, imm); \
  466. } while (0)
  467. #define emith_and_r_r_imm(d, s, imm) do { \
  468. if (d != s) \
  469. emith_move_r_r(d, s); \
  470. if ((s32)(imm) != -1) \
  471. emith_and_r_imm(d, imm); \
  472. } while (0)
  473. #define emith_or_r_r_imm(d, s, imm) do { \
  474. if (d != s) \
  475. emith_move_r_r(d, s); \
  476. if ((s32)(imm) != 0) \
  477. emith_or_r_imm(d, imm); \
  478. } while (0)
  479. #define emith_eor_r_r_imm(d, s, imm) do { \
  480. if (d != s) \
  481. emith_move_r_r(d, s); \
  482. if ((s32)(imm) != 0) \
  483. emith_eor_r_imm(d, imm); \
  484. } while (0)
  485. // shift
  486. #define emith_shift(op, d, s, cnt) do { \
  487. if (d != s) \
  488. emith_move_r_r(d, s); \
  489. EMIT_REX_IF(0, 0, d); \
  490. EMIT_OP_MODRM64(0xc1, 3, op, d); \
  491. EMIT(cnt, u8); \
  492. } while (0)
  493. #define emith_lsl(d, s, cnt) \
  494. emith_shift(4, d, s, cnt)
  495. #define emith_lsr(d, s, cnt) \
  496. emith_shift(5, d, s, cnt)
  497. #define emith_asr(d, s, cnt) \
  498. emith_shift(7, d, s, cnt)
  499. #define emith_rol(d, s, cnt) \
  500. emith_shift(0, d, s, cnt)
  501. #define emith_ror(d, s, cnt) \
  502. emith_shift(1, d, s, cnt)
  503. #define emith_rolc(r) do { \
  504. EMIT_REX_IF(0, 0, r); \
  505. EMIT_OP_MODRM64(0xd1, 3, 2, r); \
  506. } while (0)
  507. #define emith_rorc(r) do { \
  508. EMIT_REX_IF(0, 0, r); \
  509. EMIT_OP_MODRM64(0xd1, 3, 3, r); \
  510. } while (0)
  511. // misc
  512. #define emith_push(r) do { \
  513. EMIT_REX_IF(0, 0, r); \
  514. EMIT_OP(0x50 + ((r)&7)); \
  515. } while (0)
  516. #define emith_push_imm(imm) do { \
  517. EMIT_OP(0x68); \
  518. EMIT(imm, u32); \
  519. } while (0)
  520. #define emith_pop(r) do { \
  521. EMIT_REX_IF(0, 0, r); \
  522. EMIT_OP(0x58 + ((r)&7)); \
  523. } while (0)
  524. #define emith_neg_r(r) do { \
  525. EMIT_REX_IF(0, 0, r); \
  526. EMIT_OP_MODRM64(0xf7, 3, 3, r); \
  527. } while (0)
  528. #define emith_clear_msb(d, s, count) do { \
  529. u32 t = (u32)-1; \
  530. t >>= count; \
  531. if (d != s) \
  532. emith_move_r_r(d, s); \
  533. if (count) emith_and_r_imm(d, t); \
  534. } while (0)
  535. #define emith_clear_msb_c(cond, d, s, count) do { \
  536. (void)(cond); \
  537. emith_clear_msb(d, s, count); \
  538. } while (0)
  539. #define emith_sext(d, s, bits) do { \
  540. emith_lsl(d, s, 32 - (bits)); \
  541. emith_asr(d, d, 32 - (bits)); \
  542. } while (0)
  543. #define emith_uext_ptr(r) /**/
  544. #define emith_setc(r) do { \
  545. assert(is_abcdx(r)); \
  546. EMIT_REX_IF(0, 0, r); \
  547. EMIT_OP_MODRM64(0x0f92, 3, 0, r); /* SETC r */ \
  548. } while (0)
  549. // XXX: stupid mess
  550. #define emith_mul_(op, dlo, dhi, s1, s2) do { \
  551. int rmr; \
  552. if (dlo != xAX && dhi != xAX && rcache_is_hreg_used(xAX)) \
  553. emith_push(xAX); \
  554. if (dlo != xDX && dhi != xDX && rcache_is_hreg_used(xDX)) \
  555. emith_push(xDX); \
  556. if ((s1) == xAX) \
  557. rmr = s2; \
  558. else if ((s2) == xAX) \
  559. rmr = s1; \
  560. else { \
  561. emith_move_r_r(xAX, s1); \
  562. rmr = s2; \
  563. } \
  564. EMIT_REX_IF(0, 0, rmr); \
  565. EMIT_OP_MODRM64(0xf7, 3, op, rmr); /* xMUL rmr */ \
  566. if (dlo != xAX) { \
  567. EMIT_REX_IF(0, 0, dlo); \
  568. EMIT_OP(0x90 + ((dlo)&7)); /* XCHG eax, dlo */ \
  569. } \
  570. if (dhi != xDX && dhi != -1 && !(dhi == xAX && dlo == xDX)) \
  571. emith_move_r_r(dhi, (dlo == xDX ? xAX : xDX)); \
  572. if (dlo != xDX && dhi != xDX && rcache_is_hreg_used(xDX)) \
  573. emith_pop(xDX); \
  574. if (dlo != xAX && dhi != xAX && rcache_is_hreg_used(xAX)) \
  575. emith_pop(xAX); \
  576. } while (0)
  577. #define emith_mul_u64(dlo, dhi, s1, s2) \
  578. emith_mul_(4, dlo, dhi, s1, s2) /* MUL */
  579. #define emith_mul_s64(dlo, dhi, s1, s2) \
  580. emith_mul_(5, dlo, dhi, s1, s2) /* IMUL */
  581. #define emith_mul(d, s1, s2) do { \
  582. if (d == s1) { \
  583. EMIT_REX_IF(0, d, s2); \
  584. EMIT_OP_MODRM64(0x0faf, 3, d, s2); \
  585. } else if (d == s2) { \
  586. EMIT_REX_IF(0, d, s1); \
  587. EMIT_OP_MODRM64(0x0faf, 3, d, s1); \
  588. } else { \
  589. emith_move_r_r(d, s1); \
  590. EMIT_REX_IF(0, d, s2); \
  591. EMIT_OP_MODRM64(0x0faf, 3, d, s2); \
  592. } \
  593. } while (0)
  594. // (dlo,dhi) += signed(s1) * signed(s2)
  595. #define emith_mula_s64(dlo, dhi, s1, s2) do { \
  596. emith_push(dhi); \
  597. emith_push(dlo); \
  598. emith_mul_(5, dlo, dhi, s1, s2); \
  599. EMIT_REX_IF(0, dlo, xSP); \
  600. emith_deref_modrm(0x03, 0, dlo, xSP); /* add dlo, [xsp] */ \
  601. EMIT_REX_IF(0, dhi, xSP); \
  602. emith_deref_modrm(0x13, 1, dhi, xSP); /* adc dhi, [xsp+{4,8}] */ \
  603. EMIT(sizeof(void *), u8); \
  604. emith_add_r_r_ptr_imm(xSP, xSP, sizeof(void *) * 2); \
  605. } while (0)
  606. // "flag" instructions are the same
  607. #define emith_adcf_r_imm emith_adc_r_imm
  608. #define emith_subf_r_imm emith_sub_r_imm
  609. #define emith_addf_r_r emith_add_r_r
  610. #define emith_subf_r_r emith_sub_r_r
  611. #define emith_adcf_r_r emith_adc_r_r
  612. #define emith_sbcf_r_r emith_sbc_r_r
  613. #define emith_eorf_r_r emith_eor_r_r
  614. #define emith_negcf_r_r emith_negc_r_r
  615. #define emith_subf_r_r_imm emith_sub_r_r_imm
  616. #define emith_addf_r_r_r emith_add_r_r_r
  617. #define emith_subf_r_r_r emith_sub_r_r_r
  618. #define emith_adcf_r_r_r emith_adc_r_r_r
  619. #define emith_sbcf_r_r_r emith_sbc_r_r_r
  620. #define emith_eorf_r_r_r emith_eor_r_r_r
  621. #define emith_addf_r_r_r_lsr emith_add_r_r_r_lsr
  622. #define emith_lslf emith_lsl
  623. #define emith_lsrf emith_lsr
  624. #define emith_asrf emith_asr
  625. #define emith_rolf emith_rol
  626. #define emith_rorf emith_ror
  627. #define emith_rolcf emith_rolc
  628. #define emith_rorcf emith_rorc
  629. #define emith_deref_modrm(op, m, r, rs) do { \
  630. if (((rs) & 7) == 5 && m == 0) { /* xBP,xR13 not in mod 0, use mod 1 */\
  631. EMIT_OP_MODRM64(op, 1, r, rs); \
  632. EMIT(0, u8); \
  633. } else if (((rs) & 7) == 4) { /* xSP,xR12 must use SIB */ \
  634. EMIT_OP_MODRM64(op, m, r, 4); \
  635. EMIT_SIB64(0, 4, rs); \
  636. } else \
  637. EMIT_OP_MODRM64(op, m, r, rs); \
  638. } while (0)
  639. #define emith_deref_op(op, r, rs, offs) do { \
  640. /* mov r <-> [ebp+#offs] */ \
  641. if ((offs) == 0) { \
  642. emith_deref_modrm(op, 0, r, rs); \
  643. } else if ((s32)(offs) < -0x80 || (s32)(offs) >= 0x80) { \
  644. emith_deref_modrm(op, 2, r, rs); \
  645. EMIT(offs, u32); \
  646. } else { \
  647. emith_deref_modrm(op, 1, r, rs); \
  648. EMIT((u8)offs, u8); \
  649. } \
  650. } while (0)
  651. #define is_abcdx(r) !((r) & ~0x3)
  652. #define emith_read_r_r_offs(r, rs, offs) do { \
  653. EMIT_REX_IF(0, r, rs); \
  654. emith_deref_op(0x8b, r, rs, offs); \
  655. } while (0)
  656. #define emith_read_r_r_offs_ptr(r, rs, offs) do { \
  657. EMIT_REX_IF(1, r, rs); \
  658. emith_deref_op(0x8b, r, rs, offs); \
  659. } while (0)
  660. #define emith_write_r_r_offs(r, rs, offs) do { \
  661. EMIT_REX_IF(0, r, rs); \
  662. emith_deref_op(0x89, r, rs, offs); \
  663. } while (0)
  664. #define emith_write_r_r_offs_ptr(r, rs, offs) do { \
  665. EMIT_REX_IF(1, r, rs); \
  666. emith_deref_op(0x89, r, rs, offs); \
  667. } while (0)
  668. #define emith_read8_r_r_offs(r, rs, offs) do { \
  669. EMIT_REX_IF(0, r, rs); \
  670. emith_deref_op(0x0fb6, r, rs, offs); \
  671. } while (0)
  672. #define emith_read8s_r_r_offs(r, rs, offs) do { \
  673. EMIT_REX_IF(0, r, rs); \
  674. emith_deref_op(0x0fbe, r, rs, offs); \
  675. } while (0)
  676. #define emith_write8_r_r_offs(r, rs, offs) do {\
  677. EMIT_REX_IF(0, r, rs); \
  678. emith_deref_op(0x88, r, rs, offs); \
  679. } while (0)
  680. #define emith_read16_r_r_offs(r, rs, offs) do { \
  681. EMIT_REX_IF(0, r, rs); \
  682. emith_deref_op(0x0fb7, r, rs, offs); \
  683. } while (0)
  684. #define emith_read16s_r_r_offs(r, rs, offs) do { \
  685. EMIT_REX_IF(0, r, rs); \
  686. emith_deref_op(0x0fbf, r, rs, offs); \
  687. } while (0)
  688. #define emith_write16_r_r_offs(r, rs, offs) do { \
  689. EMIT(0x66, u8); /* Intel SDM Vol 2a: REX must be closest to opcode */ \
  690. EMIT_REX_IF(0, r, rs); \
  691. emith_deref_op(0x89, r, rs, offs); \
  692. } while (0)
  693. #define emith_read8_r_r_r(r, rs, rm) do { \
  694. EMIT_XREX_IF(0, r, rm, rs); \
  695. EMIT_OP_MODRM64(0x0fb6, 0, r, 4); \
  696. EMIT_SIB64(0, rs, rm); /* mov r, [rm + rs * 1] */ \
  697. } while (0)
  698. #define emith_read8s_r_r_r(r, rs, rm) do { \
  699. EMIT_XREX_IF(0, r, rm, rs); \
  700. EMIT_OP_MODRM64(0x0fbe, 0, r, 4); \
  701. EMIT_SIB64(0, rs, rm); /* mov r, [rm + rs * 1] */ \
  702. } while (0)
  703. #define emith_read16_r_r_r(r, rs, rm) do { \
  704. EMIT_XREX_IF(0, r, rm, rs); \
  705. EMIT_OP_MODRM64(0x0fb7, 0, r, 4); \
  706. EMIT_SIB64(0, rs, rm); /* mov r, [rm + rs * 1] */ \
  707. } while (0)
  708. #define emith_read16s_r_r_r(r, rs, rm) do { \
  709. EMIT_XREX_IF(0, r, rm, rs); \
  710. EMIT_OP_MODRM64(0x0fbf, 0, r, 4); \
  711. EMIT_SIB64(0, rs, rm); /* mov r, [rm + rs * 1] */ \
  712. } while (0)
  713. #define emith_read_r_r_r(r, rs, rm) do { \
  714. EMIT_XREX_IF(0, r, rm, rs); \
  715. EMIT_OP_MODRM64(0x8b, 0, r, 4); \
  716. EMIT_SIB64(0, rs, rm); /* mov r, [rm + rs * 1] */ \
  717. } while (0)
  718. #define emith_read_r_r_r_ptr(r, rs, rm) do { \
  719. EMIT_XREX_IF(1, r, rm, rs); \
  720. EMIT_OP_MODRM64(0x8b, 0, r, 4); \
  721. EMIT_SIB64(0, rs, rm); /* mov r, [rm + rs * 1] */ \
  722. } while (0)
  723. #define emith_write_r_r_r(r, rs, rm) do { \
  724. EMIT_XREX_IF(0, r, rm, rs); \
  725. EMIT_OP_MODRM64(0x89, 0, r, 4); \
  726. EMIT_SIB64(0, rs, rm); /* mov [rm + rs * 1], r */ \
  727. } while (0)
  728. #define emith_write_r_r_r_ptr(r, rs, rm) do { \
  729. EMIT_XREX_IF(1, r, rm, rs); \
  730. EMIT_OP_MODRM64(0x89, 0, r, 4); \
  731. EMIT_SIB64(0, rs, rm); /* mov [rm + rs * 1], r */ \
  732. } while (0)
  733. #define emith_ctx_read(r, offs) \
  734. emith_read_r_r_offs(r, CONTEXT_REG, offs)
  735. #define emith_ctx_read_c(cond, r, offs) \
  736. emith_ctx_read(r, offs)
  737. #define emith_ctx_read_ptr(r, offs) do { \
  738. EMIT_REX_IF(1, r, CONTEXT_REG); \
  739. emith_deref_op(0x8b, r, CONTEXT_REG, offs); \
  740. } while (0)
  741. #define emith_ctx_write(r, offs) \
  742. emith_write_r_r_offs(r, CONTEXT_REG, offs)
  743. #define emith_ctx_read_multiple(r, offs, cnt, tmpr) do { \
  744. int r_ = r, offs_ = offs, cnt_ = cnt; \
  745. for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
  746. emith_ctx_read(r_, offs_); \
  747. } while (0)
  748. #define emith_ctx_write_multiple(r, offs, cnt, tmpr) do { \
  749. int r_ = r, offs_ = offs, cnt_ = cnt; \
  750. for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
  751. emith_ctx_write(r_, offs_); \
  752. } while (0)
  753. #define emith_ret_to_ctx(offs) do { \
  754. int tmp_ = rcache_get_tmp(); \
  755. emith_pop(tmp_); \
  756. emith_ctx_write(tmp_, offs); \
  757. rcache_free_tmp(tmp_); \
  758. } while (0)
  759. #define emith_jump(ptr) do { \
  760. u32 disp = (u8 *)(ptr) - ((u8 *)tcache_ptr + 5); \
  761. EMIT_OP(0xe9); \
  762. EMIT(disp, u32); \
  763. } while (0)
  764. #define emith_jump_patchable(target) \
  765. emith_jump(target)
  766. #define emith_jump_cond(cond, ptr) do { \
  767. u32 disp = (u8 *)(ptr) - ((u8 *)tcache_ptr + 6); \
  768. EMIT_OP(0x0f80 | (cond)); \
  769. EMIT(disp, u32); \
  770. } while (0)
  771. #define emith_jump_cond_inrange(ptr) !0
  772. #define emith_jump_cond_patchable(cond, target) \
  773. emith_jump_cond(cond, target)
  774. #define emith_jump_patch(ptr, target, pos) do { \
  775. u32 disp_ = (u8 *)(target) - ((u8 *)(ptr) + 4); \
  776. u32 offs_ = (*(u8 *)(ptr) == 0x0f) ? 2 : 1; \
  777. EMIT_PTR((u8 *)(ptr) + offs_, disp_ - offs_, u32); \
  778. if ((void *)(pos) != NULL) *(u8 **)(pos) = (u8 *)ptr + offs_; \
  779. } while (0)
  780. #define emith_jump_patch_size() 4
  781. #define emith_jump_patch_inrange(ptr, target) !0
  782. #define emith_jump_at(ptr, target) do { \
  783. u32 disp_ = (u8 *)(target) - ((u8 *)(ptr) + 5); \
  784. EMIT_PTR(ptr, 0xe9, u8); \
  785. EMIT_PTR((u8 *)(ptr) + 1, disp_, u32); \
  786. } while (0)
  787. #define emith_jump_at_size() 5
  788. #define emith_call(ptr) do { \
  789. u32 disp = (u8 *)(ptr) - ((u8 *)tcache_ptr + 5); \
  790. EMIT_OP(0xe8); \
  791. EMIT(disp, u32); \
  792. } while (0)
  793. #define emith_call_cond(cond, ptr) \
  794. emith_call(ptr)
  795. #define emith_call_reg(r) do { \
  796. EMIT_REX_IF(0, 0, r); \
  797. EMIT_OP_MODRM(0xff, 3, 2, (r)&7); \
  798. } while (0)
  799. #define emith_call_ctx(offs) do { \
  800. EMIT_OP_MODRM(0xff, 2, 2, CONTEXT_REG); \
  801. EMIT(offs, u32); \
  802. } while (0)
  803. #define emith_call_cleanup() \
  804. emith_add_r_r_ptr_imm(xSP, xSP, sizeof(void *)); // remove return addr
  805. #define emith_ret() \
  806. EMIT_OP(0xc3)
  807. #define emith_add_r_ret(r) do { \
  808. EMIT_REX_IF(1, r, xSP); \
  809. emith_deref_modrm(0x03, 0, r, xSP); /* add r, [xsp] */ \
  810. } while (0)
  811. #define emith_jump_reg(r) do { \
  812. EMIT_REX_IF(0, 0, r); \
  813. EMIT_OP_MODRM(0xff, 3, 4, (r)&7); \
  814. } while (0)
  815. #define emith_jump_ctx(offs) do { \
  816. EMIT_OP_MODRM(0xff, 2, 4, CONTEXT_REG); \
  817. EMIT(offs, u32); \
  818. } while (0)
  819. #define emith_push_ret(r) do { \
  820. int r_ = (r >= 0 ? r : xSI); \
  821. emith_push(r_); /* always push to align */ \
  822. emith_add_r_r_ptr_imm(xSP, xSP, -8*4); /* args shadow space */ \
  823. } while (0)
  824. #define emith_pop_and_ret(r) do { \
  825. int r_ = (r >= 0 ? r : xSI); \
  826. emith_add_r_r_ptr_imm(xSP, xSP, 8*4); /* args shadow space */ \
  827. emith_pop(r_); \
  828. emith_ret(); \
  829. } while (0)
  830. #define emith_abijump_reg(r) \
  831. emith_jump_reg(r)
  832. #define emith_abijump_reg_c(cond, r) \
  833. emith_abijump_reg(r)
  834. #define emith_abicall(target) \
  835. emith_call(target)
  836. #define emith_abicall_cond(cond, target) \
  837. emith_abicall(target)
  838. #define emith_abicall_reg(r) \
  839. emith_call_reg(r)
  840. #define EMITH_JMP_START(cond) { \
  841. u8 *cond_ptr; \
  842. JMP8_POS(cond_ptr)
  843. #define EMITH_JMP_END(cond) \
  844. JMP8_EMIT(cond, cond_ptr); \
  845. }
  846. #define EMITH_JMP3_START(cond) { \
  847. u8 *cond_ptr, *else_ptr; \
  848. JMP8_POS(cond_ptr)
  849. #define EMITH_JMP3_MID(cond) \
  850. JMP8_POS(else_ptr); \
  851. JMP8_EMIT(cond, cond_ptr);
  852. #define EMITH_JMP3_END() \
  853. JMP8_EMIT_NC(else_ptr); \
  854. }
  855. // "simple" jump (no more than a few insns)
  856. // ARM will use conditional instructions here
  857. #define EMITH_SJMP_START EMITH_JMP_START
  858. #define EMITH_SJMP_END EMITH_JMP_END
  859. #define EMITH_SJMP3_START EMITH_JMP3_START
  860. #define EMITH_SJMP3_MID EMITH_JMP3_MID
  861. #define EMITH_SJMP3_END EMITH_JMP3_END
  862. #define EMITH_SJMP2_START(cond) \
  863. EMITH_SJMP3_START(cond)
  864. #define EMITH_SJMP2_MID(cond) \
  865. EMITH_SJMP3_MID(cond)
  866. #define EMITH_SJMP2_END(cond) \
  867. EMITH_SJMP3_END()
  868. #define EMITH_HINT_COND(cond) /**/
  869. #define emith_pass_arg_r(arg, reg) do { \
  870. int rd = 7; \
  871. host_arg2reg(rd, arg); \
  872. emith_move_r_r_ptr(rd, reg); \
  873. } while (0)
  874. #define emith_pass_arg_imm(arg, imm) do { \
  875. int rd = 7; \
  876. host_arg2reg(rd, arg); \
  877. emith_move_r_imm(rd, imm); \
  878. } while (0)
  879. #define host_instructions_updated(base, end, force) (void)(base),(void)(end)
  880. #define emith_update_cache() /**/
  881. #define emith_rw_offs_max() 0xffffffffU
  882. #ifdef __x86_64__
  883. #define HOST_REGS 16
  884. #define PTR_SCALE 3
  885. #define EMIT_XREX_IF(w, r, rm, rs) do { \
  886. int xr_ = (r) > 7 ? 1 : 0; \
  887. int xb_ = (rm) > 7 ? 1 : 0; \
  888. int xx_ = (rs) > 7 ? 1 : 0; \
  889. if ((w) | xr_ | xx_ | xb_) \
  890. EMIT_REX(w, xr_, xx_, xb_); \
  891. } while (0)
  892. #define EMIT_REX_IF(w, r, rm) \
  893. EMIT_XREX_IF(w, r, rm, 0)
  894. #ifndef _WIN32
  895. // SystemV ABI conventions:
  896. // rbx,rbp,r12-r15 are preserved, rax,rcx,rdx,rsi,rdi,r8-r11 are temporaries
  897. // parameters in rdi,rsi,rdx,rcx,r8,r9, return values in rax,rdx
  898. #define PARAM_REGS { xDI, xSI, xDX, xCX, xR8, xR9 }
  899. #define PRESERVED_REGS { xR12, xR13, xR14, xR15, xBX, xBP }
  900. #define TEMPORARY_REGS { xAX, xR10, xR11 }
  901. #define STATIC_SH2_REGS { SHR_SR,xBX , SHR_R0,xR15 }
  902. #define host_arg2reg(rd, arg) \
  903. switch (arg) { \
  904. case 0: rd = xDI; break; \
  905. case 1: rd = xSI; break; \
  906. case 2: rd = xDX; break; \
  907. default: rd = xCX; break; \
  908. }
  909. #define emith_sh2_drc_entry() do { \
  910. emith_push(xBX); \
  911. emith_push(xBP); \
  912. emith_push(xR12); \
  913. emith_push(xR13); \
  914. emith_push(xR14); \
  915. emith_push(xR15); \
  916. emith_push(xSI); /* to align */ \
  917. } while (0)
  918. #define emith_sh2_drc_exit() do { \
  919. emith_pop(xSI); \
  920. emith_pop(xR15); \
  921. emith_pop(xR14); \
  922. emith_pop(xR13); \
  923. emith_pop(xR12); \
  924. emith_pop(xBP); \
  925. emith_pop(xBX); \
  926. emith_ret(); \
  927. } while (0)
  928. #else // _WIN32
  929. // M$ ABI conventions:
  930. // rbx,rbp,rsi,rdi,r12-r15 are preserved, rcx,rdx,rax,r8,r9,r10,r11 temporaries
  931. // parameters in rcx,rdx,r8,r9, return values in rax,rdx
  932. #define PARAM_REGS { xCX, xDX, xR8, xR9 }
  933. #define PRESERVED_REGS { xSI, xDI, xR12, xR13, xR14, xR15, xBX, xBP }
  934. #define TEMPORARY_REGS { xAX, xR10, xR11 }
  935. #define STATIC_SH2_REGS { SHR_SR,xBX , SHR_R(0),xR15 , SHR_R(1),xR14 }
  936. #define host_arg2reg(rd, arg) \
  937. switch (arg) { \
  938. case 0: rd = xCX; break; \
  939. case 1: rd = xDX; break; \
  940. case 2: rd = xR8; break; \
  941. default: rd = xR9; break; \
  942. }
  943. #define emith_sh2_drc_entry() do { \
  944. emith_push(xBX); \
  945. emith_push(xBP); \
  946. emith_push(xR12); \
  947. emith_push(xR13); \
  948. emith_push(xR14); \
  949. emith_push(xR15); \
  950. emith_push(xSI); \
  951. emith_push(xDI); \
  952. emith_add_r_r_ptr_imm(xSP, xSP, -8*5); /* align + args shadow space */ \
  953. } while (0)
  954. #define emith_sh2_drc_exit() do { \
  955. emith_add_r_r_ptr_imm(xSP, xSP, 8*5); \
  956. emith_pop(xDI); \
  957. emith_pop(xSI); \
  958. emith_pop(xR15); \
  959. emith_pop(xR14); \
  960. emith_pop(xR13); \
  961. emith_pop(xR12); \
  962. emith_pop(xBP); \
  963. emith_pop(xBX); \
  964. emith_ret(); \
  965. } while (0)
  966. #endif // _WIN32
  967. #else // !__x86_64__
  968. #define HOST_REGS 8
  969. #define PTR_SCALE 2
  970. #define EMIT_REX_IF(w, r, rm) do { \
  971. assert((u32)(r) < 8u); \
  972. assert((u32)(rm) < 8u); \
  973. } while (0)
  974. #define EMIT_XREX_IF(w, r, rs, rm) do { \
  975. assert((u32)(r) < 8u); \
  976. assert((u32)(rs) < 8u); \
  977. assert((u32)(rm) < 8u); \
  978. } while (0)
  979. // MS/SystemV ABI: ebx,esi,edi,ebp are preserved, eax,ecx,edx are temporaries
  980. // DRC uses REGPARM to pass upto 3 parameters in registers eax,ecx,edx.
  981. // To avoid conflicts with param passing ebx must be declared temp here.
  982. #define PARAM_REGS { xAX, xDX, xCX }
  983. #define PRESERVED_REGS { xSI, xDI, xBP }
  984. #define TEMPORARY_REGS { xBX }
  985. #define STATIC_SH2_REGS { SHR_SR,xDI , SHR_R0,xSI }
  986. #define host_arg2reg(rd, arg) \
  987. switch (arg) { \
  988. case 0: rd = xAX; break; \
  989. case 1: rd = xDX; break; \
  990. case 2: rd = xCX; break; \
  991. default: rd = xBX; break; \
  992. }
  993. #define emith_sh2_drc_entry() do { \
  994. emith_push(xBX); \
  995. emith_push(xBP); \
  996. emith_push(xSI); \
  997. emith_push(xDI); \
  998. } while (0)
  999. #define emith_sh2_drc_exit() do { \
  1000. emith_pop(xDI); \
  1001. emith_pop(xSI); \
  1002. emith_pop(xBP); \
  1003. emith_pop(xBX); \
  1004. emith_ret(); \
  1005. } while (0)
  1006. #endif
  1007. #define emith_save_caller_regs(mask) do { \
  1008. int _c; u32 _m = mask & 0xfc7; /* AX, CX, DX, SI, DI, 8, 9, 10, 11 */ \
  1009. if (__builtin_parity(_m) == 1) _m |= 0x8; /* BX for ABI align */ \
  1010. for (_c = HOST_REGS-1; _m && _c >= 0; _m &= ~(1 << _c), _c--) \
  1011. if (_m & (1 << _c)) emith_push(_c); \
  1012. } while (0)
  1013. #define emith_restore_caller_regs(mask) do { \
  1014. int _c; u32 _m = mask & 0xfc7; \
  1015. if (__builtin_parity(_m) == 1) _m |= 0x8; /* BX for ABI align */ \
  1016. for (_c = 0; _m && _c < HOST_REGS; _m &= ~(1 << _c), _c++) \
  1017. if (_m & (1 << _c)) emith_pop(_c); \
  1018. } while (0)
  1019. #define emith_sh2_rcall(a, tab, func, mask) do { \
  1020. emith_lsr(mask, a, SH2_READ_SHIFT); \
  1021. EMIT_XREX_IF(1, tab, tab, mask); \
  1022. EMIT_OP_MODRM64(0x8d, 0, tab, 4); \
  1023. EMIT_SIB64(PTR_SCALE, mask, tab); /* lea tab, [tab + mask * {4,8}] */ \
  1024. EMIT_XREX_IF(1, tab, tab, mask); \
  1025. EMIT_OP_MODRM64(0x8d, 0, tab, 4); \
  1026. EMIT_SIB64(PTR_SCALE, mask, tab); /* lea tab, [tab + mask * {4,8}] */ \
  1027. EMIT_REX_IF(1, func, tab); \
  1028. emith_deref_modrm(0x8b, 0, func, tab); /* mov func, [tab] */ \
  1029. EMIT_REX_IF(0, mask, tab); \
  1030. emith_deref_modrm(0x8b, 1, mask, tab); \
  1031. EMIT(1 << PTR_SCALE, u8); /* mov mask, [tab + {4,8}] */ \
  1032. emith_add_r_r_ptr(func, func); \
  1033. } while (0)
  1034. #define emith_sh2_wcall(a, val, tab, func) do { \
  1035. int arg2_; \
  1036. host_arg2reg(arg2_, 2); \
  1037. emith_lsr(func, a, SH2_WRITE_SHIFT); /* tmp = a >> WRT_SHIFT */ \
  1038. EMIT_XREX_IF(1, func, tab, func); \
  1039. EMIT_OP_MODRM64(0x8b, 0, func, 4); \
  1040. EMIT_SIB64(PTR_SCALE, func, tab); /* mov tmp, [tab + tmp * {4,8}] */ \
  1041. emith_move_r_r_ptr(arg2_, CONTEXT_REG); \
  1042. emith_jump_reg(func); \
  1043. } while (0)
  1044. #define emith_sh2_dtbf_loop() do { \
  1045. u8 *jmp0; /* negative cycles check */ \
  1046. u8 *jmp1; /* unsinged overflow check */ \
  1047. int cr, rn; \
  1048. int tmp_ = rcache_get_tmp(); \
  1049. cr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
  1050. rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW);\
  1051. emith_sub_r_imm(rn, 1); \
  1052. emith_sub_r_imm(cr, (cycles+1) << 12); \
  1053. cycles = 0; \
  1054. emith_asr(tmp_, cr, 2+12); \
  1055. JMP8_POS(jmp0); /* no negative cycles */ \
  1056. emith_move_r_imm(tmp_, 0); \
  1057. JMP8_EMIT(ICOND_JNS, jmp0); \
  1058. emith_and_r_imm(cr, 0xffe); \
  1059. emith_subf_r_r(rn, tmp_); \
  1060. JMP8_POS(jmp1); /* no overflow */ \
  1061. emith_neg_r(rn); /* count left */ \
  1062. emith_lsl(rn, rn, 2+12); \
  1063. emith_or_r_r(cr, rn); \
  1064. emith_or_r_imm(cr, 1); \
  1065. emith_move_r_imm(rn, 0); \
  1066. JMP8_EMIT(ICOND_JA, jmp1); \
  1067. rcache_free_tmp(tmp_); \
  1068. } while (0)
  1069. #define emith_sh2_delay_loop(cycles, reg) do { \
  1070. int sr = rcache_get_reg(SHR_SR, RC_GR_RMW, NULL); \
  1071. int t1 = rcache_get_tmp(); \
  1072. int t2 = rcache_get_tmp(); \
  1073. int t3 = rcache_get_tmp(); \
  1074. if (t3 == xAX) { t3 = t1; t1 = xAX; } /* for MUL */ \
  1075. if (t3 == xDX) { t3 = t2; t2 = xDX; } \
  1076. /* if (sr < 0) return */ \
  1077. emith_asrf(t2, sr, 12); \
  1078. EMITH_JMP_START(DCOND_LE); \
  1079. /* turns = sr.cycles / cycles */ \
  1080. emith_move_r_imm(t3, (u32)((1ULL<<32) / (cycles)) + 1); \
  1081. emith_mul_u64(t1, t2, t2, t3); /* multiply by 1/x */ \
  1082. rcache_free_tmp(t3); \
  1083. if (reg >= 0) { \
  1084. /* if (reg <= turns) turns = reg-1 */ \
  1085. t3 = rcache_get_reg(reg, RC_GR_RMW, NULL); \
  1086. emith_cmp_r_r(t3, t2); \
  1087. EMITH_SJMP_START(DCOND_HI); \
  1088. emith_sub_r_r_imm_c(DCOND_LS, t2, t3, 1); \
  1089. EMITH_SJMP_END(DCOND_HI); \
  1090. /* if (reg <= 1) turns = 0 */ \
  1091. emith_cmp_r_imm(t3, 1); \
  1092. EMITH_SJMP_START(DCOND_HI); \
  1093. emith_move_r_imm_c(DCOND_LS, t2, 0); \
  1094. EMITH_SJMP_END(DCOND_HI); \
  1095. /* reg -= turns */ \
  1096. emith_sub_r_r(t3, t2); \
  1097. } \
  1098. /* sr.cycles -= turns * cycles; */ \
  1099. emith_move_r_imm(t1, cycles); \
  1100. emith_mul_u64(t1, t2, t1, t2); \
  1101. emith_sub_r_r_r_lsl(sr, sr, t1, 12); \
  1102. EMITH_JMP_END(DCOND_LE); \
  1103. rcache_free_tmp(t1); \
  1104. rcache_free_tmp(t2); \
  1105. } while (0)
  1106. #define emith_write_sr(sr, srcr) do { \
  1107. int tmp_ = rcache_get_tmp(); \
  1108. emith_clear_msb(tmp_, srcr, 22); \
  1109. emith_bic_r_imm(sr, 0x3ff); \
  1110. emith_or_r_r(sr, tmp_); \
  1111. rcache_free_tmp(tmp_); \
  1112. } while (0)
  1113. #define emith_carry_to_t(sr, is_sub) do { \
  1114. emith_rorc(sr); \
  1115. emith_rol(sr, sr, 1); \
  1116. } while (0)
  1117. #define emith_t_to_carry(sr, is_sub) do { \
  1118. emith_ror(sr, sr, 1); \
  1119. emith_rol(sr, sr, 1); \
  1120. } while (0)
  1121. #define emith_tpop_carry(sr, is_sub) \
  1122. emith_lsr(sr, sr, 1)
  1123. #define emith_tpush_carry(sr, is_sub) \
  1124. emith_adc_r_r(sr, sr)
  1125. /*
  1126. * T = carry(Rn = (Rn << 1) | T)
  1127. * if Q
  1128. * t = carry(Rn += Rm)
  1129. * else
  1130. * t = carry(Rn -= Rm)
  1131. * T = !(T ^ t)
  1132. */
  1133. #define emith_sh2_div1_step(rn, rm, sr) do { \
  1134. u8 *jmp0, *jmp1; \
  1135. int tmp_ = rcache_get_tmp(); \
  1136. emith_tpop_carry(sr, 0); /* Rn = 2*Rn+T */\
  1137. emith_adcf_r_r_r(rn, rn, rn); \
  1138. emith_tpush_carry(sr, 0); /* T = C1 */ \
  1139. emith_eor_r_r(tmp_, tmp_); \
  1140. emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
  1141. JMP8_POS(jmp0); /* je do_sub */ \
  1142. emith_add_r_r(rn, rm); \
  1143. JMP8_POS(jmp1); /* jmp done */ \
  1144. JMP8_EMIT(ICOND_JE, jmp0); /* do_sub: */ \
  1145. emith_sub_r_r(rn, rm); \
  1146. JMP8_EMIT_NC(jmp1); /* done: */ \
  1147. emith_adc_r_r(tmp_, tmp_); \
  1148. emith_eor_r_r(sr, tmp_);/* T = !(C1^C2) */\
  1149. emith_eor_r_imm(sr, T); \
  1150. rcache_free_tmp(tmp_); \
  1151. } while (0)
  1152. /* mh:ml += rn*rm, does saturation if required by S bit. rn, rm must be TEMP */
  1153. #define emith_sh2_macl(ml, mh, rn, rm, sr) do { \
  1154. emith_tst_r_imm(sr, S); \
  1155. EMITH_SJMP_START(DCOND_EQ); \
  1156. /* MACH top 16 bits unused if saturated. sign ext for overfl detect */ \
  1157. emith_sext(mh, mh, 16); \
  1158. EMITH_SJMP_END(DCOND_EQ); \
  1159. emith_mula_s64(ml, mh, rn, rm); \
  1160. emith_tst_r_imm(sr, S); \
  1161. EMITH_SJMP_START(DCOND_EQ); \
  1162. /* overflow if top 17 bits of MACH aren't all 1 or 0 */ \
  1163. /* to check: add MACH[15] to MACH[31:16]. this is 0 if no overflow */ \
  1164. emith_asrf(rn, mh, 16); /* sum = (MACH>>16) + ((MACH>>15)&1) */ \
  1165. emith_adcf_r_imm(rn, 0); /* (MACH>>15) is in carry after shift */ \
  1166. EMITH_SJMP_START(DCOND_EQ); /* sum != 0 -> ov */ \
  1167. emith_move_r_imm_c(DCOND_NE, ml, 0x0000); /* -overflow */ \
  1168. emith_move_r_imm_c(DCOND_NE, mh, 0x8000); \
  1169. EMITH_SJMP_START(DCOND_LE); /* sum > 0 -> +ovl */ \
  1170. emith_sub_r_imm_c(DCOND_GT, ml, 1); /* 0xffffffff */ \
  1171. emith_sub_r_imm_c(DCOND_GT, mh, 1); /* 0x00007fff */ \
  1172. EMITH_SJMP_END(DCOND_LE); \
  1173. EMITH_SJMP_END(DCOND_EQ); \
  1174. EMITH_SJMP_END(DCOND_EQ); \
  1175. } while (0)
  1176. /* mh:ml += rn*rm, does saturation if required by S bit. rn, rm must be TEMP */
  1177. #define emith_sh2_macw(ml, mh, rn, rm, sr) do { \
  1178. emith_tst_r_imm(sr, S); \
  1179. EMITH_SJMP_START(DCOND_EQ); \
  1180. /* XXX: MACH should be untouched when S is set? */ \
  1181. emith_asr(mh, ml, 31); /* sign ext MACL to MACH for ovrfl check */ \
  1182. EMITH_SJMP_END(DCOND_EQ); \
  1183. emith_mula_s64(ml, mh, rn, rm); \
  1184. emith_tst_r_imm(sr, S); \
  1185. EMITH_SJMP_START(DCOND_EQ); \
  1186. /* overflow if top 33 bits of MACH:MACL aren't all 1 or 0 */ \
  1187. /* to check: add MACL[31] to MACH. this is 0 if no overflow */ \
  1188. emith_lsr(rn, ml, 31); \
  1189. emith_addf_r_r(rn, mh); /* sum = MACH + ((MACL>>31)&1) */ \
  1190. EMITH_SJMP_START(DCOND_EQ); /* sum != 0 -> overflow */ \
  1191. /* XXX: LSB signalling only in SH1, or in SH2 too? */ \
  1192. emith_move_r_imm_c(DCOND_NE, mh, 0x00000001); /* LSB of MACH */ \
  1193. emith_move_r_imm_c(DCOND_NE, ml, 0x80000000); /* negative ovrfl */ \
  1194. EMITH_SJMP_START(DCOND_LE); /* sum > 0 -> positive ovrfl */ \
  1195. emith_sub_r_imm_c(DCOND_GT, ml, 1); /* 0x7fffffff */ \
  1196. EMITH_SJMP_END(DCOND_LE); \
  1197. EMITH_SJMP_END(DCOND_EQ); \
  1198. EMITH_SJMP_END(DCOND_EQ); \
  1199. } while (0)
  1200. #define emith_pool_check() /**/
  1201. #define emith_pool_commit(j) /**/
  1202. #define emith_insn_ptr() ((u8 *)tcache_ptr)
  1203. #define emith_flush() /**/
  1204. #ifdef T
  1205. // T bit handling
  1206. #define emith_invert_cond(cond) \
  1207. ((cond) ^ 1)
  1208. static void emith_clr_t_cond(int sr)
  1209. {
  1210. emith_bic_r_imm(sr, T);
  1211. }
  1212. static void emith_set_t_cond(int sr, int cond)
  1213. {
  1214. EMITH_SJMP_START(emith_invert_cond(cond));
  1215. emith_or_r_imm_c(cond, sr, T);
  1216. EMITH_SJMP_END(emith_invert_cond(cond));
  1217. }
  1218. #define emith_get_t_cond() -1
  1219. #define emith_sync_t(sr) ((void)sr)
  1220. #define emith_invalidate_t()
  1221. static void emith_set_t(int sr, int val)
  1222. {
  1223. if (val)
  1224. emith_or_r_imm(sr, T);
  1225. else
  1226. emith_bic_r_imm(sr, T);
  1227. }
  1228. static int emith_tst_t(int sr, int tf)
  1229. {
  1230. emith_tst_r_imm(sr, T);
  1231. return tf ? DCOND_NE: DCOND_EQ;
  1232. }
  1233. #endif